blob: a289646e8aa46b83a848b4ca9327139593068110 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include "drmP.h"
Dave Airlieeb1f8e42010-05-07 06:42:51 +000029#include "drm_crtc_helper.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020030#include "radeon_drm.h"
31#include "radeon_reg.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020032#include "radeon.h"
33#include "atom.h"
34
Jerome Glisse771fe6b2009-06-05 14:42:42 +020035irqreturn_t radeon_driver_irq_handler_kms(DRM_IRQ_ARGS)
36{
37 struct drm_device *dev = (struct drm_device *) arg;
38 struct radeon_device *rdev = dev->dev_private;
39
40 return radeon_irq_process(rdev);
41}
42
Alex Deucherd4877cf2009-12-04 16:56:37 -050043/*
44 * Handle hotplug events outside the interrupt handler proper.
45 */
46static void radeon_hotplug_work_func(struct work_struct *work)
47{
48 struct radeon_device *rdev = container_of(work, struct radeon_device,
49 hotplug_work);
50 struct drm_device *dev = rdev->ddev;
51 struct drm_mode_config *mode_config = &dev->mode_config;
52 struct drm_connector *connector;
53
54 if (mode_config->num_connector) {
55 list_for_each_entry(connector, &mode_config->connector_list, head)
56 radeon_connector_hotplug(connector);
57 }
58 /* Just fire off a uevent and let userspace tell us what to do */
Dave Airlieeb1f8e42010-05-07 06:42:51 +000059 drm_helper_hpd_irq_event(dev);
Alex Deucherd4877cf2009-12-04 16:56:37 -050060}
61
Jerome Glisse771fe6b2009-06-05 14:42:42 +020062void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
63{
64 struct radeon_device *rdev = dev->dev_private;
65 unsigned i;
66
67 /* Disable *all* interrupts */
68 rdev->irq.sw_int = false;
Alex Deucher2031f772010-04-22 12:52:11 -040069 rdev->irq.gui_idle = false;
Alex Deucher9e7b4142010-03-16 17:08:06 -040070 for (i = 0; i < rdev->num_crtc; i++)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020071 rdev->irq.crtc_vblank_int[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -050072 for (i = 0; i < 6; i++) {
Alex Deucher9e7b4142010-03-16 17:08:06 -040073 rdev->irq.hpd[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -050074 rdev->irq.pflip[i] = false;
75 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +020076 radeon_irq_set(rdev);
77 /* Clear bits */
78 radeon_irq_process(rdev);
79}
80
81int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
82{
83 struct radeon_device *rdev = dev->dev_private;
84
85 dev->max_vblank_count = 0x001fffff;
86 rdev->irq.sw_int = true;
87 radeon_irq_set(rdev);
88 return 0;
89}
90
91void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
92{
93 struct radeon_device *rdev = dev->dev_private;
94 unsigned i;
95
96 if (rdev == NULL) {
97 return;
98 }
99 /* Disable *all* interrupts */
100 rdev->irq.sw_int = false;
Alex Deucher2031f772010-04-22 12:52:11 -0400101 rdev->irq.gui_idle = false;
Alex Deucher9e7b4142010-03-16 17:08:06 -0400102 for (i = 0; i < rdev->num_crtc; i++)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200103 rdev->irq.crtc_vblank_int[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -0500104 for (i = 0; i < 6; i++) {
Jerome Glisse003e69f2010-01-07 15:39:14 +0100105 rdev->irq.hpd[i] = false;
Alex Deucher6f34be52010-11-21 10:59:01 -0500106 rdev->irq.pflip[i] = false;
107 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200108 radeon_irq_set(rdev);
109}
110
111int radeon_irq_kms_init(struct radeon_device *rdev)
112{
113 int r = 0;
114
Tejun Heo32c87fc2011-01-03 14:49:32 +0100115 INIT_WORK(&rdev->hotplug_work, radeon_hotplug_work_func);
116
Dave Airlie1614f8b2009-12-01 16:04:56 +1000117 spin_lock_init(&rdev->irq.sw_lock);
Alex Deucher9e7b4142010-03-16 17:08:06 -0400118 r = drm_vblank_init(rdev->ddev, rdev->num_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200119 if (r) {
120 return r;
121 }
Alex Deucher3e5cb982009-10-16 12:21:24 -0400122 /* enable msi */
123 rdev->msi_enabled = 0;
Alex Deucherc414a112010-03-30 17:22:32 -0400124 /* MSIs don't seem to work reliably on all IGP
125 * chips. Disable MSI on them for now.
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500126 */
127 if ((rdev->family >= CHIP_RV380) &&
Alex Deucherbbbf9b72010-11-22 17:56:36 -0500128 ((!(rdev->flags & RADEON_IS_IGP)) || (rdev->family >= CHIP_PALM)) &&
Alex Deucherda7be682010-08-12 18:05:34 -0400129 (!(rdev->flags & RADEON_IS_AGP))) {
Alex Deucher3e5cb982009-10-16 12:21:24 -0400130 int ret = pci_enable_msi(rdev->pdev);
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500131 if (!ret) {
Alex Deucher3e5cb982009-10-16 12:21:24 -0400132 rdev->msi_enabled = 1;
Alex Deucherda7be682010-08-12 18:05:34 -0400133 dev_info(rdev->dev, "radeon: using MSI.\n");
Alex Deucherd8f60cf2009-12-01 13:43:46 -0500134 }
Alex Deucher3e5cb982009-10-16 12:21:24 -0400135 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200136 rdev->irq.installed = true;
Jerome Glisse003e69f2010-01-07 15:39:14 +0100137 r = drm_irq_install(rdev->ddev);
138 if (r) {
139 rdev->irq.installed = false;
140 return r;
141 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200142 DRM_INFO("radeon: irq initialized.\n");
143 return 0;
144}
145
146void radeon_irq_kms_fini(struct radeon_device *rdev)
147{
Jerome Glisse003e69f2010-01-07 15:39:14 +0100148 drm_vblank_cleanup(rdev->ddev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200149 if (rdev->irq.installed) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200150 drm_irq_uninstall(rdev->ddev);
Jerome Glisse003e69f2010-01-07 15:39:14 +0100151 rdev->irq.installed = false;
Alex Deucher3e5cb982009-10-16 12:21:24 -0400152 if (rdev->msi_enabled)
153 pci_disable_msi(rdev->pdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200154 }
Tejun Heo32c87fc2011-01-03 14:49:32 +0100155 flush_work_sync(&rdev->hotplug_work);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200156}
Dave Airlie1614f8b2009-12-01 16:04:56 +1000157
158void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev)
159{
160 unsigned long irqflags;
161
162 spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
163 if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount == 1)) {
164 rdev->irq.sw_int = true;
165 radeon_irq_set(rdev);
166 }
167 spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
168}
169
170void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev)
171{
172 unsigned long irqflags;
173
174 spin_lock_irqsave(&rdev->irq.sw_lock, irqflags);
175 BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount <= 0);
176 if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount == 0)) {
177 rdev->irq.sw_int = false;
178 radeon_irq_set(rdev);
179 }
180 spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags);
181}
182
Alex Deucher6f34be52010-11-21 10:59:01 -0500183void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
184{
185 unsigned long irqflags;
186
187 if (crtc < 0 || crtc >= rdev->num_crtc)
188 return;
189
190 spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
191 if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
192 rdev->irq.pflip[crtc] = true;
193 radeon_irq_set(rdev);
194 }
195 spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
196}
197
198void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
199{
200 unsigned long irqflags;
201
202 if (crtc < 0 || crtc >= rdev->num_crtc)
203 return;
204
205 spin_lock_irqsave(&rdev->irq.pflip_lock[crtc], irqflags);
206 BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
207 if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
208 rdev->irq.pflip[crtc] = false;
209 radeon_irq_set(rdev);
210 }
211 spin_unlock_irqrestore(&rdev->irq.pflip_lock[crtc], irqflags);
212}
213