| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/at91rm9200.h |
| 3 | * |
| 4 | * Copyright (C) 2005 Ivan Kokshaysky |
| 5 | * Copyright (C) SAN People |
| 6 | * |
| 7 | * Common definitions. |
| 8 | * Based on AT91RM9200 datasheet revision E. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91RM9200_H |
| 17 | #define AT91RM9200_H |
| 18 | |
| 19 | /* |
| 20 | * Peripheral identifiers/interrupts. |
| 21 | */ |
| 22 | #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
| 23 | #define AT91_ID_SYS 1 /* System Peripheral */ |
| 24 | #define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */ |
| 25 | #define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */ |
| 26 | #define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */ |
| 27 | #define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */ |
| 28 | #define AT91RM9200_ID_US0 6 /* USART 0 */ |
| 29 | #define AT91RM9200_ID_US1 7 /* USART 1 */ |
| 30 | #define AT91RM9200_ID_US2 8 /* USART 2 */ |
| 31 | #define AT91RM9200_ID_US3 9 /* USART 3 */ |
| 32 | #define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */ |
| 33 | #define AT91RM9200_ID_UDP 11 /* USB Device Port */ |
| 34 | #define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */ |
| 35 | #define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */ |
| 36 | #define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */ |
| 37 | #define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */ |
| 38 | #define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */ |
| 39 | #define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */ |
| 40 | #define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */ |
| 41 | #define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */ |
| 42 | #define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */ |
| 43 | #define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */ |
| 44 | #define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */ |
| 45 | #define AT91RM9200_ID_UHP 23 /* USB Host port */ |
| 46 | #define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */ |
| 47 | #define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ |
| 48 | #define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ |
| 49 | #define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ |
| 50 | #define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ |
| 51 | #define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ |
| 52 | #define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ |
| 53 | #define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ |
| 54 | |
| 55 | |
| 56 | /* |
| 57 | * Peripheral physical base addresses. |
| 58 | */ |
| 59 | #define AT91RM9200_BASE_TCB0 0xfffa0000 |
| 60 | #define AT91RM9200_BASE_TC0 0xfffa0000 |
| 61 | #define AT91RM9200_BASE_TC1 0xfffa0040 |
| 62 | #define AT91RM9200_BASE_TC2 0xfffa0080 |
| 63 | #define AT91RM9200_BASE_TCB1 0xfffa4000 |
| 64 | #define AT91RM9200_BASE_TC3 0xfffa4000 |
| 65 | #define AT91RM9200_BASE_TC4 0xfffa4040 |
| 66 | #define AT91RM9200_BASE_TC5 0xfffa4080 |
| 67 | #define AT91RM9200_BASE_UDP 0xfffb0000 |
| 68 | #define AT91RM9200_BASE_MCI 0xfffb4000 |
| 69 | #define AT91RM9200_BASE_TWI 0xfffb8000 |
| 70 | #define AT91RM9200_BASE_EMAC 0xfffbc000 |
| 71 | #define AT91RM9200_BASE_US0 0xfffc0000 |
| 72 | #define AT91RM9200_BASE_US1 0xfffc4000 |
| 73 | #define AT91RM9200_BASE_US2 0xfffc8000 |
| 74 | #define AT91RM9200_BASE_US3 0xfffcc000 |
| 75 | #define AT91RM9200_BASE_SSC0 0xfffd0000 |
| 76 | #define AT91RM9200_BASE_SSC1 0xfffd4000 |
| 77 | #define AT91RM9200_BASE_SSC2 0xfffd8000 |
| 78 | #define AT91RM9200_BASE_SPI 0xfffe0000 |
| 79 | #define AT91_BASE_SYS 0xfffff000 |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * System Peripherals (offset from AT91_BASE_SYS) |
| 84 | */ |
| 85 | #define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */ |
| 86 | #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */ |
| 87 | #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */ |
| 88 | #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */ |
| 89 | #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */ |
| 90 | #define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */ |
| 91 | #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */ |
| 92 | #define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */ |
| 93 | #define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */ |
| 94 | #define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */ |
| 95 | |
| 96 | #define AT91_USART0 AT91RM9200_BASE_US0 |
| 97 | #define AT91_USART1 AT91RM9200_BASE_US1 |
| 98 | #define AT91_USART2 AT91RM9200_BASE_US2 |
| 99 | #define AT91_USART3 AT91RM9200_BASE_US3 |
| 100 | |
| 101 | #define AT91_MATRIX 0 /* not supported */ |
| 102 | |
| 103 | /* |
| 104 | * Internal Memory. |
| 105 | */ |
| 106 | #define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */ |
| 107 | #define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */ |
| 108 | |
| 109 | #define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */ |
| 110 | #define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ |
| 111 | |
| 112 | #define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ |
| 113 | |
| 114 | |
| 115 | #endif |