blob: 3815a8262af070b98f33d61ac31908961ee06eb2 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001#include <linux/linkage.h>
2#include <asm/assembler.h>
George G. Davis3a1e5012005-04-29 22:08:33 +01003#include "abort-macro.S"
Linus Torvalds1da177e2005-04-16 15:20:36 -07004/*
5 * Function: v6_early_abort
6 *
Russell Kingda740472011-06-26 16:01:26 +01007 * Params : r2 = pt_regs
8 * : r4 = aborted context pc
Russell King3e287be2011-06-26 14:35:07 +01009 * : r5 = aborted context psr
Linus Torvalds1da177e2005-04-16 15:20:36 -070010 *
Russell Kingda740472011-06-26 16:01:26 +010011 * Returns : r4 - r11, r13 preserved
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 *
13 * Purpose : obtain information about current aborted instruction.
George G. Davis3a1e5012005-04-29 22:08:33 +010014 * Note: we read user space. This means we might cause a data
15 * abort here if the I-TLB and D-TLB aren't seeing the same
16 * picture. Unfortunately, this does happen. We live with it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070017 */
18 .align 5
19ENTRY(v6_early_abort)
Russell King7db44c72011-01-17 15:35:37 +000020#ifdef CONFIG_CPU_V6
Seth Forshee25ef4a62009-03-02 22:39:36 +010021 sub r1, sp, #4 @ Get unused stack location
22 strex r0, r1, [r1] @ Clear the exclusive monitor
Russell King7db44c72011-01-17 15:35:37 +000023#elif defined(CONFIG_CPU_32v6K)
24 clrex
Catalin Marinas2c3a0542005-10-02 22:34:35 +010025#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -070026 mrc p15, 0, r1, c5, c0, 0 @ get FSR
27 mrc p15, 0, r0, c6, c0, 0 @ get FAR
George G. Davis3a1e5012005-04-29 22:08:33 +010028/*
Will Deaconf0c4b8d2012-04-20 17:20:08 +010029 * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
George G. Davis3a1e5012005-04-29 22:08:33 +010030 */
Will Deaconf0c4b8d2012-04-20 17:20:08 +010031#ifdef CONFIG_ARM_ERRATA_326103
32 ldr ip, =0x4107b36
33 mrc p15, 0, r3, c0, c0, 0 @ get processor id
34 teq ip, r3, lsr #4 @ r0 ARM1136?
Russell Kingda740472011-06-26 16:01:26 +010035 bne do_DataAbort
Will Deaconf0c4b8d2012-04-20 17:20:08 +010036 tst r5, #PSR_J_BIT @ Java?
37 tsteq r5, #PSR_T_BIT @ Thumb?
38 bne do_DataAbort
39 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
40 ldr r3, [r4] @ read aborted ARM instruction
Ben Dooks457c2402013-02-12 18:59:57 +000041 ARM_BE8(rev r3, r3)
42
Russell King0d147db2011-06-26 14:42:02 +010043 do_ldrd_abort tmp=ip, insn=r3
George G. Davis3a1e5012005-04-29 22:08:33 +010044 tst r3, #1 << 20 @ L = 0 -> write
45 orreq r1, r1, #1 << 11 @ yes.
Will Deaconf0c4b8d2012-04-20 17:20:08 +010046#endif
Russell Kingda740472011-06-26 16:01:26 +010047 b do_DataAbort