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Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001/*
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01002 * Support functions for OMAP GPIO
3 *
Tony Lindgren92105bb2005-09-07 17:20:26 +01004 * Copyright (C) 2003-2005 Nokia Corporation
Jan Engelhardt96de0e22007-10-19 23:21:04 +02005 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01006 *
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010010 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010015#include <linux/init.h>
16#include <linux/module.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010017#include <linux/interrupt.h>
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +020018#include <linux/syscore_ops.h>
Tony Lindgren92105bb2005-09-07 17:20:26 +010019#include <linux/err.h>
Russell Kingf8ce2542006-01-07 16:15:52 +000020#include <linux/clk.h>
Russell Kingfced80c2008-09-06 12:10:45 +010021#include <linux/io.h>
Benoit Cousson96751fc2012-02-01 16:01:39 +010022#include <linux/device.h>
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080023#include <linux/pm_runtime.h>
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +053024#include <linux/pm.h>
Benoit Cousson384ebe12011-08-16 11:53:02 +020025#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
Catalin Marinasde88cbb2013-01-18 15:31:37 +000028#include <linux/irqchip/chained_irq.h>
Tony Lindgren4b254082012-08-30 15:37:24 -070029#include <linux/gpio.h>
30#include <linux/platform_data/gpio-omap.h>
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010031
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053032#define OFF_MODE 1
33
Charulatha V03e128c2011-05-05 19:58:01 +053034static LIST_HEAD(omap_gpio_list);
35
Charulatha V6d62e212011-04-18 15:06:51 +000036struct gpio_regs {
37 u32 irqenable1;
38 u32 irqenable2;
39 u32 wake_en;
40 u32 ctrl;
41 u32 oe;
42 u32 leveldetect0;
43 u32 leveldetect1;
44 u32 risingdetect;
45 u32 fallingdetect;
46 u32 dataout;
Nishanth Menonae547352011-09-09 19:08:58 +053047 u32 debounce;
48 u32 debounce_en;
Charulatha V6d62e212011-04-18 15:06:51 +000049};
50
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010051struct gpio_bank {
Charulatha V03e128c2011-05-05 19:58:01 +053052 struct list_head node;
Tony Lindgren92105bb2005-09-07 17:20:26 +010053 void __iomem *base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010054 u16 irq;
Benoit Cousson384ebe12011-08-16 11:53:02 +020055 struct irq_domain *domain;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080056 u32 non_wakeup_gpios;
57 u32 enabled_non_wakeup_gpios;
Charulatha V6d62e212011-04-18 15:06:51 +000058 struct gpio_regs context;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -080059 u32 saved_datain;
Kevin Hilmanb144ff62008-01-16 21:56:15 -080060 u32 level_mask;
Cory Maccarrone4318f362010-01-08 10:29:04 -080061 u32 toggle_mask;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010062 spinlock_t lock;
David Brownell52e31342008-03-03 12:43:23 -080063 struct gpio_chip chip;
Jouni Hogander89db9482008-12-10 17:35:24 -080064 struct clk *dbck;
Charulatha V058af1e2009-11-22 10:11:25 -080065 u32 mod_usage;
Kevin Hilman8865b9b2009-01-27 11:15:34 -080066 u32 dbck_enable_mask;
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +053067 bool dbck_enabled;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080068 struct device *dev;
Charulatha Vd0d665a2011-08-31 00:02:21 +053069 bool is_mpuio;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -080070 bool dbck_flag;
Charulatha V0cde8d02011-05-05 20:15:16 +053071 bool loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -050072 bool context_valid;
Tony Lindgren5de62b82010-12-07 16:26:58 -080073 int stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -070074 u32 width;
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053075 int context_loss_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +053076 int power_mode;
77 bool workaround_enabled;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070078
79 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +053080 int (*get_context_loss_count)(struct device *dev);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -070081
82 struct omap_gpio_reg_offs *regs;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010083};
84
Kevin Hilman129fd222011-04-22 07:59:07 -070085#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
86#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
Charulatha Vc8eef652011-05-02 15:21:42 +053087#define GPIO_MOD_CTRL_BIT BIT(0)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +010088
Benoit Cousson25db7112012-02-23 21:50:10 +010089static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
90{
Jon Hunterede4d7a2013-03-01 11:22:47 -060091 return bank->chip.base + gpio_irq;
92}
93
94static int omap_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
95{
96 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
97
98 return irq_find_mapping(bank->domain, offset);
Benoit Cousson25db7112012-02-23 21:50:10 +010099}
100
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100101static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
102{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100103 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100104 u32 l;
105
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700106 reg += bank->regs->direction;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100107 l = __raw_readl(reg);
108 if (is_input)
109 l |= 1 << gpio;
110 else
111 l &= ~(1 << gpio);
112 __raw_writel(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530113 bank->context.oe = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100114}
115
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700116
117/* set data out value using dedicate set/clear register */
118static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100119{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100120 void __iomem *reg = bank->base;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700121 u32 l = GPIO_BIT(bank, gpio);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100122
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530123 if (enable) {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700124 reg += bank->regs->set_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530125 bank->context.dataout |= l;
126 } else {
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700127 reg += bank->regs->clr_dataout;
Tarun Kanti DebBarma2c836f72012-03-02 12:52:52 +0530128 bank->context.dataout &= ~l;
129 }
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700130
131 __raw_writel(l, reg);
132}
133
134/* set data out value using mask register */
135static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
136{
137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = GPIO_BIT(bank, gpio);
139 u32 l;
140
141 l = __raw_readl(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100146 __raw_writel(l, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530147 bank->context.dataout = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100148}
149
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530150static int _get_gpio_datain(struct gpio_bank *bank, int offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100151{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700152 void __iomem *reg = bank->base + bank->regs->datain;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100153
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530154 return (__raw_readl(reg) & (1 << offset)) != 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100155}
156
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530157static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300158{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700159 void __iomem *reg = bank->base + bank->regs->dataout;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300160
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530161 return (__raw_readl(reg) & (1 << offset)) != 0;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300162}
163
Kevin Hilmanece95282011-07-12 08:18:15 -0700164static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165{
166 int l = __raw_readl(base + reg);
167
Benoit Cousson862ff642012-02-01 15:58:56 +0100168 if (set)
Kevin Hilmanece95282011-07-12 08:18:15 -0700169 l |= mask;
170 else
171 l &= ~mask;
172
173 __raw_writel(l, base + reg);
174}
Tony Lindgren92105bb2005-09-07 17:20:26 +0100175
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530176static inline void _gpio_dbck_enable(struct gpio_bank *bank)
177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300181
182 __raw_writel(bank->dbck_enable_mask,
183 bank->base + bank->regs->debounce_en);
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530184 }
185}
186
187static inline void _gpio_dbck_disable(struct gpio_bank *bank)
188{
189 if (bank->dbck_enable_mask && bank->dbck_enabled) {
Grazvydas Ignotas9e303f22012-06-16 22:01:25 +0300190 /*
191 * Disable debounce before cutting it's clock. If debounce is
192 * enabled but the clock is not, GPIO module seems to be unable
193 * to detect events and generate interrupts at least on OMAP3.
194 */
195 __raw_writel(0, bank->base + bank->regs->debounce_en);
196
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +0530197 clk_disable(bank->dbck);
198 bank->dbck_enabled = false;
199 }
200}
201
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700202/**
203 * _set_gpio_debounce - low level gpio debounce time
204 * @bank: the gpio bank we're acting upon
205 * @gpio: the gpio number on this @gpio
206 * @debounce: debounce time to use
207 *
208 * OMAP's debounce time is in 31us steps so we need
209 * to convert and round up to the closest unit.
210 */
211static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
212 unsigned debounce)
213{
Kevin Hilman9942da02011-04-22 12:02:05 -0700214 void __iomem *reg;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700215 u32 val;
216 u32 l;
217
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800218 if (!bank->dbck_flag)
219 return;
220
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700221 if (debounce < 32)
222 debounce = 0x01;
223 else if (debounce > 7936)
224 debounce = 0xff;
225 else
226 debounce = (debounce / 0x1f) - 1;
227
Kevin Hilman129fd222011-04-22 07:59:07 -0700228 l = GPIO_BIT(bank, gpio);
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700229
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530230 clk_enable(bank->dbck);
Kevin Hilman9942da02011-04-22 12:02:05 -0700231 reg = bank->base + bank->regs->debounce;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700232 __raw_writel(debounce, reg);
233
Kevin Hilman9942da02011-04-22 12:02:05 -0700234 reg = bank->base + bank->regs->debounce_en;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700235 val = __raw_readl(reg);
236
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530237 if (debounce)
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700238 val |= l;
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530239 else
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700240 val &= ~l;
Kevin Hilmanf7ec0b02010-06-09 13:53:07 +0300241 bank->dbck_enable_mask = val;
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700242
243 __raw_writel(val, reg);
Tarun Kanti DebBarma6fd9c422011-11-24 03:58:54 +0530244 clk_disable(bank->dbck);
245 /*
246 * Enable debounce clock per module.
247 * This call is mandatory because in omap_gpio_request() when
248 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
249 * runtime callbck fails to turn on dbck because dbck_enable_mask
250 * used within _gpio_dbck_enable() is still not initialized at
251 * that point. Therefore we have to enable dbck here.
252 */
253 _gpio_dbck_enable(bank);
Nishanth Menonae547352011-09-09 19:08:58 +0530254 if (bank->dbck_enable_mask) {
255 bank->context.debounce = debounce;
256 bank->context.debounce_en = val;
257 }
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700258}
259
Jon Hunterc9c55d92012-10-26 14:26:04 -0500260/**
261 * _clear_gpio_debounce - clear debounce settings for a gpio
262 * @bank: the gpio bank we're acting upon
263 * @gpio: the gpio number on this @gpio
264 *
265 * If a gpio is using debounce, then clear the debounce enable bit and if
266 * this is the only gpio in this bank using debounce, then clear the debounce
267 * time too. The debounce clock will also be disabled when calling this function
268 * if this is the only gpio in the bank using debounce.
269 */
270static void _clear_gpio_debounce(struct gpio_bank *bank, unsigned gpio)
271{
272 u32 gpio_bit = GPIO_BIT(bank, gpio);
273
274 if (!bank->dbck_flag)
275 return;
276
277 if (!(bank->dbck_enable_mask & gpio_bit))
278 return;
279
280 bank->dbck_enable_mask &= ~gpio_bit;
281 bank->context.debounce_en &= ~gpio_bit;
282 __raw_writel(bank->context.debounce_en,
283 bank->base + bank->regs->debounce_en);
284
285 if (!bank->dbck_enable_mask) {
286 bank->context.debounce = 0;
287 __raw_writel(bank->context.debounce, bank->base +
288 bank->regs->debounce);
289 clk_disable(bank->dbck);
290 bank->dbck_enabled = false;
291 }
292}
293
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530294static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
Tarun Kanti DebBarma00ece7e2011-11-25 15:41:06 +0530295 unsigned trigger)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100296{
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800297 void __iomem *base = bank->base;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100298 u32 gpio_bit = 1 << gpio;
299
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530300 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
301 trigger & IRQ_TYPE_LEVEL_LOW);
302 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
303 trigger & IRQ_TYPE_LEVEL_HIGH);
304 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
305 trigger & IRQ_TYPE_EDGE_RISING);
306 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
307 trigger & IRQ_TYPE_EDGE_FALLING);
308
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530309 bank->context.leveldetect0 =
310 __raw_readl(bank->base + bank->regs->leveldetect0);
311 bank->context.leveldetect1 =
312 __raw_readl(bank->base + bank->regs->leveldetect1);
313 bank->context.risingdetect =
314 __raw_readl(bank->base + bank->regs->risingdetect);
315 bank->context.fallingdetect =
316 __raw_readl(bank->base + bank->regs->fallingdetect);
317
318 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530319 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530320 bank->context.wake_en =
321 __raw_readl(bank->base + bank->regs->wkup_en);
322 }
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530323
Ambresh K55b220c2011-06-15 13:40:45 -0700324 /* This part needs to be executed always for OMAP{34xx, 44xx} */
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530325 if (!bank->regs->irqctrl) {
326 /* On omap24xx proceed only when valid GPIO bit is set */
327 if (bank->non_wakeup_gpios) {
328 if (!(bank->non_wakeup_gpios & gpio_bit))
329 goto exit;
330 }
331
Chunqiu Wang699117a62009-06-24 17:13:39 +0000332 /*
333 * Log the edge gpio and manually trigger the IRQ
334 * after resume if the input level changes
335 * to avoid irq lost during PER RET/OFF mode
336 * Applies for omap2 non-wakeup gpio and all omap3 gpios
337 */
338 if (trigger & IRQ_TYPE_EDGE_BOTH)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -0800339 bank->enabled_non_wakeup_gpios |= gpio_bit;
340 else
341 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
342 }
Kevin Hilman5eb3bb92007-05-05 11:40:29 -0700343
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530344exit:
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530345 bank->level_mask =
346 __raw_readl(bank->base + bank->regs->leveldetect0) |
347 __raw_readl(bank->base + bank->regs->leveldetect1);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100348}
349
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800350#ifdef CONFIG_ARCH_OMAP1
Cory Maccarrone4318f362010-01-08 10:29:04 -0800351/*
352 * This only applies to chips that can't do both rising and falling edge
353 * detection at once. For all other chips, this function is a noop.
354 */
355static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
356{
357 void __iomem *reg = bank->base;
358 u32 l = 0;
359
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530360 if (!bank->regs->irqctrl)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800361 return;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530362
363 reg += bank->regs->irqctrl;
Cory Maccarrone4318f362010-01-08 10:29:04 -0800364
365 l = __raw_readl(reg);
366 if ((l >> gpio) & 1)
367 l &= ~(1 << gpio);
368 else
369 l |= 1 << gpio;
370
371 __raw_writel(l, reg);
372}
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530373#else
374static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
Uwe Kleine-König9198bcd2010-01-29 14:20:05 -0800375#endif
Cory Maccarrone4318f362010-01-08 10:29:04 -0800376
Tarun Kanti DebBarma00ece7e2011-11-25 15:41:06 +0530377static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
378 unsigned trigger)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100379{
380 void __iomem *reg = bank->base;
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530381 void __iomem *base = bank->base;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100382 u32 l = 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100383
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530384 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
385 set_gpio_trigger(bank, gpio, trigger);
386 } else if (bank->regs->irqctrl) {
387 reg += bank->regs->irqctrl;
388
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100389 l = __raw_readl(reg);
Janusz Krzysztofik29501572010-04-05 11:38:06 +0000390 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
Cory Maccarrone4318f362010-01-08 10:29:04 -0800391 bank->toggle_mask |= 1 << gpio;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100392 if (trigger & IRQ_TYPE_EDGE_RISING)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100393 l |= 1 << gpio;
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100394 else if (trigger & IRQ_TYPE_EDGE_FALLING)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100395 l &= ~(1 << gpio);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100396 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530397 return -EINVAL;
398
399 __raw_writel(l, reg);
400 } else if (bank->regs->edgectrl1) {
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100401 if (gpio & 0x08)
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530402 reg += bank->regs->edgectrl2;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100403 else
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530404 reg += bank->regs->edgectrl1;
405
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100406 gpio &= 0x07;
407 l = __raw_readl(reg);
408 l &= ~(3 << (gpio << 1));
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100409 if (trigger & IRQ_TYPE_EDGE_RISING)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100410 l |= 2 << (gpio << 1);
Dmitry Baryshkov6cab4862008-07-27 04:23:31 +0100411 if (trigger & IRQ_TYPE_EDGE_FALLING)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100412 l |= 1 << (gpio << 1);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530413
414 /* Enable wake-up during idle for dynamic tick */
415 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530416 bank->context.wake_en =
417 __raw_readl(bank->base + bank->regs->wkup_en);
Tarun Kanti DebBarma5e571f32011-09-13 15:02:14 +0530418 __raw_writel(l, reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100419 }
Tony Lindgren92105bb2005-09-07 17:20:26 +0100420 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100421}
422
Lennert Buytenheke9191022010-11-29 11:17:17 +0100423static int gpio_irq_type(struct irq_data *d, unsigned type)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100424{
Benoit Cousson25db7112012-02-23 21:50:10 +0100425 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Tony Lindgren4b254082012-08-30 15:37:24 -0700426 unsigned gpio = 0;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100427 int retval;
David Brownella6472532008-03-03 04:33:30 -0800428 unsigned long flags;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100429
Jon Hunter8d4c2772013-03-01 11:22:48 -0600430 if (WARN_ON(!bank->mod_usage))
431 return -EINVAL;
432
Tony Lindgren4b254082012-08-30 15:37:24 -0700433#ifdef CONFIG_ARCH_OMAP1
434 if (d->irq > IH_MPUIO_BASE)
Lennert Buytenheke9191022010-11-29 11:17:17 +0100435 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
Tony Lindgren4b254082012-08-30 15:37:24 -0700436#endif
437
438 if (!gpio)
Jon Hunterede4d7a2013-03-01 11:22:47 -0600439 gpio = irq_to_gpio(bank, d->hwirq);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100440
David Brownelle5c56ed2006-12-06 17:13:59 -0800441 if (type & ~IRQ_TYPE_SENSE_MASK)
Tony Lindgren6e60e792006-04-02 17:46:23 +0100442 return -EINVAL;
David Brownelle5c56ed2006-12-06 17:13:59 -0800443
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530444 if (!bank->regs->leveldetect0 &&
445 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
Tony Lindgren92105bb2005-09-07 17:20:26 +0100446 return -EINVAL;
447
David Brownella6472532008-03-03 04:33:30 -0800448 spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman129fd222011-04-22 07:59:07 -0700449 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
David Brownella6472532008-03-03 04:33:30 -0800450 spin_unlock_irqrestore(&bank->lock, flags);
Kevin Hilman672e3022008-01-16 21:56:16 -0800451
452 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100453 __irq_set_handler_locked(d->irq, handle_level_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800454 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100455 __irq_set_handler_locked(d->irq, handle_edge_irq);
Kevin Hilman672e3022008-01-16 21:56:16 -0800456
Tony Lindgren92105bb2005-09-07 17:20:26 +0100457 return retval;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100458}
459
460static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
461{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100462 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100463
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700464 reg += bank->regs->irqstatus;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100465 __raw_writel(gpio_mask, reg);
Hiroshi DOYUbee79302006-09-25 12:41:46 +0300466
467 /* Workaround for clearing DSP GPIO interrupts to allow retention */
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700468 if (bank->regs->irqstatus2) {
469 reg = bank->base + bank->regs->irqstatus2;
Roger Quadrosbedfd152009-04-23 11:10:50 -0700470 __raw_writel(gpio_mask, reg);
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700471 }
Roger Quadrosbedfd152009-04-23 11:10:50 -0700472
473 /* Flush posted write for the irq status to avoid spurious interrupts */
474 __raw_readl(reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100475}
476
477static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
478{
Kevin Hilman129fd222011-04-22 07:59:07 -0700479 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100480}
481
Imre Deakea6dedd2006-06-26 16:16:00 -0700482static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
483{
484 void __iomem *reg = bank->base;
Imre Deak99c47702006-06-26 16:16:07 -0700485 u32 l;
Kevin Hilmanc390aad02011-04-21 09:33:36 -0700486 u32 mask = (1 << bank->width) - 1;
Imre Deakea6dedd2006-06-26 16:16:00 -0700487
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700488 reg += bank->regs->irqenable;
Imre Deak99c47702006-06-26 16:16:07 -0700489 l = __raw_readl(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700490 if (bank->regs->irqenable_inv)
Imre Deak99c47702006-06-26 16:16:07 -0700491 l = ~l;
492 l &= mask;
493 return l;
Imre Deakea6dedd2006-06-26 16:16:00 -0700494}
495
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700496static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100497{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100498 void __iomem *reg = bank->base;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100499 u32 l;
500
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700501 if (bank->regs->set_irqenable) {
502 reg += bank->regs->set_irqenable;
503 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530504 bank->context.irqenable1 |= gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700505 } else {
506 reg += bank->regs->irqenable;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100507 l = __raw_readl(reg);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700508 if (bank->regs->irqenable_inv)
509 l &= ~gpio_mask;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100510 else
511 l |= gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530512 bank->context.irqenable1 = l;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100513 }
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700514
515 __raw_writel(l, reg);
516}
517
518static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
519{
520 void __iomem *reg = bank->base;
521 u32 l;
522
523 if (bank->regs->clr_irqenable) {
524 reg += bank->regs->clr_irqenable;
525 l = gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530526 bank->context.irqenable1 &= ~gpio_mask;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700527 } else {
528 reg += bank->regs->irqenable;
529 l = __raw_readl(reg);
530 if (bank->regs->irqenable_inv)
531 l |= gpio_mask;
532 else
533 l &= ~gpio_mask;
Tarun Kanti DebBarma2a900eb2012-03-06 12:08:16 +0530534 bank->context.irqenable1 = l;
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700535 }
536
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100537 __raw_writel(l, reg);
538}
539
540static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
541{
Tarun Kanti DebBarma8276536c2011-11-25 15:27:37 +0530542 if (enable)
543 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
544 else
545 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100546}
547
Tony Lindgren92105bb2005-09-07 17:20:26 +0100548/*
549 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
550 * 1510 does not seem to have a wake-up register. If JTAG is connected
551 * to the target, system will wake up always on GPIO events. While
552 * system is running all registered GPIO interrupts need to have wake-up
553 * enabled. When system is suspended, only selected GPIO interrupts need
554 * to have wake-up enabled.
555 */
556static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
557{
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700558 u32 gpio_bit = GPIO_BIT(bank, gpio);
559 unsigned long flags;
David Brownella6472532008-03-03 04:33:30 -0800560
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700561 if (bank->non_wakeup_gpios & gpio_bit) {
Benoit Cousson862ff642012-02-01 15:58:56 +0100562 dev_err(bank->dev,
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700563 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100564 return -EINVAL;
565 }
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700566
567 spin_lock_irqsave(&bank->lock, flags);
568 if (enable)
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530569 bank->context.wake_en |= gpio_bit;
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700570 else
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530571 bank->context.wake_en &= ~gpio_bit;
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700572
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530573 __raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
Kevin Hilmanf64ad1a2011-04-22 09:45:27 -0700574 spin_unlock_irqrestore(&bank->lock, flags);
575
576 return 0;
Tony Lindgren92105bb2005-09-07 17:20:26 +0100577}
578
Tony Lindgren4196dd62006-09-25 12:41:38 +0300579static void _reset_gpio(struct gpio_bank *bank, int gpio)
580{
Kevin Hilman129fd222011-04-22 07:59:07 -0700581 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300582 _set_gpio_irqenable(bank, gpio, 0);
583 _clear_gpio_irqstatus(bank, gpio);
Kevin Hilman129fd222011-04-22 07:59:07 -0700584 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
Jon Hunterc9c55d92012-10-26 14:26:04 -0500585 _clear_gpio_debounce(bank, gpio);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300586}
587
Tony Lindgren92105bb2005-09-07 17:20:26 +0100588/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
Lennert Buytenheke9191022010-11-29 11:17:17 +0100589static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
Tony Lindgren92105bb2005-09-07 17:20:26 +0100590{
Benoit Cousson25db7112012-02-23 21:50:10 +0100591 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Jon Hunterede4d7a2013-03-01 11:22:47 -0600592 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100593
Benoit Cousson25db7112012-02-23 21:50:10 +0100594 return _set_gpio_wakeup(bank, gpio, enable);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100595}
596
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800597static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100598{
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800599 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
David Brownella6472532008-03-03 04:33:30 -0800600 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100601
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530602 /*
603 * If this is the first gpio_request for the bank,
604 * enable the bank module.
605 */
606 if (!bank->mod_usage)
607 pm_runtime_get_sync(bank->dev);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100608
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530609 spin_lock_irqsave(&bank->lock, flags);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300610 /* Set trigger to none. You need to enable the desired trigger with
611 * request_irq() or set_irq_type().
612 */
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800613 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
Tony Lindgren92105bb2005-09-07 17:20:26 +0100614
Charulatha Vfad96ea2011-05-25 11:23:50 +0530615 if (bank->regs->pinctrl) {
616 void __iomem *reg = bank->base + bank->regs->pinctrl;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100617
Tony Lindgren92105bb2005-09-07 17:20:26 +0100618 /* Claim the pin for MPU */
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800619 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100620 }
Charulatha Vfad96ea2011-05-25 11:23:50 +0530621
Charulatha Vc8eef652011-05-02 15:21:42 +0530622 if (bank->regs->ctrl && !bank->mod_usage) {
623 void __iomem *reg = bank->base + bank->regs->ctrl;
624 u32 ctrl;
Charulatha V9f096862010-05-14 12:05:27 -0700625
Charulatha Vc8eef652011-05-02 15:21:42 +0530626 ctrl = __raw_readl(reg);
627 /* Module is enabled, clocks are not gated */
628 ctrl &= ~GPIO_MOD_CTRL_BIT;
629 __raw_writel(ctrl, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530630 bank->context.ctrl = ctrl;
Charulatha V058af1e2009-11-22 10:11:25 -0800631 }
Charulatha Vc8eef652011-05-02 15:21:42 +0530632
633 bank->mod_usage |= 1 << offset;
634
David Brownella6472532008-03-03 04:33:30 -0800635 spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100636
637 return 0;
638}
639
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800640static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100641{
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800642 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +0530643 void __iomem *base = bank->base;
David Brownella6472532008-03-03 04:33:30 -0800644 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100645
David Brownella6472532008-03-03 04:33:30 -0800646 spin_lock_irqsave(&bank->lock, flags);
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +0530647
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530648 if (bank->regs->wkup_en) {
Tony Lindgren92105bb2005-09-07 17:20:26 +0100649 /* Disable wake-up during idle for dynamic tick */
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +0530650 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530651 bank->context.wake_en =
652 __raw_readl(bank->base + bank->regs->wkup_en);
653 }
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +0530654
Charulatha Vc8eef652011-05-02 15:21:42 +0530655 bank->mod_usage &= ~(1 << offset);
Charulatha V9f096862010-05-14 12:05:27 -0700656
Charulatha Vc8eef652011-05-02 15:21:42 +0530657 if (bank->regs->ctrl && !bank->mod_usage) {
658 void __iomem *reg = bank->base + bank->regs->ctrl;
659 u32 ctrl;
660
661 ctrl = __raw_readl(reg);
662 /* Module is disabled, clocks are gated */
663 ctrl |= GPIO_MOD_CTRL_BIT;
664 __raw_writel(ctrl, reg);
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +0530665 bank->context.ctrl = ctrl;
Charulatha V058af1e2009-11-22 10:11:25 -0800666 }
Charulatha Vc8eef652011-05-02 15:21:42 +0530667
Jarkko Nikula3ff164e2008-12-10 17:35:27 -0800668 _reset_gpio(bank, bank->chip.base + offset);
David Brownella6472532008-03-03 04:33:30 -0800669 spin_unlock_irqrestore(&bank->lock, flags);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530670
671 /*
672 * If this is the last gpio to be freed in the bank,
673 * disable the bank module.
674 */
675 if (!bank->mod_usage)
676 pm_runtime_put(bank->dev);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100677}
678
679/*
680 * We need to unmask the GPIO bank interrupt as soon as possible to
681 * avoid missing GPIO interrupts for other lines in the bank.
682 * Then we need to mask-read-clear-unmask the triggered GPIO lines
683 * in the bank to avoid missing nested interrupts for a GPIO line.
684 * If we wait to unmask individual GPIO lines in the bank after the
685 * line's interrupt handler has been run, we may miss some nested
686 * interrupts.
687 */
Russell King10dd5ce2006-11-23 11:41:32 +0000688static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100689{
Tony Lindgren92105bb2005-09-07 17:20:26 +0100690 void __iomem *isr_reg = NULL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100691 u32 isr;
Jon Hunter3513cde2013-04-04 15:16:14 -0500692 unsigned int bit;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100693 struct gpio_bank *bank;
Imre Deakea6dedd2006-06-26 16:16:00 -0700694 int unmasked = 0;
Will Deaconee144182011-02-21 13:46:08 +0000695 struct irq_chip *chip = irq_desc_get_chip(desc);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100696
Will Deaconee144182011-02-21 13:46:08 +0000697 chained_irq_enter(chip, desc);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100698
Thomas Gleixner6845664a2011-03-24 13:25:22 +0100699 bank = irq_get_handler_data(irq);
Kevin Hilmaneef4bec2011-04-21 09:17:35 -0700700 isr_reg = bank->base + bank->regs->irqstatus;
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530701 pm_runtime_get_sync(bank->dev);
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800702
703 if (WARN_ON(!isr_reg))
704 goto exit;
705
Laurent Navete83507b2013-03-20 13:15:57 +0100706 while (1) {
Tony Lindgren6e60e792006-04-02 17:46:23 +0100707 u32 isr_saved, level_mask = 0;
Imre Deakea6dedd2006-06-26 16:16:00 -0700708 u32 enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100709
Imre Deakea6dedd2006-06-26 16:16:00 -0700710 enabled = _get_gpio_irqbank_mask(bank);
711 isr_saved = isr = __raw_readl(isr_reg) & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100712
Tarun Kanti DebBarma9ea14d82011-08-30 15:05:44 +0530713 if (bank->level_mask)
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800714 level_mask = bank->level_mask & enabled;
Tony Lindgren6e60e792006-04-02 17:46:23 +0100715
716 /* clear edge sensitive interrupts before handler(s) are
717 called so that we don't miss any interrupt occurred while
718 executing them */
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700719 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
Tony Lindgren6e60e792006-04-02 17:46:23 +0100720 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
Kevin Hilman28f3b5a2011-04-21 09:53:06 -0700721 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
Tony Lindgren6e60e792006-04-02 17:46:23 +0100722
723 /* if there is only edge sensitive GPIO pin interrupts
724 configured, we could unmask GPIO bank interrupt immediately */
Imre Deakea6dedd2006-06-26 16:16:00 -0700725 if (!level_mask && !unmasked) {
726 unmasked = 1;
Will Deaconee144182011-02-21 13:46:08 +0000727 chained_irq_exit(chip, desc);
Imre Deakea6dedd2006-06-26 16:16:00 -0700728 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100729
Tony Lindgren92105bb2005-09-07 17:20:26 +0100730 if (!isr)
731 break;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100732
Jon Hunter3513cde2013-04-04 15:16:14 -0500733 while (isr) {
734 bit = __ffs(isr);
735 isr &= ~(1 << bit);
Benoit Cousson25db7112012-02-23 21:50:10 +0100736
Cory Maccarrone4318f362010-01-08 10:29:04 -0800737 /*
738 * Some chips can't respond to both rising and falling
739 * at the same time. If this irq was requested with
740 * both flags, we need to flip the ICR data for the IRQ
741 * to respond to the IRQ for the opposite direction.
742 * This will be indicated in the bank toggle_mask.
743 */
Jon Hunter3513cde2013-04-04 15:16:14 -0500744 if (bank->toggle_mask & (1 << bit))
745 _toggle_gpio_edge_triggering(bank, bit);
Cory Maccarrone4318f362010-01-08 10:29:04 -0800746
Jon Hunter3513cde2013-04-04 15:16:14 -0500747 generic_handle_irq(irq_find_mapping(bank->domain, bit));
Tony Lindgren92105bb2005-09-07 17:20:26 +0100748 }
Tony Lindgren1a8bfa12005-11-10 14:26:50 +0000749 }
Imre Deakea6dedd2006-06-26 16:16:00 -0700750 /* if bank has any level sensitive GPIO pin interrupt
751 configured, we must unmask the bank interrupt only after
752 handler(s) are executed in order to avoid spurious bank
753 interrupt */
Evgeny Kuznetsovb1cc4c52010-12-07 16:25:40 -0800754exit:
Imre Deakea6dedd2006-06-26 16:16:00 -0700755 if (!unmasked)
Will Deaconee144182011-02-21 13:46:08 +0000756 chained_irq_exit(chip, desc);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +0530757 pm_runtime_put(bank->dev);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100758}
759
Lennert Buytenheke9191022010-11-29 11:17:17 +0100760static void gpio_irq_shutdown(struct irq_data *d)
Tony Lindgren4196dd62006-09-25 12:41:38 +0300761{
Lennert Buytenheke9191022010-11-29 11:17:17 +0100762 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Jon Hunterede4d7a2013-03-01 11:22:47 -0600763 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
Colin Cross85ec7b92011-06-06 13:38:18 -0700764 unsigned long flags;
Tony Lindgren4196dd62006-09-25 12:41:38 +0300765
Colin Cross85ec7b92011-06-06 13:38:18 -0700766 spin_lock_irqsave(&bank->lock, flags);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300767 _reset_gpio(bank, gpio);
Colin Cross85ec7b92011-06-06 13:38:18 -0700768 spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren4196dd62006-09-25 12:41:38 +0300769}
770
Lennert Buytenheke9191022010-11-29 11:17:17 +0100771static void gpio_ack_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100772{
Lennert Buytenheke9191022010-11-29 11:17:17 +0100773 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Jon Hunterede4d7a2013-03-01 11:22:47 -0600774 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100775
776 _clear_gpio_irqstatus(bank, gpio);
777}
778
Lennert Buytenheke9191022010-11-29 11:17:17 +0100779static void gpio_mask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100780{
Lennert Buytenheke9191022010-11-29 11:17:17 +0100781 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Jon Hunterede4d7a2013-03-01 11:22:47 -0600782 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
Colin Cross85ec7b92011-06-06 13:38:18 -0700783 unsigned long flags;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100784
Colin Cross85ec7b92011-06-06 13:38:18 -0700785 spin_lock_irqsave(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100786 _set_gpio_irqenable(bank, gpio, 0);
Kevin Hilman129fd222011-04-22 07:59:07 -0700787 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
Colin Cross85ec7b92011-06-06 13:38:18 -0700788 spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100789}
790
Lennert Buytenheke9191022010-11-29 11:17:17 +0100791static void gpio_unmask_irq(struct irq_data *d)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100792{
Lennert Buytenheke9191022010-11-29 11:17:17 +0100793 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
Jon Hunterede4d7a2013-03-01 11:22:47 -0600794 unsigned int gpio = irq_to_gpio(bank, d->hwirq);
Kevin Hilman129fd222011-04-22 07:59:07 -0700795 unsigned int irq_mask = GPIO_BIT(bank, gpio);
Thomas Gleixner8c04a172011-03-24 12:40:15 +0100796 u32 trigger = irqd_get_trigger_type(d);
Colin Cross85ec7b92011-06-06 13:38:18 -0700797 unsigned long flags;
Kevin Hilman55b60192009-06-04 15:57:10 -0700798
Colin Cross85ec7b92011-06-06 13:38:18 -0700799 spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman55b60192009-06-04 15:57:10 -0700800 if (trigger)
Kevin Hilman129fd222011-04-22 07:59:07 -0700801 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
Kevin Hilmanb144ff62008-01-16 21:56:15 -0800802
803 /* For level-triggered GPIOs, the clearing must be done after
804 * the HW source is cleared, thus after the handler has run */
805 if (bank->level_mask & irq_mask) {
806 _set_gpio_irqenable(bank, gpio, 0);
807 _clear_gpio_irqstatus(bank, gpio);
808 }
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100809
Kevin Hilman4de8c752008-01-16 21:56:14 -0800810 _set_gpio_irqenable(bank, gpio, 1);
Colin Cross85ec7b92011-06-06 13:38:18 -0700811 spin_unlock_irqrestore(&bank->lock, flags);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100812}
813
David Brownelle5c56ed2006-12-06 17:13:59 -0800814static struct irq_chip gpio_irq_chip = {
815 .name = "GPIO",
Lennert Buytenheke9191022010-11-29 11:17:17 +0100816 .irq_shutdown = gpio_irq_shutdown,
817 .irq_ack = gpio_ack_irq,
818 .irq_mask = gpio_mask_irq,
819 .irq_unmask = gpio_unmask_irq,
820 .irq_set_type = gpio_irq_type,
821 .irq_set_wake = gpio_wake_enable,
David Brownelle5c56ed2006-12-06 17:13:59 -0800822};
823
824/*---------------------------------------------------------------------*/
825
Magnus Damm79ee0312009-07-08 13:22:04 +0200826static int omap_mpuio_suspend_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800827{
Magnus Damm79ee0312009-07-08 13:22:04 +0200828 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800829 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800830 void __iomem *mask_reg = bank->base +
831 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800832 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800833
David Brownella6472532008-03-03 04:33:30 -0800834 spin_lock_irqsave(&bank->lock, flags);
Tarun Kanti DebBarma0aa27272012-04-27 19:43:33 +0530835 __raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
David Brownella6472532008-03-03 04:33:30 -0800836 spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800837
838 return 0;
839}
840
Magnus Damm79ee0312009-07-08 13:22:04 +0200841static int omap_mpuio_resume_noirq(struct device *dev)
David Brownell11a78b72006-12-06 17:14:11 -0800842{
Magnus Damm79ee0312009-07-08 13:22:04 +0200843 struct platform_device *pdev = to_platform_device(dev);
David Brownell11a78b72006-12-06 17:14:11 -0800844 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tony Lindgren5de62b82010-12-07 16:26:58 -0800845 void __iomem *mask_reg = bank->base +
846 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
David Brownella6472532008-03-03 04:33:30 -0800847 unsigned long flags;
David Brownell11a78b72006-12-06 17:14:11 -0800848
David Brownella6472532008-03-03 04:33:30 -0800849 spin_lock_irqsave(&bank->lock, flags);
Tarun Kanti DebBarma499fa282012-04-27 19:43:34 +0530850 __raw_writel(bank->context.wake_en, mask_reg);
David Brownella6472532008-03-03 04:33:30 -0800851 spin_unlock_irqrestore(&bank->lock, flags);
David Brownell11a78b72006-12-06 17:14:11 -0800852
853 return 0;
854}
855
Alexey Dobriyan47145212009-12-14 18:00:08 -0800856static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
Magnus Damm79ee0312009-07-08 13:22:04 +0200857 .suspend_noirq = omap_mpuio_suspend_noirq,
858 .resume_noirq = omap_mpuio_resume_noirq,
859};
860
Rafael J. Wysocki3c437ff2011-04-22 22:02:46 +0200861/* use platform_driver for this. */
David Brownell11a78b72006-12-06 17:14:11 -0800862static struct platform_driver omap_mpuio_driver = {
David Brownell11a78b72006-12-06 17:14:11 -0800863 .driver = {
864 .name = "mpuio",
Magnus Damm79ee0312009-07-08 13:22:04 +0200865 .pm = &omap_mpuio_dev_pm_ops,
David Brownell11a78b72006-12-06 17:14:11 -0800866 },
867};
868
869static struct platform_device omap_mpuio_device = {
870 .name = "mpuio",
871 .id = -1,
872 .dev = {
873 .driver = &omap_mpuio_driver.driver,
874 }
875 /* could list the /proc/iomem resources */
876};
877
Charulatha V03e128c2011-05-05 19:58:01 +0530878static inline void mpuio_init(struct gpio_bank *bank)
David Brownell11a78b72006-12-06 17:14:11 -0800879{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800880 platform_set_drvdata(&omap_mpuio_device, bank);
David Brownellfcf126d2007-04-02 12:46:47 -0700881
David Brownell11a78b72006-12-06 17:14:11 -0800882 if (platform_driver_register(&omap_mpuio_driver) == 0)
883 (void) platform_device_register(&omap_mpuio_device);
884}
885
David Brownelle5c56ed2006-12-06 17:13:59 -0800886/*---------------------------------------------------------------------*/
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +0100887
David Brownell52e31342008-03-03 12:43:23 -0800888static int gpio_input(struct gpio_chip *chip, unsigned offset)
889{
890 struct gpio_bank *bank;
891 unsigned long flags;
892
893 bank = container_of(chip, struct gpio_bank, chip);
894 spin_lock_irqsave(&bank->lock, flags);
895 _set_gpio_direction(bank, offset, 1);
896 spin_unlock_irqrestore(&bank->lock, flags);
897 return 0;
898}
899
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300900static int gpio_is_input(struct gpio_bank *bank, int mask)
901{
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700902 void __iomem *reg = bank->base + bank->regs->direction;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300903
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300904 return __raw_readl(reg) & mask;
905}
906
David Brownell52e31342008-03-03 12:43:23 -0800907static int gpio_get(struct gpio_chip *chip, unsigned offset)
908{
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300909 struct gpio_bank *bank;
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300910 u32 mask;
911
Charulatha Va8be8da2011-04-22 16:38:16 +0530912 bank = container_of(chip, struct gpio_bank, chip);
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530913 mask = (1 << offset);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300914
915 if (gpio_is_input(bank, mask))
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530916 return _get_gpio_datain(bank, offset);
Roger Quadrosb37c45b2009-08-05 16:53:24 +0300917 else
Tarun Kanti DebBarma7fcca712012-02-27 11:46:09 +0530918 return _get_gpio_dataout(bank, offset);
David Brownell52e31342008-03-03 12:43:23 -0800919}
920
921static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
922{
923 struct gpio_bank *bank;
924 unsigned long flags;
925
926 bank = container_of(chip, struct gpio_bank, chip);
927 spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700928 bank->set_dataout(bank, offset, value);
David Brownell52e31342008-03-03 12:43:23 -0800929 _set_gpio_direction(bank, offset, 0);
930 spin_unlock_irqrestore(&bank->lock, flags);
931 return 0;
932}
933
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700934static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
935 unsigned debounce)
936{
937 struct gpio_bank *bank;
938 unsigned long flags;
939
940 bank = container_of(chip, struct gpio_bank, chip);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -0800941
Felipe Balbi168ef3d2010-05-26 14:42:23 -0700942 spin_lock_irqsave(&bank->lock, flags);
943 _set_gpio_debounce(bank, offset, debounce);
944 spin_unlock_irqrestore(&bank->lock, flags);
945
946 return 0;
947}
948
David Brownell52e31342008-03-03 12:43:23 -0800949static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
950{
951 struct gpio_bank *bank;
952 unsigned long flags;
953
954 bank = container_of(chip, struct gpio_bank, chip);
955 spin_lock_irqsave(&bank->lock, flags);
Kevin Hilmanfa87931a2011-04-20 16:31:23 -0700956 bank->set_dataout(bank, offset, value);
David Brownell52e31342008-03-03 12:43:23 -0800957 spin_unlock_irqrestore(&bank->lock, flags);
958}
959
960/*---------------------------------------------------------------------*/
961
Tony Lindgren9a748052010-12-07 16:26:56 -0800962static void __init omap_gpio_show_rev(struct gpio_bank *bank)
Tony Lindgren9f7065d2009-10-19 15:25:20 -0700963{
Kevin Hilmane5ff4442011-04-22 14:37:16 -0700964 static bool called;
Tony Lindgren9f7065d2009-10-19 15:25:20 -0700965 u32 rev;
966
Kevin Hilmane5ff4442011-04-22 14:37:16 -0700967 if (called || bank->regs->revision == USHRT_MAX)
Tony Lindgren9f7065d2009-10-19 15:25:20 -0700968 return;
969
Kevin Hilmane5ff4442011-04-22 14:37:16 -0700970 rev = __raw_readw(bank->base + bank->regs->revision);
971 pr_info("OMAP GPIO hardware version %d.%d\n",
Tony Lindgren9f7065d2009-10-19 15:25:20 -0700972 (rev >> 4) & 0x0f, rev & 0x0f);
Kevin Hilmane5ff4442011-04-22 14:37:16 -0700973
974 called = true;
Tony Lindgren9f7065d2009-10-19 15:25:20 -0700975}
976
David Brownell8ba55c52008-02-26 11:10:50 -0800977/* This lock class tells lockdep that GPIO irqs are in a different
978 * category than their parents, so it won't report false recursion.
979 */
980static struct lock_class_key gpio_lock_class;
981
Charulatha V03e128c2011-05-05 19:58:01 +0530982static void omap_gpio_mod_init(struct gpio_bank *bank)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -0800983{
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530984 void __iomem *base = bank->base;
985 u32 l = 0xffffffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -0800986
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530987 if (bank->width == 16)
988 l = 0xffff;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -0800989
Charulatha Vd0d665a2011-08-31 00:02:21 +0530990 if (bank->is_mpuio) {
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530991 __raw_writel(l, bank->base + bank->regs->irqenable);
992 return;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -0800993 }
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530994
995 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
Tarun Kanti DebBarma6edd94d2012-04-30 12:50:12 +0530996 _gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530997 if (bank->regs->debounce_en)
Tarun Kanti DebBarma6edd94d2012-04-30 12:50:12 +0530998 __raw_writel(0, base + bank->regs->debounce_en);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +0530999
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301000 /* Save OE default value (0xffffffff) in the context */
1001 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301002 /* Initialize interface clk ungated, module enabled */
1003 if (bank->regs->ctrl)
Tarun Kanti DebBarma6edd94d2012-04-30 12:50:12 +05301004 __raw_writel(0, base + bank->regs->ctrl);
Tarun Kanti DebBarma34672012012-07-11 14:43:14 +05301005
1006 bank->dbck = clk_get(bank->dev, "dbclk");
1007 if (IS_ERR(bank->dbck))
1008 dev_err(bank->dev, "Could not get gpio dbck\n");
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001009}
1010
Bill Pemberton38363092012-11-19 13:22:34 -05001011static void
Kevin Hilmanf8b46b52011-04-21 13:23:34 -07001012omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
1013 unsigned int num)
1014{
1015 struct irq_chip_generic *gc;
1016 struct irq_chip_type *ct;
1017
1018 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
1019 handle_simple_irq);
Todd Poynor83233742011-07-18 07:43:14 -07001020 if (!gc) {
1021 dev_err(bank->dev, "Memory alloc failed for gc\n");
1022 return;
1023 }
1024
Kevin Hilmanf8b46b52011-04-21 13:23:34 -07001025 ct = gc->chip_types;
1026
1027 /* NOTE: No ack required, reading IRQ status clears it. */
1028 ct->chip.irq_mask = irq_gc_mask_set_bit;
1029 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1030 ct->chip.irq_set_type = gpio_irq_type;
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +05301031
1032 if (bank->regs->wkup_en)
Julia Lawall388f4302013-08-13 09:16:56 +02001033 ct->chip.irq_set_wake = gpio_wake_enable;
Kevin Hilmanf8b46b52011-04-21 13:23:34 -07001034
1035 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1036 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1037 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1038}
1039
Bill Pemberton38363092012-11-19 13:22:34 -05001040static void omap_gpio_chip_init(struct gpio_bank *bank)
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001041{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001042 int j;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001043 static int gpio;
1044
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001045 /*
1046 * REVISIT eventually switch from OMAP-specific gpio structs
1047 * over to the generic ones
1048 */
1049 bank->chip.request = omap_gpio_request;
1050 bank->chip.free = omap_gpio_free;
1051 bank->chip.direction_input = gpio_input;
1052 bank->chip.get = gpio_get;
1053 bank->chip.direction_output = gpio_output;
1054 bank->chip.set_debounce = gpio_debounce;
1055 bank->chip.set = gpio_set;
Jon Hunterede4d7a2013-03-01 11:22:47 -06001056 bank->chip.to_irq = omap_gpio_to_irq;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301057 if (bank->is_mpuio) {
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001058 bank->chip.label = "mpuio";
Tarun Kanti DebBarma6ed87c52011-09-13 14:41:44 +05301059 if (bank->regs->wkup_en)
1060 bank->chip.dev = &omap_mpuio_device.dev;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001061 bank->chip.base = OMAP_MPUIO(0);
1062 } else {
1063 bank->chip.label = "gpio";
1064 bank->chip.base = gpio;
Kevin Hilmand5f46242011-04-21 09:23:00 -07001065 gpio += bank->width;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001066 }
Kevin Hilmand5f46242011-04-21 09:23:00 -07001067 bank->chip.ngpio = bank->width;
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001068
1069 gpiochip_add(&bank->chip);
1070
Jon Hunterede4d7a2013-03-01 11:22:47 -06001071 for (j = 0; j < bank->width; j++) {
1072 int irq = irq_create_mapping(bank->domain, j);
1073 irq_set_lockdep_class(irq, &gpio_lock_class);
1074 irq_set_chip_data(irq, bank);
Charulatha Vd0d665a2011-08-31 00:02:21 +05301075 if (bank->is_mpuio) {
Jon Hunterede4d7a2013-03-01 11:22:47 -06001076 omap_mpuio_alloc_gc(bank, irq, bank->width);
Kevin Hilmanf8b46b52011-04-21 13:23:34 -07001077 } else {
Jon Hunterede4d7a2013-03-01 11:22:47 -06001078 irq_set_chip_and_handler(irq, &gpio_irq_chip,
1079 handle_simple_irq);
1080 set_irq_flags(irq, IRQF_VALID);
Kevin Hilmanf8b46b52011-04-21 13:23:34 -07001081 }
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001082 }
Thomas Gleixner6845664a2011-03-24 13:25:22 +01001083 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1084 irq_set_handler_data(bank->irq, bank);
Varadarajan, Charulatha2fae7fb2010-12-07 16:26:55 -08001085}
1086
Benoit Cousson384ebe12011-08-16 11:53:02 +02001087static const struct of_device_id omap_gpio_match[];
1088
Bill Pemberton38363092012-11-19 13:22:34 -05001089static int omap_gpio_probe(struct platform_device *pdev)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001090{
Benoit Cousson862ff642012-02-01 15:58:56 +01001091 struct device *dev = &pdev->dev;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001092 struct device_node *node = dev->of_node;
1093 const struct of_device_id *match;
Uwe Kleine-Königf6817a22012-05-21 21:57:39 +02001094 const struct omap_gpio_platform_data *pdata;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001095 struct resource *res;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001096 struct gpio_bank *bank;
Javier Martinez Canillas397eada2013-06-24 17:13:23 +02001097#ifdef CONFIG_ARCH_OMAP1
1098 int irq_base;
1099#endif
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001100
Benoit Cousson384ebe12011-08-16 11:53:02 +02001101 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1102
Jingoo Hane56aee12013-07-30 17:08:05 +09001103 pdata = match ? match->data : dev_get_platdata(dev);
Benoit Cousson384ebe12011-08-16 11:53:02 +02001104 if (!pdata)
Benoit Cousson96751fc2012-02-01 16:01:39 +01001105 return -EINVAL;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001106
Tobias Klauser086d5852012-10-05 11:37:38 +02001107 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);
Charulatha V03e128c2011-05-05 19:58:01 +05301108 if (!bank) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001109 dev_err(dev, "Memory alloc failed\n");
Benoit Cousson96751fc2012-02-01 16:01:39 +01001110 return -ENOMEM;
Charulatha V03e128c2011-05-05 19:58:01 +05301111 }
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001112
1113 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1114 if (unlikely(!res)) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001115 dev_err(dev, "Invalid IRQ resource\n");
Benoit Cousson96751fc2012-02-01 16:01:39 +01001116 return -ENODEV;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001117 }
1118
1119 bank->irq = res->start;
Benoit Cousson862ff642012-02-01 15:58:56 +01001120 bank->dev = dev;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001121 bank->dbck_flag = pdata->dbck_flag;
Tony Lindgren5de62b82010-12-07 16:26:58 -08001122 bank->stride = pdata->bank_stride;
Kevin Hilmand5f46242011-04-21 09:23:00 -07001123 bank->width = pdata->bank_width;
Charulatha Vd0d665a2011-08-31 00:02:21 +05301124 bank->is_mpuio = pdata->is_mpuio;
Charulatha V803a2432011-05-05 17:04:12 +05301125 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001126 bank->regs = pdata->regs;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001127#ifdef CONFIG_OF_GPIO
1128 bank->chip.of_node = of_node_get(node);
1129#endif
Jon Huntera2797be2013-04-04 15:16:15 -05001130 if (node) {
1131 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1132 bank->loses_context = true;
1133 } else {
1134 bank->loses_context = pdata->loses_context;
Jon Hunter352a2d52013-04-15 13:06:54 -05001135
1136 if (bank->loses_context)
1137 bank->get_context_loss_count =
1138 pdata->get_context_loss_count;
Benoit Cousson384ebe12011-08-16 11:53:02 +02001139 }
1140
Javier Martinez Canillas397eada2013-06-24 17:13:23 +02001141#ifdef CONFIG_ARCH_OMAP1
1142 /*
1143 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1144 * irq_alloc_descs() and irq_domain_add_legacy() and just use a
1145 * linear IRQ domain mapping for all OMAP platforms.
1146 */
1147 irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1148 if (irq_base < 0) {
1149 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1150 return -ENODEV;
1151 }
Benoit Cousson384ebe12011-08-16 11:53:02 +02001152
Javier Martinez Canillas397eada2013-06-24 17:13:23 +02001153 bank->domain = irq_domain_add_legacy(node, bank->width, irq_base,
1154 0, &irq_domain_simple_ops, NULL);
1155#else
Jon Hunterede4d7a2013-03-01 11:22:47 -06001156 bank->domain = irq_domain_add_linear(node, bank->width,
1157 &irq_domain_simple_ops, NULL);
Javier Martinez Canillas397eada2013-06-24 17:13:23 +02001158#endif
1159 if (!bank->domain) {
1160 dev_err(dev, "Couldn't register an IRQ domain\n");
Benoit Cousson384ebe12011-08-16 11:53:02 +02001161 return -ENODEV;
Javier Martinez Canillas397eada2013-06-24 17:13:23 +02001162 }
Kevin Hilmanfa87931a2011-04-20 16:31:23 -07001163
1164 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1165 bank->set_dataout = _set_gpio_dataout_reg;
1166 else
1167 bank->set_dataout = _set_gpio_dataout_mask;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001168
1169 spin_lock_init(&bank->lock);
1170
1171 /* Static mapping, never released */
1172 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1173 if (unlikely(!res)) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001174 dev_err(dev, "Invalid mem resource\n");
Jon Hunter879fe322013-04-04 15:16:12 -05001175 irq_domain_remove(bank->domain);
Benoit Cousson96751fc2012-02-01 16:01:39 +01001176 return -ENODEV;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001177 }
1178
Benoit Cousson96751fc2012-02-01 16:01:39 +01001179 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1180 pdev->name)) {
1181 dev_err(dev, "Region already claimed\n");
Jon Hunter879fe322013-04-04 15:16:12 -05001182 irq_domain_remove(bank->domain);
Benoit Cousson96751fc2012-02-01 16:01:39 +01001183 return -EBUSY;
1184 }
1185
1186 bank->base = devm_ioremap(dev, res->start, resource_size(res));
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001187 if (!bank->base) {
Benoit Cousson862ff642012-02-01 15:58:56 +01001188 dev_err(dev, "Could not ioremap\n");
Jon Hunter879fe322013-04-04 15:16:12 -05001189 irq_domain_remove(bank->domain);
Benoit Cousson96751fc2012-02-01 16:01:39 +01001190 return -ENOMEM;
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001191 }
1192
Tarun Kanti DebBarma065cd792011-11-24 01:48:52 +05301193 platform_set_drvdata(pdev, bank);
1194
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001195 pm_runtime_enable(bank->dev);
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301196 pm_runtime_irq_safe(bank->dev);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001197 pm_runtime_get_sync(bank->dev);
1198
Charulatha Vd0d665a2011-08-31 00:02:21 +05301199 if (bank->is_mpuio)
Tarun Kanti DebBarmaab985f02011-09-13 15:12:05 +05301200 mpuio_init(bank);
1201
Charulatha V03e128c2011-05-05 19:58:01 +05301202 omap_gpio_mod_init(bank);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001203 omap_gpio_chip_init(bank);
Tony Lindgren9a748052010-12-07 16:26:56 -08001204 omap_gpio_show_rev(bank);
Tony Lindgren9f7065d2009-10-19 15:25:20 -07001205
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301206 pm_runtime_put(bank->dev);
1207
Charulatha V03e128c2011-05-05 19:58:01 +05301208 list_add_tail(&bank->node, &omap_gpio_list);
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001209
Jon Hunter879fe322013-04-04 15:16:12 -05001210 return 0;
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001211}
1212
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301213#ifdef CONFIG_ARCH_OMAP2PLUS
1214
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301215#if defined(CONFIG_PM_RUNTIME)
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301216static void omap_gpio_restore_context(struct gpio_bank *bank);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001217
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301218static int omap_gpio_runtime_suspend(struct device *dev)
1219{
1220 struct platform_device *pdev = to_platform_device(dev);
1221 struct gpio_bank *bank = platform_get_drvdata(pdev);
1222 u32 l1 = 0, l2 = 0;
1223 unsigned long flags;
Kevin Hilman68942ed2012-03-05 15:10:04 -08001224 u32 wake_low, wake_hi;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301225
1226 spin_lock_irqsave(&bank->lock, flags);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001227
1228 /*
1229 * Only edges can generate a wakeup event to the PRCM.
1230 *
1231 * Therefore, ensure any wake-up capable GPIOs have
1232 * edge-detection enabled before going idle to ensure a wakeup
1233 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1234 * NDA TRM 25.5.3.1)
1235 *
1236 * The normal values will be restored upon ->runtime_resume()
1237 * by writing back the values saved in bank->context.
1238 */
1239 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1240 if (wake_low)
1241 __raw_writel(wake_low | bank->context.fallingdetect,
1242 bank->base + bank->regs->fallingdetect);
1243 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1244 if (wake_hi)
1245 __raw_writel(wake_hi | bank->context.risingdetect,
1246 bank->base + bank->regs->risingdetect);
1247
Kevin Hilmanb3c64bc2012-05-17 16:42:16 -07001248 if (!bank->enabled_non_wakeup_gpios)
1249 goto update_gpio_context_count;
1250
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301251 if (bank->power_mode != OFF_MODE) {
1252 bank->power_mode = 0;
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301253 goto update_gpio_context_count;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301254 }
1255 /*
1256 * If going to OFF, remove triggering for all
1257 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1258 * generated. See OMAP2420 Errata item 1.101.
1259 */
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301260 bank->saved_datain = __raw_readl(bank->base +
1261 bank->regs->datain);
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301262 l1 = bank->context.fallingdetect;
1263 l2 = bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301264
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301265 l1 &= ~bank->enabled_non_wakeup_gpios;
1266 l2 &= ~bank->enabled_non_wakeup_gpios;
1267
1268 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1269 __raw_writel(l2, bank->base + bank->regs->risingdetect);
1270
1271 bank->workaround_enabled = true;
1272
Tarun Kanti DebBarma41d87cb2011-11-15 12:52:38 +05301273update_gpio_context_count:
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301274 if (bank->get_context_loss_count)
1275 bank->context_loss_count =
1276 bank->get_context_loss_count(bank->dev);
1277
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +05301278 _gpio_dbck_disable(bank);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301279 spin_unlock_irqrestore(&bank->lock, flags);
1280
1281 return 0;
1282}
1283
Jon Hunter352a2d52013-04-15 13:06:54 -05001284static void omap_gpio_init_context(struct gpio_bank *p);
1285
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301286static int omap_gpio_runtime_resume(struct device *dev)
1287{
1288 struct platform_device *pdev = to_platform_device(dev);
1289 struct gpio_bank *bank = platform_get_drvdata(pdev);
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301290 u32 l = 0, gen, gen0, gen1;
1291 unsigned long flags;
Jon Huntera2797be2013-04-04 15:16:15 -05001292 int c;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301293
1294 spin_lock_irqsave(&bank->lock, flags);
Jon Hunter352a2d52013-04-15 13:06:54 -05001295
1296 /*
1297 * On the first resume during the probe, the context has not
1298 * been initialised and so initialise it now. Also initialise
1299 * the context loss count.
1300 */
1301 if (bank->loses_context && !bank->context_valid) {
1302 omap_gpio_init_context(bank);
1303
1304 if (bank->get_context_loss_count)
1305 bank->context_loss_count =
1306 bank->get_context_loss_count(bank->dev);
1307 }
1308
Tarun Kanti DebBarma72f83af92011-11-24 03:03:28 +05301309 _gpio_dbck_enable(bank);
Kevin Hilman68942ed2012-03-05 15:10:04 -08001310
1311 /*
1312 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1313 * GPIOs were set to edge trigger also in order to be able to
1314 * generate a PRCM wakeup. Here we restore the
1315 * pre-runtime_suspend() values for edge triggering.
1316 */
1317 __raw_writel(bank->context.fallingdetect,
1318 bank->base + bank->regs->fallingdetect);
1319 __raw_writel(bank->context.risingdetect,
1320 bank->base + bank->regs->risingdetect);
1321
Jon Huntera2797be2013-04-04 15:16:15 -05001322 if (bank->loses_context) {
1323 if (!bank->get_context_loss_count) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301324 omap_gpio_restore_context(bank);
1325 } else {
Jon Huntera2797be2013-04-04 15:16:15 -05001326 c = bank->get_context_loss_count(bank->dev);
1327 if (c != bank->context_loss_count) {
1328 omap_gpio_restore_context(bank);
1329 } else {
1330 spin_unlock_irqrestore(&bank->lock, flags);
1331 return 0;
1332 }
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301333 }
1334 }
1335
Tarun Kanti DebBarma1b1287032012-04-27 19:43:38 +05301336 if (!bank->workaround_enabled) {
1337 spin_unlock_irqrestore(&bank->lock, flags);
1338 return 0;
1339 }
1340
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301341 l = __raw_readl(bank->base + bank->regs->datain);
1342
1343 /*
1344 * Check if any of the non-wakeup interrupt GPIOs have changed
1345 * state. If so, generate an IRQ by software. This is
1346 * horribly racy, but it's the best we can do to work around
1347 * this silicon bug.
1348 */
1349 l ^= bank->saved_datain;
1350 l &= bank->enabled_non_wakeup_gpios;
1351
1352 /*
1353 * No need to generate IRQs for the rising edge for gpio IRQs
1354 * configured with falling edge only; and vice versa.
1355 */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301356 gen0 = l & bank->context.fallingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301357 gen0 &= bank->saved_datain;
1358
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301359 gen1 = l & bank->context.risingdetect;
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301360 gen1 &= ~(bank->saved_datain);
1361
1362 /* FIXME: Consider GPIO IRQs with level detections properly! */
Tarun Kanti DebBarmac6f31c92012-04-27 19:43:32 +05301363 gen = l & (~(bank->context.fallingdetect) &
1364 ~(bank->context.risingdetect));
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301365 /* Consider all GPIO IRQs needed to be updated */
1366 gen |= gen0 | gen1;
1367
1368 if (gen) {
1369 u32 old0, old1;
1370
1371 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1372 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1373
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301374 if (!bank->regs->irqstatus_raw0) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301375 __raw_writel(old0 | gen, bank->base +
1376 bank->regs->leveldetect0);
1377 __raw_writel(old1 | gen, bank->base +
1378 bank->regs->leveldetect1);
1379 }
1380
Tarun Kanti DebBarma4e962e82012-04-27 19:43:37 +05301381 if (bank->regs->irqstatus_raw0) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301382 __raw_writel(old0 | l, bank->base +
1383 bank->regs->leveldetect0);
1384 __raw_writel(old1 | l, bank->base +
1385 bank->regs->leveldetect1);
1386 }
1387 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1388 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1389 }
1390
1391 bank->workaround_enabled = false;
1392 spin_unlock_irqrestore(&bank->lock, flags);
1393
1394 return 0;
1395}
1396#endif /* CONFIG_PM_RUNTIME */
1397
1398void omap2_gpio_prepare_for_idle(int pwr_mode)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001399{
Charulatha V03e128c2011-05-05 19:58:01 +05301400 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001401
Charulatha V03e128c2011-05-05 19:58:01 +05301402 list_for_each_entry(bank, &omap_gpio_list, node) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301403 if (!bank->mod_usage || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301404 continue;
1405
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301406 bank->power_mode = pwr_mode;
1407
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301408 pm_runtime_put_sync_suspend(bank->dev);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001409 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001410}
1411
Kevin Hilman43ffcd92009-01-27 11:09:24 -08001412void omap2_gpio_resume_after_idle(void)
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001413{
Charulatha V03e128c2011-05-05 19:58:01 +05301414 struct gpio_bank *bank;
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001415
Charulatha V03e128c2011-05-05 19:58:01 +05301416 list_for_each_entry(bank, &omap_gpio_list, node) {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301417 if (!bank->mod_usage || !bank->loses_context)
Charulatha V03e128c2011-05-05 19:58:01 +05301418 continue;
1419
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301420 pm_runtime_get_sync(bank->dev);
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001421 }
Juha Yrjola3ac4fa92006-12-06 17:13:52 -08001422}
1423
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301424#if defined(CONFIG_PM_RUNTIME)
Jon Hunter352a2d52013-04-15 13:06:54 -05001425static void omap_gpio_init_context(struct gpio_bank *p)
1426{
1427 struct omap_gpio_reg_offs *regs = p->regs;
1428 void __iomem *base = p->base;
1429
1430 p->context.ctrl = __raw_readl(base + regs->ctrl);
1431 p->context.oe = __raw_readl(base + regs->direction);
1432 p->context.wake_en = __raw_readl(base + regs->wkup_en);
1433 p->context.leveldetect0 = __raw_readl(base + regs->leveldetect0);
1434 p->context.leveldetect1 = __raw_readl(base + regs->leveldetect1);
1435 p->context.risingdetect = __raw_readl(base + regs->risingdetect);
1436 p->context.fallingdetect = __raw_readl(base + regs->fallingdetect);
1437 p->context.irqenable1 = __raw_readl(base + regs->irqenable);
1438 p->context.irqenable2 = __raw_readl(base + regs->irqenable2);
1439
1440 if (regs->set_dataout && p->regs->clr_dataout)
1441 p->context.dataout = __raw_readl(base + regs->set_dataout);
1442 else
1443 p->context.dataout = __raw_readl(base + regs->dataout);
1444
1445 p->context_valid = true;
1446}
1447
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301448static void omap_gpio_restore_context(struct gpio_bank *bank)
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301449{
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301450 __raw_writel(bank->context.wake_en,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301451 bank->base + bank->regs->wkup_en);
1452 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301453 __raw_writel(bank->context.leveldetect0,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301454 bank->base + bank->regs->leveldetect0);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301455 __raw_writel(bank->context.leveldetect1,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301456 bank->base + bank->regs->leveldetect1);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301457 __raw_writel(bank->context.risingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301458 bank->base + bank->regs->risingdetect);
Tarun Kanti DebBarma60a34372011-09-29 04:47:25 +05301459 __raw_writel(bank->context.fallingdetect,
Tarun Kanti DebBarmaae10f232011-08-30 15:24:27 +05301460 bank->base + bank->regs->fallingdetect);
Nishanth Menonf86bcc32011-09-09 19:14:08 +05301461 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1462 __raw_writel(bank->context.dataout,
1463 bank->base + bank->regs->set_dataout);
1464 else
1465 __raw_writel(bank->context.dataout,
1466 bank->base + bank->regs->dataout);
Nishanth Menon6d13eaa2011-08-29 18:54:50 +05301467 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1468
Nishanth Menonae547352011-09-09 19:08:58 +05301469 if (bank->dbck_enable_mask) {
1470 __raw_writel(bank->context.debounce, bank->base +
1471 bank->regs->debounce);
1472 __raw_writel(bank->context.debounce_en,
1473 bank->base + bank->regs->debounce_en);
1474 }
Nishanth Menonba805be2011-08-29 18:41:08 +05301475
1476 __raw_writel(bank->context.irqenable1,
1477 bank->base + bank->regs->irqenable);
1478 __raw_writel(bank->context.irqenable2,
1479 bank->base + bank->regs->irqenable2);
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301480}
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301481#endif /* CONFIG_PM_RUNTIME */
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301482#else
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301483#define omap_gpio_runtime_suspend NULL
1484#define omap_gpio_runtime_resume NULL
Arnd Bergmannea4a21a2013-05-31 17:59:46 +02001485static inline void omap_gpio_init_context(struct gpio_bank *p) {}
Rajendra Nayak40c670f2008-09-26 17:47:48 +05301486#endif
1487
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301488static const struct dev_pm_ops gpio_pm_ops = {
Tarun Kanti DebBarma2dc983c2011-11-24 02:44:29 +05301489 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1490 NULL)
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301491};
1492
Benoit Cousson384ebe12011-08-16 11:53:02 +02001493#if defined(CONFIG_OF)
1494static struct omap_gpio_reg_offs omap2_gpio_regs = {
1495 .revision = OMAP24XX_GPIO_REVISION,
1496 .direction = OMAP24XX_GPIO_OE,
1497 .datain = OMAP24XX_GPIO_DATAIN,
1498 .dataout = OMAP24XX_GPIO_DATAOUT,
1499 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1500 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1501 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1502 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1503 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1504 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1505 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1506 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1507 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1508 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1509 .ctrl = OMAP24XX_GPIO_CTRL,
1510 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1511 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1512 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1513 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1514 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1515};
1516
1517static struct omap_gpio_reg_offs omap4_gpio_regs = {
1518 .revision = OMAP4_GPIO_REVISION,
1519 .direction = OMAP4_GPIO_OE,
1520 .datain = OMAP4_GPIO_DATAIN,
1521 .dataout = OMAP4_GPIO_DATAOUT,
1522 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1523 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1524 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1525 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1526 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1527 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1528 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1529 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1530 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1531 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1532 .ctrl = OMAP4_GPIO_CTRL,
1533 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1534 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1535 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1536 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1537 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1538};
1539
Chen Gange9a65bb2013-02-06 18:44:32 +08001540static const struct omap_gpio_platform_data omap2_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001541 .regs = &omap2_gpio_regs,
1542 .bank_width = 32,
1543 .dbck_flag = false,
1544};
1545
Chen Gange9a65bb2013-02-06 18:44:32 +08001546static const struct omap_gpio_platform_data omap3_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001547 .regs = &omap2_gpio_regs,
1548 .bank_width = 32,
1549 .dbck_flag = true,
1550};
1551
Chen Gange9a65bb2013-02-06 18:44:32 +08001552static const struct omap_gpio_platform_data omap4_pdata = {
Benoit Cousson384ebe12011-08-16 11:53:02 +02001553 .regs = &omap4_gpio_regs,
1554 .bank_width = 32,
1555 .dbck_flag = true,
1556};
1557
1558static const struct of_device_id omap_gpio_match[] = {
1559 {
1560 .compatible = "ti,omap4-gpio",
1561 .data = &omap4_pdata,
1562 },
1563 {
1564 .compatible = "ti,omap3-gpio",
1565 .data = &omap3_pdata,
1566 },
1567 {
1568 .compatible = "ti,omap2-gpio",
1569 .data = &omap2_pdata,
1570 },
1571 { },
1572};
1573MODULE_DEVICE_TABLE(of, omap_gpio_match);
1574#endif
1575
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001576static struct platform_driver omap_gpio_driver = {
1577 .probe = omap_gpio_probe,
1578 .driver = {
1579 .name = "omap_gpio",
Tarun Kanti DebBarma55b93c32011-09-29 07:23:22 +05301580 .pm = &gpio_pm_ops,
Benoit Cousson384ebe12011-08-16 11:53:02 +02001581 .of_match_table = of_match_ptr(omap_gpio_match),
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001582 },
1583};
1584
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001585/*
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001586 * gpio driver register needs to be done before
1587 * machine_init functions access gpio APIs.
1588 * Hence omap_gpio_drv_reg() is a postcore_initcall.
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001589 */
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001590static int __init omap_gpio_drv_reg(void)
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001591{
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001592 return platform_driver_register(&omap_gpio_driver);
Tony Lindgren5e1c5ff2005-07-10 19:58:15 +01001593}
Varadarajan, Charulatha77640aa2010-12-07 16:26:57 -08001594postcore_initcall(omap_gpio_drv_reg);