Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 1 | /* |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 2 | * Synopsys DesignWare I2C adapter driver (master only). |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 3 | * |
| 4 | * Based on the TI DAVINCI I2C adapter driver. |
| 5 | * |
| 6 | * Copyright (C) 2006 Texas Instruments. |
| 7 | * Copyright (C) 2007 MontaVista Software Inc. |
| 8 | * Copyright (C) 2009 Provigent Ltd. |
| 9 | * |
| 10 | * ---------------------------------------------------------------------------- |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or modify |
| 13 | * it under the terms of the GNU General Public License as published by |
| 14 | * the Free Software Foundation; either version 2 of the License, or |
| 15 | * (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 25 | * ---------------------------------------------------------------------------- |
| 26 | * |
| 27 | */ |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 28 | #include <linux/export.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 29 | #include <linux/clk.h> |
| 30 | #include <linux/errno.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 31 | #include <linux/err.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 32 | #include <linux/i2c.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 33 | #include <linux/interrupt.h> |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 34 | #include <linux/io.h> |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 36 | #include <linux/delay.h> |
Mika Westerberg | 9dd3162 | 2013-01-17 12:31:04 +0200 | [diff] [blame] | 37 | #include <linux/module.h> |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 38 | #include "i2c-designware-core.h" |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 39 | |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 40 | /* |
| 41 | * Registers offset |
| 42 | */ |
| 43 | #define DW_IC_CON 0x0 |
| 44 | #define DW_IC_TAR 0x4 |
| 45 | #define DW_IC_DATA_CMD 0x10 |
| 46 | #define DW_IC_SS_SCL_HCNT 0x14 |
| 47 | #define DW_IC_SS_SCL_LCNT 0x18 |
| 48 | #define DW_IC_FS_SCL_HCNT 0x1c |
| 49 | #define DW_IC_FS_SCL_LCNT 0x20 |
| 50 | #define DW_IC_INTR_STAT 0x2c |
| 51 | #define DW_IC_INTR_MASK 0x30 |
| 52 | #define DW_IC_RAW_INTR_STAT 0x34 |
| 53 | #define DW_IC_RX_TL 0x38 |
| 54 | #define DW_IC_TX_TL 0x3c |
| 55 | #define DW_IC_CLR_INTR 0x40 |
| 56 | #define DW_IC_CLR_RX_UNDER 0x44 |
| 57 | #define DW_IC_CLR_RX_OVER 0x48 |
| 58 | #define DW_IC_CLR_TX_OVER 0x4c |
| 59 | #define DW_IC_CLR_RD_REQ 0x50 |
| 60 | #define DW_IC_CLR_TX_ABRT 0x54 |
| 61 | #define DW_IC_CLR_RX_DONE 0x58 |
| 62 | #define DW_IC_CLR_ACTIVITY 0x5c |
| 63 | #define DW_IC_CLR_STOP_DET 0x60 |
| 64 | #define DW_IC_CLR_START_DET 0x64 |
| 65 | #define DW_IC_CLR_GEN_CALL 0x68 |
| 66 | #define DW_IC_ENABLE 0x6c |
| 67 | #define DW_IC_STATUS 0x70 |
| 68 | #define DW_IC_TXFLR 0x74 |
| 69 | #define DW_IC_RXFLR 0x78 |
| 70 | #define DW_IC_TX_ABRT_SOURCE 0x80 |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 71 | #define DW_IC_ENABLE_STATUS 0x9c |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 72 | #define DW_IC_COMP_PARAM_1 0xf4 |
| 73 | #define DW_IC_COMP_TYPE 0xfc |
| 74 | #define DW_IC_COMP_TYPE_VALUE 0x44570140 |
| 75 | |
| 76 | #define DW_IC_INTR_RX_UNDER 0x001 |
| 77 | #define DW_IC_INTR_RX_OVER 0x002 |
| 78 | #define DW_IC_INTR_RX_FULL 0x004 |
| 79 | #define DW_IC_INTR_TX_OVER 0x008 |
| 80 | #define DW_IC_INTR_TX_EMPTY 0x010 |
| 81 | #define DW_IC_INTR_RD_REQ 0x020 |
| 82 | #define DW_IC_INTR_TX_ABRT 0x040 |
| 83 | #define DW_IC_INTR_RX_DONE 0x080 |
| 84 | #define DW_IC_INTR_ACTIVITY 0x100 |
| 85 | #define DW_IC_INTR_STOP_DET 0x200 |
| 86 | #define DW_IC_INTR_START_DET 0x400 |
| 87 | #define DW_IC_INTR_GEN_CALL 0x800 |
| 88 | |
| 89 | #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ |
| 90 | DW_IC_INTR_TX_EMPTY | \ |
| 91 | DW_IC_INTR_TX_ABRT | \ |
| 92 | DW_IC_INTR_STOP_DET) |
| 93 | |
| 94 | #define DW_IC_STATUS_ACTIVITY 0x1 |
| 95 | |
| 96 | #define DW_IC_ERR_TX_ABRT 0x1 |
| 97 | |
| 98 | /* |
| 99 | * status codes |
| 100 | */ |
| 101 | #define STATUS_IDLE 0x0 |
| 102 | #define STATUS_WRITE_IN_PROGRESS 0x1 |
| 103 | #define STATUS_READ_IN_PROGRESS 0x2 |
| 104 | |
| 105 | #define TIMEOUT 20 /* ms */ |
| 106 | |
| 107 | /* |
| 108 | * hardware abort codes from the DW_IC_TX_ABRT_SOURCE register |
| 109 | * |
| 110 | * only expected abort codes are listed here |
| 111 | * refer to the datasheet for the full list |
| 112 | */ |
| 113 | #define ABRT_7B_ADDR_NOACK 0 |
| 114 | #define ABRT_10ADDR1_NOACK 1 |
| 115 | #define ABRT_10ADDR2_NOACK 2 |
| 116 | #define ABRT_TXDATA_NOACK 3 |
| 117 | #define ABRT_GCALL_NOACK 4 |
| 118 | #define ABRT_GCALL_READ 5 |
| 119 | #define ABRT_SBYTE_ACKDET 7 |
| 120 | #define ABRT_SBYTE_NORSTRT 9 |
| 121 | #define ABRT_10B_RD_NORSTRT 10 |
| 122 | #define ABRT_MASTER_DIS 11 |
| 123 | #define ARB_LOST 12 |
| 124 | |
| 125 | #define DW_IC_TX_ABRT_7B_ADDR_NOACK (1UL << ABRT_7B_ADDR_NOACK) |
| 126 | #define DW_IC_TX_ABRT_10ADDR1_NOACK (1UL << ABRT_10ADDR1_NOACK) |
| 127 | #define DW_IC_TX_ABRT_10ADDR2_NOACK (1UL << ABRT_10ADDR2_NOACK) |
| 128 | #define DW_IC_TX_ABRT_TXDATA_NOACK (1UL << ABRT_TXDATA_NOACK) |
| 129 | #define DW_IC_TX_ABRT_GCALL_NOACK (1UL << ABRT_GCALL_NOACK) |
| 130 | #define DW_IC_TX_ABRT_GCALL_READ (1UL << ABRT_GCALL_READ) |
| 131 | #define DW_IC_TX_ABRT_SBYTE_ACKDET (1UL << ABRT_SBYTE_ACKDET) |
| 132 | #define DW_IC_TX_ABRT_SBYTE_NORSTRT (1UL << ABRT_SBYTE_NORSTRT) |
| 133 | #define DW_IC_TX_ABRT_10B_RD_NORSTRT (1UL << ABRT_10B_RD_NORSTRT) |
| 134 | #define DW_IC_TX_ABRT_MASTER_DIS (1UL << ABRT_MASTER_DIS) |
| 135 | #define DW_IC_TX_ARB_LOST (1UL << ARB_LOST) |
| 136 | |
| 137 | #define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \ |
| 138 | DW_IC_TX_ABRT_10ADDR1_NOACK | \ |
| 139 | DW_IC_TX_ABRT_10ADDR2_NOACK | \ |
| 140 | DW_IC_TX_ABRT_TXDATA_NOACK | \ |
| 141 | DW_IC_TX_ABRT_GCALL_NOACK) |
| 142 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 143 | static char *abort_sources[] = { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 144 | [ABRT_7B_ADDR_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 145 | "slave address not acknowledged (7bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 146 | [ABRT_10ADDR1_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 147 | "first address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 148 | [ABRT_10ADDR2_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 149 | "second address byte not acknowledged (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 150 | [ABRT_TXDATA_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 151 | "data not acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 152 | [ABRT_GCALL_NOACK] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 153 | "no acknowledgement for a general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 154 | [ABRT_GCALL_READ] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 155 | "read after general call", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 156 | [ABRT_SBYTE_ACKDET] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 157 | "start byte acknowledged", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 158 | [ABRT_SBYTE_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 159 | "trying to send start byte when restart is disabled", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 160 | [ABRT_10B_RD_NORSTRT] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 161 | "trying to read when restart is disabled (10bit mode)", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 162 | [ABRT_MASTER_DIS] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 163 | "trying to use disabled adapter", |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 164 | [ARB_LOST] = |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 165 | "lost arbitration", |
| 166 | }; |
| 167 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 168 | u32 dw_readl(struct dw_i2c_dev *dev, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 169 | { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 170 | u32 value; |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 171 | |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 172 | if (dev->accessor_flags & ACCESS_16BIT) |
| 173 | value = readw(dev->base + offset) | |
| 174 | (readw(dev->base + offset + 2) << 16); |
| 175 | else |
| 176 | value = readl(dev->base + offset); |
| 177 | |
| 178 | if (dev->accessor_flags & ACCESS_SWAP) |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 179 | return swab32(value); |
| 180 | else |
| 181 | return value; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 182 | } |
| 183 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 184 | void dw_writel(struct dw_i2c_dev *dev, u32 b, int offset) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 185 | { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 186 | if (dev->accessor_flags & ACCESS_SWAP) |
Jean-Hugues Deschenes | 18c4089 | 2011-10-06 11:26:27 -0700 | [diff] [blame] | 187 | b = swab32(b); |
| 188 | |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 189 | if (dev->accessor_flags & ACCESS_16BIT) { |
| 190 | writew((u16)b, dev->base + offset); |
| 191 | writew((u16)(b >> 16), dev->base + offset + 2); |
| 192 | } else { |
| 193 | writel(b, dev->base + offset); |
| 194 | } |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 195 | } |
| 196 | |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 197 | static u32 |
| 198 | i2c_dw_scl_hcnt(u32 ic_clk, u32 tSYMBOL, u32 tf, int cond, int offset) |
| 199 | { |
| 200 | /* |
| 201 | * DesignWare I2C core doesn't seem to have solid strategy to meet |
| 202 | * the tHD;STA timing spec. Configuring _HCNT based on tHIGH spec |
| 203 | * will result in violation of the tHD;STA spec. |
| 204 | */ |
| 205 | if (cond) |
| 206 | /* |
| 207 | * Conditional expression: |
| 208 | * |
| 209 | * IC_[FS]S_SCL_HCNT + (1+4+3) >= IC_CLK * tHIGH |
| 210 | * |
| 211 | * This is based on the DW manuals, and represents an ideal |
| 212 | * configuration. The resulting I2C bus speed will be |
| 213 | * faster than any of the others. |
| 214 | * |
| 215 | * If your hardware is free from tHD;STA issue, try this one. |
| 216 | */ |
| 217 | return (ic_clk * tSYMBOL + 5000) / 10000 - 8 + offset; |
| 218 | else |
| 219 | /* |
| 220 | * Conditional expression: |
| 221 | * |
| 222 | * IC_[FS]S_SCL_HCNT + 3 >= IC_CLK * (tHD;STA + tf) |
| 223 | * |
| 224 | * This is just experimental rule; the tHD;STA period turned |
| 225 | * out to be proportinal to (_HCNT + 3). With this setting, |
| 226 | * we could meet both tHIGH and tHD;STA timing specs. |
| 227 | * |
| 228 | * If unsure, you'd better to take this alternative. |
| 229 | * |
| 230 | * The reason why we need to take into account "tf" here, |
| 231 | * is the same as described in i2c_dw_scl_lcnt(). |
| 232 | */ |
| 233 | return (ic_clk * (tSYMBOL + tf) + 5000) / 10000 - 3 + offset; |
| 234 | } |
| 235 | |
| 236 | static u32 i2c_dw_scl_lcnt(u32 ic_clk, u32 tLOW, u32 tf, int offset) |
| 237 | { |
| 238 | /* |
| 239 | * Conditional expression: |
| 240 | * |
| 241 | * IC_[FS]S_SCL_LCNT + 1 >= IC_CLK * (tLOW + tf) |
| 242 | * |
| 243 | * DW I2C core starts counting the SCL CNTs for the LOW period |
| 244 | * of the SCL clock (tLOW) as soon as it pulls the SCL line. |
| 245 | * In order to meet the tLOW timing spec, we need to take into |
| 246 | * account the fall time of SCL signal (tf). Default tf value |
| 247 | * should be 0.3 us, for safety. |
| 248 | */ |
| 249 | return ((ic_clk * (tLOW + tf) + 5000) / 10000) - 1 + offset; |
| 250 | } |
| 251 | |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 252 | static void __i2c_dw_enable(struct dw_i2c_dev *dev, bool enable) |
| 253 | { |
| 254 | int timeout = 100; |
| 255 | |
| 256 | do { |
| 257 | dw_writel(dev, enable, DW_IC_ENABLE); |
| 258 | if ((dw_readl(dev, DW_IC_ENABLE_STATUS) & 1) == enable) |
| 259 | return; |
| 260 | |
| 261 | /* |
| 262 | * Wait 10 times the signaling period of the highest I2C |
| 263 | * transfer supported by the driver (for 400KHz this is |
| 264 | * 25us) as described in the DesignWare I2C databook. |
| 265 | */ |
| 266 | usleep_range(25, 250); |
| 267 | } while (timeout--); |
| 268 | |
| 269 | dev_warn(dev->dev, "timeout in %sabling adapter\n", |
| 270 | enable ? "en" : "dis"); |
| 271 | } |
| 272 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 273 | /** |
| 274 | * i2c_dw_init() - initialize the designware i2c master hardware |
| 275 | * @dev: device private data |
| 276 | * |
| 277 | * This functions configures and enables the I2C master. |
| 278 | * This function is called during I2C init function, and in case of timeout at |
| 279 | * run time. |
| 280 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 281 | int i2c_dw_init(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 282 | { |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 283 | u32 input_clock_khz; |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 284 | u32 hcnt, lcnt; |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 285 | u32 reg; |
| 286 | |
Dirk Brandewie | 1d31b58 | 2011-10-06 11:26:30 -0700 | [diff] [blame] | 287 | input_clock_khz = dev->get_clk_rate_khz(dev); |
| 288 | |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 289 | reg = dw_readl(dev, DW_IC_COMP_TYPE); |
| 290 | if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) { |
Stefan Roese | a8a9f3f | 2012-04-18 15:01:41 +0200 | [diff] [blame] | 291 | /* Configure register endianess access */ |
| 292 | dev->accessor_flags |= ACCESS_SWAP; |
| 293 | } else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) { |
| 294 | /* Configure register access mode 16bit */ |
| 295 | dev->accessor_flags |= ACCESS_16BIT; |
| 296 | } else if (reg != DW_IC_COMP_TYPE_VALUE) { |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 297 | dev_err(dev->dev, "Unknown Synopsys component type: " |
| 298 | "0x%08x\n", reg); |
| 299 | return -ENODEV; |
| 300 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 301 | |
| 302 | /* Disable the adapter */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 303 | __i2c_dw_enable(dev, false); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 304 | |
| 305 | /* set standard and fast speed deviders for high/low periods */ |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 306 | |
| 307 | /* Standard-mode */ |
| 308 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 309 | 40, /* tHD;STA = tHIGH = 4.0 us */ |
| 310 | 3, /* tf = 0.3 us */ |
| 311 | 0, /* 0: DW default, 1: Ideal */ |
| 312 | 0); /* No offset */ |
| 313 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 314 | 47, /* tLOW = 4.7 us */ |
| 315 | 3, /* tf = 0.3 us */ |
| 316 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 317 | dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT); |
| 318 | dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 319 | dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
| 320 | |
| 321 | /* Fast-mode */ |
| 322 | hcnt = i2c_dw_scl_hcnt(input_clock_khz, |
| 323 | 6, /* tHD;STA = tHIGH = 0.6 us */ |
| 324 | 3, /* tf = 0.3 us */ |
| 325 | 0, /* 0: DW default, 1: Ideal */ |
| 326 | 0); /* No offset */ |
| 327 | lcnt = i2c_dw_scl_lcnt(input_clock_khz, |
| 328 | 13, /* tLOW = 1.3 us */ |
| 329 | 3, /* tf = 0.3 us */ |
| 330 | 0); /* No offset */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 331 | dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT); |
| 332 | dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT); |
Shinya Kuribayashi | d60c7e8 | 2009-11-06 21:47:01 +0900 | [diff] [blame] | 333 | dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 334 | |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 335 | /* Configure Tx/Rx FIFO threshold levels */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 336 | dw_writel(dev, dev->tx_fifo_depth - 1, DW_IC_TX_TL); |
| 337 | dw_writel(dev, 0, DW_IC_RX_TL); |
Shinya Kuribayashi | 4cb6d1d | 2009-11-06 21:48:12 +0900 | [diff] [blame] | 338 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 339 | /* configure the i2c master */ |
Dirk Brandewie | e18563f | 2011-10-06 11:26:32 -0700 | [diff] [blame] | 340 | dw_writel(dev, dev->master_cfg , DW_IC_CON); |
Dirk Brandewie | 4a423a8 | 2011-10-06 11:26:28 -0700 | [diff] [blame] | 341 | return 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 342 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 343 | EXPORT_SYMBOL_GPL(i2c_dw_init); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 344 | |
| 345 | /* |
| 346 | * Waiting for bus not busy |
| 347 | */ |
| 348 | static int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev) |
| 349 | { |
| 350 | int timeout = TIMEOUT; |
| 351 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 352 | while (dw_readl(dev, DW_IC_STATUS) & DW_IC_STATUS_ACTIVITY) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 353 | if (timeout <= 0) { |
| 354 | dev_warn(dev->dev, "timeout waiting for bus ready\n"); |
| 355 | return -ETIMEDOUT; |
| 356 | } |
| 357 | timeout--; |
Mika Westerberg | 1451b91 | 2013-04-10 00:36:41 +0000 | [diff] [blame] | 358 | usleep_range(1000, 1100); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 359 | } |
| 360 | |
| 361 | return 0; |
| 362 | } |
| 363 | |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 364 | static void i2c_dw_xfer_init(struct dw_i2c_dev *dev) |
| 365 | { |
| 366 | struct i2c_msg *msgs = dev->msgs; |
| 367 | u32 ic_con; |
| 368 | |
| 369 | /* Disable the adapter */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 370 | __i2c_dw_enable(dev, false); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 371 | |
| 372 | /* set the slave (target) address */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 373 | dw_writel(dev, msgs[dev->msg_write_idx].addr, DW_IC_TAR); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 374 | |
| 375 | /* if the slave address is ten bit address, enable 10BITADDR */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 376 | ic_con = dw_readl(dev, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 377 | if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) |
| 378 | ic_con |= DW_IC_CON_10BITADDR_MASTER; |
| 379 | else |
| 380 | ic_con &= ~DW_IC_CON_10BITADDR_MASTER; |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 381 | dw_writel(dev, ic_con, DW_IC_CON); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 382 | |
| 383 | /* Enable the adapter */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 384 | __i2c_dw_enable(dev, true); |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 385 | |
Mika Westerberg | 2a2d95e | 2013-05-13 00:54:30 +0000 | [diff] [blame] | 386 | /* Clear and enable interrupts */ |
| 387 | i2c_dw_clear_int(dev); |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 388 | dw_writel(dev, DW_IC_INTR_DEFAULT_MASK, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 389 | } |
| 390 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 391 | /* |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 392 | * Initiate (and continue) low level master read/write transaction. |
| 393 | * This function is only called from i2c_dw_isr, and pumping i2c_msg |
| 394 | * messages into the tx buffer. Even if the size of i2c_msg data is |
| 395 | * longer than the size of the tx buffer, it handles everything. |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 396 | */ |
Jean Delvare | bccd780 | 2012-10-05 22:23:53 +0200 | [diff] [blame] | 397 | static void |
Shinya Kuribayashi | e77cf23 | 2009-11-06 21:46:04 +0900 | [diff] [blame] | 398 | i2c_dw_xfer_msg(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 399 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 400 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 401 | u32 intr_mask; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 402 | int tx_limit, rx_limit; |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 403 | u32 addr = msgs[dev->msg_write_idx].addr; |
| 404 | u32 buf_len = dev->tx_buf_len; |
Justin P. Mattock | 6993248 | 2011-07-26 23:06:29 -0700 | [diff] [blame] | 405 | u8 *buf = dev->tx_buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 406 | |
Shinya Kuribayashi | 201d6a7 | 2009-11-06 21:50:40 +0900 | [diff] [blame] | 407 | intr_mask = DW_IC_INTR_DEFAULT_MASK; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 408 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 409 | for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { |
Shinya Kuribayashi | a0e06ea | 2009-11-06 21:52:22 +0900 | [diff] [blame] | 410 | /* |
| 411 | * if target address has changed, we need to |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 412 | * reprogram the target address in the i2c |
| 413 | * adapter when we are done with this transfer |
| 414 | */ |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 415 | if (msgs[dev->msg_write_idx].addr != addr) { |
| 416 | dev_err(dev->dev, |
| 417 | "%s: invalid target address\n", __func__); |
| 418 | dev->msg_err = -EINVAL; |
| 419 | break; |
| 420 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 421 | |
| 422 | if (msgs[dev->msg_write_idx].len == 0) { |
| 423 | dev_err(dev->dev, |
| 424 | "%s: invalid message length\n", __func__); |
| 425 | dev->msg_err = -EINVAL; |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 426 | break; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 427 | } |
| 428 | |
| 429 | if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { |
| 430 | /* new i2c_msg */ |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 431 | buf = msgs[dev->msg_write_idx].buf; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 432 | buf_len = msgs[dev->msg_write_idx].len; |
| 433 | } |
| 434 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 435 | tx_limit = dev->tx_fifo_depth - dw_readl(dev, DW_IC_TXFLR); |
| 436 | rx_limit = dev->rx_fifo_depth - dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 437 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 438 | while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) { |
Mika Westerberg | 17a76b4 | 2013-01-17 12:31:05 +0200 | [diff] [blame] | 439 | u32 cmd = 0; |
| 440 | |
| 441 | /* |
| 442 | * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must |
| 443 | * manually set the stop bit. However, it cannot be |
| 444 | * detected from the registers so we set it always |
| 445 | * when writing/reading the last byte. |
| 446 | */ |
| 447 | if (dev->msg_write_idx == dev->msgs_num - 1 && |
| 448 | buf_len == 1) |
| 449 | cmd |= BIT(9); |
| 450 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 451 | if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { |
Josef Ahmad | e6f34ce | 2013-04-19 17:28:10 +0100 | [diff] [blame] | 452 | |
| 453 | /* avoid rx buffer overrun */ |
| 454 | if (rx_limit - dev->rx_outstanding <= 0) |
| 455 | break; |
| 456 | |
Mika Westerberg | 17a76b4 | 2013-01-17 12:31:05 +0200 | [diff] [blame] | 457 | dw_writel(dev, cmd | 0x100, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 458 | rx_limit--; |
Josef Ahmad | e6f34ce | 2013-04-19 17:28:10 +0100 | [diff] [blame] | 459 | dev->rx_outstanding++; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 460 | } else |
Mika Westerberg | 17a76b4 | 2013-01-17 12:31:05 +0200 | [diff] [blame] | 461 | dw_writel(dev, cmd | *buf++, DW_IC_DATA_CMD); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 462 | tx_limit--; buf_len--; |
| 463 | } |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 464 | |
Shinya Kuribayashi | 26ea15b | 2009-11-06 21:49:14 +0900 | [diff] [blame] | 465 | dev->tx_buf = buf; |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 466 | dev->tx_buf_len = buf_len; |
| 467 | |
| 468 | if (buf_len > 0) { |
| 469 | /* more bytes to be written */ |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 470 | dev->status |= STATUS_WRITE_IN_PROGRESS; |
| 471 | break; |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 472 | } else |
Shinya Kuribayashi | c70c5cd | 2009-11-06 21:47:30 +0900 | [diff] [blame] | 473 | dev->status &= ~STATUS_WRITE_IN_PROGRESS; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 474 | } |
| 475 | |
Shinya Kuribayashi | 69151e5 | 2009-11-06 21:51:00 +0900 | [diff] [blame] | 476 | /* |
| 477 | * If i2c_msg index search is completed, we don't need TX_EMPTY |
| 478 | * interrupt any more. |
| 479 | */ |
| 480 | if (dev->msg_write_idx == dev->msgs_num) |
| 481 | intr_mask &= ~DW_IC_INTR_TX_EMPTY; |
| 482 | |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 483 | if (dev->msg_err) |
| 484 | intr_mask = 0; |
| 485 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 486 | dw_writel(dev, intr_mask, DW_IC_INTR_MASK); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | static void |
Shinya Kuribayashi | 78839bd | 2009-11-06 21:45:39 +0900 | [diff] [blame] | 490 | i2c_dw_read(struct dw_i2c_dev *dev) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 491 | { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 492 | struct i2c_msg *msgs = dev->msgs; |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 493 | int rx_valid; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 494 | |
Shinya Kuribayashi | 6d2ea48 | 2009-11-06 21:46:29 +0900 | [diff] [blame] | 495 | for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { |
Shinya Kuribayashi | ed5e1dd | 2009-11-06 21:43:52 +0900 | [diff] [blame] | 496 | u32 len; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 497 | u8 *buf; |
| 498 | |
| 499 | if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) |
| 500 | continue; |
| 501 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 502 | if (!(dev->status & STATUS_READ_IN_PROGRESS)) { |
| 503 | len = msgs[dev->msg_read_idx].len; |
| 504 | buf = msgs[dev->msg_read_idx].buf; |
| 505 | } else { |
| 506 | len = dev->rx_buf_len; |
| 507 | buf = dev->rx_buf; |
| 508 | } |
| 509 | |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 510 | rx_valid = dw_readl(dev, DW_IC_RXFLR); |
Shinya Kuribayashi | ae72222 | 2009-11-06 21:49:39 +0900 | [diff] [blame] | 511 | |
Josef Ahmad | e6f34ce | 2013-04-19 17:28:10 +0100 | [diff] [blame] | 512 | for (; len > 0 && rx_valid > 0; len--, rx_valid--) { |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 513 | *buf++ = dw_readl(dev, DW_IC_DATA_CMD); |
Josef Ahmad | e6f34ce | 2013-04-19 17:28:10 +0100 | [diff] [blame] | 514 | dev->rx_outstanding--; |
| 515 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 516 | |
| 517 | if (len > 0) { |
| 518 | dev->status |= STATUS_READ_IN_PROGRESS; |
| 519 | dev->rx_buf_len = len; |
| 520 | dev->rx_buf = buf; |
| 521 | return; |
| 522 | } else |
| 523 | dev->status &= ~STATUS_READ_IN_PROGRESS; |
| 524 | } |
| 525 | } |
| 526 | |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 527 | static int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev) |
| 528 | { |
| 529 | unsigned long abort_source = dev->abort_source; |
| 530 | int i; |
| 531 | |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 532 | if (abort_source & DW_IC_TX_ABRT_NOACK) { |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 533 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | 6d1ea0f | 2009-11-16 20:40:14 +0900 | [diff] [blame] | 534 | dev_dbg(dev->dev, |
| 535 | "%s: %s\n", __func__, abort_sources[i]); |
| 536 | return -EREMOTEIO; |
| 537 | } |
| 538 | |
Akinobu Mita | 984b3f5 | 2010-03-05 13:41:37 -0800 | [diff] [blame] | 539 | for_each_set_bit(i, &abort_source, ARRAY_SIZE(abort_sources)) |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 540 | dev_err(dev->dev, "%s: %s\n", __func__, abort_sources[i]); |
| 541 | |
| 542 | if (abort_source & DW_IC_TX_ARB_LOST) |
| 543 | return -EAGAIN; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 544 | else if (abort_source & DW_IC_TX_ABRT_GCALL_READ) |
| 545 | return -EINVAL; /* wrong msgs[] data */ |
| 546 | else |
| 547 | return -EIO; |
| 548 | } |
| 549 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 550 | /* |
| 551 | * Prepare controller for a transaction and call i2c_dw_xfer_msg |
| 552 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 553 | int |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 554 | i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) |
| 555 | { |
| 556 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 557 | int ret; |
| 558 | |
| 559 | dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); |
| 560 | |
| 561 | mutex_lock(&dev->lock); |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 562 | pm_runtime_get_sync(dev->dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 563 | |
| 564 | INIT_COMPLETION(dev->cmd_complete); |
| 565 | dev->msgs = msgs; |
| 566 | dev->msgs_num = num; |
| 567 | dev->cmd_err = 0; |
| 568 | dev->msg_write_idx = 0; |
| 569 | dev->msg_read_idx = 0; |
| 570 | dev->msg_err = 0; |
| 571 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 572 | dev->abort_source = 0; |
Josef Ahmad | e6f34ce | 2013-04-19 17:28:10 +0100 | [diff] [blame] | 573 | dev->rx_outstanding = 0; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 574 | |
| 575 | ret = i2c_dw_wait_bus_not_busy(dev); |
| 576 | if (ret < 0) |
| 577 | goto done; |
| 578 | |
| 579 | /* start the transfers */ |
Shinya Kuribayashi | 81e798b | 2009-11-06 21:48:55 +0900 | [diff] [blame] | 580 | i2c_dw_xfer_init(dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 581 | |
| 582 | /* wait for tx to complete */ |
| 583 | ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, HZ); |
| 584 | if (ret == 0) { |
| 585 | dev_err(dev->dev, "controller timed out\n"); |
| 586 | i2c_dw_init(dev); |
| 587 | ret = -ETIMEDOUT; |
| 588 | goto done; |
| 589 | } else if (ret < 0) |
| 590 | goto done; |
| 591 | |
| 592 | if (dev->msg_err) { |
| 593 | ret = dev->msg_err; |
| 594 | goto done; |
| 595 | } |
| 596 | |
| 597 | /* no error */ |
| 598 | if (likely(!dev->cmd_err)) { |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 599 | /* Disable the adapter */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 600 | __i2c_dw_enable(dev, false); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 601 | ret = num; |
| 602 | goto done; |
| 603 | } |
| 604 | |
| 605 | /* We have an error */ |
| 606 | if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { |
Shinya Kuribayashi | ce6eb57 | 2009-11-06 21:51:57 +0900 | [diff] [blame] | 607 | ret = i2c_dw_handle_tx_abort(dev); |
| 608 | goto done; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 609 | } |
| 610 | ret = -EIO; |
| 611 | |
| 612 | done: |
Mika Westerberg | 4345233 | 2013-04-10 00:36:42 +0000 | [diff] [blame] | 613 | pm_runtime_mark_last_busy(dev->dev); |
| 614 | pm_runtime_put_autosuspend(dev->dev); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 615 | mutex_unlock(&dev->lock); |
| 616 | |
| 617 | return ret; |
| 618 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 619 | EXPORT_SYMBOL_GPL(i2c_dw_xfer); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 620 | |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 621 | u32 i2c_dw_func(struct i2c_adapter *adap) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 622 | { |
Dirk Brandewie | 2fa8326 | 2011-10-06 11:26:31 -0700 | [diff] [blame] | 623 | struct dw_i2c_dev *dev = i2c_get_adapdata(adap); |
| 624 | return dev->functionality; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 625 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 626 | EXPORT_SYMBOL_GPL(i2c_dw_func); |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 627 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 628 | static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev) |
| 629 | { |
| 630 | u32 stat; |
| 631 | |
| 632 | /* |
| 633 | * The IC_INTR_STAT register just indicates "enabled" interrupts. |
| 634 | * Ths unmasked raw version of interrupt status bits are available |
| 635 | * in the IC_RAW_INTR_STAT register. |
| 636 | * |
| 637 | * That is, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 638 | * stat = dw_readl(IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 639 | * equals to, |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 640 | * stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 641 | * |
| 642 | * The raw version might be useful for debugging purposes. |
| 643 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 644 | stat = dw_readl(dev, DW_IC_INTR_STAT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 645 | |
| 646 | /* |
| 647 | * Do not use the IC_CLR_INTR register to clear interrupts, or |
| 648 | * you'll miss some interrupts, triggered during the period from |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 649 | * dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR). |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 650 | * |
| 651 | * Instead, use the separately-prepared IC_CLR_* registers. |
| 652 | */ |
| 653 | if (stat & DW_IC_INTR_RX_UNDER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 654 | dw_readl(dev, DW_IC_CLR_RX_UNDER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 655 | if (stat & DW_IC_INTR_RX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 656 | dw_readl(dev, DW_IC_CLR_RX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 657 | if (stat & DW_IC_INTR_TX_OVER) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 658 | dw_readl(dev, DW_IC_CLR_TX_OVER); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 659 | if (stat & DW_IC_INTR_RD_REQ) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 660 | dw_readl(dev, DW_IC_CLR_RD_REQ); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 661 | if (stat & DW_IC_INTR_TX_ABRT) { |
| 662 | /* |
| 663 | * The IC_TX_ABRT_SOURCE register is cleared whenever |
| 664 | * the IC_CLR_TX_ABRT is read. Preserve it beforehand. |
| 665 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 666 | dev->abort_source = dw_readl(dev, DW_IC_TX_ABRT_SOURCE); |
| 667 | dw_readl(dev, DW_IC_CLR_TX_ABRT); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 668 | } |
| 669 | if (stat & DW_IC_INTR_RX_DONE) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 670 | dw_readl(dev, DW_IC_CLR_RX_DONE); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 671 | if (stat & DW_IC_INTR_ACTIVITY) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 672 | dw_readl(dev, DW_IC_CLR_ACTIVITY); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 673 | if (stat & DW_IC_INTR_STOP_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 674 | dw_readl(dev, DW_IC_CLR_STOP_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 675 | if (stat & DW_IC_INTR_START_DET) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 676 | dw_readl(dev, DW_IC_CLR_START_DET); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 677 | if (stat & DW_IC_INTR_GEN_CALL) |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 678 | dw_readl(dev, DW_IC_CLR_GEN_CALL); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 679 | |
| 680 | return stat; |
| 681 | } |
| 682 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 683 | /* |
| 684 | * Interrupt service routine. This gets called whenever an I2C interrupt |
| 685 | * occurs. |
| 686 | */ |
Dirk Brandewie | 2373f6b | 2011-10-29 10:57:23 +0100 | [diff] [blame] | 687 | irqreturn_t i2c_dw_isr(int this_irq, void *dev_id) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 688 | { |
| 689 | struct dw_i2c_dev *dev = dev_id; |
Dirk Brandewie | af06cf6 | 2011-10-06 11:26:33 -0700 | [diff] [blame] | 690 | u32 stat, enabled; |
| 691 | |
| 692 | enabled = dw_readl(dev, DW_IC_ENABLE); |
| 693 | stat = dw_readl(dev, DW_IC_RAW_INTR_STAT); |
| 694 | dev_dbg(dev->dev, "%s: %s enabled= 0x%x stat=0x%x\n", __func__, |
| 695 | dev->adapter.name, enabled, stat); |
| 696 | if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY)) |
| 697 | return IRQ_NONE; |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 698 | |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 699 | stat = i2c_dw_read_clear_intrbits(dev); |
Shinya Kuribayashi | e28000a | 2009-11-06 21:44:37 +0900 | [diff] [blame] | 700 | |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 701 | if (stat & DW_IC_INTR_TX_ABRT) { |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 702 | dev->cmd_err |= DW_IC_ERR_TX_ABRT; |
| 703 | dev->status = STATUS_IDLE; |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 704 | |
| 705 | /* |
| 706 | * Anytime TX_ABRT is set, the contents of the tx/rx |
| 707 | * buffers are flushed. Make sure to skip them. |
| 708 | */ |
Jean-Hugues Deschenes | 7f27960 | 2011-10-06 11:26:25 -0700 | [diff] [blame] | 709 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 710 | goto tx_aborted; |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 711 | } |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 712 | |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 713 | if (stat & DW_IC_INTR_RX_FULL) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 714 | i2c_dw_read(dev); |
Shinya Kuribayashi | 21a89d4 | 2009-11-06 21:48:33 +0900 | [diff] [blame] | 715 | |
| 716 | if (stat & DW_IC_INTR_TX_EMPTY) |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 717 | i2c_dw_xfer_msg(dev); |
Shinya Kuribayashi | 0774539 | 2009-11-06 21:47:51 +0900 | [diff] [blame] | 718 | |
| 719 | /* |
| 720 | * No need to modify or disable the interrupt mask here. |
| 721 | * i2c_dw_xfer_msg() will take care of it according to |
| 722 | * the current transmit status. |
| 723 | */ |
| 724 | |
Shinya Kuribayashi | 597fe31 | 2009-11-06 21:51:36 +0900 | [diff] [blame] | 725 | tx_aborted: |
Shinya Kuribayashi | 8f588e4 | 2009-11-06 21:51:18 +0900 | [diff] [blame] | 726 | if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) |
Baruch Siach | 1ab52cf | 2009-06-22 16:36:29 +0300 | [diff] [blame] | 727 | complete(&dev->cmd_complete); |
| 728 | |
| 729 | return IRQ_HANDLED; |
| 730 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 731 | EXPORT_SYMBOL_GPL(i2c_dw_isr); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 732 | |
| 733 | void i2c_dw_enable(struct dw_i2c_dev *dev) |
| 734 | { |
| 735 | /* Enable the adapter */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 736 | __i2c_dw_enable(dev, true); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 737 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 738 | EXPORT_SYMBOL_GPL(i2c_dw_enable); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 739 | |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 740 | u32 i2c_dw_is_enabled(struct dw_i2c_dev *dev) |
| 741 | { |
| 742 | return dw_readl(dev, DW_IC_ENABLE); |
| 743 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 744 | EXPORT_SYMBOL_GPL(i2c_dw_is_enabled); |
Dirk Brandewie | 18dbdda | 2011-10-06 11:26:36 -0700 | [diff] [blame] | 745 | |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 746 | void i2c_dw_disable(struct dw_i2c_dev *dev) |
| 747 | { |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 748 | /* Disable controller */ |
Mika Westerberg | 3ca4ed8 | 2013-04-10 00:36:40 +0000 | [diff] [blame] | 749 | __i2c_dw_enable(dev, false); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 750 | |
| 751 | /* Disable all interupts */ |
| 752 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
| 753 | dw_readl(dev, DW_IC_CLR_INTR); |
| 754 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 755 | EXPORT_SYMBOL_GPL(i2c_dw_disable); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 756 | |
| 757 | void i2c_dw_clear_int(struct dw_i2c_dev *dev) |
| 758 | { |
| 759 | dw_readl(dev, DW_IC_CLR_INTR); |
| 760 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 761 | EXPORT_SYMBOL_GPL(i2c_dw_clear_int); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 762 | |
| 763 | void i2c_dw_disable_int(struct dw_i2c_dev *dev) |
| 764 | { |
| 765 | dw_writel(dev, 0, DW_IC_INTR_MASK); |
| 766 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 767 | EXPORT_SYMBOL_GPL(i2c_dw_disable_int); |
Dirk Brandewie | f3fa9f3 | 2011-10-06 11:26:34 -0700 | [diff] [blame] | 768 | |
| 769 | u32 i2c_dw_read_comp_param(struct dw_i2c_dev *dev) |
| 770 | { |
| 771 | return dw_readl(dev, DW_IC_COMP_PARAM_1); |
| 772 | } |
Axel Lin | e68bb91 | 2012-09-10 10:14:02 +0200 | [diff] [blame] | 773 | EXPORT_SYMBOL_GPL(i2c_dw_read_comp_param); |
Mika Westerberg | 9dd3162 | 2013-01-17 12:31:04 +0200 | [diff] [blame] | 774 | |
| 775 | MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter core"); |
| 776 | MODULE_LICENSE("GPL"); |