blob: c4871c55bd8b641544a86a281121cad4c9219e42 [file] [log] [blame]
Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2007-2009 Texas Instruments
Tony Lindgren646e3ed2008-10-06 15:49:36 +03008 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000012 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
Tony Lindgren1dbae812005-11-10 14:26:51 +000019#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010022#include <linux/io.h>
Paul Walmsley2f135ea2009-06-19 19:08:25 -060023#include <linux/clk.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000024
Tony Lindgren120db2c2006-04-02 17:46:27 +010025#include <asm/tlb.h>
Tony Lindgren120db2c2006-04-02 17:46:27 +010026#include <asm/mach/map.h>
27
Tony Lindgren45c3eb72012-11-30 08:41:50 -080028#include <linux/omap-dma.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030029
Tony Lindgrendc843282012-10-03 11:23:43 -070030#include "omap_hwmod.h"
Tony Lindgrendbc04162012-08-31 10:59:07 -070031#include "soc.h"
Tony Lindgrenee0839c2012-02-24 10:34:35 -080032#include "iomap.h"
33#include "voltage.h"
34#include "powerdomain.h"
35#include "clockdomain.h"
36#include "common.h"
Vaibhav Hiremathe30384a2012-05-29 15:26:41 +053037#include "clock.h"
Paul Walmsleye80a9722010-01-26 20:13:12 -070038#include "clock2xxx.h"
Paul Walmsley657ebfa2010-02-22 22:09:20 -070039#include "clock3xxx.h"
Paul Walmsleye80a9722010-01-26 20:13:12 -070040#include "clock44xx.h"
Tony Lindgren1d5aef42012-10-03 16:36:40 -070041#include "omap-pm.h"
Paul Walmsley3e6ece12012-10-17 00:46:45 +000042#include "sdrc.h"
Paul Walmsleyb6a42262012-10-29 20:50:21 -060043#include "control.h"
Tony Lindgren3d82cbb2012-10-15 12:50:46 -070044#include "serial.h"
Tony Lindgrenbf027ca2012-10-29 13:54:06 -070045#include "sram.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060046#include "cm2xxx.h"
47#include "cm3xxx.h"
Tero Kristo7632a022014-10-27 08:39:23 -070048#include "cm33xx.h"
Tero Kristoab6c9bb2014-10-27 08:39:25 -070049#include "cm44xx.h"
Paul Walmsleyd9a16f92012-10-29 20:57:39 -060050#include "prm.h"
51#include "cm.h"
52#include "prcm_mpu44xx.h"
53#include "prminst44xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070054#include "prm2xxx.h"
55#include "prm3xxx.h"
Tero Kristod9bbe842014-10-27 08:39:24 -070056#include "prm33xx.h"
Paul Walmsley63a293e2012-11-21 16:15:16 -070057#include "prm44xx.h"
Tero Kristo69a1e7a2014-02-24 18:51:05 +020058#include "opp2xxx.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000059
Tony Lindgren1dbae812005-11-10 14:26:51 +000060/*
Tero Kristocfa96672013-10-22 11:53:02 +030061 * omap_clk_soc_init: points to a function that does the SoC-specific
Rajendra Nayakff931c82013-03-21 16:34:52 +053062 * clock initializations
63 */
Tero Kristocfa96672013-10-22 11:53:02 +030064static int (*omap_clk_soc_init)(void);
Rajendra Nayakff931c82013-03-21 16:34:52 +053065
66/*
Tony Lindgren1dbae812005-11-10 14:26:51 +000067 * The machine specific code may provide the extra mapping besides the
68 * default mapping provided here.
69 */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030070
Tony Lindgrene48f8142012-03-06 11:49:22 -080071#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030072static struct map_desc omap24xx_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000073 {
74 .virtual = L3_24XX_VIRT,
75 .pfn = __phys_to_pfn(L3_24XX_PHYS),
76 .length = L3_24XX_SIZE,
77 .type = MT_DEVICE
78 },
Kyungmin Park09f21ed2008-02-20 15:30:06 -080079 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030080 .virtual = L4_24XX_VIRT,
81 .pfn = __phys_to_pfn(L4_24XX_PHYS),
82 .length = L4_24XX_SIZE,
Syed Mohammed Khasim72d0f1c2006-12-06 17:14:05 -080083 .type = MT_DEVICE
84 },
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030085};
86
Tony Lindgren59b479e2011-01-27 16:39:40 -080087#ifdef CONFIG_SOC_OMAP2420
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030088static struct map_desc omap242x_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000089 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070090 .virtual = DSP_MEM_2420_VIRT,
91 .pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
92 .length = DSP_MEM_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080093 .type = MT_DEVICE
94 },
95 {
Paul Walmsley7adb9982010-01-08 15:23:05 -070096 .virtual = DSP_IPI_2420_VIRT,
97 .pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
98 .length = DSP_IPI_2420_SIZE,
Tony Lindgrenc40fae952006-12-07 13:58:10 -080099 .type = MT_DEVICE
100 },
101 {
Paul Walmsley7adb9982010-01-08 15:23:05 -0700102 .virtual = DSP_MMU_2420_VIRT,
103 .pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
104 .length = DSP_MMU_2420_SIZE,
Tony Lindgren1dbae812005-11-10 14:26:51 +0000105 .type = MT_DEVICE
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300106 },
Tony Lindgren1dbae812005-11-10 14:26:51 +0000107};
108
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300109#endif
110
Tony Lindgren59b479e2011-01-27 16:39:40 -0800111#ifdef CONFIG_SOC_OMAP2430
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300112static struct map_desc omap243x_io_desc[] __initdata = {
113 {
114 .virtual = L4_WK_243X_VIRT,
115 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
116 .length = L4_WK_243X_SIZE,
117 .type = MT_DEVICE
118 },
119 {
120 .virtual = OMAP243X_GPMC_VIRT,
121 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
122 .length = OMAP243X_GPMC_SIZE,
123 .type = MT_DEVICE
124 },
125 {
126 .virtual = OMAP243X_SDRC_VIRT,
127 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
128 .length = OMAP243X_SDRC_SIZE,
129 .type = MT_DEVICE
130 },
131 {
132 .virtual = OMAP243X_SMS_VIRT,
133 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
134 .length = OMAP243X_SMS_SIZE,
135 .type = MT_DEVICE
136 },
137};
138#endif
139#endif
140
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800141#ifdef CONFIG_ARCH_OMAP3
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300142static struct map_desc omap34xx_io_desc[] __initdata = {
143 {
144 .virtual = L3_34XX_VIRT,
145 .pfn = __phys_to_pfn(L3_34XX_PHYS),
146 .length = L3_34XX_SIZE,
147 .type = MT_DEVICE
148 },
149 {
150 .virtual = L4_34XX_VIRT,
151 .pfn = __phys_to_pfn(L4_34XX_PHYS),
152 .length = L4_34XX_SIZE,
153 .type = MT_DEVICE
154 },
155 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300156 .virtual = OMAP34XX_GPMC_VIRT,
157 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
158 .length = OMAP34XX_GPMC_SIZE,
159 .type = MT_DEVICE
160 },
161 {
162 .virtual = OMAP343X_SMS_VIRT,
163 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
164 .length = OMAP343X_SMS_SIZE,
165 .type = MT_DEVICE
166 },
167 {
168 .virtual = OMAP343X_SDRC_VIRT,
169 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
170 .length = OMAP343X_SDRC_SIZE,
171 .type = MT_DEVICE
172 },
173 {
174 .virtual = L4_PER_34XX_VIRT,
175 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
176 .length = L4_PER_34XX_SIZE,
177 .type = MT_DEVICE
178 },
179 {
180 .virtual = L4_EMU_34XX_VIRT,
181 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
182 .length = L4_EMU_34XX_SIZE,
183 .type = MT_DEVICE
184 },
185};
186#endif
Hemant Pedanekar01001712011-02-16 08:31:39 -0800187
Kevin Hilman33959552012-05-10 11:10:07 -0700188#ifdef CONFIG_SOC_TI81XX
Hemant Pedanekara9203602011-12-13 10:46:44 -0800189static struct map_desc omapti81xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800190 {
191 .virtual = L4_34XX_VIRT,
192 .pfn = __phys_to_pfn(L4_34XX_PHYS),
193 .length = L4_34XX_SIZE,
194 .type = MT_DEVICE
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800195 }
196};
197#endif
198
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530199#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800200static struct map_desc omapam33xx_io_desc[] __initdata = {
Hemant Pedanekar01001712011-02-16 08:31:39 -0800201 {
202 .virtual = L4_34XX_VIRT,
203 .pfn = __phys_to_pfn(L4_34XX_PHYS),
204 .length = L4_34XX_SIZE,
205 .type = MT_DEVICE
206 },
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800207 {
208 .virtual = L4_WK_AM33XX_VIRT,
209 .pfn = __phys_to_pfn(L4_WK_AM33XX_PHYS),
210 .length = L4_WK_AM33XX_SIZE,
211 .type = MT_DEVICE
212 }
Hemant Pedanekar01001712011-02-16 08:31:39 -0800213};
214#endif
215
Santosh Shilimkar44169072009-05-28 14:16:04 -0700216#ifdef CONFIG_ARCH_OMAP4
217static struct map_desc omap44xx_io_desc[] __initdata = {
218 {
219 .virtual = L3_44XX_VIRT,
220 .pfn = __phys_to_pfn(L3_44XX_PHYS),
221 .length = L3_44XX_SIZE,
222 .type = MT_DEVICE,
223 },
224 {
225 .virtual = L4_44XX_VIRT,
226 .pfn = __phys_to_pfn(L4_44XX_PHYS),
227 .length = L4_44XX_SIZE,
228 .type = MT_DEVICE,
229 },
230 {
Santosh Shilimkar44169072009-05-28 14:16:04 -0700231 .virtual = L4_PER_44XX_VIRT,
232 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
233 .length = L4_PER_44XX_SIZE,
234 .type = MT_DEVICE,
235 },
Santosh Shilimkar44169072009-05-28 14:16:04 -0700236};
237#endif
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300238
R Sricharana3a93842013-07-03 11:52:04 +0530239#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
R Sricharan05e152c2012-06-05 16:21:32 +0530240static struct map_desc omap54xx_io_desc[] __initdata = {
241 {
242 .virtual = L3_54XX_VIRT,
243 .pfn = __phys_to_pfn(L3_54XX_PHYS),
244 .length = L3_54XX_SIZE,
245 .type = MT_DEVICE,
246 },
247 {
248 .virtual = L4_54XX_VIRT,
249 .pfn = __phys_to_pfn(L4_54XX_PHYS),
250 .length = L4_54XX_SIZE,
251 .type = MT_DEVICE,
252 },
253 {
254 .virtual = L4_WK_54XX_VIRT,
255 .pfn = __phys_to_pfn(L4_WK_54XX_PHYS),
256 .length = L4_WK_54XX_SIZE,
257 .type = MT_DEVICE,
258 },
259 {
260 .virtual = L4_PER_54XX_VIRT,
261 .pfn = __phys_to_pfn(L4_PER_54XX_PHYS),
262 .length = L4_PER_54XX_SIZE,
263 .type = MT_DEVICE,
264 },
265};
266#endif
267
Tony Lindgren59b479e2011-01-27 16:39:40 -0800268#ifdef CONFIG_SOC_OMAP2420
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600269void __init omap242x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800270{
271 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
272 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800273}
274#endif
275
Tony Lindgren59b479e2011-01-27 16:39:40 -0800276#ifdef CONFIG_SOC_OMAP2430
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600277void __init omap243x_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800278{
279 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
280 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800281}
282#endif
283
Tony Lindgrena8eb7ca2010-02-12 12:26:48 -0800284#ifdef CONFIG_ARCH_OMAP3
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600285void __init omap3_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800286{
287 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800288}
289#endif
290
Kevin Hilman33959552012-05-10 11:10:07 -0700291#ifdef CONFIG_SOC_TI81XX
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600292void __init ti81xx_map_io(void)
Hemant Pedanekar01001712011-02-16 08:31:39 -0800293{
Hemant Pedanekara9203602011-12-13 10:46:44 -0800294 iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
Hemant Pedanekar01001712011-02-16 08:31:39 -0800295}
296#endif
297
Afzal Mohammedaddb1542013-05-27 20:06:13 +0530298#if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_AM43XX)
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600299void __init am33xx_map_io(void)
Afzal Mohammed1e6cb142011-12-13 10:46:43 -0800300{
301 iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800302}
303#endif
304
305#ifdef CONFIG_ARCH_OMAP4
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600306void __init omap4_map_io(void)
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800307{
308 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
Santosh Shilimkar2ec1fc42012-02-02 19:33:55 +0530309 omap_barriers_init();
Tony Lindgren6fbd55d2010-02-12 12:26:47 -0800310}
311#endif
312
R Sricharana3a93842013-07-03 11:52:04 +0530313#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600314void __init omap5_map_io(void)
R Sricharan05e152c2012-06-05 16:21:32 +0530315{
316 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
Santosh Shilimkar1348bbf2013-02-15 18:05:49 +0530317 omap_barriers_init();
R Sricharan05e152c2012-06-05 16:21:32 +0530318}
319#endif
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600320/*
321 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
322 *
323 * Sets the CORE DPLL3 M2 divider to the same value that it's at
324 * currently. This has the effect of setting the SDRC SDRAM AC timing
325 * registers to the values currently defined by the kernel. Currently
326 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
327 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
328 * or passes along the return value of clk_set_rate().
329 */
330static int __init _omap2_init_reprogram_sdrc(void)
331{
332 struct clk *dpll3_m2_ck;
333 int v = -EINVAL;
334 long rate;
335
336 if (!cpu_is_omap34xx())
337 return 0;
338
339 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
Aaro Koskinene281f7e2010-11-30 14:17:58 +0000340 if (IS_ERR(dpll3_m2_ck))
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600341 return -EINVAL;
342
343 rate = clk_get_rate(dpll3_m2_ck);
344 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
345 v = clk_set_rate(dpll3_m2_ck, rate);
346 if (v)
347 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
348
349 clk_put(dpll3_m2_ck);
350
351 return v;
352}
353
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700354static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
355{
356 return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
357}
358
Tony Lindgren7b250af2011-10-04 18:26:28 -0700359static void __init omap_hwmod_init_postsetup(void)
Tony Lindgren120db2c2006-04-02 17:46:27 +0100360{
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700361 u8 postsetup_state;
362
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700363 /* Set the default postsetup state for all hwmods */
Rafael J. Wysockibf7c5442014-12-13 00:42:49 +0100364#ifdef CONFIG_PM
Paul Walmsley2092e5c2010-12-14 12:42:35 -0700365 postsetup_state = _HWMOD_STATE_IDLE;
366#else
367 postsetup_state = _HWMOD_STATE_ENABLED;
368#endif
369 omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
Benoit Cousson55d2cb02010-05-12 17:54:36 +0200370
Kevin Hilman53da4ce2010-12-09 09:13:48 -0600371 omap_pm_if_early_init();
Paul Walmsley48057342010-12-21 15:25:10 -0700372}
373
Arnd Bergmann069d0a72013-07-05 16:20:17 +0200374static void __init __maybe_unused omap_common_late_init(void)
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200375{
376 omap_mux_late_init();
377 omap2_common_pm_late_init();
Ruslan Bilovol6770b212013-02-14 13:55:24 +0200378 omap_soc_device_init();
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200379}
380
Paul Walmsley16110792012-01-25 12:57:46 -0700381#ifdef CONFIG_SOC_OMAP2420
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700382void __init omap2420_init_early(void)
383{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600384 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000));
385 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE),
386 OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE));
387 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE),
388 NULL);
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600389 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE));
390 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), NULL);
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530391 omap2xxx_check_revision();
Paul Walmsley63a293e2012-11-21 16:15:16 -0700392 omap2xxx_prm_init();
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600393 omap2xxx_cm_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700394 omap2xxx_voltagedomains_init();
395 omap242x_powerdomains_init();
396 omap242x_clockdomains_init();
397 omap2420_hwmod_init();
398 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200399 omap_clk_soc_init = omap2420_dt_clk_init;
400 rate_table = omap2420_rate_table;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700401}
Shawn Guobbd707a2012-04-26 16:06:50 +0800402
403void __init omap2420_init_late(void)
404{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200405 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800406 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530407 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800408}
Paul Walmsley16110792012-01-25 12:57:46 -0700409#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700410
Paul Walmsley16110792012-01-25 12:57:46 -0700411#ifdef CONFIG_SOC_OMAP2430
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700412void __init omap2430_init_early(void)
413{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600414 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000));
415 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE),
416 OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE));
417 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE),
418 NULL);
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600419 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE));
420 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), NULL);
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530421 omap2xxx_check_revision();
Paul Walmsley63a293e2012-11-21 16:15:16 -0700422 omap2xxx_prm_init();
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600423 omap2xxx_cm_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700424 omap2xxx_voltagedomains_init();
425 omap243x_powerdomains_init();
426 omap243x_clockdomains_init();
427 omap2430_hwmod_init();
428 omap_hwmod_init_postsetup();
Tero Kristo6a194a62014-03-04 10:53:54 +0200429 omap_clk_soc_init = omap2430_dt_clk_init;
430 rate_table = omap2430_rate_table;
Tony Lindgren7b250af2011-10-04 18:26:28 -0700431}
Shawn Guobbd707a2012-04-26 16:06:50 +0800432
433void __init omap2430_init_late(void)
434{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200435 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800436 omap2_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530437 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800438}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530439#endif
Tony Lindgren7b250af2011-10-04 18:26:28 -0700440
441/*
442 * Currently only board-omap3beagle.c should call this because of the
443 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
444 */
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530445#ifdef CONFIG_ARCH_OMAP3
Tony Lindgren7b250af2011-10-04 18:26:28 -0700446void __init omap3_init_early(void)
447{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600448 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000));
449 omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE),
450 OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE));
451 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE),
452 NULL);
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600453 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE));
454 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL);
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530455 omap3xxx_check_revision();
456 omap3xxx_check_features();
Paul Walmsley63a293e2012-11-21 16:15:16 -0700457 omap3xxx_prm_init();
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -0600458 omap3xxx_cm_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700459 omap3xxx_voltagedomains_init();
460 omap3xxx_powerdomains_init();
461 omap3xxx_clockdomains_init();
462 omap3xxx_hwmod_init();
463 omap_hwmod_init_postsetup();
Tero Kristoeded36f2014-12-16 18:20:55 +0200464 if (!of_have_populated_dt()) {
465 omap3_prcm_legacy_iomaps_init();
466 if (soc_is_am35xx())
467 omap_clk_soc_init = am35xx_clk_legacy_init;
468 else if (cpu_is_omap3630())
469 omap_clk_soc_init = omap36xx_clk_legacy_init;
470 else if (omap_rev() == OMAP3430_REV_ES1_0)
471 omap_clk_soc_init = omap3430es1_clk_legacy_init;
472 else
473 omap_clk_soc_init = omap3430_clk_legacy_init;
474 }
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700475}
476
477void __init omap3430_init_early(void)
478{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700479 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300480 if (of_have_populated_dt())
481 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700482}
483
484void __init omap35xx_init_early(void)
485{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700486 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300487 if (of_have_populated_dt())
488 omap_clk_soc_init = omap3430_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700489}
490
491void __init omap3630_init_early(void)
492{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700493 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300494 if (of_have_populated_dt())
495 omap_clk_soc_init = omap3630_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700496}
497
498void __init am35xx_init_early(void)
499{
Tony Lindgren7b250af2011-10-04 18:26:28 -0700500 omap3_init_early();
Tero Kristo3e049152013-08-02 14:32:30 +0300501 if (of_have_populated_dt())
502 omap_clk_soc_init = am35xx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700503}
504
Shawn Guobbd707a2012-04-26 16:06:50 +0800505void __init omap3_init_late(void)
506{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200507 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800508 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530509 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800510}
511
512void __init omap3430_init_late(void)
513{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200514 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800515 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530516 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800517}
518
519void __init omap35xx_init_late(void)
520{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200521 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800522 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530523 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800524}
525
526void __init omap3630_init_late(void)
527{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200528 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800529 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530530 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800531}
532
533void __init am35xx_init_late(void)
534{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200535 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800536 omap3_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530537 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800538}
539
540void __init ti81xx_init_late(void)
541{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200542 omap_common_late_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530543 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800544}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530545#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700546
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800547#ifdef CONFIG_SOC_TI81XX
548void __init ti814x_init_early(void)
549{
550 omap2_set_globals_tap(TI814X_CLASS,
551 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
552 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
553 NULL);
554 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
555 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
556 omap3xxx_check_revision();
557 ti81xx_check_features();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800558 am33xx_prm_init();
559 am33xx_cm_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800560 omap3xxx_voltagedomains_init();
561 omap3xxx_powerdomains_init();
562 ti81xx_clockdomains_init();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800563 ti81xx_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800564 omap_hwmod_init_postsetup();
565 if (of_have_populated_dt())
566 omap_clk_soc_init = ti81xx_dt_clk_init;
567}
568
569void __init ti816x_init_early(void)
570{
571 omap2_set_globals_tap(TI816X_CLASS,
572 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE));
573 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE),
574 NULL);
575 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE));
576 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(TI81XX_PRCM_BASE), NULL);
577 omap3xxx_check_revision();
578 ti81xx_check_features();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800579 am33xx_prm_init();
580 am33xx_cm_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800581 omap3xxx_voltagedomains_init();
582 omap3xxx_powerdomains_init();
583 ti81xx_clockdomains_init();
Tony Lindgren4d38bd12015-01-26 09:26:32 -0800584 ti81xx_hwmod_init();
Aida Mynzhasovaa64459c2015-01-26 09:26:32 -0800585 omap_hwmod_init_postsetup();
586 if (of_have_populated_dt())
587 omap_clk_soc_init = ti81xx_dt_clk_init;
588}
589#endif
590
Afzal Mohammed08f30982012-05-11 00:38:49 +0530591#ifdef CONFIG_SOC_AM33XX
592void __init am33xx_init_early(void)
593{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600594 omap2_set_globals_tap(AM335X_CLASS,
595 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
596 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
597 NULL);
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600598 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE));
599 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRCM_BASE), NULL);
Afzal Mohammed08f30982012-05-11 00:38:49 +0530600 omap3xxx_check_revision();
Vaibhav Hiremath7bcad172013-05-17 15:43:41 +0530601 am33xx_check_features();
Tero Kristod9bbe842014-10-27 08:39:24 -0700602 am33xx_prm_init();
Tero Kristo7632a022014-10-27 08:39:23 -0700603 am33xx_cm_init();
Vaibhav Hiremath3f0ea762012-06-18 00:47:27 -0600604 am33xx_powerdomains_init();
Vaibhav Hiremath9c80f3a2012-06-18 00:47:27 -0600605 am33xx_clockdomains_init();
Vaibhav Hirematha2cfc502012-07-25 13:51:13 -0600606 am33xx_hwmod_init();
607 omap_hwmod_init_postsetup();
Tero Kristo149c09d2013-07-19 11:37:17 +0300608 omap_clk_soc_init = am33xx_dt_clk_init;
Afzal Mohammed08f30982012-05-11 00:38:49 +0530609}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500610
611void __init am33xx_init_late(void)
612{
613 omap_common_late_init();
614}
Afzal Mohammed08f30982012-05-11 00:38:49 +0530615#endif
616
Afzal Mohammedc5107022013-05-27 20:06:23 +0530617#ifdef CONFIG_SOC_AM43XX
618void __init am43xx_init_early(void)
619{
620 omap2_set_globals_tap(AM335X_CLASS,
621 AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE));
622 omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE),
623 NULL);
624 omap2_set_globals_prm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE));
625 omap2_set_globals_cm(AM33XX_L4_WK_IO_ADDRESS(AM43XX_PRCM_BASE), NULL);
Ambresh K8835cf62013-10-12 15:46:37 +0530626 omap_prm_base_init();
627 omap_cm_base_init();
Afzal Mohammedc5107022013-05-27 20:06:23 +0530628 omap3xxx_check_revision();
Afzal Mohammed7a2e0512014-02-07 15:51:25 +0530629 am33xx_check_features();
Tero Kristo8843b112014-10-27 08:39:23 -0700630 omap44xx_prm_init();
Tero Kristo7632a022014-10-27 08:39:23 -0700631 omap4_cm_init();
Ambresh K8835cf62013-10-12 15:46:37 +0530632 am43xx_powerdomains_init();
633 am43xx_clockdomains_init();
634 am43xx_hwmod_init();
635 omap_hwmod_init_postsetup();
Sekhar Norid941f862014-04-22 13:58:03 +0530636 omap_l2_cache_init();
Tero Kristod22031e2013-11-21 16:49:59 +0200637 omap_clk_soc_init = am43xx_dt_clk_init;
Afzal Mohammedc5107022013-05-27 20:06:23 +0530638}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500639
640void __init am43xx_init_late(void)
641{
642 omap_common_late_init();
643}
Afzal Mohammedc5107022013-05-27 20:06:23 +0530644#endif
645
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530646#ifdef CONFIG_ARCH_OMAP4
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700647void __init omap4430_init_early(void)
648{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600649 omap2_set_globals_tap(OMAP443X_CLASS,
650 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE));
651 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE),
652 OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600653 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE));
654 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE),
655 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE));
656 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE));
657 omap_prm_base_init();
658 omap_cm_base_init();
Vaibhav Hiremath4de34f32011-12-19 15:50:15 +0530659 omap4xxx_check_revision();
660 omap4xxx_check_features();
Tero Kristo7632a022014-10-27 08:39:23 -0700661 omap4_cm_init();
Nishanth Menonde70af42014-01-20 14:06:37 -0600662 omap4_pm_init_early();
Paul Walmsley63a293e2012-11-21 16:15:16 -0700663 omap44xx_prm_init();
Tony Lindgren7b250af2011-10-04 18:26:28 -0700664 omap44xx_voltagedomains_init();
665 omap44xx_powerdomains_init();
666 omap44xx_clockdomains_init();
667 omap44xx_hwmod_init();
668 omap_hwmod_init_postsetup();
Sekhar Norib39b14e2014-04-22 13:58:01 +0530669 omap_l2_cache_init();
Tero Kristoc8c88d82013-07-18 16:04:00 +0300670 omap_clk_soc_init = omap4xxx_dt_clk_init;
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700671}
Shawn Guobbd707a2012-04-26 16:06:50 +0800672
673void __init omap4430_init_late(void)
674{
Ruslan Bilovol4ed12be2013-02-14 13:55:22 +0200675 omap_common_late_init();
Shawn Guobbd707a2012-04-26 16:06:50 +0800676 omap4_pm_init();
Rajendra Nayak23fb8ba2012-06-01 14:02:49 +0530677 omap2_clk_enable_autoidle_all();
Shawn Guobbd707a2012-04-26 16:06:50 +0800678}
Sanjeev Premic4e2d242011-10-13 21:44:10 +0530679#endif
Tony Lindgren8f5b5a42011-08-22 23:57:24 -0700680
R Sricharan05e152c2012-06-05 16:21:32 +0530681#ifdef CONFIG_SOC_OMAP5
682void __init omap5_init_early(void)
683{
Paul Walmsleyb6a42262012-10-29 20:50:21 -0600684 omap2_set_globals_tap(OMAP54XX_CLASS,
685 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE));
686 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
687 OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE));
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600688 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
689 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE),
690 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
691 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500692 omap4_pm_init_early();
Paul Walmsleyd9a16f92012-10-29 20:57:39 -0600693 omap_prm_base_init();
694 omap_cm_base_init();
Santosh Shilimkare4020aa2013-05-29 12:38:12 -0400695 omap44xx_prm_init();
R Sricharan05e152c2012-06-05 16:21:32 +0530696 omap5xxx_check_revision();
Tero Kristo7632a022014-10-27 08:39:23 -0700697 omap4_cm_init();
Santosh Shilimkare4020aa2013-05-29 12:38:12 -0400698 omap54xx_voltagedomains_init();
699 omap54xx_powerdomains_init();
700 omap54xx_clockdomains_init();
701 omap54xx_hwmod_init();
702 omap_hwmod_init_postsetup();
Tero Kristocfa96672013-10-22 11:53:02 +0300703 omap_clk_soc_init = omap5xxx_dt_clk_init;
R Sricharan05e152c2012-06-05 16:21:32 +0530704}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500705
706void __init omap5_init_late(void)
707{
708 omap_common_late_init();
Santosh Shilimkar628ed472014-05-20 16:19:23 -0500709 omap4_pm_init();
710 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500711}
R Sricharan05e152c2012-06-05 16:21:32 +0530712#endif
713
R Sricharana3a93842013-07-03 11:52:04 +0530714#ifdef CONFIG_SOC_DRA7XX
715void __init dra7xx_init_early(void)
716{
717 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
718 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
719 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
720 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
721 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
722 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
723 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500724 omap4_pm_init_early();
R Sricharana3a93842013-07-03 11:52:04 +0530725 omap_prm_base_init();
726 omap_cm_base_init();
Ambresh K7de516a2013-08-23 04:05:08 -0600727 omap44xx_prm_init();
Nishanth Menon733d20e2014-05-19 10:27:11 -0500728 dra7xxx_check_revision();
Tero Kristo7632a022014-10-27 08:39:23 -0700729 omap4_cm_init();
Ambresh K7de516a2013-08-23 04:05:08 -0600730 dra7xx_powerdomains_init();
731 dra7xx_clockdomains_init();
732 dra7xx_hwmod_init();
733 omap_hwmod_init_postsetup();
Tero Kristof1cf4982013-08-29 11:35:43 +0300734 omap_clk_soc_init = dra7xx_dt_clk_init;
R Sricharana3a93842013-07-03 11:52:04 +0530735}
Nishanth Menon765e7a02013-10-16 10:39:02 -0500736
737void __init dra7xx_init_late(void)
738{
739 omap_common_late_init();
Rajendra Nayak6af16a12014-08-22 09:02:34 -0500740 omap4_pm_init();
741 omap2_clk_enable_autoidle_all();
Nishanth Menon765e7a02013-10-16 10:39:02 -0500742}
R Sricharana3a93842013-07-03 11:52:04 +0530743#endif
744
745
Tony Lindgrena4ca9db2011-08-22 23:57:23 -0700746void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
Paul Walmsley48057342010-12-21 15:25:10 -0700747 struct omap_sdrc_params *sdrc_cs1)
748{
Tony Lindgrena66cb342011-10-04 13:52:57 -0700749 omap_sram_init();
750
Hemant Pedanekar01001712011-02-16 08:31:39 -0800751 if (cpu_is_omap24xx() || omap3_has_sdrc()) {
Kevin Hilmanaa4b1f62010-03-10 17:16:31 +0000752 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
753 _omap2_init_reprogram_sdrc();
754 }
Tony Lindgren1dbae812005-11-10 14:26:51 +0000755}
Tero Kristocfa96672013-10-22 11:53:02 +0300756
757int __init omap_clk_init(void)
758{
759 int ret = 0;
760
761 if (!omap_clk_soc_init)
762 return 0;
763
Tero Kristo8111e012014-07-02 11:47:39 +0300764 ti_clk_init_features();
765
Tero Kristoeded36f2014-12-16 18:20:55 +0200766 if (of_have_populated_dt()) {
767 ret = of_prcm_init();
768 if (ret)
769 return ret;
Tero Kristoc08ee142014-09-12 15:01:57 +0300770
Tero Kristoeded36f2014-12-16 18:20:55 +0200771 of_clk_init(NULL);
Tero Kristoc08ee142014-09-12 15:01:57 +0300772
Tero Kristoeded36f2014-12-16 18:20:55 +0200773 ti_dt_clk_init_retry_clks();
Tero Kristoc08ee142014-09-12 15:01:57 +0300774
Tero Kristoeded36f2014-12-16 18:20:55 +0200775 ti_dt_clockdomains_setup();
776 }
Tero Kristoc08ee142014-09-12 15:01:57 +0300777
778 ret = omap_clk_soc_init();
Tero Kristocfa96672013-10-22 11:53:02 +0300779
780 return ret;
781}