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Rohit Vaswani2aec37c2013-12-20 11:09:15 -08001/dts-v1/;
2
3#include "skeleton.dtsi"
4
Stephen Boyd3933d262014-01-16 17:25:03 -08005#include <dt-bindings/clock/qcom,gcc-msm8974.h>
6
Rohit Vaswani2aec37c2013-12-20 11:09:15 -08007/ {
8 model = "Qualcomm MSM8974";
9 compatible = "qcom,msm8974";
10 interrupt-parent = <&intc>;
11
Stephen Boyd3bff5472014-02-21 11:09:50 +000012 cpu-pmu {
13 compatible = "qcom,krait-pmu";
14 interrupts = <1 7 0xf04>;
15 };
16
Rohit Vaswani2aec37c2013-12-20 11:09:15 -080017 soc: soc {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21 compatible = "simple-bus";
22
23 intc: interrupt-controller@f9000000 {
24 compatible = "qcom,msm-qgic2";
25 interrupt-controller;
26 #interrupt-cells = <3>;
27 reg = <0xf9000000 0x1000>,
28 <0xf9002000 0x1000>;
29 };
30
31 timer {
32 compatible = "arm,armv7-timer";
33 interrupts = <1 2 0xf08>,
34 <1 3 0xf08>,
35 <1 4 0xf08>,
36 <1 1 0xf08>;
37 clock-frequency = <19200000>;
38 };
Stephen Boyd74e848f2013-12-20 11:09:18 -080039
Stephen Boyd47c5a5d2013-12-20 11:09:19 -080040 timer@f9020000 {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44 compatible = "arm,armv7-timer-mem";
45 reg = <0xf9020000 0x1000>;
46 clock-frequency = <19200000>;
47
48 frame@f9021000 {
49 frame-number = <0>;
50 interrupts = <0 8 0x4>,
51 <0 7 0x4>;
52 reg = <0xf9021000 0x1000>,
53 <0xf9022000 0x1000>;
54 };
55
56 frame@f9023000 {
57 frame-number = <1>;
58 interrupts = <0 9 0x4>;
59 reg = <0xf9023000 0x1000>;
60 status = "disabled";
61 };
62
63 frame@f9024000 {
64 frame-number = <2>;
65 interrupts = <0 10 0x4>;
66 reg = <0xf9024000 0x1000>;
67 status = "disabled";
68 };
69
70 frame@f9025000 {
71 frame-number = <3>;
72 interrupts = <0 11 0x4>;
73 reg = <0xf9025000 0x1000>;
74 status = "disabled";
75 };
76
77 frame@f9026000 {
78 frame-number = <4>;
79 interrupts = <0 12 0x4>;
80 reg = <0xf9026000 0x1000>;
81 status = "disabled";
82 };
83
84 frame@f9027000 {
85 frame-number = <5>;
86 interrupts = <0 13 0x4>;
87 reg = <0xf9027000 0x1000>;
88 status = "disabled";
89 };
90
91 frame@f9028000 {
92 frame-number = <6>;
93 interrupts = <0 14 0x4>;
94 reg = <0xf9028000 0x1000>;
95 status = "disabled";
96 };
97 };
98
Stephen Boyd74e848f2013-12-20 11:09:18 -080099 restart@fc4ab000 {
100 compatible = "qcom,pshold";
101 reg = <0xfc4ab000 0x4>;
102 };
Stephen Boyd3933d262014-01-16 17:25:03 -0800103
104 gcc: clock-controller@fc400000 {
105 compatible = "qcom,gcc-msm8974";
106 #clock-cells = <1>;
107 #reset-cells = <1>;
108 reg = <0xfc400000 0x4000>;
109 };
110
111 mmcc: clock-controller@fd8c0000 {
112 compatible = "qcom,mmcc-msm8974";
113 #clock-cells = <1>;
114 #reset-cells = <1>;
115 reg = <0xfd8c0000 0x6000>;
116 };
117
118 serial@f991e000 {
119 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
120 reg = <0xf991e000 0x1000>;
121 interrupts = <0 108 0x0>;
122 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
123 clock-names = "core", "iface";
124 };
Rohit Vaswani2aec37c2013-12-20 11:09:15 -0800125 };
126};