| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/at91_rstc.h |
| 3 | * |
| Andrew Victor | 3d73e89 | 2008-09-18 21:44:20 +0100 | [diff] [blame^] | 4 | * Copyright (C) 2007 Andrew Victor |
| 5 | * Copyright (C) 2007 Atmel Corporation. |
| 6 | * |
| Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 7 | * Reset Controller (RSTC) - System peripherals regsters. |
| 8 | * Based on AT91SAM9261 datasheet revision D. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91_RSTC_H |
| 17 | #define AT91_RSTC_H |
| 18 | |
| 19 | #define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */ |
| 20 | #define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */ |
| 21 | #define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */ |
| 22 | #define AT91_RSTC_EXTRST (1 << 3) /* External Reset */ |
| 23 | #define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */ |
| 24 | |
| 25 | #define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */ |
| 26 | #define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */ |
| 27 | #define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ |
| 28 | #define AT91_RSTC_RSTTYP_GENERAL (0 << 8) |
| 29 | #define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) |
| 30 | #define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) |
| 31 | #define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) |
| 32 | #define AT91_RSTC_RSTTYP_USER (4 << 8) |
| 33 | #define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */ |
| 34 | #define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */ |
| 35 | |
| 36 | #define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */ |
| 37 | #define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */ |
| 38 | #define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */ |
| 39 | #define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */ |
| 40 | |
| 41 | #endif |