blob: 89fef4712e9beb437b18ed8cc1b0d8e5509b71a6 [file] [log] [blame]
Alexander Shiyan161b96c2012-11-07 21:30:29 +04001/*
2 * CLPS711X SPI bus driver
3 *
Alexander Shiyan98984792014-01-10 17:02:05 +04004 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
Alexander Shiyan161b96c2012-11-07 21:30:29 +04005 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/io.h>
13#include <linux/clk.h>
14#include <linux/init.h>
15#include <linux/gpio.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/platform_device.h>
20#include <linux/spi/spi.h>
21#include <linux/platform_data/spi-clps711x.h>
22
23#include <mach/hardware.h>
24
25#define DRIVER_NAME "spi-clps711x"
26
27struct spi_clps711x_data {
28 struct completion done;
29
30 struct clk *spi_clk;
31 u32 max_speed_hz;
32
33 u8 *tx_buf;
34 u8 *rx_buf;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040035 unsigned int bpw;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040036 int len;
37
38 int chipselect[0];
39};
40
41static int spi_clps711x_setup(struct spi_device *spi)
42{
43 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
44
Alexander Shiyan161b96c2012-11-07 21:30:29 +040045 /* We are expect that SPI-device is not selected */
46 gpio_direction_output(hw->chipselect[spi->chip_select],
47 !(spi->mode & SPI_CS_HIGH));
48
49 return 0;
50}
51
52static void spi_clps711x_setup_mode(struct spi_device *spi)
53{
54 /* Setup edge for transfer */
55 if (spi->mode & SPI_CPHA)
56 clps_writew(clps_readw(SYSCON3) | SYSCON3_ADCCKNSEN, SYSCON3);
57 else
58 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCKNSEN, SYSCON3);
59}
60
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040061static void spi_clps711x_setup_xfer(struct spi_device *spi,
62 struct spi_transfer *xfer)
Alexander Shiyan161b96c2012-11-07 21:30:29 +040063{
64 u32 speed = xfer->speed_hz ? : spi->max_speed_hz;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040065 struct spi_clps711x_data *hw = spi_master_get_devdata(spi->master);
66
Alexander Shiyan161b96c2012-11-07 21:30:29 +040067 /* Setup SPI frequency divider */
68 if (!speed || (speed >= hw->max_speed_hz))
69 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
70 SYSCON1_ADCKSEL(3), SYSCON1);
71 else if (speed >= (hw->max_speed_hz / 2))
72 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
73 SYSCON1_ADCKSEL(2), SYSCON1);
74 else if (speed >= (hw->max_speed_hz / 8))
75 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
76 SYSCON1_ADCKSEL(1), SYSCON1);
77 else
78 clps_writel((clps_readl(SYSCON1) & ~SYSCON1_ADCKSEL_MASK) |
79 SYSCON1_ADCKSEL(0), SYSCON1);
Alexander Shiyan161b96c2012-11-07 21:30:29 +040080}
81
82static int spi_clps711x_transfer_one_message(struct spi_master *master,
83 struct spi_message *msg)
84{
85 struct spi_clps711x_data *hw = spi_master_get_devdata(master);
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040086 struct spi_device *spi = msg->spi;
Alexander Shiyan161b96c2012-11-07 21:30:29 +040087 struct spi_transfer *xfer;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040088 int cs = hw->chipselect[spi->chip_select];
Alexander Shiyan161b96c2012-11-07 21:30:29 +040089
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040090 spi_clps711x_setup_mode(spi);
Alexander Shiyan161b96c2012-11-07 21:30:29 +040091
92 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
Alexander Shiyanc7a26f12014-02-02 10:59:48 +040093 u8 data;
94
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040095 spi_clps711x_setup_xfer(spi, xfer);
Alexander Shiyan161b96c2012-11-07 21:30:29 +040096
Alexander Shiyan8dda9d92014-02-02 10:59:49 +040097 gpio_set_value(cs, !!(spi->mode & SPI_CS_HIGH));
Alexander Shiyan161b96c2012-11-07 21:30:29 +040098
Wolfram Sang16735d02013-11-14 14:32:02 -080099 reinit_completion(&hw->done);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400100
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400101 hw->len = xfer->len;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400102 hw->bpw = xfer->bits_per_word ? : spi->bits_per_word;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400103 hw->tx_buf = (u8 *)xfer->tx_buf;
104 hw->rx_buf = (u8 *)xfer->rx_buf;
105
106 /* Initiate transfer */
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400107 data = hw->tx_buf ? *hw->tx_buf++ : 0;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400108 clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
109 SYNCIO);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400110
111 wait_for_completion(&hw->done);
112
113 if (xfer->delay_usecs)
114 udelay(xfer->delay_usecs);
115
116 if (xfer->cs_change ||
117 list_is_last(&xfer->transfer_list, &msg->transfers))
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400118 gpio_set_value(cs, !(spi->mode & SPI_CS_HIGH));
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400119
120 msg->actual_length += xfer->len;
121 }
122
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400123 msg->status = 0;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400124 spi_finalize_current_message(master);
125
126 return 0;
127}
128
129static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
130{
131 struct spi_clps711x_data *hw = (struct spi_clps711x_data *)dev_id;
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400132 u8 data;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400133
134 /* Handle RX */
135 data = clps_readb(SYNCIO);
136 if (hw->rx_buf)
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400137 *hw->rx_buf++ = data;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400138
139 /* Handle TX */
Alexander Shiyanc7a26f12014-02-02 10:59:48 +0400140 if (--hw->len > 0) {
141 data = hw->tx_buf ? *hw->tx_buf++ : 0;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400142 clps_writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
143 SYNCIO);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400144 } else
145 complete(&hw->done);
146
147 return IRQ_HANDLED;
148}
149
Grant Likelyfd4a3192012-12-07 16:57:14 +0000150static int spi_clps711x_probe(struct platform_device *pdev)
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400151{
152 int i, ret;
153 struct spi_master *master;
154 struct spi_clps711x_data *hw;
155 struct spi_clps711x_pdata *pdata = dev_get_platdata(&pdev->dev);
156
157 if (!pdata) {
158 dev_err(&pdev->dev, "No platform data supplied\n");
159 return -EINVAL;
160 }
161
162 if (pdata->num_chipselect < 1) {
163 dev_err(&pdev->dev, "At least one CS must be defined\n");
164 return -EINVAL;
165 }
166
167 master = spi_alloc_master(&pdev->dev,
168 sizeof(struct spi_clps711x_data) +
169 sizeof(int) * pdata->num_chipselect);
170 if (!master) {
171 dev_err(&pdev->dev, "SPI allocating memory error\n");
172 return -ENOMEM;
173 }
174
175 master->bus_num = pdev->id;
176 master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
Alexander Shiyan8dda9d92014-02-02 10:59:49 +0400177 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400178 master->num_chipselect = pdata->num_chipselect;
179 master->setup = spi_clps711x_setup;
180 master->transfer_one_message = spi_clps711x_transfer_one_message;
181
182 hw = spi_master_get_devdata(master);
183
184 for (i = 0; i < master->num_chipselect; i++) {
185 hw->chipselect[i] = pdata->chipselect[i];
186 if (!gpio_is_valid(hw->chipselect[i])) {
187 dev_err(&pdev->dev, "Invalid CS GPIO %i\n", i);
188 ret = -EINVAL;
189 goto err_out;
190 }
Alexander Shiyan98984792014-01-10 17:02:05 +0400191 if (devm_gpio_request(&pdev->dev, hw->chipselect[i], NULL)) {
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400192 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i);
193 ret = -EINVAL;
194 goto err_out;
195 }
196 }
197
198 hw->spi_clk = devm_clk_get(&pdev->dev, "spi");
199 if (IS_ERR(hw->spi_clk)) {
200 dev_err(&pdev->dev, "Can't get clocks\n");
201 ret = PTR_ERR(hw->spi_clk);
202 goto err_out;
203 }
204 hw->max_speed_hz = clk_get_rate(hw->spi_clk);
205
206 init_completion(&hw->done);
207 platform_set_drvdata(pdev, master);
208
209 /* Disable extended mode due hardware problems */
210 clps_writew(clps_readw(SYSCON3) & ~SYSCON3_ADCCON, SYSCON3);
211
212 /* Clear possible pending interrupt */
213 clps_readl(SYNCIO);
214
215 ret = devm_request_irq(&pdev->dev, IRQ_SSEOTI, spi_clps711x_isr, 0,
216 dev_name(&pdev->dev), hw);
217 if (ret) {
218 dev_err(&pdev->dev, "Can't request IRQ\n");
Sachin Kamatc7083792013-09-27 15:32:53 +0530219 goto err_out;
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400220 }
221
Jingoo Hanc493fc42013-09-24 13:27:48 +0900222 ret = devm_spi_register_master(&pdev->dev, master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400223 if (!ret) {
224 dev_info(&pdev->dev,
225 "SPI bus driver initialized. Master clock %u Hz\n",
226 hw->max_speed_hz);
227 return 0;
228 }
229
230 dev_err(&pdev->dev, "Failed to register master\n");
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400231
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400232err_out:
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400233 spi_master_put(master);
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400234
235 return ret;
236}
237
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400238static struct platform_driver clps711x_spi_driver = {
239 .driver = {
240 .name = DRIVER_NAME,
241 .owner = THIS_MODULE,
242 },
243 .probe = spi_clps711x_probe,
Alexander Shiyan161b96c2012-11-07 21:30:29 +0400244};
245module_platform_driver(clps711x_spi_driver);
246
247MODULE_LICENSE("GPL");
248MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
249MODULE_DESCRIPTION("CLPS711X SPI bus driver");
Axel Lin350a9b32014-01-14 17:01:54 +0800250MODULE_ALIAS("platform:" DRIVER_NAME);