blob: b59c74100a84f5f16345da689a7d719740091100 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001comment "Processor Type"
2
3config CPU_32
4 bool
5 default y
6
7# Select CPU types depending on the architecture selected. This selects
8# which CPUs we support in the kernel image, and the compiler instruction
9# optimiser behaviour.
10
11# ARM610
12config CPU_ARM610
13 bool "Support ARM610 processor"
14 depends on ARCH_RPC
15 select CPU_32v3
16 select CPU_CACHE_V3
17 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010018 select CPU_COPY_V3 if MMU
19 select CPU_TLB_V3 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070020 help
21 The ARM610 is the successor to the ARM3 processor
22 and was produced by VLSI Technology Inc.
23
24 Say Y if you want support for the ARM610 processor.
25 Otherwise, say N.
26
27# ARM710
28config CPU_ARM710
29 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
30 default y if ARCH_CLPS7500
31 select CPU_32v3
32 select CPU_CACHE_V3
33 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010034 select CPU_COPY_V3 if MMU
35 select CPU_TLB_V3 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070036 help
37 A 32-bit RISC microprocessor based on the ARM7 processor core
38 designed by Advanced RISC Machines Ltd. The ARM710 is the
39 successor to the ARM610 processor. It was released in
40 July 1994 by VLSI Technology Inc.
41
42 Say Y if you want support for the ARM710 processor.
43 Otherwise, say N.
44
45# ARM720T
46config CPU_ARM720T
47 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
48 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010049 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070050 select CPU_ABRT_LV4T
51 select CPU_CACHE_V4
52 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010053 select CPU_COPY_V4WT if MMU
54 select CPU_TLB_V4WT if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070055 help
56 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
57 MMU built around an ARM7TDMI core.
58
59 Say Y if you want support for the ARM720T processor.
60 Otherwise, say N.
61
62# ARM920T
63config CPU_ARM920T
Ben Dooks3434d9d2006-06-24 21:21:28 +010064 bool "Support ARM920T processor"
65 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
66 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010067 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 select CPU_ABRT_EV4T
69 select CPU_CACHE_V4WT
70 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010071 select CPU_COPY_V4WB if MMU
72 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070073 help
74 The ARM920T is licensed to be produced by numerous vendors,
75 and is used in the Maverick EP9312 and the Samsung S3C2410.
76
77 More information on the Maverick EP9312 at
78 <http://linuxdevices.com/products/PD2382866068.html>.
79
80 Say Y if you want support for the ARM920T processor.
81 Otherwise, say N.
82
83# ARM922T
84config CPU_ARM922T
85 bool "Support ARM922T processor" if ARCH_INTEGRATOR
Russell King0fec53a2006-01-08 22:37:46 +000086 depends on ARCH_LH7A40X || ARCH_INTEGRATOR
87 default y if ARCH_LH7A40X
Lennert Buytenhek260e98e2006-08-28 12:51:20 +010088 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -070089 select CPU_ABRT_EV4T
90 select CPU_CACHE_V4WT
91 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +010092 select CPU_COPY_V4WB if MMU
93 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -070094 help
95 The ARM922T is a version of the ARM920T, but with smaller
96 instruction and data caches. It is used in Altera's
97 Excalibur XA device family.
98
99 Say Y if you want support for the ARM922T processor.
100 Otherwise, say N.
101
102# ARM925T
103config CPU_ARM925T
Tony Lindgrenb288f752005-07-10 19:58:08 +0100104 bool "Support ARM925T processor" if ARCH_OMAP1
Tony Lindgren3179a012005-11-10 14:26:48 +0000105 depends on ARCH_OMAP15XX
106 default y if ARCH_OMAP15XX
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100107 select CPU_32v4T
Linus Torvalds1da177e2005-04-16 15:20:36 -0700108 select CPU_ABRT_EV4T
109 select CPU_CACHE_V4WT
110 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100111 select CPU_COPY_V4WB if MMU
112 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700113 help
114 The ARM925T is a mix between the ARM920T and ARM926T, but with
115 different instruction and data caches. It is used in TI's OMAP
116 device family.
117
118 Say Y if you want support for the ARM925T processor.
119 Otherwise, say N.
120
121# ARM926T
122config CPU_ARM926T
Catalin Marinas8ad68bb2005-10-31 14:25:02 +0000123 bool "Support ARM926T processor"
Andrew Victor8fc5ffa2006-06-29 16:06:33 +0100124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126 select CPU_32v5
127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100129 select CPU_COPY_V4WB if MMU
130 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700131 help
132 This is a variant of the ARM920. It has slightly different
133 instruction sequences for cache and TLB operations. Curiously,
134 there is no documentation on it at the ARM corporate website.
135
136 Say Y if you want support for the ARM926T processor.
137 Otherwise, say N.
138
139# ARM1020 - needs validating
140config CPU_ARM1020
141 bool "Support ARM1020T (rev 0) processor"
142 depends on ARCH_INTEGRATOR
143 select CPU_32v5
144 select CPU_ABRT_EV4T
145 select CPU_CACHE_V4WT
146 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100147 select CPU_COPY_V4WB if MMU
148 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700149 help
150 The ARM1020 is the 32K cached version of the ARM10 processor,
151 with an addition of a floating-point unit.
152
153 Say Y if you want support for the ARM1020 processor.
154 Otherwise, say N.
155
156# ARM1020E - needs validating
157config CPU_ARM1020E
158 bool "Support ARM1020E processor"
159 depends on ARCH_INTEGRATOR
160 select CPU_32v5
161 select CPU_ABRT_EV4T
162 select CPU_CACHE_V4WT
163 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100164 select CPU_COPY_V4WB if MMU
165 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166 depends on n
167
168# ARM1022E
169config CPU_ARM1022
170 bool "Support ARM1022E processor"
171 depends on ARCH_INTEGRATOR
172 select CPU_32v5
173 select CPU_ABRT_EV4T
174 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100175 select CPU_COPY_V4WB if MMU # can probably do better
176 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700177 help
178 The ARM1022E is an implementation of the ARMv5TE architecture
179 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
180 embedded trace macrocell, and a floating-point unit.
181
182 Say Y if you want support for the ARM1022E processor.
183 Otherwise, say N.
184
185# ARM1026EJ-S
186config CPU_ARM1026
187 bool "Support ARM1026EJ-S processor"
188 depends on ARCH_INTEGRATOR
189 select CPU_32v5
190 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
191 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100192 select CPU_COPY_V4WB if MMU # can probably do better
193 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 help
195 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
196 based upon the ARM10 integer core.
197
198 Say Y if you want support for the ARM1026EJ-S processor.
199 Otherwise, say N.
200
201# SA110
202config CPU_SA110
203 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
204 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
205 select CPU_32v3 if ARCH_RPC
206 select CPU_32v4 if !ARCH_RPC
207 select CPU_ABRT_EV4
208 select CPU_CACHE_V4WB
209 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100210 select CPU_COPY_V4WB if MMU
211 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700212 help
213 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
214 is available at five speeds ranging from 100 MHz to 233 MHz.
215 More information is available at
216 <http://developer.intel.com/design/strong/sa110.htm>.
217
218 Say Y if you want support for the SA-110 processor.
219 Otherwise, say N.
220
221# SA1100
222config CPU_SA1100
223 bool
224 depends on ARCH_SA1100
225 default y
226 select CPU_32v4
227 select CPU_ABRT_EV4
228 select CPU_CACHE_V4WB
229 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100230 select CPU_TLB_V4WB if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231
232# XScale
233config CPU_XSCALE
234 bool
Lennert Buytenhek3f7e5812006-09-18 23:10:26 +0100235 depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_PXA || ARCH_IXP4XX || ARCH_IXP2000
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236 default y
237 select CPU_32v5
238 select CPU_ABRT_EV5T
239 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100240 select CPU_TLB_V4WBI if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100242# XScale Core Version 3
243config CPU_XSC3
244 bool
245 depends on ARCH_IXP23XX
246 default y
247 select CPU_32v5
248 select CPU_ABRT_EV5T
249 select CPU_CACHE_VIVT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100250 select CPU_TLB_V4WBI if MMU
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100251 select IO_36
252
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253# ARMv6
254config CPU_V6
255 bool "Support ARM V6 processor"
Tony Lindgren1dbae812005-11-10 14:26:51 +0000256 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700257 select CPU_32v6
258 select CPU_ABRT_EV6
259 select CPU_CACHE_V6
260 select CPU_CACHE_VIPT
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100261 select CPU_COPY_V6 if MMU
262 select CPU_TLB_V6 if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700263
Russell King4a5f79e2005-11-03 15:48:21 +0000264# ARMv6k
265config CPU_32v6K
266 bool "Support ARM V6K processor extensions" if !SMP
267 depends on CPU_V6
268 default y if SMP
269 help
270 Say Y here if your ARMv6 processor supports the 'K' extension.
271 This enables the kernel to use some instructions not present
272 on previous processors, and as such a kernel build with this
273 enabled will not boot on processors with do not support these
274 instructions.
275
Linus Torvalds1da177e2005-04-16 15:20:36 -0700276# Figure out what processor architecture version we should be using.
277# This defines the compiler instruction set which depends on the machine type.
278config CPU_32v3
279 bool
Russell King60b6cf62006-06-19 17:36:43 +0100280 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000281 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700282
283config CPU_32v4
284 bool
Russell King60b6cf62006-06-19 17:36:43 +0100285 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000286 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700287
Lennert Buytenhek260e98e2006-08-28 12:51:20 +0100288config CPU_32v4T
289 bool
290 select TLS_REG_EMUL if SMP || !MMU
291 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
292
Linus Torvalds1da177e2005-04-16 15:20:36 -0700293config CPU_32v5
294 bool
Russell King60b6cf62006-06-19 17:36:43 +0100295 select TLS_REG_EMUL if SMP || !MMU
Russell King48fa14f2006-03-16 14:52:33 +0000296 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298config CPU_32v6
299 bool
300
301# The abort model
302config CPU_ABRT_EV4
303 bool
304
305config CPU_ABRT_EV4T
306 bool
307
308config CPU_ABRT_LV4T
309 bool
310
311config CPU_ABRT_EV5T
312 bool
313
314config CPU_ABRT_EV5TJ
315 bool
316
317config CPU_ABRT_EV6
318 bool
319
320# The cache model
321config CPU_CACHE_V3
322 bool
323
324config CPU_CACHE_V4
325 bool
326
327config CPU_CACHE_V4WT
328 bool
329
330config CPU_CACHE_V4WB
331 bool
332
333config CPU_CACHE_V6
334 bool
335
336config CPU_CACHE_VIVT
337 bool
338
339config CPU_CACHE_VIPT
340 bool
341
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100342if MMU
Linus Torvalds1da177e2005-04-16 15:20:36 -0700343# The copy-page model
344config CPU_COPY_V3
345 bool
346
347config CPU_COPY_V4WT
348 bool
349
350config CPU_COPY_V4WB
351 bool
352
353config CPU_COPY_V6
354 bool
355
356# This selects the TLB model
357config CPU_TLB_V3
358 bool
359 help
360 ARM Architecture Version 3 TLB.
361
362config CPU_TLB_V4WT
363 bool
364 help
365 ARM Architecture Version 4 TLB with writethrough cache.
366
367config CPU_TLB_V4WB
368 bool
369 help
370 ARM Architecture Version 4 TLB with writeback cache.
371
372config CPU_TLB_V4WBI
373 bool
374 help
375 ARM Architecture Version 4 TLB with writeback cache and invalidate
376 instruction cache entry.
377
378config CPU_TLB_V6
379 bool
380
Hyok S. Choif9c21a62006-06-21 22:26:29 +0100381endif
382
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100383#
384# CPU supports 36-bit I/O
385#
386config IO_36
387 bool
388
Linus Torvalds1da177e2005-04-16 15:20:36 -0700389comment "Processor Features"
390
391config ARM_THUMB
392 bool "Support Thumb user binaries"
Lennert Buytenhek23bdf862006-03-28 21:00:40 +0100393 depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 default y
395 help
396 Say Y if you want to include kernel support for running user space
397 Thumb binaries.
398
399 The Thumb instruction set is a compressed form of the standard ARM
400 instruction set resulting in smaller binaries at the expense of
401 slightly less efficient code.
402
403 If you don't know what this all is, saying Y is a safe choice.
404
405config CPU_BIG_ENDIAN
406 bool "Build big-endian kernel"
407 depends on ARCH_SUPPORTS_BIG_ENDIAN
408 help
409 Say Y if you plan on running a kernel in big-endian mode.
410 Note that your board must be properly built and your board
411 port must properly enable any big-endian related features
412 of your chipset/board/processor.
413
414config CPU_ICACHE_DISABLE
415 bool "Disable I-Cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100416 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700417 help
418 Say Y here to disable the processor instruction cache. Unless
419 you have a reason not to or are unsure, say N.
420
421config CPU_DCACHE_DISABLE
422 bool "Disable D-Cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100423 depends on CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424 help
425 Say Y here to disable the processor data cache. Unless
426 you have a reason not to or are unsure, say N.
427
428config CPU_DCACHE_WRITETHROUGH
429 bool "Force write through D-cache"
Catalin Marinase03eb522005-10-05 23:06:36 +0100430 depends on (CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_V6) && !CPU_DCACHE_DISABLE
Linus Torvalds1da177e2005-04-16 15:20:36 -0700431 default y if CPU_ARM925T
432 help
433 Say Y here to use the data cache in writethrough mode. Unless you
434 specifically require this or are unsure, say N.
435
436config CPU_CACHE_ROUND_ROBIN
437 bool "Round robin I and D cache replacement algorithm"
438 depends on (CPU_ARM926T || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
439 help
440 Say Y here to use the predictable round-robin cache replacement
441 policy. Unless you specifically require this or are unsure, say N.
442
443config CPU_BPREDICT_DISABLE
444 bool "Disable branch prediction"
Catalin Marinase03eb522005-10-05 23:06:36 +0100445 depends on CPU_ARM1020 || CPU_V6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 help
447 Say Y here to disable branch prediction. If unsure, say N.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100448
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100449config TLS_REG_EMUL
450 bool
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100451 help
Nicolas Pitre70489c82005-05-12 19:27:12 +0100452 An SMP system using a pre-ARMv6 processor (there are apparently
453 a few prototypes like that in existence) and therefore access to
454 that required register must be emulated.
Nicolas Pitre4b0e07a2005-05-05 23:24:45 +0100455
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100456config HAS_TLS_REG
457 bool
Nicolas Pitre70489c82005-05-12 19:27:12 +0100458 depends on !TLS_REG_EMUL
459 default y if SMP || CPU_32v7
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100460 help
461 This selects support for the CP15 thread register.
Nicolas Pitre70489c82005-05-12 19:27:12 +0100462 It is defined to be available on some ARMv6 processors (including
463 all SMP capable ARMv6's) or later processors. User space may
464 assume directly accessing that register and always obtain the
465 expected value only on ARMv7 and above.
Nicolas Pitre2d2669b2005-04-29 22:08:33 +0100466
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100467config NEEDS_SYSCALL_FOR_CMPXCHG
468 bool
Nicolas Pitredcef1f62005-06-08 19:00:47 +0100469 help
470 SMP on a pre-ARMv6 processor? Well OK then.
471 Forget about fast user space cmpxchg support.
472 It is just not possible.
473