Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 1 | menu "Processor selection" |
| 2 | |
| 3 | # |
| 4 | # Processor families |
| 5 | # |
| 6 | config CPU_SH2 |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 7 | select SH_WRITETHROUGH if !CPU_SH2A |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 8 | bool |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 9 | |
| 10 | config CPU_SH2A |
| 11 | bool |
| 12 | select CPU_SH2 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 13 | |
| 14 | config CPU_SH3 |
| 15 | bool |
| 16 | select CPU_HAS_INTEVT |
| 17 | select CPU_HAS_SR_RB |
| 18 | |
| 19 | config CPU_SH4 |
| 20 | bool |
| 21 | select CPU_HAS_INTEVT |
| 22 | select CPU_HAS_SR_RB |
Stuart Menefy | 9b3a53a | 2006-11-24 11:42:24 +0900 | [diff] [blame] | 23 | select CPU_HAS_PTEA if !CPU_SUBTYPE_ST40 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 24 | |
| 25 | config CPU_SH4A |
| 26 | bool |
| 27 | select CPU_SH4 |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 28 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 29 | config CPU_SH4AL_DSP |
| 30 | bool |
| 31 | select CPU_SH4A |
| 32 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 33 | config CPU_SUBTYPE_ST40 |
| 34 | bool |
| 35 | select CPU_SH4 |
| 36 | select CPU_HAS_INTC2_IRQ |
| 37 | |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame^] | 38 | config CPU_SHX2 |
| 39 | bool |
| 40 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 41 | # |
| 42 | # Processor subtypes |
| 43 | # |
| 44 | |
| 45 | comment "SH-2 Processor Support" |
| 46 | |
| 47 | config CPU_SUBTYPE_SH7604 |
| 48 | bool "Support SH7604 processor" |
| 49 | select CPU_SH2 |
| 50 | |
Yoshinori Sato | 9d4436a | 2006-11-05 15:40:13 +0900 | [diff] [blame] | 51 | config CPU_SUBTYPE_SH7619 |
| 52 | bool "Support SH7619 processor" |
| 53 | select CPU_SH2 |
| 54 | |
| 55 | comment "SH-2A Processor Support" |
| 56 | |
| 57 | config CPU_SUBTYPE_SH7206 |
| 58 | bool "Support SH7206 processor" |
| 59 | select CPU_SH2A |
| 60 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 61 | comment "SH-3 Processor Support" |
| 62 | |
| 63 | config CPU_SUBTYPE_SH7300 |
| 64 | bool "Support SH7300 processor" |
| 65 | select CPU_SH3 |
| 66 | |
| 67 | config CPU_SUBTYPE_SH7705 |
| 68 | bool "Support SH7705 processor" |
| 69 | select CPU_SH3 |
| 70 | select CPU_HAS_PINT_IRQ |
| 71 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 72 | config CPU_SUBTYPE_SH7706 |
| 73 | bool "Support SH7706 processor" |
| 74 | select CPU_SH3 |
| 75 | help |
| 76 | Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU. |
| 77 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 78 | config CPU_SUBTYPE_SH7707 |
| 79 | bool "Support SH7707 processor" |
| 80 | select CPU_SH3 |
| 81 | select CPU_HAS_PINT_IRQ |
| 82 | help |
| 83 | Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU. |
| 84 | |
| 85 | config CPU_SUBTYPE_SH7708 |
| 86 | bool "Support SH7708 processor" |
| 87 | select CPU_SH3 |
| 88 | help |
| 89 | Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or |
| 90 | if you have a 100 Mhz SH-3 HD6417708R CPU. |
| 91 | |
| 92 | config CPU_SUBTYPE_SH7709 |
| 93 | bool "Support SH7709 processor" |
| 94 | select CPU_SH3 |
| 95 | select CPU_HAS_PINT_IRQ |
| 96 | help |
| 97 | Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU. |
| 98 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 99 | config CPU_SUBTYPE_SH7710 |
| 100 | bool "Support SH7710 processor" |
| 101 | select CPU_SH3 |
| 102 | help |
| 103 | Select SH7710 if you have a SH3-DSP SH7710 CPU. |
| 104 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 105 | comment "SH-4 Processor Support" |
| 106 | |
| 107 | config CPU_SUBTYPE_SH7750 |
| 108 | bool "Support SH7750 processor" |
| 109 | select CPU_SH4 |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 110 | select CPU_HAS_IPR_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 111 | help |
| 112 | Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. |
| 113 | |
| 114 | config CPU_SUBTYPE_SH7091 |
| 115 | bool "Support SH7091 processor" |
| 116 | select CPU_SH4 |
| 117 | select CPU_SUBTYPE_SH7750 |
| 118 | help |
| 119 | Select SH7091 if you have an SH-4 based Sega device (such as |
| 120 | the Dreamcast, Naomi, and Naomi 2). |
| 121 | |
| 122 | config CPU_SUBTYPE_SH7750R |
| 123 | bool "Support SH7750R processor" |
| 124 | select CPU_SH4 |
| 125 | select CPU_SUBTYPE_SH7750 |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 126 | select CPU_HAS_IPR_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 127 | |
| 128 | config CPU_SUBTYPE_SH7750S |
| 129 | bool "Support SH7750S processor" |
| 130 | select CPU_SH4 |
| 131 | select CPU_SUBTYPE_SH7750 |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 132 | select CPU_HAS_IPR_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 133 | |
| 134 | config CPU_SUBTYPE_SH7751 |
| 135 | bool "Support SH7751 processor" |
| 136 | select CPU_SH4 |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 137 | select CPU_HAS_IPR_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 138 | help |
| 139 | Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, |
| 140 | or if you have a HD6417751R CPU. |
| 141 | |
| 142 | config CPU_SUBTYPE_SH7751R |
| 143 | bool "Support SH7751R processor" |
| 144 | select CPU_SH4 |
| 145 | select CPU_SUBTYPE_SH7751 |
Jamie Lenehan | ea0f8fe | 2006-12-06 12:05:02 +0900 | [diff] [blame] | 146 | select CPU_HAS_IPR_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 147 | |
| 148 | config CPU_SUBTYPE_SH7760 |
| 149 | bool "Support SH7760 processor" |
| 150 | select CPU_SH4 |
| 151 | select CPU_HAS_INTC2_IRQ |
| 152 | |
| 153 | config CPU_SUBTYPE_SH4_202 |
| 154 | bool "Support SH4-202 processor" |
| 155 | select CPU_SH4 |
| 156 | |
| 157 | comment "ST40 Processor Support" |
| 158 | |
| 159 | config CPU_SUBTYPE_ST40STB1 |
| 160 | bool "Support ST40STB1/ST40RA processors" |
| 161 | select CPU_SUBTYPE_ST40 |
| 162 | help |
| 163 | Select ST40STB1 if you have a ST40RA CPU. |
| 164 | This was previously called the ST40STB1, hence the option name. |
| 165 | |
| 166 | config CPU_SUBTYPE_ST40GX1 |
| 167 | bool "Support ST40GX1 processor" |
| 168 | select CPU_SUBTYPE_ST40 |
| 169 | help |
| 170 | Select ST40GX1 if you have a ST40GX1 CPU. |
| 171 | |
| 172 | comment "SH-4A Processor Support" |
| 173 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 174 | config CPU_SUBTYPE_SH7770 |
| 175 | bool "Support SH7770 processor" |
| 176 | select CPU_SH4A |
| 177 | |
| 178 | config CPU_SUBTYPE_SH7780 |
| 179 | bool "Support SH7780 processor" |
| 180 | select CPU_SH4A |
Paul Mundt | a328ff9 | 2006-09-27 16:14:54 +0900 | [diff] [blame] | 181 | select CPU_HAS_INTC2_IRQ |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 182 | |
Paul Mundt | b552c7e | 2006-11-20 14:14:29 +0900 | [diff] [blame] | 183 | config CPU_SUBTYPE_SH7785 |
| 184 | bool "Support SH7785 processor" |
| 185 | select CPU_SH4A |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame^] | 186 | select CPU_SHX2 |
Paul Mundt | b552c7e | 2006-11-20 14:14:29 +0900 | [diff] [blame] | 187 | select CPU_HAS_INTC2_IRQ |
| 188 | |
Paul Mundt | e5723e0 | 2006-09-27 17:38:11 +0900 | [diff] [blame] | 189 | comment "SH4AL-DSP Processor Support" |
| 190 | |
| 191 | config CPU_SUBTYPE_SH73180 |
| 192 | bool "Support SH73180 processor" |
| 193 | select CPU_SH4AL_DSP |
| 194 | |
| 195 | config CPU_SUBTYPE_SH7343 |
| 196 | bool "Support SH7343 processor" |
| 197 | select CPU_SH4AL_DSP |
| 198 | |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame^] | 199 | config CPU_SUBTYPE_SH7722 |
| 200 | bool "Support SH7722 processor" |
| 201 | select CPU_SH4AL_DSP |
| 202 | select CPU_SHX2 |
| 203 | select CPU_HAS_IPR_IRQ |
| 204 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 205 | endmenu |
| 206 | |
| 207 | menu "Memory management options" |
| 208 | |
| 209 | config MMU |
| 210 | bool "Support for memory management hardware" |
| 211 | depends on !CPU_SH2 |
| 212 | default y |
| 213 | help |
| 214 | Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to |
| 215 | boot on these systems, this option must not be set. |
| 216 | |
| 217 | On other systems (such as the SH-3 and 4) where an MMU exists, |
| 218 | turning this off will boot the kernel on these machines with the |
| 219 | MMU implicitly switched off. |
| 220 | |
Paul Mundt | e7f93a3 | 2006-09-27 17:19:13 +0900 | [diff] [blame] | 221 | config PAGE_OFFSET |
| 222 | hex |
| 223 | default "0x80000000" if MMU |
| 224 | default "0x00000000" |
| 225 | |
| 226 | config MEMORY_START |
| 227 | hex "Physical memory start address" |
| 228 | default "0x08000000" |
| 229 | ---help--- |
| 230 | Computers built with Hitachi SuperH processors always |
| 231 | map the ROM starting at address zero. But the processor |
| 232 | does not specify the range that RAM takes. |
| 233 | |
| 234 | The physical memory (RAM) start address will be automatically |
| 235 | set to 08000000. Other platforms, such as the Solution Engine |
| 236 | boards typically map RAM at 0C000000. |
| 237 | |
| 238 | Tweak this only when porting to a new machine which does not |
| 239 | already have a defconfig. Changing it from the known correct |
| 240 | value on any of the known systems will only lead to disaster. |
| 241 | |
| 242 | config MEMORY_SIZE |
| 243 | hex "Physical memory size" |
| 244 | default "0x00400000" |
| 245 | help |
| 246 | This sets the default memory size assumed by your SH kernel. It can |
| 247 | be overridden as normal by the 'mem=' argument on the kernel command |
| 248 | line. If unsure, consult your board specifications or just leave it |
| 249 | as 0x00400000 which was the default value before this became |
| 250 | configurable. |
| 251 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 252 | config 32BIT |
| 253 | bool "Support 32-bit physical addressing through PMB" |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 254 | depends on CPU_SH4A && MMU && (!X2TLB || BROKEN) |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 255 | default y |
| 256 | help |
| 257 | If you say Y here, physical addressing will be extended to |
| 258 | 32-bits through the SH-4A PMB. If this is not set, legacy |
| 259 | 29-bit physical addressing will be used. |
| 260 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 261 | config X2TLB |
| 262 | bool "Enable extended TLB mode" |
Paul Mundt | 41504c3 | 2006-12-11 20:28:03 +0900 | [diff] [blame^] | 263 | depends on CPU_SHX2 && MMU && EXPERIMENTAL |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 264 | help |
| 265 | Selecting this option will enable the extended mode of the SH-X2 |
| 266 | TLB. For legacy SH-X behaviour and interoperability, say N. For |
| 267 | all of the fun new features and a willingless to submit bug reports, |
| 268 | say Y. |
| 269 | |
Paul Mundt | 19f9a34 | 2006-09-27 18:33:49 +0900 | [diff] [blame] | 270 | config VSYSCALL |
| 271 | bool "Support vsyscall page" |
| 272 | depends on MMU |
| 273 | default y |
| 274 | help |
| 275 | This will enable support for the kernel mapping a vDSO page |
| 276 | in process space, and subsequently handing down the entry point |
| 277 | to the libc through the ELF auxiliary vector. |
| 278 | |
| 279 | From the kernel side this is used for the signal trampoline. |
| 280 | For systems with an MMU that can afford to give up a page, |
| 281 | (the default value) say Y. |
| 282 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 283 | choice |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 284 | prompt "Kernel page size" |
| 285 | default PAGE_SIZE_4KB |
| 286 | |
| 287 | config PAGE_SIZE_4KB |
| 288 | bool "4kB" |
| 289 | help |
| 290 | This is the default page size used by all SuperH CPUs. |
| 291 | |
| 292 | config PAGE_SIZE_8KB |
| 293 | bool "8kB" |
| 294 | depends on EXPERIMENTAL && X2TLB |
| 295 | help |
| 296 | This enables 8kB pages as supported by SH-X2 and later MMUs. |
| 297 | |
| 298 | config PAGE_SIZE_64KB |
| 299 | bool "64kB" |
| 300 | depends on EXPERIMENTAL && CPU_SH4 |
| 301 | help |
| 302 | This enables support for 64kB pages, possible on all SH-4 |
| 303 | CPUs and later. Highly experimental, not recommended. |
| 304 | |
| 305 | endchoice |
| 306 | |
| 307 | choice |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 308 | prompt "HugeTLB page size" |
| 309 | depends on HUGETLB_PAGE && CPU_SH4 && MMU |
| 310 | default HUGETLB_PAGE_SIZE_64K |
| 311 | |
| 312 | config HUGETLB_PAGE_SIZE_64K |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 313 | bool "64kB" |
| 314 | |
| 315 | config HUGETLB_PAGE_SIZE_256K |
| 316 | bool "256kB" |
| 317 | depends on X2TLB |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 318 | |
| 319 | config HUGETLB_PAGE_SIZE_1MB |
| 320 | bool "1MB" |
| 321 | |
Paul Mundt | 21440cf | 2006-11-20 14:30:26 +0900 | [diff] [blame] | 322 | config HUGETLB_PAGE_SIZE_4MB |
| 323 | bool "4MB" |
| 324 | depends on X2TLB |
| 325 | |
| 326 | config HUGETLB_PAGE_SIZE_64MB |
| 327 | bool "64MB" |
| 328 | depends on X2TLB |
| 329 | |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 330 | endchoice |
| 331 | |
| 332 | source "mm/Kconfig" |
| 333 | |
| 334 | endmenu |
| 335 | |
| 336 | menu "Cache configuration" |
| 337 | |
| 338 | config SH7705_CACHE_32KB |
| 339 | bool "Enable 32KB cache size for SH7705" |
| 340 | depends on CPU_SUBTYPE_SH7705 |
| 341 | default y |
| 342 | |
| 343 | config SH_DIRECT_MAPPED |
| 344 | bool "Use direct-mapped caching" |
| 345 | default n |
| 346 | help |
| 347 | Selecting this option will configure the caches to be direct-mapped, |
| 348 | even if the cache supports a 2 or 4-way mode. This is useful primarily |
| 349 | for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R, |
| 350 | SH4-202, SH4-501, etc.) |
| 351 | |
| 352 | Turn this option off for platforms that do not have a direct-mapped |
| 353 | cache, and you have no need to run the caches in such a configuration. |
| 354 | |
| 355 | config SH_WRITETHROUGH |
| 356 | bool "Use write-through caching" |
Paul Mundt | cad8244 | 2006-01-16 22:14:19 -0800 | [diff] [blame] | 357 | help |
| 358 | Selecting this option will configure the caches in write-through |
| 359 | mode, as opposed to the default write-back configuration. |
| 360 | |
| 361 | Since there's sill some aliasing issues on SH-4, this option will |
| 362 | unfortunately still require the majority of flushing functions to |
| 363 | be implemented to deal with aliasing. |
| 364 | |
| 365 | If unsure, say N. |
| 366 | |
| 367 | config SH_OCRAM |
| 368 | bool "Operand Cache RAM (OCRAM) support" |
| 369 | help |
| 370 | Selecting this option will automatically tear down the number of |
| 371 | sets in the dcache by half, which in turn exposes a memory range. |
| 372 | |
| 373 | The addresses for the OC RAM base will vary according to the |
| 374 | processor version. Consult vendor documentation for specifics. |
| 375 | |
| 376 | If unsure, say N. |
| 377 | |
| 378 | endmenu |