Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/include/linux/mtd/nand.h |
| 3 | * |
| 4 | * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com> |
| 5 | * Steven J. Hill <sjhill@realitydiluted.com> |
| 6 | * Thomas Gleixner <tglx@linutronix.de> |
| 7 | * |
Vitaly Wool | 962034f | 2005-09-15 14:58:53 +0100 | [diff] [blame] | 8 | * $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | * |
| 14 | * Info: |
| 15 | * Contains standard defines and IDs for NAND flash devices |
| 16 | * |
| 17 | * Changelog: |
| 18 | * 01-31-2000 DMW Created |
| 19 | * 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers |
| 20 | * so it can be used by other NAND flash device |
| 21 | * drivers. I also changed the copyright since none |
| 22 | * of the original contents of this file are specific |
| 23 | * to DoC devices. David can whack me with a baseball |
| 24 | * bat later if I did something naughty. |
| 25 | * 10-11-2000 SJH Added private NAND flash structure for driver |
| 26 | * 10-24-2000 SJH Added prototype for 'nand_scan' function |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 27 | * 10-29-2001 TG changed nand_chip structure to support |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | * hardwarespecific function for accessing control lines |
| 29 | * 02-21-2002 TG added support for different read/write adress and |
| 30 | * ready/busy line access function |
| 31 | * 02-26-2002 TG added chip_delay to nand_chip structure to optimize |
| 32 | * command delay times for different chips |
| 33 | * 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate |
| 34 | * defines in jffs2/wbuf.c |
| 35 | * 08-07-2002 TG forced bad block location to byte 5 of OOB, even if |
| 36 | * CONFIG_MTD_NAND_ECC_JFFS2 is not set |
| 37 | * 08-10-2002 TG extensions to nand_chip structure to support HW-ECC |
| 38 | * |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 39 | * 08-29-2002 tglx nand_chip structure: data_poi for selecting |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 40 | * internal / fs-driver buffer |
| 41 | * support for 6byte/512byte hardware ECC |
| 42 | * read_ecc, write_ecc extended for different oob-layout |
| 43 | * oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB, |
| 44 | * NAND_YAFFS_OOB |
| 45 | * 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 46 | * Split manufacturer and device ID structures |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 47 | * |
| 48 | * 02-08-2004 tglx added option field to nand structure for chip anomalities |
| 49 | * 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id |
| 50 | * update of nand_chip structure description |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 51 | * 01-17-2005 dmarlin added extended commands for AG-AND device and added option |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 52 | * for BBT_AUTO_REFRESH. |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 53 | * 01-20-2005 dmarlin added optional pointer to hardware specific callback for |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 54 | * extra error status checks. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 55 | */ |
| 56 | #ifndef __LINUX_MTD_NAND_H |
| 57 | #define __LINUX_MTD_NAND_H |
| 58 | |
| 59 | #include <linux/config.h> |
| 60 | #include <linux/wait.h> |
| 61 | #include <linux/spinlock.h> |
| 62 | #include <linux/mtd/mtd.h> |
| 63 | |
| 64 | struct mtd_info; |
| 65 | /* Scan and identify a NAND device */ |
| 66 | extern int nand_scan (struct mtd_info *mtd, int max_chips); |
| 67 | /* Free resources held by the NAND device */ |
| 68 | extern void nand_release (struct mtd_info *mtd); |
| 69 | |
| 70 | /* Read raw data from the device without ECC */ |
| 71 | extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen); |
| 72 | |
| 73 | |
| 74 | /* The maximum number of NAND chips in an array */ |
| 75 | #define NAND_MAX_CHIPS 8 |
| 76 | |
| 77 | /* This constant declares the max. oobsize / page, which |
| 78 | * is supported now. If you add a chip with bigger oobsize/page |
| 79 | * adjust this accordingly. |
| 80 | */ |
| 81 | #define NAND_MAX_OOBSIZE 64 |
| 82 | |
| 83 | /* |
| 84 | * Constants for hardware specific CLE/ALE/NCE function |
| 85 | */ |
| 86 | /* Select the chip by setting nCE to low */ |
| 87 | #define NAND_CTL_SETNCE 1 |
| 88 | /* Deselect the chip by setting nCE to high */ |
| 89 | #define NAND_CTL_CLRNCE 2 |
| 90 | /* Select the command latch by setting CLE to high */ |
| 91 | #define NAND_CTL_SETCLE 3 |
| 92 | /* Deselect the command latch by setting CLE to low */ |
| 93 | #define NAND_CTL_CLRCLE 4 |
| 94 | /* Select the address latch by setting ALE to high */ |
| 95 | #define NAND_CTL_SETALE 5 |
| 96 | /* Deselect the address latch by setting ALE to low */ |
| 97 | #define NAND_CTL_CLRALE 6 |
| 98 | /* Set write protection by setting WP to high. Not used! */ |
| 99 | #define NAND_CTL_SETWP 7 |
| 100 | /* Clear write protection by setting WP to low. Not used! */ |
| 101 | #define NAND_CTL_CLRWP 8 |
| 102 | |
| 103 | /* |
| 104 | * Standard NAND flash commands |
| 105 | */ |
| 106 | #define NAND_CMD_READ0 0 |
| 107 | #define NAND_CMD_READ1 1 |
| 108 | #define NAND_CMD_PAGEPROG 0x10 |
| 109 | #define NAND_CMD_READOOB 0x50 |
| 110 | #define NAND_CMD_ERASE1 0x60 |
| 111 | #define NAND_CMD_STATUS 0x70 |
| 112 | #define NAND_CMD_STATUS_MULTI 0x71 |
| 113 | #define NAND_CMD_SEQIN 0x80 |
| 114 | #define NAND_CMD_READID 0x90 |
| 115 | #define NAND_CMD_ERASE2 0xd0 |
| 116 | #define NAND_CMD_RESET 0xff |
| 117 | |
| 118 | /* Extended commands for large page devices */ |
| 119 | #define NAND_CMD_READSTART 0x30 |
| 120 | #define NAND_CMD_CACHEDPROG 0x15 |
| 121 | |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 122 | /* Extended commands for AG-AND device */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 123 | /* |
| 124 | * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 125 | * there is no way to distinguish that from NAND_CMD_READ0 |
| 126 | * until the remaining sequence of commands has been completed |
| 127 | * so add a high order bit and mask it off in the command. |
| 128 | */ |
| 129 | #define NAND_CMD_DEPLETE1 0x100 |
| 130 | #define NAND_CMD_DEPLETE2 0x38 |
| 131 | #define NAND_CMD_STATUS_MULTI 0x71 |
| 132 | #define NAND_CMD_STATUS_ERROR 0x72 |
| 133 | /* multi-bank error status (banks 0-3) */ |
| 134 | #define NAND_CMD_STATUS_ERROR0 0x73 |
| 135 | #define NAND_CMD_STATUS_ERROR1 0x74 |
| 136 | #define NAND_CMD_STATUS_ERROR2 0x75 |
| 137 | #define NAND_CMD_STATUS_ERROR3 0x76 |
| 138 | #define NAND_CMD_STATUS_RESET 0x7f |
| 139 | #define NAND_CMD_STATUS_CLEAR 0xff |
| 140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | /* Status bits */ |
| 142 | #define NAND_STATUS_FAIL 0x01 |
| 143 | #define NAND_STATUS_FAIL_N1 0x02 |
| 144 | #define NAND_STATUS_TRUE_READY 0x20 |
| 145 | #define NAND_STATUS_READY 0x40 |
| 146 | #define NAND_STATUS_WP 0x80 |
| 147 | |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 148 | /* |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 149 | * Constants for ECC_MODES |
| 150 | */ |
| 151 | |
| 152 | /* No ECC. Usage is not recommended ! */ |
| 153 | #define NAND_ECC_NONE 0 |
| 154 | /* Software ECC 3 byte ECC per 256 Byte data */ |
| 155 | #define NAND_ECC_SOFT 1 |
| 156 | /* Hardware ECC 3 byte ECC per 256 Byte data */ |
| 157 | #define NAND_ECC_HW3_256 2 |
| 158 | /* Hardware ECC 3 byte ECC per 512 Byte data */ |
| 159 | #define NAND_ECC_HW3_512 3 |
| 160 | /* Hardware ECC 3 byte ECC per 512 Byte data */ |
| 161 | #define NAND_ECC_HW6_512 4 |
| 162 | /* Hardware ECC 8 byte ECC per 512 Byte data */ |
| 163 | #define NAND_ECC_HW8_512 6 |
| 164 | /* Hardware ECC 12 byte ECC per 2048 Byte data */ |
| 165 | #define NAND_ECC_HW12_2048 7 |
| 166 | |
| 167 | /* |
| 168 | * Constants for Hardware ECC |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 169 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | /* Reset Hardware ECC for read */ |
| 171 | #define NAND_ECC_READ 0 |
| 172 | /* Reset Hardware ECC for write */ |
| 173 | #define NAND_ECC_WRITE 1 |
| 174 | /* Enable Hardware ECC before syndrom is read back from flash */ |
| 175 | #define NAND_ECC_READSYN 2 |
| 176 | |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 177 | /* Bit mask for flags passed to do_nand_read_ecc */ |
| 178 | #define NAND_GET_DEVICE 0x80 |
| 179 | |
| 180 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | /* Option constants for bizarre disfunctionality and real |
| 182 | * features |
| 183 | */ |
| 184 | /* Chip can not auto increment pages */ |
| 185 | #define NAND_NO_AUTOINCR 0x00000001 |
| 186 | /* Buswitdh is 16 bit */ |
| 187 | #define NAND_BUSWIDTH_16 0x00000002 |
| 188 | /* Device supports partial programming without padding */ |
| 189 | #define NAND_NO_PADDING 0x00000004 |
| 190 | /* Chip has cache program function */ |
| 191 | #define NAND_CACHEPRG 0x00000008 |
| 192 | /* Chip has copy back function */ |
| 193 | #define NAND_COPYBACK 0x00000010 |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 194 | /* AND Chip which has 4 banks and a confusing page / block |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | * assignment. See Renesas datasheet for further information */ |
| 196 | #define NAND_IS_AND 0x00000020 |
| 197 | /* Chip has a array of 4 pages which can be read without |
| 198 | * additional ready /busy waits */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 199 | #define NAND_4PAGE_ARRAY 0x00000040 |
David A. Marlin | 28a48de | 2005-01-17 18:29:21 +0000 | [diff] [blame] | 200 | /* Chip requires that BBT is periodically rewritten to prevent |
| 201 | * bits from adjacent blocks from 'leaking' in altering data. |
| 202 | * This happens with the Renesas AG-AND chips, possibly others. */ |
| 203 | #define BBT_AUTO_REFRESH 0x00000080 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | |
| 205 | /* Options valid for Samsung large page devices */ |
| 206 | #define NAND_SAMSUNG_LP_OPTIONS \ |
| 207 | (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) |
| 208 | |
| 209 | /* Macros to identify the above */ |
| 210 | #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) |
| 211 | #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) |
| 212 | #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) |
| 213 | #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) |
| 214 | |
| 215 | /* Mask to zero out the chip options, which come from the id table */ |
| 216 | #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) |
| 217 | |
| 218 | /* Non chip related options */ |
| 219 | /* Use a flash based bad block table. This option is passed to the |
| 220 | * default bad block table function. */ |
| 221 | #define NAND_USE_FLASH_BBT 0x00010000 |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 222 | /* The hw ecc generator provides a syndrome instead a ecc value on read |
| 223 | * This can only work if we have the ecc bytes directly behind the |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | * data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */ |
| 225 | #define NAND_HWECC_SYNDROME 0x00020000 |
Thomas Gleixner | 0040bf3 | 2005-02-09 12:20:00 +0000 | [diff] [blame] | 226 | /* This option skips the bbt scan during initialization. */ |
| 227 | #define NAND_SKIP_BBTSCAN 0x00040000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 228 | |
| 229 | /* Options set by nand scan */ |
Thomas Gleixner | a36ed29 | 2006-05-23 11:37:03 +0200 | [diff] [blame] | 230 | /* Nand scan has allocated controller struct */ |
| 231 | #define NAND_CONTROLLER_ALLOC 0x20000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 232 | /* Nand scan has allocated oob_buf */ |
| 233 | #define NAND_OOBBUF_ALLOC 0x40000000 |
| 234 | /* Nand scan has allocated data_buf */ |
| 235 | #define NAND_DATABUF_ALLOC 0x80000000 |
| 236 | |
| 237 | |
| 238 | /* |
| 239 | * nand_state_t - chip states |
| 240 | * Enumeration for NAND flash chip state |
| 241 | */ |
| 242 | typedef enum { |
| 243 | FL_READY, |
| 244 | FL_READING, |
| 245 | FL_WRITING, |
| 246 | FL_ERASING, |
| 247 | FL_SYNCING, |
| 248 | FL_CACHEDPRG, |
Vitaly Wool | 962034f | 2005-09-15 14:58:53 +0100 | [diff] [blame] | 249 | FL_PM_SUSPENDED, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 250 | } nand_state_t; |
| 251 | |
| 252 | /* Keep gcc happy */ |
| 253 | struct nand_chip; |
| 254 | |
| 255 | /** |
| 256 | * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 257 | * @lock: protection lock |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 258 | * @active: the mtd device which holds the controller currently |
Thomas Gleixner | 0dfc624 | 2005-05-31 20:39:20 +0100 | [diff] [blame] | 259 | * @wq: wait queue to sleep on if a NAND operation is in progress |
| 260 | * used instead of the per chip wait queue when a hw controller is available |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 261 | */ |
| 262 | struct nand_hw_control { |
| 263 | spinlock_t lock; |
| 264 | struct nand_chip *active; |
Thomas Gleixner | 0dfc624 | 2005-05-31 20:39:20 +0100 | [diff] [blame] | 265 | wait_queue_head_t wq; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | }; |
| 267 | |
| 268 | /** |
| 269 | * struct nand_chip - NAND Private Flash Chip Data |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 270 | * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device |
| 271 | * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | * @read_byte: [REPLACEABLE] read one byte from the chip |
| 273 | * @write_byte: [REPLACEABLE] write one byte to the chip |
| 274 | * @read_word: [REPLACEABLE] read one word from the chip |
| 275 | * @write_word: [REPLACEABLE] write one word to the chip |
| 276 | * @write_buf: [REPLACEABLE] write data from the buffer to the chip |
| 277 | * @read_buf: [REPLACEABLE] read data from the chip into the buffer |
| 278 | * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data |
| 279 | * @select_chip: [REPLACEABLE] select chip nr |
| 280 | * @block_bad: [REPLACEABLE] check, if the block is bad |
| 281 | * @block_markbad: [REPLACEABLE] mark the block bad |
| 282 | * @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines |
| 283 | * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line |
| 284 | * If set to NULL no access to ready/busy is available and the ready/busy information |
| 285 | * is read from the chip status register |
| 286 | * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip |
| 287 | * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready |
| 288 | * @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware |
| 289 | * @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw) |
| 290 | * @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only |
| 291 | * be provided if a hardware ECC is available |
| 292 | * @erase_cmd: [INTERN] erase command write function, selectable due to AND support |
| 293 | * @scan_bbt: [REPLACEABLE] function to scan bad block table |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 294 | * @eccmode: [BOARDSPECIFIC] mode of ecc, see defines |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 295 | * @eccsize: [INTERN] databytes used per ecc-calculation |
| 296 | * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step |
| 297 | * @eccsteps: [INTERN] number of ecc calculation steps per page |
| 298 | * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress |
| 300 | * @state: [INTERN] the current state of the NAND device |
| 301 | * @page_shift: [INTERN] number of address bits in a page (column address bits) |
| 302 | * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock |
| 303 | * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry |
| 304 | * @chip_shift: [INTERN] number of address bits in one chip |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 305 | * @data_buf: [INTERN] internal buffer for one page + oob |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 306 | * @oob_buf: [INTERN] oob buffer for one eraseblock |
| 307 | * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized |
| 308 | * @data_poi: [INTERN] pointer to a data buffer |
| 309 | * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about |
| 310 | * special functionality. See the defines for further explanation |
| 311 | * @badblockpos: [INTERN] position of the bad block marker in the oob area |
| 312 | * @numchips: [INTERN] number of physical chips |
| 313 | * @chipsize: [INTERN] the size of one chip for multichip arrays |
| 314 | * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 |
| 315 | * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf |
| 316 | * @autooob: [REPLACEABLE] the default (auto)placement scheme |
| 317 | * @bbt: [INTERN] bad block table pointer |
| 318 | * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup |
| 319 | * @bbt_md: [REPLACEABLE] bad block table mirror descriptor |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 320 | * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan |
Thomas Gleixner | a36ed29 | 2006-05-23 11:37:03 +0200 | [diff] [blame] | 321 | * @controller: [REPLACEABLE] a pointer to a hardware controller structure |
| 322 | * which is shared among multiple independend devices |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 323 | * @priv: [OPTIONAL] pointer to private chip date |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 324 | * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 325 | * (determine if errors are correctable) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 326 | */ |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 327 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 328 | struct nand_chip { |
| 329 | void __iomem *IO_ADDR_R; |
| 330 | void __iomem *IO_ADDR_W; |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 331 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 332 | u_char (*read_byte)(struct mtd_info *mtd); |
| 333 | void (*write_byte)(struct mtd_info *mtd, u_char byte); |
| 334 | u16 (*read_word)(struct mtd_info *mtd); |
| 335 | void (*write_word)(struct mtd_info *mtd, u16 word); |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 336 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 337 | void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len); |
| 338 | void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len); |
| 339 | int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len); |
| 340 | void (*select_chip)(struct mtd_info *mtd, int chip); |
| 341 | int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); |
| 342 | int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); |
| 343 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
| 344 | int (*dev_ready)(struct mtd_info *mtd); |
| 345 | void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); |
| 346 | int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state); |
| 347 | int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code); |
| 348 | int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc); |
| 349 | void (*enable_hwecc)(struct mtd_info *mtd, int mode); |
| 350 | void (*erase_cmd)(struct mtd_info *mtd, int page); |
| 351 | int (*scan_bbt)(struct mtd_info *mtd); |
| 352 | int eccmode; |
| 353 | int eccsize; |
| 354 | int eccbytes; |
| 355 | int eccsteps; |
| 356 | int chip_delay; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | wait_queue_head_t wq; |
| 358 | nand_state_t state; |
| 359 | int page_shift; |
| 360 | int phys_erase_shift; |
| 361 | int bbt_erase_shift; |
| 362 | int chip_shift; |
| 363 | u_char *data_buf; |
| 364 | u_char *oob_buf; |
| 365 | int oobdirty; |
| 366 | u_char *data_poi; |
| 367 | unsigned int options; |
| 368 | int badblockpos; |
| 369 | int numchips; |
| 370 | unsigned long chipsize; |
| 371 | int pagemask; |
| 372 | int pagebuf; |
| 373 | struct nand_oobinfo *autooob; |
| 374 | uint8_t *bbt; |
| 375 | struct nand_bbt_descr *bbt_td; |
| 376 | struct nand_bbt_descr *bbt_md; |
| 377 | struct nand_bbt_descr *badblock_pattern; |
| 378 | struct nand_hw_control *controller; |
| 379 | void *priv; |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 380 | int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | }; |
| 382 | |
| 383 | /* |
| 384 | * NAND Flash Manufacturer ID Codes |
| 385 | */ |
| 386 | #define NAND_MFR_TOSHIBA 0x98 |
| 387 | #define NAND_MFR_SAMSUNG 0xec |
| 388 | #define NAND_MFR_FUJITSU 0x04 |
| 389 | #define NAND_MFR_NATIONAL 0x8f |
| 390 | #define NAND_MFR_RENESAS 0x07 |
| 391 | #define NAND_MFR_STMICRO 0x20 |
Nicolas S. Dade | f1f67a9 | 2005-05-24 01:46:34 -0700 | [diff] [blame] | 392 | #define NAND_MFR_HYNIX 0xad |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | |
| 394 | /** |
| 395 | * struct nand_flash_dev - NAND Flash Device ID Structure |
| 396 | * |
| 397 | * @name: Identify the device type |
| 398 | * @id: device ID code |
| 399 | * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 400 | * If the pagesize is 0, then the real pagesize |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | * and the eraseize are determined from the |
| 402 | * extended id bytes in the chip |
| 403 | * @erasesize: Size of an erase block in the flash device. |
| 404 | * @chipsize: Total chipsize in Mega Bytes |
| 405 | * @options: Bitfield to store chip relevant options |
| 406 | */ |
| 407 | struct nand_flash_dev { |
| 408 | char *name; |
| 409 | int id; |
| 410 | unsigned long pagesize; |
| 411 | unsigned long chipsize; |
| 412 | unsigned long erasesize; |
| 413 | unsigned long options; |
| 414 | }; |
| 415 | |
| 416 | /** |
| 417 | * struct nand_manufacturers - NAND Flash Manufacturer ID Structure |
| 418 | * @name: Manufacturer name |
| 419 | * @id: manufacturer ID code of device. |
| 420 | */ |
| 421 | struct nand_manufacturers { |
| 422 | int id; |
| 423 | char * name; |
| 424 | }; |
| 425 | |
| 426 | extern struct nand_flash_dev nand_flash_ids[]; |
| 427 | extern struct nand_manufacturers nand_manuf_ids[]; |
| 428 | |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 429 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 430 | * struct nand_bbt_descr - bad block table descriptor |
| 431 | * @options: options for this descriptor |
| 432 | * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE |
| 433 | * when bbt is searched, then we store the found bbts pages here. |
| 434 | * Its an array and supports up to 8 chips now |
| 435 | * @offs: offset of the pattern in the oob area of the page |
| 436 | * @veroffs: offset of the bbt version counter in the oob are of the page |
| 437 | * @version: version read from the bbt page during scan |
| 438 | * @len: length of the pattern, if 0 no pattern check is performed |
| 439 | * @maxblocks: maximum number of blocks to search for a bbt. This number of |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 440 | * blocks is reserved at the end of the device where the tables are |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | * written. |
| 442 | * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than |
| 443 | * bad) block in the stored bbt |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 444 | * @pattern: pattern to identify bad block table or factory marked good / |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 445 | * bad blocks, can be NULL, if len = 0 |
| 446 | * |
Thomas Gleixner | 61ecfa8 | 2005-11-07 11:15:31 +0000 | [diff] [blame] | 447 | * Descriptor for the bad block table marker and the descriptor for the |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 448 | * pattern which identifies good and bad blocks. The assumption is made |
| 449 | * that the pattern and the version count are always located in the oob area |
| 450 | * of the first block. |
| 451 | */ |
| 452 | struct nand_bbt_descr { |
| 453 | int options; |
| 454 | int pages[NAND_MAX_CHIPS]; |
| 455 | int offs; |
| 456 | int veroffs; |
| 457 | uint8_t version[NAND_MAX_CHIPS]; |
| 458 | int len; |
| 459 | int maxblocks; |
| 460 | int reserved_block_code; |
| 461 | uint8_t *pattern; |
| 462 | }; |
| 463 | |
| 464 | /* Options for the bad block table descriptors */ |
| 465 | |
| 466 | /* The number of bits used per block in the bbt on the device */ |
| 467 | #define NAND_BBT_NRBITS_MSK 0x0000000F |
| 468 | #define NAND_BBT_1BIT 0x00000001 |
| 469 | #define NAND_BBT_2BIT 0x00000002 |
| 470 | #define NAND_BBT_4BIT 0x00000004 |
| 471 | #define NAND_BBT_8BIT 0x00000008 |
| 472 | /* The bad block table is in the last good block of the device */ |
| 473 | #define NAND_BBT_LASTBLOCK 0x00000010 |
| 474 | /* The bbt is at the given page, else we must scan for the bbt */ |
| 475 | #define NAND_BBT_ABSPAGE 0x00000020 |
| 476 | /* The bbt is at the given page, else we must scan for the bbt */ |
| 477 | #define NAND_BBT_SEARCH 0x00000040 |
| 478 | /* bbt is stored per chip on multichip devices */ |
| 479 | #define NAND_BBT_PERCHIP 0x00000080 |
| 480 | /* bbt has a version counter at offset veroffs */ |
| 481 | #define NAND_BBT_VERSION 0x00000100 |
| 482 | /* Create a bbt if none axists */ |
| 483 | #define NAND_BBT_CREATE 0x00000200 |
| 484 | /* Search good / bad pattern through all pages of a block */ |
| 485 | #define NAND_BBT_SCANALLPAGES 0x00000400 |
| 486 | /* Scan block empty during good / bad block scan */ |
| 487 | #define NAND_BBT_SCANEMPTY 0x00000800 |
| 488 | /* Write bbt if neccecary */ |
| 489 | #define NAND_BBT_WRITE 0x00001000 |
| 490 | /* Read and write back block contents when writing bbt */ |
| 491 | #define NAND_BBT_SAVECONTENT 0x00002000 |
| 492 | /* Search good / bad pattern on the first and the second page */ |
| 493 | #define NAND_BBT_SCAN2NDPAGE 0x00004000 |
| 494 | |
| 495 | /* The maximum number of blocks to scan for a bbt */ |
| 496 | #define NAND_BBT_SCAN_MAXBLOCKS 4 |
| 497 | |
| 498 | extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd); |
| 499 | extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs); |
| 500 | extern int nand_default_bbt (struct mtd_info *mtd); |
| 501 | extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt); |
| 502 | extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt); |
David A. Marlin | 068e3c0 | 2005-01-24 03:07:46 +0000 | [diff] [blame] | 503 | extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, |
| 504 | size_t * retlen, u_char * buf, u_char * oob_buf, |
| 505 | struct nand_oobinfo *oobsel, int flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 506 | |
| 507 | /* |
| 508 | * Constants for oob configuration |
| 509 | */ |
| 510 | #define NAND_SMALL_BADBLOCK_POS 5 |
| 511 | #define NAND_LARGE_BADBLOCK_POS 0 |
| 512 | |
Thomas Gleixner | 41796c2 | 2006-05-23 11:38:59 +0200 | [diff] [blame^] | 513 | /** |
| 514 | * struct platform_nand_chip - chip level device structure |
| 515 | * |
| 516 | * @nr_chips: max. number of chips to scan for |
| 517 | * @chip_offs: chip number offset |
| 518 | * @nr_partitions: number of partitions pointed to be partitoons (or zero) |
| 519 | * @partitions: mtd partition list |
| 520 | * @chip_delay: R/B delay value in us |
| 521 | * @options: Option flags, e.g. 16bit buswidth |
| 522 | * @priv: hardware controller specific settings |
| 523 | */ |
| 524 | struct platform_nand_chip { |
| 525 | int nr_chips; |
| 526 | int chip_offset; |
| 527 | int nr_partitions; |
| 528 | struct mtd_partition *partitions; |
| 529 | int chip_delay; |
| 530 | unsigned int options; |
| 531 | void *priv; |
| 532 | }; |
| 533 | |
| 534 | /** |
| 535 | * struct platform_nand_ctrl - controller level device structure |
| 536 | * |
| 537 | * @hwcontrol: platform specific hardware control structure |
| 538 | * @dev_ready: platform specific function to read ready/busy pin |
| 539 | * @select_chip: platform specific chip select function |
| 540 | * @priv_data: private data to transport driver specific settings |
| 541 | * |
| 542 | * All fields are optional and depend on the hardware driver requirements |
| 543 | */ |
| 544 | struct platform_nand_ctrl { |
| 545 | void (*hwcontrol)(struct mtd_info *mtd, int cmd); |
| 546 | int (*dev_ready)(struct mtd_info *mtd); |
| 547 | void (*select_chip)(struct mtd_info *mtd, int chip); |
| 548 | void *priv; |
| 549 | }; |
| 550 | |
| 551 | /* Some helpers to access the data structures */ |
| 552 | static inline |
| 553 | struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) |
| 554 | { |
| 555 | struct nand_chip *chip = mtd->priv; |
| 556 | |
| 557 | return chip->priv; |
| 558 | } |
| 559 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 560 | #endif /* __LINUX_MTD_NAND_H */ |