blob: 41b7b6dc1d0d1ff32a0be15c2c394d000195a6a8 [file] [log] [blame]
SAN People73a59c12006-01-09 17:05:41 +00001/*
Andrew Victor9d041262007-02-05 11:42:07 +01002 * linux/arch/arm/mach-at91/at91rm9200_time.c
SAN People73a59c12006-01-09 17:05:41 +00003 *
4 * Copyright (C) 2003 SAN People
5 * Copyright (C) 2003 ATMEL
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
David Brownell5e802df2007-07-31 01:41:26 +010022#include <linux/kernel.h>
SAN People73a59c12006-01-09 17:05:41 +000023#include <linux/interrupt.h>
Thomas Gleixner07d265d2006-07-01 23:01:50 +010024#include <linux/irq.h>
David Brownell5e802df2007-07-31 01:41:26 +010025#include <linux/clockchips.h>
Joachim Eastwood9fce85c2012-04-04 19:15:15 +020026#include <linux/export.h>
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010027#include <linux/mfd/syscon.h>
28#include <linux/mfd/syscon/atmel-st.h>
Joachim Eastwood454c46d2012-10-28 18:31:07 +000029#include <linux/of_irq.h>
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010030#include <linux/regmap.h>
SAN People73a59c12006-01-09 17:05:41 +000031
Andrew Victor963151f2006-06-19 15:23:41 +010032static unsigned long last_crtr;
David Brownell5e802df2007-07-31 01:41:26 +010033static u32 irqmask;
34static struct clock_event_device clkevt;
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010035static struct regmap *regmap_st;
Andrew Victor963151f2006-06-19 15:23:41 +010036
Alexandre Belloni0afb46b2015-03-13 11:54:37 +010037#define AT91_SLOW_CLOCK 32768
Jean-Christophe PLAGNIOL-VILLARD2f5893c2011-10-16 18:17:09 +080038#define RM9200_TIMER_LATCH ((AT91_SLOW_CLOCK + HZ/2) / HZ)
39
SAN People73a59c12006-01-09 17:05:41 +000040/*
David Brownell5e802df2007-07-31 01:41:26 +010041 * The ST_CRTR is updated asynchronously to the master clock ... but
42 * the updates as seen by the CPU don't seem to be strictly monotonic.
43 * Waiting until we read the same value twice avoids glitching.
SAN People73a59c12006-01-09 17:05:41 +000044 */
David Brownell5e802df2007-07-31 01:41:26 +010045static inline unsigned long read_CRTR(void)
46{
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010047 unsigned int x1, x2;
SAN People73a59c12006-01-09 17:05:41 +000048
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010049 regmap_read(regmap_st, AT91_ST_CRTR, &x1);
SAN People73a59c12006-01-09 17:05:41 +000050 do {
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010051 regmap_read(regmap_st, AT91_ST_CRTR, &x2);
David Brownell5e802df2007-07-31 01:41:26 +010052 if (x1 == x2)
53 break;
54 x1 = x2;
55 } while (1);
SAN People73a59c12006-01-09 17:05:41 +000056 return x1;
57}
58
59/*
SAN People73a59c12006-01-09 17:05:41 +000060 * IRQ handler for the timer.
61 */
Linus Torvalds0cd61b62006-10-06 10:53:39 -070062static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id)
SAN People73a59c12006-01-09 17:05:41 +000063{
Alexandre Belloniadf2edf2015-03-12 13:07:32 +010064 u32 sr;
65
66 regmap_read(regmap_st, AT91_ST_SR, &sr);
67 sr &= irqmask;
SAN People73a59c12006-01-09 17:05:41 +000068
Uwe Kleine-König501d7032009-09-21 09:30:09 +020069 /*
70 * irqs should be disabled here, but as the irq is shared they are only
71 * guaranteed to be off if the timer irq is registered first.
72 */
73 WARN_ON_ONCE(!irqs_disabled());
74
David Brownell5e802df2007-07-31 01:41:26 +010075 /* simulate "oneshot" timer with alarm */
76 if (sr & AT91_ST_ALMS) {
77 clkevt.event_handler(&clkevt);
SAN People73a59c12006-01-09 17:05:41 +000078 return IRQ_HANDLED;
79 }
David Brownell5e802df2007-07-31 01:41:26 +010080
81 /* periodic mode should handle delayed ticks */
82 if (sr & AT91_ST_PITS) {
83 u32 crtr = read_CRTR();
84
Jean-Christophe PLAGNIOL-VILLARD2f5893c2011-10-16 18:17:09 +080085 while (((crtr - last_crtr) & AT91_ST_CRTV) >= RM9200_TIMER_LATCH) {
86 last_crtr += RM9200_TIMER_LATCH;
David Brownell5e802df2007-07-31 01:41:26 +010087 clkevt.event_handler(&clkevt);
88 }
89 return IRQ_HANDLED;
90 }
91
92 /* this irq is shared ... */
93 return IRQ_NONE;
SAN People73a59c12006-01-09 17:05:41 +000094}
95
Magnus Damm8e196082009-04-21 12:24:00 -070096static cycle_t read_clk32k(struct clocksource *cs)
Andrew Victor2a6f9902006-06-19 15:26:50 +010097{
David Brownell5e802df2007-07-31 01:41:26 +010098 return read_CRTR();
Andrew Victor2a6f9902006-06-19 15:26:50 +010099}
100
David Brownell5e802df2007-07-31 01:41:26 +0100101static struct clocksource clk32k = {
102 .name = "32k_counter",
103 .rating = 150,
104 .read = read_clk32k,
105 .mask = CLOCKSOURCE_MASK(20),
David Brownell5e802df2007-07-31 01:41:26 +0100106 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
107};
108
Viresh Kumar8ab28232015-06-18 16:24:45 +0530109static void clkdev32k_disable_and_flush_irq(void)
David Brownell5e802df2007-07-31 01:41:26 +0100110{
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100111 unsigned int val;
112
David Brownell5e802df2007-07-31 01:41:26 +0100113 /* Disable and flush pending timer interrupts */
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100114 regmap_write(regmap_st, AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS);
115 regmap_read(regmap_st, AT91_ST_SR, &val);
David Brownell5e802df2007-07-31 01:41:26 +0100116 last_crtr = read_CRTR();
Viresh Kumar8ab28232015-06-18 16:24:45 +0530117}
118
119static int clkevt32k_shutdown(struct clock_event_device *evt)
120{
121 clkdev32k_disable_and_flush_irq();
122 irqmask = 0;
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100123 regmap_write(regmap_st, AT91_ST_IER, irqmask);
Viresh Kumar8ab28232015-06-18 16:24:45 +0530124 return 0;
125}
126
127static int clkevt32k_set_oneshot(struct clock_event_device *dev)
128{
129 clkdev32k_disable_and_flush_irq();
130
131 /*
132 * ALM for oneshot irqs, set by next_event()
133 * before 32 seconds have passed.
134 */
135 irqmask = AT91_ST_ALMS;
136 regmap_write(regmap_st, AT91_ST_RTAR, last_crtr);
137 regmap_write(regmap_st, AT91_ST_IER, irqmask);
138 return 0;
139}
140
141static int clkevt32k_set_periodic(struct clock_event_device *dev)
142{
143 clkdev32k_disable_and_flush_irq();
144
145 /* PIT for periodic irqs; fixed rate of 1/HZ */
146 irqmask = AT91_ST_PITS;
147 regmap_write(regmap_st, AT91_ST_PIMR, RM9200_TIMER_LATCH);
148 regmap_write(regmap_st, AT91_ST_IER, irqmask);
149 return 0;
David Brownell5e802df2007-07-31 01:41:26 +0100150}
151
152static int
153clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
154{
David Brownell5e802df2007-07-31 01:41:26 +0100155 u32 alm;
156 int status = 0;
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100157 unsigned int val;
David Brownell5e802df2007-07-31 01:41:26 +0100158
159 BUG_ON(delta < 2);
160
David Brownell5e802df2007-07-31 01:41:26 +0100161 /* The alarm IRQ uses absolute time (now+delta), not the relative
162 * time (delta) in our calling convention. Like all clockevents
163 * using such "match" hardware, we have a race to defend against.
164 *
165 * Our defense here is to have set up the clockevent device so the
166 * delta is at least two. That way we never end up writing RTAR
167 * with the value then held in CRTR ... which would mean the match
168 * wouldn't trigger until 32 seconds later, after CRTR wraps.
169 */
170 alm = read_CRTR();
171
172 /* Cancel any pending alarm; flush any pending IRQ */
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100173 regmap_write(regmap_st, AT91_ST_RTAR, alm);
174 regmap_read(regmap_st, AT91_ST_SR, &val);
David Brownell5e802df2007-07-31 01:41:26 +0100175
176 /* Schedule alarm by writing RTAR. */
177 alm += delta;
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100178 regmap_write(regmap_st, AT91_ST_RTAR, alm);
David Brownell5e802df2007-07-31 01:41:26 +0100179
David Brownell5e802df2007-07-31 01:41:26 +0100180 return status;
181}
182
183static struct clock_event_device clkevt = {
Viresh Kumar8ab28232015-06-18 16:24:45 +0530184 .name = "at91_tick",
185 .features = CLOCK_EVT_FEAT_PERIODIC |
186 CLOCK_EVT_FEAT_ONESHOT,
187 .rating = 150,
188 .set_next_event = clkevt32k_next_event,
189 .set_state_shutdown = clkevt32k_shutdown,
190 .set_state_periodic = clkevt32k_set_periodic,
191 .set_state_oneshot = clkevt32k_set_oneshot,
192 .tick_resume = clkevt32k_shutdown,
David Brownell5e802df2007-07-31 01:41:26 +0100193};
194
SAN People73a59c12006-01-09 17:05:41 +0000195/*
David Brownell5e802df2007-07-31 01:41:26 +0100196 * ST (system timer) module supports both clockevents and clocksource.
SAN People73a59c12006-01-09 17:05:41 +0000197 */
Alexandre Bellonibbfc97e2015-03-12 13:07:30 +0100198static void __init atmel_st_timer_init(struct device_node *node)
SAN People73a59c12006-01-09 17:05:41 +0000199{
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100200 unsigned int val;
Alexandre Belloni0afb46b2015-03-13 11:54:37 +0100201 int irq, ret;
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100202
203 regmap_st = syscon_node_to_regmap(node);
204 if (IS_ERR(regmap_st))
205 panic(pr_fmt("Unable to get regmap\n"));
Joachim Eastwood454c46d2012-10-28 18:31:07 +0000206
David Brownell5e802df2007-07-31 01:41:26 +0100207 /* Disable all timer interrupts, and clear any pending ones */
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100208 regmap_write(regmap_st, AT91_ST_IDR,
David Brownell5e802df2007-07-31 01:41:26 +0100209 AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100210 regmap_read(regmap_st, AT91_ST_SR, &val);
211
212 /* Get the interrupts property */
Alexandre Belloni0afb46b2015-03-13 11:54:37 +0100213 irq = irq_of_parse_and_map(node, 0);
214 if (!irq)
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100215 panic(pr_fmt("Unable to get IRQ from DT\n"));
SAN People73a59c12006-01-09 17:05:41 +0000216
Andrew Victor2a6f9902006-06-19 15:26:50 +0100217 /* Make IRQs happen for the system timer */
Alexandre Belloni0afb46b2015-03-13 11:54:37 +0100218 ret = request_irq(irq, at91rm9200_timer_interrupt,
219 IRQF_SHARED | IRQF_TIMER | IRQF_IRQPOLL,
220 "at91_tick", regmap_st);
221 if (ret)
222 panic(pr_fmt("Unable to setup IRQ\n"));
SAN People73a59c12006-01-09 17:05:41 +0000223
David Brownell5e802df2007-07-31 01:41:26 +0100224 /* The 32KiHz "Slow Clock" (tick every 30517.58 nanoseconds) is used
225 * directly for the clocksource and all clockevents, after adjusting
226 * its prescaler from the 1 Hz default.
227 */
Alexandre Belloniadf2edf2015-03-12 13:07:32 +0100228 regmap_write(regmap_st, AT91_ST_RTMR, 1);
SAN People73a59c12006-01-09 17:05:41 +0000229
David Brownell5e802df2007-07-31 01:41:26 +0100230 /* Setup timer clockevent, with minimum of two ticks (important!!) */
Rusty Russell320ab2b2008-12-13 21:20:26 +1030231 clkevt.cpumask = cpumask_of(0);
Uwe Kleine-König1c283532013-10-08 16:38:53 +0200232 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
233 2, AT91_ST_ALMV);
SAN People73a59c12006-01-09 17:05:41 +0000234
David Brownell5e802df2007-07-31 01:41:26 +0100235 /* register clocksource */
Russell King132b1632010-12-13 13:14:55 +0000236 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
Andrew Victor2a6f9902006-06-19 15:26:50 +0100237}
Alexandre Bellonibbfc97e2015-03-12 13:07:30 +0100238CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
239 atmel_st_timer_init);