Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> |
| 3 | * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation; either version 2 of the License, or |
| 8 | * (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/io.h> |
David Howells | ca4d3e67 | 2010-10-07 14:08:54 +0100 | [diff] [blame] | 22 | #include <linux/irq.h> |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 23 | |
| 24 | #include <asm/irq_cpu.h> |
| 25 | #include <asm/mipsregs.h> |
| 26 | #include <asm/mach-ar7/ar7.h> |
| 27 | |
| 28 | #define EXCEPT_OFFSET 0x80 |
| 29 | #define PACE_OFFSET 0xA0 |
| 30 | #define CHNLS_OFFSET 0x200 |
| 31 | |
| 32 | #define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) |
| 33 | #define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8) |
| 34 | #define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */ |
| 35 | #define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ |
| 36 | #define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */ |
| 37 | #define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */ |
| 38 | #define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */ |
| 39 | #define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */ |
| 40 | #define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */ |
| 41 | #define PIR_OFFSET (0x40) |
| 42 | #define MSR_OFFSET (0x44) |
| 43 | #define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */ |
| 44 | #define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */ |
| 45 | |
| 46 | #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) |
| 47 | |
| 48 | #define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4)) |
| 49 | |
| 50 | static int ar7_irq_base; |
| 51 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 52 | static void ar7_unmask_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 53 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 54 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 55 | REG(ESR_OFFSET(d->irq - ar7_irq_base))); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 56 | } |
| 57 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 58 | static void ar7_mask_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 59 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 60 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 61 | REG(ECR_OFFSET(d->irq - ar7_irq_base))); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 62 | } |
| 63 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 64 | static void ar7_ack_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 65 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 66 | writel(1 << ((d->irq - ar7_irq_base) % 32), |
| 67 | REG(CR_OFFSET(d->irq - ar7_irq_base))); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 68 | } |
| 69 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 70 | static void ar7_unmask_sec_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 71 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 72 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 73 | } |
| 74 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 75 | static void ar7_mask_sec_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 76 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 77 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 78 | } |
| 79 | |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 80 | static void ar7_ack_sec_irq(struct irq_data *d) |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 81 | { |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 82 | writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 83 | } |
| 84 | |
| 85 | static struct irq_chip ar7_irq_type = { |
| 86 | .name = "AR7", |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 87 | .irq_unmask = ar7_unmask_irq, |
| 88 | .irq_mask = ar7_mask_irq, |
| 89 | .irq_ack = ar7_ack_irq |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 90 | }; |
| 91 | |
| 92 | static struct irq_chip ar7_sec_irq_type = { |
| 93 | .name = "AR7", |
Thomas Gleixner | 41d735e | 2011-03-23 21:08:46 +0000 | [diff] [blame^] | 94 | .irq_unmask = ar7_unmask_sec_irq, |
| 95 | .irq_mask = ar7_mask_sec_irq, |
| 96 | .irq_ack = ar7_ack_sec_irq, |
Florian Fainelli | 7ca5dc1 | 2009-06-24 11:12:57 +0200 | [diff] [blame] | 97 | }; |
| 98 | |
| 99 | static struct irqaction ar7_cascade_action = { |
| 100 | .handler = no_action, |
| 101 | .name = "AR7 cascade interrupt" |
| 102 | }; |
| 103 | |
| 104 | static void __init ar7_irq_init(int base) |
| 105 | { |
| 106 | int i; |
| 107 | /* |
| 108 | * Disable interrupts and clear pending |
| 109 | */ |
| 110 | writel(0xffffffff, REG(ECR_OFFSET(0))); |
| 111 | writel(0xff, REG(ECR_OFFSET(32))); |
| 112 | writel(0xffffffff, REG(SEC_ECR_OFFSET)); |
| 113 | writel(0xffffffff, REG(CR_OFFSET(0))); |
| 114 | writel(0xff, REG(CR_OFFSET(32))); |
| 115 | writel(0xffffffff, REG(SEC_CR_OFFSET)); |
| 116 | |
| 117 | ar7_irq_base = base; |
| 118 | |
| 119 | for (i = 0; i < 40; i++) { |
| 120 | writel(i, REG(CHNL_OFFSET(i))); |
| 121 | /* Primary IRQ's */ |
| 122 | set_irq_chip_and_handler(base + i, &ar7_irq_type, |
| 123 | handle_level_irq); |
| 124 | /* Secondary IRQ's */ |
| 125 | if (i < 32) |
| 126 | set_irq_chip_and_handler(base + i + 40, |
| 127 | &ar7_sec_irq_type, |
| 128 | handle_level_irq); |
| 129 | } |
| 130 | |
| 131 | setup_irq(2, &ar7_cascade_action); |
| 132 | setup_irq(ar7_irq_base, &ar7_cascade_action); |
| 133 | set_c0_status(IE_IRQ0); |
| 134 | } |
| 135 | |
| 136 | void __init arch_init_irq(void) |
| 137 | { |
| 138 | mips_cpu_irq_init(); |
| 139 | ar7_irq_init(8); |
| 140 | } |
| 141 | |
| 142 | static void ar7_cascade(void) |
| 143 | { |
| 144 | u32 status; |
| 145 | int i, irq; |
| 146 | |
| 147 | /* Primary IRQ's */ |
| 148 | irq = readl(REG(PIR_OFFSET)) & 0x3f; |
| 149 | if (irq) { |
| 150 | do_IRQ(ar7_irq_base + irq); |
| 151 | return; |
| 152 | } |
| 153 | |
| 154 | /* Secondary IRQ's are cascaded through primary '0' */ |
| 155 | writel(1, REG(CR_OFFSET(irq))); |
| 156 | status = readl(REG(SEC_SR_OFFSET)); |
| 157 | for (i = 0; i < 32; i++) { |
| 158 | if (status & 1) { |
| 159 | do_IRQ(ar7_irq_base + i + 40); |
| 160 | return; |
| 161 | } |
| 162 | status >>= 1; |
| 163 | } |
| 164 | |
| 165 | spurious_interrupt(); |
| 166 | } |
| 167 | |
| 168 | asmlinkage void plat_irq_dispatch(void) |
| 169 | { |
| 170 | unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; |
| 171 | if (pending & STATUSF_IP7) /* cpu timer */ |
| 172 | do_IRQ(7); |
| 173 | else if (pending & STATUSF_IP2) /* int0 hardware line */ |
| 174 | ar7_cascade(); |
| 175 | else |
| 176 | spurious_interrupt(); |
| 177 | } |