blob: ad3d124a972db01d28daf9d870eddf209a648efd [file] [log] [blame]
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001/*
2 * Copyright (C) 2012 Avionic Design GmbH
Mikko Perttunenad926012016-12-14 13:16:11 +02003 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00004 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9
Mikko Perttunenad926012016-12-14 13:16:11 +020010#include <linux/bitops.h>
Thierry Reding776dc382013-10-14 14:43:22 +020011#include <linux/host1x.h>
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010012#include <linux/idr.h>
Thierry Redingdf06b752014-06-26 21:41:53 +020013#include <linux/iommu.h>
Thierry Reding776dc382013-10-14 14:43:22 +020014
Thierry Reding1503ca42014-11-24 17:41:23 +010015#include <drm/drm_atomic.h>
Thierry Reding07866962014-11-24 17:08:06 +010016#include <drm/drm_atomic_helper.h>
17
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000018#include "drm.h"
Arto Merilainende2ba662013-03-22 16:34:08 +020019#include "gem.h"
Thierry Redingd8f4a9e2012-11-15 21:28:22 +000020
21#define DRIVER_NAME "tegra"
22#define DRIVER_DESC "NVIDIA Tegra graphics"
23#define DRIVER_DATE "20120330"
24#define DRIVER_MAJOR 0
25#define DRIVER_MINOR 0
26#define DRIVER_PATCHLEVEL 0
27
Mikko Perttunenad926012016-12-14 13:16:11 +020028#define CARVEOUT_SZ SZ_64M
Dmitry Osipenko368f6222017-06-15 02:18:26 +030029#define CDMA_GATHER_FETCHES_MAX_NB 16383
Mikko Perttunenad926012016-12-14 13:16:11 +020030
Thierry Reding08943e62013-09-26 16:08:18 +020031struct tegra_drm_file {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +010032 struct idr contexts;
33 struct mutex lock;
Thierry Reding08943e62013-09-26 16:08:18 +020034};
35
Thierry Reding1503ca42014-11-24 17:41:23 +010036static void tegra_atomic_schedule(struct tegra_drm *tegra,
37 struct drm_atomic_state *state)
38{
39 tegra->commit.state = state;
40 schedule_work(&tegra->commit.work);
41}
42
43static void tegra_atomic_complete(struct tegra_drm *tegra,
44 struct drm_atomic_state *state)
45{
46 struct drm_device *drm = tegra->drm;
47
48 /*
49 * Everything below can be run asynchronously without the need to grab
50 * any modeset locks at all under one condition: It must be guaranteed
51 * that the asynchronous work has either been cancelled (if the driver
52 * supports it, which at least requires that the framebuffers get
53 * cleaned up with drm_atomic_helper_cleanup_planes()) or completed
54 * before the new state gets committed on the software side with
55 * drm_atomic_helper_swap_state().
56 *
57 * This scheme allows new atomic state updates to be prepared and
58 * checked in parallel to the asynchronous completion of the previous
59 * update. Which is important since compositors need to figure out the
60 * composition of the next frame right after having submitted the
61 * current layout.
62 */
63
Daniel Vetter1af434a2015-02-22 12:24:19 +010064 drm_atomic_helper_commit_modeset_disables(drm, state);
Daniel Vetter1af434a2015-02-22 12:24:19 +010065 drm_atomic_helper_commit_modeset_enables(drm, state);
Liu Ying2b58e982016-08-29 17:12:03 +080066 drm_atomic_helper_commit_planes(drm, state,
67 DRM_PLANE_COMMIT_ACTIVE_ONLY);
Thierry Reding1503ca42014-11-24 17:41:23 +010068
69 drm_atomic_helper_wait_for_vblanks(drm, state);
70
71 drm_atomic_helper_cleanup_planes(drm, state);
Chris Wilson08536952016-10-14 13:18:18 +010072 drm_atomic_state_put(state);
Thierry Reding1503ca42014-11-24 17:41:23 +010073}
74
75static void tegra_atomic_work(struct work_struct *work)
76{
77 struct tegra_drm *tegra = container_of(work, struct tegra_drm,
78 commit.work);
79
80 tegra_atomic_complete(tegra, tegra->commit.state);
81}
82
83static int tegra_atomic_commit(struct drm_device *drm,
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020084 struct drm_atomic_state *state, bool nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +010085{
86 struct tegra_drm *tegra = drm->dev_private;
87 int err;
88
89 err = drm_atomic_helper_prepare_planes(drm, state);
90 if (err)
91 return err;
92
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +020093 /* serialize outstanding nonblocking commits */
Thierry Reding1503ca42014-11-24 17:41:23 +010094 mutex_lock(&tegra->commit.lock);
95 flush_work(&tegra->commit.work);
96
97 /*
98 * This is the point of no return - everything below never fails except
99 * when the hw goes bonghits. Which means we can commit the new state on
100 * the software side now.
101 */
102
Daniel Vetter5e84c262016-06-10 00:06:32 +0200103 drm_atomic_helper_swap_state(state, true);
Thierry Reding1503ca42014-11-24 17:41:23 +0100104
Chris Wilson08536952016-10-14 13:18:18 +0100105 drm_atomic_state_get(state);
Maarten Lankhorst2dacdd72016-04-26 16:11:42 +0200106 if (nonblock)
Thierry Reding1503ca42014-11-24 17:41:23 +0100107 tegra_atomic_schedule(tegra, state);
108 else
109 tegra_atomic_complete(tegra, state);
110
111 mutex_unlock(&tegra->commit.lock);
112 return 0;
113}
114
Thierry Redingf9914212014-11-26 13:03:57 +0100115static const struct drm_mode_config_funcs tegra_drm_mode_funcs = {
116 .fb_create = tegra_fb_create,
Archit Tanejab110ef32015-10-27 13:40:59 +0530117#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Redingf9914212014-11-26 13:03:57 +0100118 .output_poll_changed = tegra_fb_output_poll_changed,
119#endif
Thierry Reding07866962014-11-24 17:08:06 +0100120 .atomic_check = drm_atomic_helper_check,
Thierry Reding1503ca42014-11-24 17:41:23 +0100121 .atomic_commit = tegra_atomic_commit,
Thierry Redingf9914212014-11-26 13:03:57 +0100122};
123
Thierry Reding776dc382013-10-14 14:43:22 +0200124static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000125{
Thierry Reding776dc382013-10-14 14:43:22 +0200126 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Reding386a2a72013-09-24 13:22:17 +0200127 struct tegra_drm *tegra;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000128 int err;
129
Thierry Reding776dc382013-10-14 14:43:22 +0200130 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
Thierry Reding386a2a72013-09-24 13:22:17 +0200131 if (!tegra)
Terje Bergstrom692e6d72013-03-22 16:34:07 +0200132 return -ENOMEM;
133
Thierry Redingdf06b752014-06-26 21:41:53 +0200134 if (iommu_present(&platform_bus_type)) {
Mikko Perttunenad926012016-12-14 13:16:11 +0200135 u64 carveout_start, carveout_end, gem_start, gem_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100136 struct iommu_domain_geometry *geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200137 unsigned long order;
Thierry Reding4553f732015-01-19 16:15:04 +0100138
Thierry Redingdf06b752014-06-26 21:41:53 +0200139 tegra->domain = iommu_domain_alloc(&platform_bus_type);
Dan Carpenterbf19b882014-12-04 14:00:35 +0300140 if (!tegra->domain) {
141 err = -ENOMEM;
Thierry Redingdf06b752014-06-26 21:41:53 +0200142 goto free;
143 }
144
Thierry Reding4553f732015-01-19 16:15:04 +0100145 geometry = &tegra->domain->geometry;
Mikko Perttunenad926012016-12-14 13:16:11 +0200146 gem_start = geometry->aperture_start;
147 gem_end = geometry->aperture_end - CARVEOUT_SZ;
148 carveout_start = gem_end + 1;
149 carveout_end = geometry->aperture_end;
Thierry Reding4553f732015-01-19 16:15:04 +0100150
Mikko Perttunenad926012016-12-14 13:16:11 +0200151 order = __ffs(tegra->domain->pgsize_bitmap);
152 init_iova_domain(&tegra->carveout.domain, 1UL << order,
153 carveout_start >> order,
154 carveout_end >> order);
155
156 tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
157 tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
158
159 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100160 mutex_init(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200161
162 DRM_DEBUG("IOMMU apertures:\n");
163 DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end);
164 DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start,
165 carveout_end);
Thierry Redingdf06b752014-06-26 21:41:53 +0200166 }
167
Thierry Reding386a2a72013-09-24 13:22:17 +0200168 mutex_init(&tegra->clients_lock);
169 INIT_LIST_HEAD(&tegra->clients);
Thierry Reding1503ca42014-11-24 17:41:23 +0100170
171 mutex_init(&tegra->commit.lock);
172 INIT_WORK(&tegra->commit.work, tegra_atomic_work);
173
Thierry Reding386a2a72013-09-24 13:22:17 +0200174 drm->dev_private = tegra;
175 tegra->drm = drm;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000176
177 drm_mode_config_init(drm);
178
Thierry Redingf9914212014-11-26 13:03:57 +0100179 drm->mode_config.min_width = 0;
180 drm->mode_config.min_height = 0;
181
182 drm->mode_config.max_width = 4096;
183 drm->mode_config.max_height = 4096;
184
Alexandre Courbot5e911442016-11-08 16:50:42 +0900185 drm->mode_config.allow_fb_modifiers = true;
186
Thierry Redingf9914212014-11-26 13:03:57 +0100187 drm->mode_config.funcs = &tegra_drm_mode_funcs;
188
Thierry Redinge2215322014-06-27 17:19:25 +0200189 err = tegra_drm_fb_prepare(drm);
190 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100191 goto config;
Thierry Redinge2215322014-06-27 17:19:25 +0200192
193 drm_kms_helper_poll_init(drm);
194
Thierry Reding776dc382013-10-14 14:43:22 +0200195 err = host1x_device_init(device);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000196 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100197 goto fbdev;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000198
Thierry Reding603f0cc2013-04-22 21:22:14 +0200199 /*
200 * We don't use the drm_irq_install() helpers provided by the DRM
201 * core, so we need to set this manually in order to allow the
202 * DRM_IOCTL_WAIT_VBLANK to operate correctly.
203 */
Ville Syrjälä44238432013-10-04 14:53:37 +0300204 drm->irq_enabled = true;
Thierry Reding603f0cc2013-04-22 21:22:14 +0200205
Thierry Reding42e9ce02015-01-28 14:43:05 +0100206 /* syncpoints are used for full 32-bit hardware VBLANK counters */
Thierry Reding42e9ce02015-01-28 14:43:05 +0100207 drm->max_vblank_count = 0xffffffff;
208
Thierry Reding6e5ff992012-11-28 11:45:47 +0100209 err = drm_vblank_init(drm, drm->mode_config.num_crtc);
210 if (err < 0)
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100211 goto device;
Thierry Reding6e5ff992012-11-28 11:45:47 +0100212
Thierry Reding31930d42015-07-02 17:04:06 +0200213 drm_mode_config_reset(drm);
214
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000215 err = tegra_drm_fb_init(drm);
216 if (err < 0)
Daniel Vetter00a91212017-05-24 16:52:08 +0200217 goto device;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000218
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000219 return 0;
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100220
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100221device:
222 host1x_device_exit(device);
223fbdev:
224 drm_kms_helper_poll_fini(drm);
225 tegra_drm_fb_free(drm);
226config:
227 drm_mode_config_cleanup(drm);
Thierry Redingdf06b752014-06-26 21:41:53 +0200228
229 if (tegra->domain) {
230 iommu_domain_free(tegra->domain);
231 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100232 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200233 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200234 }
235free:
Thierry Reding1d1e6fe2014-11-06 14:12:08 +0100236 kfree(tegra);
237 return err;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000238}
239
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200240static void tegra_drm_unload(struct drm_device *drm)
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000241{
Thierry Reding776dc382013-10-14 14:43:22 +0200242 struct host1x_device *device = to_host1x_device(drm->dev);
Thierry Redingdf06b752014-06-26 21:41:53 +0200243 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding776dc382013-10-14 14:43:22 +0200244 int err;
245
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000246 drm_kms_helper_poll_fini(drm);
247 tegra_drm_fb_exit(drm);
Thierry Redingf002abc2013-10-14 14:06:02 +0200248 drm_mode_config_cleanup(drm);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000249
Thierry Reding776dc382013-10-14 14:43:22 +0200250 err = host1x_device_exit(device);
251 if (err < 0)
Gabriel Krisman Bertazi11b3c202017-01-06 15:57:31 -0200252 return;
Thierry Reding776dc382013-10-14 14:43:22 +0200253
Thierry Redingdf06b752014-06-26 21:41:53 +0200254 if (tegra->domain) {
255 iommu_domain_free(tegra->domain);
256 drm_mm_takedown(&tegra->mm);
Thierry Reding347ad49d2017-03-09 20:04:56 +0100257 mutex_destroy(&tegra->mm_lock);
Mikko Perttunenad926012016-12-14 13:16:11 +0200258 put_iova_domain(&tegra->carveout.domain);
Thierry Redingdf06b752014-06-26 21:41:53 +0200259 }
260
Thierry Reding1053f4dd2014-11-04 16:17:55 +0100261 kfree(tegra);
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000262}
263
264static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
265{
Thierry Reding08943e62013-09-26 16:08:18 +0200266 struct tegra_drm_file *fpriv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200267
268 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
269 if (!fpriv)
270 return -ENOMEM;
271
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100272 idr_init(&fpriv->contexts);
273 mutex_init(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200274 filp->driver_priv = fpriv;
275
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000276 return 0;
277}
278
Thierry Redingc88c3632013-09-26 16:08:22 +0200279static void tegra_drm_context_free(struct tegra_drm_context *context)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200280{
281 context->client->ops->close_channel(context);
282 kfree(context);
283}
284
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000285static void tegra_drm_lastclose(struct drm_device *drm)
286{
Archit Tanejab110ef32015-10-27 13:40:59 +0530287#ifdef CONFIG_DRM_FBDEV_EMULATION
Thierry Reding386a2a72013-09-24 13:22:17 +0200288 struct tegra_drm *tegra = drm->dev_private;
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000289
Thierry Reding386a2a72013-09-24 13:22:17 +0200290 tegra_fbdev_restore_mode(tegra->fbdev);
Thierry Reding60c2f702013-10-31 13:28:50 +0100291#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000292}
293
Thierry Redingc40f0f12013-10-10 11:00:33 +0200294static struct host1x_bo *
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100295host1x_bo_lookup(struct drm_file *file, u32 handle)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200296{
297 struct drm_gem_object *gem;
298 struct tegra_bo *bo;
299
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100300 gem = drm_gem_object_lookup(file, handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200301 if (!gem)
302 return NULL;
303
Daniel Vettera07cdfe2015-11-23 10:32:48 +0100304 drm_gem_object_unreference_unlocked(gem);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200305
306 bo = to_tegra_bo(gem);
307 return &bo->base;
308}
309
Thierry Reding961e3be2014-06-10 10:25:00 +0200310static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
311 struct drm_tegra_reloc __user *src,
312 struct drm_device *drm,
313 struct drm_file *file)
314{
315 u32 cmdbuf, target;
316 int err;
317
318 err = get_user(cmdbuf, &src->cmdbuf.handle);
319 if (err < 0)
320 return err;
321
322 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
323 if (err < 0)
324 return err;
325
326 err = get_user(target, &src->target.handle);
327 if (err < 0)
328 return err;
329
David Ung31f40f82015-01-20 18:37:35 -0800330 err = get_user(dest->target.offset, &src->target.offset);
Thierry Reding961e3be2014-06-10 10:25:00 +0200331 if (err < 0)
332 return err;
333
334 err = get_user(dest->shift, &src->shift);
335 if (err < 0)
336 return err;
337
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100338 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf);
Thierry Reding961e3be2014-06-10 10:25:00 +0200339 if (!dest->cmdbuf.bo)
340 return -ENOENT;
341
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100342 dest->target.bo = host1x_bo_lookup(file, target);
Thierry Reding961e3be2014-06-10 10:25:00 +0200343 if (!dest->target.bo)
344 return -ENOENT;
345
346 return 0;
347}
348
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300349static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest,
350 struct drm_tegra_waitchk __user *src,
351 struct drm_file *file)
352{
353 u32 cmdbuf;
354 int err;
355
356 err = get_user(cmdbuf, &src->handle);
357 if (err < 0)
358 return err;
359
360 err = get_user(dest->offset, &src->offset);
361 if (err < 0)
362 return err;
363
364 err = get_user(dest->syncpt_id, &src->syncpt);
365 if (err < 0)
366 return err;
367
368 err = get_user(dest->thresh, &src->thresh);
369 if (err < 0)
370 return err;
371
372 dest->bo = host1x_bo_lookup(file, cmdbuf);
373 if (!dest->bo)
374 return -ENOENT;
375
376 return 0;
377}
378
Thierry Redingc40f0f12013-10-10 11:00:33 +0200379int tegra_drm_submit(struct tegra_drm_context *context,
380 struct drm_tegra_submit *args, struct drm_device *drm,
381 struct drm_file *file)
382{
383 unsigned int num_cmdbufs = args->num_cmdbufs;
384 unsigned int num_relocs = args->num_relocs;
385 unsigned int num_waitchks = args->num_waitchks;
386 struct drm_tegra_cmdbuf __user *cmdbufs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100387 (void __user *)(uintptr_t)args->cmdbufs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200388 struct drm_tegra_reloc __user *relocs =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100389 (void __user *)(uintptr_t)args->relocs;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200390 struct drm_tegra_waitchk __user *waitchks =
Thierry Redinga7ed68f2013-11-08 13:15:43 +0100391 (void __user *)(uintptr_t)args->waitchks;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200392 struct drm_tegra_syncpt syncpt;
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300393 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
394 struct host1x_syncpt *sp;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200395 struct host1x_job *job;
396 int err;
397
398 /* We don't yet support other than one syncpt_incr struct per submit */
399 if (args->num_syncpts != 1)
400 return -EINVAL;
401
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300402 /* We don't yet support waitchks */
403 if (args->num_waitchks != 0)
404 return -EINVAL;
405
Thierry Redingc40f0f12013-10-10 11:00:33 +0200406 job = host1x_job_alloc(context->channel, args->num_cmdbufs,
407 args->num_relocs, args->num_waitchks);
408 if (!job)
409 return -ENOMEM;
410
411 job->num_relocs = args->num_relocs;
412 job->num_waitchk = args->num_waitchks;
413 job->client = (u32)args->context;
414 job->class = context->client->base.class;
415 job->serialize = true;
416
417 while (num_cmdbufs) {
418 struct drm_tegra_cmdbuf cmdbuf;
419 struct host1x_bo *bo;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300420 struct tegra_bo *obj;
421 u64 offset;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200422
Dan Carpenter9a991602013-11-08 13:07:37 +0300423 if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) {
424 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200425 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300426 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200427
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300428 /*
429 * The maximum number of CDMA gather fetches is 16383, a higher
430 * value means the words count is malformed.
431 */
432 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
433 err = -EINVAL;
434 goto fail;
435 }
436
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100437 bo = host1x_bo_lookup(file, cmdbuf.handle);
Thierry Redingc40f0f12013-10-10 11:00:33 +0200438 if (!bo) {
439 err = -ENOENT;
440 goto fail;
441 }
442
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300443 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
444 obj = host1x_to_tegra_bo(bo);
445
446 /*
447 * Gather buffer base address must be 4-bytes aligned,
448 * unaligned offset is malformed and cause commands stream
449 * corruption on the buffer address relocation.
450 */
451 if (offset & 3 || offset >= obj->gem.size) {
452 err = -EINVAL;
453 goto fail;
454 }
455
Thierry Redingc40f0f12013-10-10 11:00:33 +0200456 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
457 num_cmdbufs--;
458 cmdbufs++;
459 }
460
Thierry Reding961e3be2014-06-10 10:25:00 +0200461 /* copy and resolve relocations from submit */
Thierry Redingc40f0f12013-10-10 11:00:33 +0200462 while (num_relocs--) {
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300463 struct host1x_reloc *reloc;
464 struct tegra_bo *obj;
465
Thierry Reding961e3be2014-06-10 10:25:00 +0200466 err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs],
467 &relocs[num_relocs], drm,
468 file);
469 if (err < 0)
Thierry Redingc40f0f12013-10-10 11:00:33 +0200470 goto fail;
Dmitry Osipenko368f6222017-06-15 02:18:26 +0300471
472 reloc = &job->relocarray[num_relocs];
473 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
474
475 /*
476 * The unaligned cmdbuf offset will cause an unaligned write
477 * during of the relocations patching, corrupting the commands
478 * stream.
479 */
480 if (reloc->cmdbuf.offset & 3 ||
481 reloc->cmdbuf.offset >= obj->gem.size) {
482 err = -EINVAL;
483 goto fail;
484 }
485
486 obj = host1x_to_tegra_bo(reloc->target.bo);
487
488 if (reloc->target.offset >= obj->gem.size) {
489 err = -EINVAL;
490 goto fail;
491 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200492 }
493
Dmitry Osipenkod0fbbdf2017-06-15 02:18:27 +0300494 /* copy and resolve waitchks from submit */
495 while (num_waitchks--) {
496 struct host1x_waitchk *wait = &job->waitchk[num_waitchks];
497 struct tegra_bo *obj;
498
499 err = host1x_waitchk_copy_from_user(wait,
500 &waitchks[num_waitchks],
501 file);
502 if (err < 0)
503 goto fail;
504
505 obj = host1x_to_tegra_bo(wait->bo);
506
507 /*
508 * The unaligned offset will cause an unaligned write during
509 * of the waitchks patching, corrupting the commands stream.
510 */
511 if (wait->offset & 3 ||
512 wait->offset >= obj->gem.size) {
513 err = -EINVAL;
514 goto fail;
515 }
Dan Carpenter9a991602013-11-08 13:07:37 +0300516 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200517
Dan Carpenter9a991602013-11-08 13:07:37 +0300518 if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts,
519 sizeof(syncpt))) {
520 err = -EFAULT;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200521 goto fail;
Dan Carpenter9a991602013-11-08 13:07:37 +0300522 }
Thierry Redingc40f0f12013-10-10 11:00:33 +0200523
Dmitry Osipenkoe0b2ce02017-06-15 02:18:28 +0300524 /* check whether syncpoint ID is valid */
525 sp = host1x_syncpt_get(host1x, syncpt.id);
526 if (!sp) {
527 err = -ENOENT;
528 goto fail;
529 }
530
Thierry Redingc40f0f12013-10-10 11:00:33 +0200531 job->is_addr_reg = context->client->ops->is_addr_reg;
Dmitry Osipenko0f563a42017-06-15 02:18:37 +0300532 job->is_valid_class = context->client->ops->is_valid_class;
Thierry Redingc40f0f12013-10-10 11:00:33 +0200533 job->syncpt_incrs = syncpt.incrs;
534 job->syncpt_id = syncpt.id;
535 job->timeout = 10000;
536
537 if (args->timeout && args->timeout < 10000)
538 job->timeout = args->timeout;
539
540 err = host1x_job_pin(job, context->client->base.dev);
541 if (err)
542 goto fail;
543
544 err = host1x_job_submit(job);
545 if (err)
546 goto fail_submit;
547
548 args->fence = job->syncpt_end;
549
550 host1x_job_put(job);
551 return 0;
552
553fail_submit:
554 host1x_job_unpin(job);
555fail:
556 host1x_job_put(job);
557 return err;
558}
559
560
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200561#ifdef CONFIG_DRM_TEGRA_STAGING
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200562static int tegra_gem_create(struct drm_device *drm, void *data,
563 struct drm_file *file)
564{
565 struct drm_tegra_gem_create *args = data;
566 struct tegra_bo *bo;
567
Thierry Reding773af772013-10-04 22:34:01 +0200568 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200569 &args->handle);
570 if (IS_ERR(bo))
571 return PTR_ERR(bo);
572
573 return 0;
574}
575
576static int tegra_gem_mmap(struct drm_device *drm, void *data,
577 struct drm_file *file)
578{
579 struct drm_tegra_gem_mmap *args = data;
580 struct drm_gem_object *gem;
581 struct tegra_bo *bo;
582
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100583 gem = drm_gem_object_lookup(file, args->handle);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200584 if (!gem)
585 return -EINVAL;
586
587 bo = to_tegra_bo(gem);
588
David Herrmann2bc7b0c2013-08-13 14:19:58 +0200589 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200590
Daniel Vetter11533302015-11-23 10:32:40 +0100591 drm_gem_object_unreference_unlocked(gem);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200592
593 return 0;
594}
595
596static int tegra_syncpt_read(struct drm_device *drm, void *data,
597 struct drm_file *file)
598{
Thierry Reding776dc382013-10-14 14:43:22 +0200599 struct host1x *host = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200600 struct drm_tegra_syncpt_read *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200601 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200602
Thierry Reding776dc382013-10-14 14:43:22 +0200603 sp = host1x_syncpt_get(host, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200604 if (!sp)
605 return -EINVAL;
606
607 args->value = host1x_syncpt_read_min(sp);
608 return 0;
609}
610
611static int tegra_syncpt_incr(struct drm_device *drm, void *data,
612 struct drm_file *file)
613{
Thierry Reding776dc382013-10-14 14:43:22 +0200614 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200615 struct drm_tegra_syncpt_incr *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200616 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200617
Thierry Reding776dc382013-10-14 14:43:22 +0200618 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200619 if (!sp)
620 return -EINVAL;
621
Arto Merilainenebae30b2013-05-29 13:26:08 +0300622 return host1x_syncpt_incr(sp);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200623}
624
625static int tegra_syncpt_wait(struct drm_device *drm, void *data,
626 struct drm_file *file)
627{
Thierry Reding776dc382013-10-14 14:43:22 +0200628 struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200629 struct drm_tegra_syncpt_wait *args = data;
Thierry Reding776dc382013-10-14 14:43:22 +0200630 struct host1x_syncpt *sp;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200631
Thierry Reding776dc382013-10-14 14:43:22 +0200632 sp = host1x_syncpt_get(host1x, args->id);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200633 if (!sp)
634 return -EINVAL;
635
636 return host1x_syncpt_wait(sp, args->thresh, args->timeout,
637 &args->value);
638}
639
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100640static int tegra_client_open(struct tegra_drm_file *fpriv,
641 struct tegra_drm_client *client,
642 struct tegra_drm_context *context)
643{
644 int err;
645
646 err = client->ops->open_channel(client, context);
647 if (err < 0)
648 return err;
649
Dmitry Osipenkod6c153e2017-06-15 02:18:25 +0300650 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100651 if (err < 0) {
652 client->ops->close_channel(context);
653 return err;
654 }
655
656 context->client = client;
657 context->id = err;
658
659 return 0;
660}
661
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200662static int tegra_open_channel(struct drm_device *drm, void *data,
663 struct drm_file *file)
664{
Thierry Reding08943e62013-09-26 16:08:18 +0200665 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding386a2a72013-09-24 13:22:17 +0200666 struct tegra_drm *tegra = drm->dev_private;
667 struct drm_tegra_open_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200668 struct tegra_drm_context *context;
Thierry Reding53fa7f72013-09-24 15:35:40 +0200669 struct tegra_drm_client *client;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200670 int err = -ENODEV;
671
672 context = kzalloc(sizeof(*context), GFP_KERNEL);
673 if (!context)
674 return -ENOMEM;
675
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100676 mutex_lock(&fpriv->lock);
677
Thierry Reding776dc382013-10-14 14:43:22 +0200678 list_for_each_entry(client, &tegra->clients, list)
Thierry Reding53fa7f72013-09-24 15:35:40 +0200679 if (client->base.class == args->client) {
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100680 err = tegra_client_open(fpriv, client, context);
681 if (err < 0)
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200682 break;
683
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100684 args->context = context->id;
685 break;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200686 }
687
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100688 if (err < 0)
689 kfree(context);
690
691 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200692 return err;
693}
694
695static int tegra_close_channel(struct drm_device *drm, void *data,
696 struct drm_file *file)
697{
Thierry Reding08943e62013-09-26 16:08:18 +0200698 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding776dc382013-10-14 14:43:22 +0200699 struct drm_tegra_close_channel *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200700 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100701 int err = 0;
Thierry Redingc88c3632013-09-26 16:08:22 +0200702
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100703 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200704
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300705 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100706 if (!context) {
707 err = -EINVAL;
708 goto unlock;
709 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200710
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100711 idr_remove(&fpriv->contexts, context->id);
Thierry Redingc88c3632013-09-26 16:08:22 +0200712 tegra_drm_context_free(context);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200713
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100714unlock:
715 mutex_unlock(&fpriv->lock);
716 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200717}
718
719static int tegra_get_syncpt(struct drm_device *drm, void *data,
720 struct drm_file *file)
721{
Thierry Reding08943e62013-09-26 16:08:18 +0200722 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200723 struct drm_tegra_get_syncpt *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200724 struct tegra_drm_context *context;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200725 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100726 int err = 0;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200727
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100728 mutex_lock(&fpriv->lock);
Thierry Redingc88c3632013-09-26 16:08:22 +0200729
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300730 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100731 if (!context) {
732 err = -ENODEV;
733 goto unlock;
734 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200735
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100736 if (args->index >= context->client->base.num_syncpts) {
737 err = -EINVAL;
738 goto unlock;
739 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200740
Thierry Reding53fa7f72013-09-24 15:35:40 +0200741 syncpt = context->client->base.syncpts[args->index];
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200742 args->id = host1x_syncpt_id(syncpt);
743
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100744unlock:
745 mutex_unlock(&fpriv->lock);
746 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200747}
748
749static int tegra_submit(struct drm_device *drm, void *data,
750 struct drm_file *file)
751{
Thierry Reding08943e62013-09-26 16:08:18 +0200752 struct tegra_drm_file *fpriv = file->driver_priv;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200753 struct drm_tegra_submit *args = data;
Thierry Redingc88c3632013-09-26 16:08:22 +0200754 struct tegra_drm_context *context;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100755 int err;
Thierry Redingc88c3632013-09-26 16:08:22 +0200756
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100757 mutex_lock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200758
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300759 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100760 if (!context) {
761 err = -ENODEV;
762 goto unlock;
763 }
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200764
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100765 err = context->client->ops->submit(context, args, drm, file);
766
767unlock:
768 mutex_unlock(&fpriv->lock);
769 return err;
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200770}
Arto Merilainenc54a1692013-10-14 15:21:54 +0300771
772static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
773 struct drm_file *file)
774{
775 struct tegra_drm_file *fpriv = file->driver_priv;
776 struct drm_tegra_get_syncpt_base *args = data;
777 struct tegra_drm_context *context;
778 struct host1x_syncpt_base *base;
779 struct host1x_syncpt *syncpt;
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100780 int err = 0;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300781
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100782 mutex_lock(&fpriv->lock);
Arto Merilainenc54a1692013-10-14 15:21:54 +0300783
Dmitry Osipenko1066a892017-06-15 02:18:24 +0300784 context = idr_find(&fpriv->contexts, args->context);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100785 if (!context) {
786 err = -ENODEV;
787 goto unlock;
788 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300789
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100790 if (args->syncpt >= context->client->base.num_syncpts) {
791 err = -EINVAL;
792 goto unlock;
793 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300794
795 syncpt = context->client->base.syncpts[args->syncpt];
796
797 base = host1x_syncpt_get_base(syncpt);
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100798 if (!base) {
799 err = -ENXIO;
800 goto unlock;
801 }
Arto Merilainenc54a1692013-10-14 15:21:54 +0300802
803 args->id = host1x_syncpt_base_id(base);
804
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100805unlock:
806 mutex_unlock(&fpriv->lock);
807 return err;
Arto Merilainenc54a1692013-10-14 15:21:54 +0300808}
Thierry Reding7678d712014-06-03 14:56:57 +0200809
810static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
811 struct drm_file *file)
812{
813 struct drm_tegra_gem_set_tiling *args = data;
814 enum tegra_bo_tiling_mode mode;
815 struct drm_gem_object *gem;
816 unsigned long value = 0;
817 struct tegra_bo *bo;
818
819 switch (args->mode) {
820 case DRM_TEGRA_GEM_TILING_MODE_PITCH:
821 mode = TEGRA_BO_TILING_MODE_PITCH;
822
823 if (args->value != 0)
824 return -EINVAL;
825
826 break;
827
828 case DRM_TEGRA_GEM_TILING_MODE_TILED:
829 mode = TEGRA_BO_TILING_MODE_TILED;
830
831 if (args->value != 0)
832 return -EINVAL;
833
834 break;
835
836 case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
837 mode = TEGRA_BO_TILING_MODE_BLOCK;
838
839 if (args->value > 5)
840 return -EINVAL;
841
842 value = args->value;
843 break;
844
845 default:
846 return -EINVAL;
847 }
848
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100849 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200850 if (!gem)
851 return -ENOENT;
852
853 bo = to_tegra_bo(gem);
854
855 bo->tiling.mode = mode;
856 bo->tiling.value = value;
857
Daniel Vetter11533302015-11-23 10:32:40 +0100858 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200859
860 return 0;
861}
862
863static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
864 struct drm_file *file)
865{
866 struct drm_tegra_gem_get_tiling *args = data;
867 struct drm_gem_object *gem;
868 struct tegra_bo *bo;
869 int err = 0;
870
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100871 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7678d712014-06-03 14:56:57 +0200872 if (!gem)
873 return -ENOENT;
874
875 bo = to_tegra_bo(gem);
876
877 switch (bo->tiling.mode) {
878 case TEGRA_BO_TILING_MODE_PITCH:
879 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
880 args->value = 0;
881 break;
882
883 case TEGRA_BO_TILING_MODE_TILED:
884 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
885 args->value = 0;
886 break;
887
888 case TEGRA_BO_TILING_MODE_BLOCK:
889 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
890 args->value = bo->tiling.value;
891 break;
892
893 default:
894 err = -EINVAL;
895 break;
896 }
897
Daniel Vetter11533302015-11-23 10:32:40 +0100898 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7678d712014-06-03 14:56:57 +0200899
900 return err;
901}
Thierry Reding7b129082014-06-10 12:04:03 +0200902
903static int tegra_gem_set_flags(struct drm_device *drm, void *data,
904 struct drm_file *file)
905{
906 struct drm_tegra_gem_set_flags *args = data;
907 struct drm_gem_object *gem;
908 struct tegra_bo *bo;
909
910 if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
911 return -EINVAL;
912
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100913 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200914 if (!gem)
915 return -ENOENT;
916
917 bo = to_tegra_bo(gem);
918 bo->flags = 0;
919
920 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
921 bo->flags |= TEGRA_BO_BOTTOM_UP;
922
Daniel Vetter11533302015-11-23 10:32:40 +0100923 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200924
925 return 0;
926}
927
928static int tegra_gem_get_flags(struct drm_device *drm, void *data,
929 struct drm_file *file)
930{
931 struct drm_tegra_gem_get_flags *args = data;
932 struct drm_gem_object *gem;
933 struct tegra_bo *bo;
934
Chris Wilsona8ad0bd2016-05-09 11:04:54 +0100935 gem = drm_gem_object_lookup(file, args->handle);
Thierry Reding7b129082014-06-10 12:04:03 +0200936 if (!gem)
937 return -ENOENT;
938
939 bo = to_tegra_bo(gem);
940 args->flags = 0;
941
942 if (bo->flags & TEGRA_BO_BOTTOM_UP)
943 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
944
Daniel Vetter11533302015-11-23 10:32:40 +0100945 drm_gem_object_unreference_unlocked(gem);
Thierry Reding7b129082014-06-10 12:04:03 +0200946
947 return 0;
948}
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200949#endif
950
Rob Clarkbaa70942013-08-02 13:27:49 -0400951static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200952#ifdef CONFIG_DRM_TEGRA_STAGING
Daniel Vetterf8c47142015-09-08 13:56:30 +0200953 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0),
954 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0),
955 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0),
956 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0),
957 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0),
958 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0),
959 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0),
960 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0),
961 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0),
962 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0),
963 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0),
964 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0),
965 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0),
966 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0),
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200967#endif
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000968};
969
970static const struct file_operations tegra_drm_fops = {
971 .owner = THIS_MODULE,
972 .open = drm_open,
973 .release = drm_release,
974 .unlocked_ioctl = drm_ioctl,
Arto Merilainende2ba662013-03-22 16:34:08 +0200975 .mmap = tegra_drm_mmap,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000976 .poll = drm_poll,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000977 .read = drm_read,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000978 .compat_ioctl = drm_compat_ioctl,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +0000979 .llseek = noop_llseek,
980};
981
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100982static int tegra_drm_context_cleanup(int id, void *p, void *data)
983{
984 struct tegra_drm_context *context = p;
985
986 tegra_drm_context_free(context);
987
988 return 0;
989}
990
Daniel Vetterbda0ecc2017-05-08 10:26:31 +0200991static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
Thierry Reding3c03c462012-11-28 12:00:18 +0100992{
Thierry Reding08943e62013-09-26 16:08:18 +0200993 struct tegra_drm_file *fpriv = file->driver_priv;
Thierry Reding3c03c462012-11-28 12:00:18 +0100994
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100995 mutex_lock(&fpriv->lock);
996 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL);
997 mutex_unlock(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +0200998
Thierry Redingbdd2f9c2017-03-09 20:04:55 +0100999 idr_destroy(&fpriv->contexts);
1000 mutex_destroy(&fpriv->lock);
Terje Bergstromd43f81c2013-03-22 16:34:09 +02001001 kfree(fpriv);
Thierry Reding3c03c462012-11-28 12:00:18 +01001002}
1003
Thierry Redinge450fcc2013-02-13 16:13:16 +01001004#ifdef CONFIG_DEBUG_FS
1005static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
1006{
1007 struct drm_info_node *node = (struct drm_info_node *)s->private;
1008 struct drm_device *drm = node->minor->dev;
1009 struct drm_framebuffer *fb;
1010
1011 mutex_lock(&drm->mode_config.fb_lock);
1012
1013 list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
1014 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
Ville Syrjäläb00c6002016-12-14 23:31:35 +02001015 fb->base.id, fb->width, fb->height,
1016 fb->format->depth,
Ville Syrjälä272725c2016-12-14 23:32:20 +02001017 fb->format->cpp[0] * 8,
Dave Airlie747a5982016-04-15 15:10:35 +10001018 drm_framebuffer_read_refcount(fb));
Thierry Redinge450fcc2013-02-13 16:13:16 +01001019 }
1020
1021 mutex_unlock(&drm->mode_config.fb_lock);
1022
1023 return 0;
1024}
1025
Thierry Reding28c23372015-01-23 09:16:03 +01001026static int tegra_debugfs_iova(struct seq_file *s, void *data)
1027{
1028 struct drm_info_node *node = (struct drm_info_node *)s->private;
1029 struct drm_device *drm = node->minor->dev;
1030 struct tegra_drm *tegra = drm->dev_private;
Daniel Vetterb5c37142016-12-29 12:09:24 +01001031 struct drm_printer p = drm_seq_file_printer(s);
Thierry Reding28c23372015-01-23 09:16:03 +01001032
Thierry Reding347ad49d2017-03-09 20:04:56 +01001033 mutex_lock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001034 drm_mm_print(&tegra->mm, &p);
Thierry Reding347ad49d2017-03-09 20:04:56 +01001035 mutex_unlock(&tegra->mm_lock);
Daniel Vetterb5c37142016-12-29 12:09:24 +01001036
1037 return 0;
Thierry Reding28c23372015-01-23 09:16:03 +01001038}
1039
Thierry Redinge450fcc2013-02-13 16:13:16 +01001040static struct drm_info_list tegra_debugfs_list[] = {
1041 { "framebuffers", tegra_debugfs_framebuffers, 0 },
Thierry Reding28c23372015-01-23 09:16:03 +01001042 { "iova", tegra_debugfs_iova, 0 },
Thierry Redinge450fcc2013-02-13 16:13:16 +01001043};
1044
1045static int tegra_debugfs_init(struct drm_minor *minor)
1046{
1047 return drm_debugfs_create_files(tegra_debugfs_list,
1048 ARRAY_SIZE(tegra_debugfs_list),
1049 minor->debugfs_root, minor);
1050}
Thierry Redinge450fcc2013-02-13 16:13:16 +01001051#endif
1052
Thierry Reding9b57f5f2013-11-08 13:17:14 +01001053static struct drm_driver tegra_drm_driver = {
Thierry Redingad906592015-09-24 18:38:09 +02001054 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
1055 DRIVER_ATOMIC,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001056 .load = tegra_drm_load,
1057 .unload = tegra_drm_unload,
1058 .open = tegra_drm_open,
Daniel Vetterbda0ecc2017-05-08 10:26:31 +02001059 .postclose = tegra_drm_postclose,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001060 .lastclose = tegra_drm_lastclose,
1061
Thierry Redinge450fcc2013-02-13 16:13:16 +01001062#if defined(CONFIG_DEBUG_FS)
1063 .debugfs_init = tegra_debugfs_init,
Thierry Redinge450fcc2013-02-13 16:13:16 +01001064#endif
1065
Daniel Vetter1ddbdbd2016-04-26 19:30:00 +02001066 .gem_free_object_unlocked = tegra_bo_free_object,
Arto Merilainende2ba662013-03-22 16:34:08 +02001067 .gem_vm_ops = &tegra_bo_vm_ops,
Thierry Reding38003912013-12-12 10:00:43 +01001068
1069 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1070 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1071 .gem_prime_export = tegra_gem_prime_export,
1072 .gem_prime_import = tegra_gem_prime_import,
1073
Arto Merilainende2ba662013-03-22 16:34:08 +02001074 .dumb_create = tegra_bo_dumb_create,
1075 .dumb_map_offset = tegra_bo_dumb_map_offset,
Daniel Vetter43387b32013-07-16 09:12:04 +02001076 .dumb_destroy = drm_gem_dumb_destroy,
Thierry Redingd8f4a9e2012-11-15 21:28:22 +00001077
1078 .ioctls = tegra_drm_ioctls,
1079 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
1080 .fops = &tegra_drm_fops,
1081
1082 .name = DRIVER_NAME,
1083 .desc = DRIVER_DESC,
1084 .date = DRIVER_DATE,
1085 .major = DRIVER_MAJOR,
1086 .minor = DRIVER_MINOR,
1087 .patchlevel = DRIVER_PATCHLEVEL,
1088};
Thierry Reding776dc382013-10-14 14:43:22 +02001089
1090int tegra_drm_register_client(struct tegra_drm *tegra,
1091 struct tegra_drm_client *client)
1092{
1093 mutex_lock(&tegra->clients_lock);
1094 list_add_tail(&client->list, &tegra->clients);
1095 mutex_unlock(&tegra->clients_lock);
1096
1097 return 0;
1098}
1099
1100int tegra_drm_unregister_client(struct tegra_drm *tegra,
1101 struct tegra_drm_client *client)
1102{
1103 mutex_lock(&tegra->clients_lock);
1104 list_del_init(&client->list);
1105 mutex_unlock(&tegra->clients_lock);
1106
1107 return 0;
1108}
1109
Mikko Perttunenad926012016-12-14 13:16:11 +02001110void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size,
1111 dma_addr_t *dma)
1112{
1113 struct iova *alloc;
1114 void *virt;
1115 gfp_t gfp;
1116 int err;
1117
1118 if (tegra->domain)
1119 size = iova_align(&tegra->carveout.domain, size);
1120 else
1121 size = PAGE_ALIGN(size);
1122
1123 gfp = GFP_KERNEL | __GFP_ZERO;
1124 if (!tegra->domain) {
1125 /*
1126 * Many units only support 32-bit addresses, even on 64-bit
1127 * SoCs. If there is no IOMMU to translate into a 32-bit IO
1128 * virtual address space, force allocations to be in the
1129 * lower 32-bit range.
1130 */
1131 gfp |= GFP_DMA;
1132 }
1133
1134 virt = (void *)__get_free_pages(gfp, get_order(size));
1135 if (!virt)
1136 return ERR_PTR(-ENOMEM);
1137
1138 if (!tegra->domain) {
1139 /*
1140 * If IOMMU is disabled, devices address physical memory
1141 * directly.
1142 */
1143 *dma = virt_to_phys(virt);
1144 return virt;
1145 }
1146
1147 alloc = alloc_iova(&tegra->carveout.domain,
1148 size >> tegra->carveout.shift,
1149 tegra->carveout.limit, true);
1150 if (!alloc) {
1151 err = -EBUSY;
1152 goto free_pages;
1153 }
1154
1155 *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1156 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1157 size, IOMMU_READ | IOMMU_WRITE);
1158 if (err < 0)
1159 goto free_iova;
1160
1161 return virt;
1162
1163free_iova:
1164 __free_iova(&tegra->carveout.domain, alloc);
1165free_pages:
1166 free_pages((unsigned long)virt, get_order(size));
1167
1168 return ERR_PTR(err);
1169}
1170
1171void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1172 dma_addr_t dma)
1173{
1174 if (tegra->domain)
1175 size = iova_align(&tegra->carveout.domain, size);
1176 else
1177 size = PAGE_ALIGN(size);
1178
1179 if (tegra->domain) {
1180 iommu_unmap(tegra->domain, dma, size);
1181 free_iova(&tegra->carveout.domain,
1182 iova_pfn(&tegra->carveout.domain, dma));
1183 }
1184
1185 free_pages((unsigned long)virt, get_order(size));
1186}
1187
Thierry Reding9910f5c2014-05-22 09:57:15 +02001188static int host1x_drm_probe(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001189{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001190 struct drm_driver *driver = &tegra_drm_driver;
1191 struct drm_device *drm;
1192 int err;
1193
1194 drm = drm_dev_alloc(driver, &dev->dev);
Tom Gundersen0f288602016-09-21 16:59:19 +02001195 if (IS_ERR(drm))
1196 return PTR_ERR(drm);
Thierry Reding9910f5c2014-05-22 09:57:15 +02001197
Thierry Reding9910f5c2014-05-22 09:57:15 +02001198 dev_set_drvdata(&dev->dev, drm);
1199
1200 err = drm_dev_register(drm, 0);
1201 if (err < 0)
1202 goto unref;
1203
Thierry Reding9910f5c2014-05-22 09:57:15 +02001204 return 0;
1205
1206unref:
1207 drm_dev_unref(drm);
1208 return err;
Thierry Reding776dc382013-10-14 14:43:22 +02001209}
1210
Thierry Reding9910f5c2014-05-22 09:57:15 +02001211static int host1x_drm_remove(struct host1x_device *dev)
Thierry Reding776dc382013-10-14 14:43:22 +02001212{
Thierry Reding9910f5c2014-05-22 09:57:15 +02001213 struct drm_device *drm = dev_get_drvdata(&dev->dev);
1214
1215 drm_dev_unregister(drm);
1216 drm_dev_unref(drm);
Thierry Reding776dc382013-10-14 14:43:22 +02001217
1218 return 0;
1219}
1220
Thierry Reding359ae682014-12-18 17:15:25 +01001221#ifdef CONFIG_PM_SLEEP
1222static int host1x_drm_suspend(struct device *dev)
1223{
1224 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001225 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001226
1227 drm_kms_helper_poll_disable(drm);
Thierry Reding986c58d2015-08-11 13:11:49 +02001228 tegra_drm_fb_suspend(drm);
1229
1230 tegra->state = drm_atomic_helper_suspend(drm);
1231 if (IS_ERR(tegra->state)) {
1232 tegra_drm_fb_resume(drm);
1233 drm_kms_helper_poll_enable(drm);
1234 return PTR_ERR(tegra->state);
1235 }
Thierry Reding359ae682014-12-18 17:15:25 +01001236
1237 return 0;
1238}
1239
1240static int host1x_drm_resume(struct device *dev)
1241{
1242 struct drm_device *drm = dev_get_drvdata(dev);
Thierry Reding986c58d2015-08-11 13:11:49 +02001243 struct tegra_drm *tegra = drm->dev_private;
Thierry Reding359ae682014-12-18 17:15:25 +01001244
Thierry Reding986c58d2015-08-11 13:11:49 +02001245 drm_atomic_helper_resume(drm, tegra->state);
1246 tegra_drm_fb_resume(drm);
Thierry Reding359ae682014-12-18 17:15:25 +01001247 drm_kms_helper_poll_enable(drm);
1248
1249 return 0;
1250}
1251#endif
1252
Thierry Redinga13f1dc2015-08-11 13:22:44 +02001253static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1254 host1x_drm_resume);
Thierry Reding359ae682014-12-18 17:15:25 +01001255
Thierry Reding776dc382013-10-14 14:43:22 +02001256static const struct of_device_id host1x_drm_subdevs[] = {
1257 { .compatible = "nvidia,tegra20-dc", },
1258 { .compatible = "nvidia,tegra20-hdmi", },
1259 { .compatible = "nvidia,tegra20-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001260 { .compatible = "nvidia,tegra20-gr3d", },
Thierry Reding776dc382013-10-14 14:43:22 +02001261 { .compatible = "nvidia,tegra30-dc", },
1262 { .compatible = "nvidia,tegra30-hdmi", },
1263 { .compatible = "nvidia,tegra30-gr2d", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001264 { .compatible = "nvidia,tegra30-gr3d", },
Thierry Redingdec72732013-09-03 08:45:46 +02001265 { .compatible = "nvidia,tegra114-dsi", },
Mikko Perttunen7d1d28a2013-09-30 16:54:47 +02001266 { .compatible = "nvidia,tegra114-hdmi", },
Thierry Reding5f60ed02013-02-28 08:08:01 +01001267 { .compatible = "nvidia,tegra114-gr3d", },
Thierry Reding8620fc62013-12-12 11:03:59 +01001268 { .compatible = "nvidia,tegra124-dc", },
Thierry Reding6b6b6042013-11-15 16:06:05 +01001269 { .compatible = "nvidia,tegra124-sor", },
Thierry Redingfb7be702013-11-15 16:07:32 +01001270 { .compatible = "nvidia,tegra124-hdmi", },
Thierry Reding7d338582015-04-10 11:35:21 +02001271 { .compatible = "nvidia,tegra124-dsi", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001272 { .compatible = "nvidia,tegra124-vic", },
Thierry Redingc06c7932015-04-10 11:35:21 +02001273 { .compatible = "nvidia,tegra132-dsi", },
Thierry Reding5b4f5162015-03-27 10:31:58 +01001274 { .compatible = "nvidia,tegra210-dc", },
Thierry Redingddfb4062015-04-08 16:56:22 +02001275 { .compatible = "nvidia,tegra210-dsi", },
Thierry Reding3309ac82015-07-30 10:32:46 +02001276 { .compatible = "nvidia,tegra210-sor", },
Thierry Reding459cc2c2015-07-30 10:34:24 +02001277 { .compatible = "nvidia,tegra210-sor1", },
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001278 { .compatible = "nvidia,tegra210-vic", },
Thierry Reding776dc382013-10-14 14:43:22 +02001279 { /* sentinel */ }
1280};
1281
1282static struct host1x_driver host1x_drm_driver = {
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001283 .driver = {
1284 .name = "drm",
Thierry Reding359ae682014-12-18 17:15:25 +01001285 .pm = &host1x_drm_pm_ops,
Thierry Redingf4c5cf82014-12-18 15:29:14 +01001286 },
Thierry Reding776dc382013-10-14 14:43:22 +02001287 .probe = host1x_drm_probe,
1288 .remove = host1x_drm_remove,
1289 .subdevs = host1x_drm_subdevs,
1290};
1291
Thierry Reding473112e2015-09-10 16:07:14 +02001292static struct platform_driver * const drivers[] = {
1293 &tegra_dc_driver,
1294 &tegra_hdmi_driver,
1295 &tegra_dsi_driver,
1296 &tegra_dpaux_driver,
1297 &tegra_sor_driver,
1298 &tegra_gr2d_driver,
1299 &tegra_gr3d_driver,
Arto Merilainen0ae797a2016-12-14 13:16:13 +02001300 &tegra_vic_driver,
Thierry Reding473112e2015-09-10 16:07:14 +02001301};
1302
Thierry Reding776dc382013-10-14 14:43:22 +02001303static int __init host1x_drm_init(void)
1304{
1305 int err;
1306
1307 err = host1x_driver_register(&host1x_drm_driver);
1308 if (err < 0)
1309 return err;
1310
Thierry Reding473112e2015-09-10 16:07:14 +02001311 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001312 if (err < 0)
1313 goto unregister_host1x;
1314
Thierry Reding776dc382013-10-14 14:43:22 +02001315 return 0;
1316
Thierry Reding776dc382013-10-14 14:43:22 +02001317unregister_host1x:
1318 host1x_driver_unregister(&host1x_drm_driver);
1319 return err;
1320}
1321module_init(host1x_drm_init);
1322
1323static void __exit host1x_drm_exit(void)
1324{
Thierry Reding473112e2015-09-10 16:07:14 +02001325 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
Thierry Reding776dc382013-10-14 14:43:22 +02001326 host1x_driver_unregister(&host1x_drm_driver);
1327}
1328module_exit(host1x_drm_exit);
1329
1330MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1331MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1332MODULE_LICENSE("GPL v2");