Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Avionic Design GmbH |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 3 | * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 10 | #include <linux/bitops.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 11 | #include <linux/host1x.h> |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 12 | #include <linux/idr.h> |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 13 | #include <linux/iommu.h> |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 14 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 15 | #include <drm/drm_atomic.h> |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 16 | #include <drm/drm_atomic_helper.h> |
| 17 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 18 | #include "drm.h" |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 19 | #include "gem.h" |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 20 | |
| 21 | #define DRIVER_NAME "tegra" |
| 22 | #define DRIVER_DESC "NVIDIA Tegra graphics" |
| 23 | #define DRIVER_DATE "20120330" |
| 24 | #define DRIVER_MAJOR 0 |
| 25 | #define DRIVER_MINOR 0 |
| 26 | #define DRIVER_PATCHLEVEL 0 |
| 27 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 28 | #define CARVEOUT_SZ SZ_64M |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 29 | #define CDMA_GATHER_FETCHES_MAX_NB 16383 |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 30 | |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 31 | struct tegra_drm_file { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 32 | struct idr contexts; |
| 33 | struct mutex lock; |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 34 | }; |
| 35 | |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 36 | static void tegra_atomic_schedule(struct tegra_drm *tegra, |
| 37 | struct drm_atomic_state *state) |
| 38 | { |
| 39 | tegra->commit.state = state; |
| 40 | schedule_work(&tegra->commit.work); |
| 41 | } |
| 42 | |
| 43 | static void tegra_atomic_complete(struct tegra_drm *tegra, |
| 44 | struct drm_atomic_state *state) |
| 45 | { |
| 46 | struct drm_device *drm = tegra->drm; |
| 47 | |
| 48 | /* |
| 49 | * Everything below can be run asynchronously without the need to grab |
| 50 | * any modeset locks at all under one condition: It must be guaranteed |
| 51 | * that the asynchronous work has either been cancelled (if the driver |
| 52 | * supports it, which at least requires that the framebuffers get |
| 53 | * cleaned up with drm_atomic_helper_cleanup_planes()) or completed |
| 54 | * before the new state gets committed on the software side with |
| 55 | * drm_atomic_helper_swap_state(). |
| 56 | * |
| 57 | * This scheme allows new atomic state updates to be prepared and |
| 58 | * checked in parallel to the asynchronous completion of the previous |
| 59 | * update. Which is important since compositors need to figure out the |
| 60 | * composition of the next frame right after having submitted the |
| 61 | * current layout. |
| 62 | */ |
| 63 | |
Daniel Vetter | 1af434a | 2015-02-22 12:24:19 +0100 | [diff] [blame] | 64 | drm_atomic_helper_commit_modeset_disables(drm, state); |
Daniel Vetter | 1af434a | 2015-02-22 12:24:19 +0100 | [diff] [blame] | 65 | drm_atomic_helper_commit_modeset_enables(drm, state); |
Liu Ying | 2b58e98 | 2016-08-29 17:12:03 +0800 | [diff] [blame] | 66 | drm_atomic_helper_commit_planes(drm, state, |
| 67 | DRM_PLANE_COMMIT_ACTIVE_ONLY); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 68 | |
| 69 | drm_atomic_helper_wait_for_vblanks(drm, state); |
| 70 | |
| 71 | drm_atomic_helper_cleanup_planes(drm, state); |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 72 | drm_atomic_state_put(state); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static void tegra_atomic_work(struct work_struct *work) |
| 76 | { |
| 77 | struct tegra_drm *tegra = container_of(work, struct tegra_drm, |
| 78 | commit.work); |
| 79 | |
| 80 | tegra_atomic_complete(tegra, tegra->commit.state); |
| 81 | } |
| 82 | |
| 83 | static int tegra_atomic_commit(struct drm_device *drm, |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 84 | struct drm_atomic_state *state, bool nonblock) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 85 | { |
| 86 | struct tegra_drm *tegra = drm->dev_private; |
| 87 | int err; |
| 88 | |
| 89 | err = drm_atomic_helper_prepare_planes(drm, state); |
| 90 | if (err) |
| 91 | return err; |
| 92 | |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 93 | /* serialize outstanding nonblocking commits */ |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 94 | mutex_lock(&tegra->commit.lock); |
| 95 | flush_work(&tegra->commit.work); |
| 96 | |
| 97 | /* |
| 98 | * This is the point of no return - everything below never fails except |
| 99 | * when the hw goes bonghits. Which means we can commit the new state on |
| 100 | * the software side now. |
| 101 | */ |
| 102 | |
Daniel Vetter | 5e84c26 | 2016-06-10 00:06:32 +0200 | [diff] [blame] | 103 | drm_atomic_helper_swap_state(state, true); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 104 | |
Chris Wilson | 0853695 | 2016-10-14 13:18:18 +0100 | [diff] [blame] | 105 | drm_atomic_state_get(state); |
Maarten Lankhorst | 2dacdd7 | 2016-04-26 16:11:42 +0200 | [diff] [blame] | 106 | if (nonblock) |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 107 | tegra_atomic_schedule(tegra, state); |
| 108 | else |
| 109 | tegra_atomic_complete(tegra, state); |
| 110 | |
| 111 | mutex_unlock(&tegra->commit.lock); |
| 112 | return 0; |
| 113 | } |
| 114 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 115 | static const struct drm_mode_config_funcs tegra_drm_mode_funcs = { |
| 116 | .fb_create = tegra_fb_create, |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 117 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 118 | .output_poll_changed = tegra_fb_output_poll_changed, |
| 119 | #endif |
Thierry Reding | 0786696 | 2014-11-24 17:08:06 +0100 | [diff] [blame] | 120 | .atomic_check = drm_atomic_helper_check, |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 121 | .atomic_commit = tegra_atomic_commit, |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 122 | }; |
| 123 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 124 | static int tegra_drm_load(struct drm_device *drm, unsigned long flags) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 125 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 126 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 127 | struct tegra_drm *tegra; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 128 | int err; |
| 129 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 130 | tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 131 | if (!tegra) |
Terje Bergstrom | 692e6d7 | 2013-03-22 16:34:07 +0200 | [diff] [blame] | 132 | return -ENOMEM; |
| 133 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 134 | if (iommu_present(&platform_bus_type)) { |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 135 | u64 carveout_start, carveout_end, gem_start, gem_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 136 | struct iommu_domain_geometry *geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 137 | unsigned long order; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 138 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 139 | tegra->domain = iommu_domain_alloc(&platform_bus_type); |
Dan Carpenter | bf19b88 | 2014-12-04 14:00:35 +0300 | [diff] [blame] | 140 | if (!tegra->domain) { |
| 141 | err = -ENOMEM; |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 142 | goto free; |
| 143 | } |
| 144 | |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 145 | geometry = &tegra->domain->geometry; |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 146 | gem_start = geometry->aperture_start; |
| 147 | gem_end = geometry->aperture_end - CARVEOUT_SZ; |
| 148 | carveout_start = gem_end + 1; |
| 149 | carveout_end = geometry->aperture_end; |
Thierry Reding | 4553f73 | 2015-01-19 16:15:04 +0100 | [diff] [blame] | 150 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 151 | order = __ffs(tegra->domain->pgsize_bitmap); |
| 152 | init_iova_domain(&tegra->carveout.domain, 1UL << order, |
| 153 | carveout_start >> order, |
| 154 | carveout_end >> order); |
| 155 | |
| 156 | tegra->carveout.shift = iova_shift(&tegra->carveout.domain); |
| 157 | tegra->carveout.limit = carveout_end >> tegra->carveout.shift; |
| 158 | |
| 159 | drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 160 | mutex_init(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 161 | |
| 162 | DRM_DEBUG("IOMMU apertures:\n"); |
| 163 | DRM_DEBUG(" GEM: %#llx-%#llx\n", gem_start, gem_end); |
| 164 | DRM_DEBUG(" Carveout: %#llx-%#llx\n", carveout_start, |
| 165 | carveout_end); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 166 | } |
| 167 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 168 | mutex_init(&tegra->clients_lock); |
| 169 | INIT_LIST_HEAD(&tegra->clients); |
Thierry Reding | 1503ca4 | 2014-11-24 17:41:23 +0100 | [diff] [blame] | 170 | |
| 171 | mutex_init(&tegra->commit.lock); |
| 172 | INIT_WORK(&tegra->commit.work, tegra_atomic_work); |
| 173 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 174 | drm->dev_private = tegra; |
| 175 | tegra->drm = drm; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 176 | |
| 177 | drm_mode_config_init(drm); |
| 178 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 179 | drm->mode_config.min_width = 0; |
| 180 | drm->mode_config.min_height = 0; |
| 181 | |
| 182 | drm->mode_config.max_width = 4096; |
| 183 | drm->mode_config.max_height = 4096; |
| 184 | |
Alexandre Courbot | 5e91144 | 2016-11-08 16:50:42 +0900 | [diff] [blame] | 185 | drm->mode_config.allow_fb_modifiers = true; |
| 186 | |
Thierry Reding | f991421 | 2014-11-26 13:03:57 +0100 | [diff] [blame] | 187 | drm->mode_config.funcs = &tegra_drm_mode_funcs; |
| 188 | |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 189 | err = tegra_drm_fb_prepare(drm); |
| 190 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 191 | goto config; |
Thierry Reding | e221532 | 2014-06-27 17:19:25 +0200 | [diff] [blame] | 192 | |
| 193 | drm_kms_helper_poll_init(drm); |
| 194 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 195 | err = host1x_device_init(device); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 196 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 197 | goto fbdev; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 198 | |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 199 | /* |
| 200 | * We don't use the drm_irq_install() helpers provided by the DRM |
| 201 | * core, so we need to set this manually in order to allow the |
| 202 | * DRM_IOCTL_WAIT_VBLANK to operate correctly. |
| 203 | */ |
Ville Syrjälä | 4423843 | 2013-10-04 14:53:37 +0300 | [diff] [blame] | 204 | drm->irq_enabled = true; |
Thierry Reding | 603f0cc | 2013-04-22 21:22:14 +0200 | [diff] [blame] | 205 | |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 206 | /* syncpoints are used for full 32-bit hardware VBLANK counters */ |
Thierry Reding | 42e9ce0 | 2015-01-28 14:43:05 +0100 | [diff] [blame] | 207 | drm->max_vblank_count = 0xffffffff; |
| 208 | |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 209 | err = drm_vblank_init(drm, drm->mode_config.num_crtc); |
| 210 | if (err < 0) |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 211 | goto device; |
Thierry Reding | 6e5ff99 | 2012-11-28 11:45:47 +0100 | [diff] [blame] | 212 | |
Thierry Reding | 31930d4 | 2015-07-02 17:04:06 +0200 | [diff] [blame] | 213 | drm_mode_config_reset(drm); |
| 214 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 215 | err = tegra_drm_fb_init(drm); |
| 216 | if (err < 0) |
Daniel Vetter | 00a9121 | 2017-05-24 16:52:08 +0200 | [diff] [blame] | 217 | goto device; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 218 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 219 | return 0; |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 220 | |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 221 | device: |
| 222 | host1x_device_exit(device); |
| 223 | fbdev: |
| 224 | drm_kms_helper_poll_fini(drm); |
| 225 | tegra_drm_fb_free(drm); |
| 226 | config: |
| 227 | drm_mode_config_cleanup(drm); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 228 | |
| 229 | if (tegra->domain) { |
| 230 | iommu_domain_free(tegra->domain); |
| 231 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 232 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 233 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 234 | } |
| 235 | free: |
Thierry Reding | 1d1e6fe | 2014-11-06 14:12:08 +0100 | [diff] [blame] | 236 | kfree(tegra); |
| 237 | return err; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 238 | } |
| 239 | |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 240 | static void tegra_drm_unload(struct drm_device *drm) |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 241 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 242 | struct host1x_device *device = to_host1x_device(drm->dev); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 243 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 244 | int err; |
| 245 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 246 | drm_kms_helper_poll_fini(drm); |
| 247 | tegra_drm_fb_exit(drm); |
Thierry Reding | f002abc | 2013-10-14 14:06:02 +0200 | [diff] [blame] | 248 | drm_mode_config_cleanup(drm); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 249 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 250 | err = host1x_device_exit(device); |
| 251 | if (err < 0) |
Gabriel Krisman Bertazi | 11b3c20 | 2017-01-06 15:57:31 -0200 | [diff] [blame] | 252 | return; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 253 | |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 254 | if (tegra->domain) { |
| 255 | iommu_domain_free(tegra->domain); |
| 256 | drm_mm_takedown(&tegra->mm); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 257 | mutex_destroy(&tegra->mm_lock); |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 258 | put_iova_domain(&tegra->carveout.domain); |
Thierry Reding | df06b75 | 2014-06-26 21:41:53 +0200 | [diff] [blame] | 259 | } |
| 260 | |
Thierry Reding | 1053f4dd | 2014-11-04 16:17:55 +0100 | [diff] [blame] | 261 | kfree(tegra); |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 262 | } |
| 263 | |
| 264 | static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) |
| 265 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 266 | struct tegra_drm_file *fpriv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 267 | |
| 268 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); |
| 269 | if (!fpriv) |
| 270 | return -ENOMEM; |
| 271 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 272 | idr_init(&fpriv->contexts); |
| 273 | mutex_init(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 274 | filp->driver_priv = fpriv; |
| 275 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 276 | return 0; |
| 277 | } |
| 278 | |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 279 | static void tegra_drm_context_free(struct tegra_drm_context *context) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 280 | { |
| 281 | context->client->ops->close_channel(context); |
| 282 | kfree(context); |
| 283 | } |
| 284 | |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 285 | static void tegra_drm_lastclose(struct drm_device *drm) |
| 286 | { |
Archit Taneja | b110ef3 | 2015-10-27 13:40:59 +0530 | [diff] [blame] | 287 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 288 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 289 | |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 290 | tegra_fbdev_restore_mode(tegra->fbdev); |
Thierry Reding | 60c2f70 | 2013-10-31 13:28:50 +0100 | [diff] [blame] | 291 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 294 | static struct host1x_bo * |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 295 | host1x_bo_lookup(struct drm_file *file, u32 handle) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 296 | { |
| 297 | struct drm_gem_object *gem; |
| 298 | struct tegra_bo *bo; |
| 299 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 300 | gem = drm_gem_object_lookup(file, handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 301 | if (!gem) |
| 302 | return NULL; |
| 303 | |
Daniel Vetter | a07cdfe | 2015-11-23 10:32:48 +0100 | [diff] [blame] | 304 | drm_gem_object_unreference_unlocked(gem); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 305 | |
| 306 | bo = to_tegra_bo(gem); |
| 307 | return &bo->base; |
| 308 | } |
| 309 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 310 | static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, |
| 311 | struct drm_tegra_reloc __user *src, |
| 312 | struct drm_device *drm, |
| 313 | struct drm_file *file) |
| 314 | { |
| 315 | u32 cmdbuf, target; |
| 316 | int err; |
| 317 | |
| 318 | err = get_user(cmdbuf, &src->cmdbuf.handle); |
| 319 | if (err < 0) |
| 320 | return err; |
| 321 | |
| 322 | err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); |
| 323 | if (err < 0) |
| 324 | return err; |
| 325 | |
| 326 | err = get_user(target, &src->target.handle); |
| 327 | if (err < 0) |
| 328 | return err; |
| 329 | |
David Ung | 31f40f8 | 2015-01-20 18:37:35 -0800 | [diff] [blame] | 330 | err = get_user(dest->target.offset, &src->target.offset); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 331 | if (err < 0) |
| 332 | return err; |
| 333 | |
| 334 | err = get_user(dest->shift, &src->shift); |
| 335 | if (err < 0) |
| 336 | return err; |
| 337 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 338 | dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 339 | if (!dest->cmdbuf.bo) |
| 340 | return -ENOENT; |
| 341 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 342 | dest->target.bo = host1x_bo_lookup(file, target); |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 343 | if (!dest->target.bo) |
| 344 | return -ENOENT; |
| 345 | |
| 346 | return 0; |
| 347 | } |
| 348 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 349 | static int host1x_waitchk_copy_from_user(struct host1x_waitchk *dest, |
| 350 | struct drm_tegra_waitchk __user *src, |
| 351 | struct drm_file *file) |
| 352 | { |
| 353 | u32 cmdbuf; |
| 354 | int err; |
| 355 | |
| 356 | err = get_user(cmdbuf, &src->handle); |
| 357 | if (err < 0) |
| 358 | return err; |
| 359 | |
| 360 | err = get_user(dest->offset, &src->offset); |
| 361 | if (err < 0) |
| 362 | return err; |
| 363 | |
| 364 | err = get_user(dest->syncpt_id, &src->syncpt); |
| 365 | if (err < 0) |
| 366 | return err; |
| 367 | |
| 368 | err = get_user(dest->thresh, &src->thresh); |
| 369 | if (err < 0) |
| 370 | return err; |
| 371 | |
| 372 | dest->bo = host1x_bo_lookup(file, cmdbuf); |
| 373 | if (!dest->bo) |
| 374 | return -ENOENT; |
| 375 | |
| 376 | return 0; |
| 377 | } |
| 378 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 379 | int tegra_drm_submit(struct tegra_drm_context *context, |
| 380 | struct drm_tegra_submit *args, struct drm_device *drm, |
| 381 | struct drm_file *file) |
| 382 | { |
| 383 | unsigned int num_cmdbufs = args->num_cmdbufs; |
| 384 | unsigned int num_relocs = args->num_relocs; |
| 385 | unsigned int num_waitchks = args->num_waitchks; |
| 386 | struct drm_tegra_cmdbuf __user *cmdbufs = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 387 | (void __user *)(uintptr_t)args->cmdbufs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 388 | struct drm_tegra_reloc __user *relocs = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 389 | (void __user *)(uintptr_t)args->relocs; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 390 | struct drm_tegra_waitchk __user *waitchks = |
Thierry Reding | a7ed68f | 2013-11-08 13:15:43 +0100 | [diff] [blame] | 391 | (void __user *)(uintptr_t)args->waitchks; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 392 | struct drm_tegra_syncpt syncpt; |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 393 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
| 394 | struct host1x_syncpt *sp; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 395 | struct host1x_job *job; |
| 396 | int err; |
| 397 | |
| 398 | /* We don't yet support other than one syncpt_incr struct per submit */ |
| 399 | if (args->num_syncpts != 1) |
| 400 | return -EINVAL; |
| 401 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 402 | /* We don't yet support waitchks */ |
| 403 | if (args->num_waitchks != 0) |
| 404 | return -EINVAL; |
| 405 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 406 | job = host1x_job_alloc(context->channel, args->num_cmdbufs, |
| 407 | args->num_relocs, args->num_waitchks); |
| 408 | if (!job) |
| 409 | return -ENOMEM; |
| 410 | |
| 411 | job->num_relocs = args->num_relocs; |
| 412 | job->num_waitchk = args->num_waitchks; |
| 413 | job->client = (u32)args->context; |
| 414 | job->class = context->client->base.class; |
| 415 | job->serialize = true; |
| 416 | |
| 417 | while (num_cmdbufs) { |
| 418 | struct drm_tegra_cmdbuf cmdbuf; |
| 419 | struct host1x_bo *bo; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 420 | struct tegra_bo *obj; |
| 421 | u64 offset; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 422 | |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 423 | if (copy_from_user(&cmdbuf, cmdbufs, sizeof(cmdbuf))) { |
| 424 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 425 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 426 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 427 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 428 | /* |
| 429 | * The maximum number of CDMA gather fetches is 16383, a higher |
| 430 | * value means the words count is malformed. |
| 431 | */ |
| 432 | if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { |
| 433 | err = -EINVAL; |
| 434 | goto fail; |
| 435 | } |
| 436 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 437 | bo = host1x_bo_lookup(file, cmdbuf.handle); |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 438 | if (!bo) { |
| 439 | err = -ENOENT; |
| 440 | goto fail; |
| 441 | } |
| 442 | |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 443 | offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); |
| 444 | obj = host1x_to_tegra_bo(bo); |
| 445 | |
| 446 | /* |
| 447 | * Gather buffer base address must be 4-bytes aligned, |
| 448 | * unaligned offset is malformed and cause commands stream |
| 449 | * corruption on the buffer address relocation. |
| 450 | */ |
| 451 | if (offset & 3 || offset >= obj->gem.size) { |
| 452 | err = -EINVAL; |
| 453 | goto fail; |
| 454 | } |
| 455 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 456 | host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); |
| 457 | num_cmdbufs--; |
| 458 | cmdbufs++; |
| 459 | } |
| 460 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 461 | /* copy and resolve relocations from submit */ |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 462 | while (num_relocs--) { |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 463 | struct host1x_reloc *reloc; |
| 464 | struct tegra_bo *obj; |
| 465 | |
Thierry Reding | 961e3be | 2014-06-10 10:25:00 +0200 | [diff] [blame] | 466 | err = host1x_reloc_copy_from_user(&job->relocarray[num_relocs], |
| 467 | &relocs[num_relocs], drm, |
| 468 | file); |
| 469 | if (err < 0) |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 470 | goto fail; |
Dmitry Osipenko | 368f622 | 2017-06-15 02:18:26 +0300 | [diff] [blame] | 471 | |
| 472 | reloc = &job->relocarray[num_relocs]; |
| 473 | obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); |
| 474 | |
| 475 | /* |
| 476 | * The unaligned cmdbuf offset will cause an unaligned write |
| 477 | * during of the relocations patching, corrupting the commands |
| 478 | * stream. |
| 479 | */ |
| 480 | if (reloc->cmdbuf.offset & 3 || |
| 481 | reloc->cmdbuf.offset >= obj->gem.size) { |
| 482 | err = -EINVAL; |
| 483 | goto fail; |
| 484 | } |
| 485 | |
| 486 | obj = host1x_to_tegra_bo(reloc->target.bo); |
| 487 | |
| 488 | if (reloc->target.offset >= obj->gem.size) { |
| 489 | err = -EINVAL; |
| 490 | goto fail; |
| 491 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 492 | } |
| 493 | |
Dmitry Osipenko | d0fbbdf | 2017-06-15 02:18:27 +0300 | [diff] [blame] | 494 | /* copy and resolve waitchks from submit */ |
| 495 | while (num_waitchks--) { |
| 496 | struct host1x_waitchk *wait = &job->waitchk[num_waitchks]; |
| 497 | struct tegra_bo *obj; |
| 498 | |
| 499 | err = host1x_waitchk_copy_from_user(wait, |
| 500 | &waitchks[num_waitchks], |
| 501 | file); |
| 502 | if (err < 0) |
| 503 | goto fail; |
| 504 | |
| 505 | obj = host1x_to_tegra_bo(wait->bo); |
| 506 | |
| 507 | /* |
| 508 | * The unaligned offset will cause an unaligned write during |
| 509 | * of the waitchks patching, corrupting the commands stream. |
| 510 | */ |
| 511 | if (wait->offset & 3 || |
| 512 | wait->offset >= obj->gem.size) { |
| 513 | err = -EINVAL; |
| 514 | goto fail; |
| 515 | } |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 516 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 517 | |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 518 | if (copy_from_user(&syncpt, (void __user *)(uintptr_t)args->syncpts, |
| 519 | sizeof(syncpt))) { |
| 520 | err = -EFAULT; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 521 | goto fail; |
Dan Carpenter | 9a99160 | 2013-11-08 13:07:37 +0300 | [diff] [blame] | 522 | } |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 523 | |
Dmitry Osipenko | e0b2ce0 | 2017-06-15 02:18:28 +0300 | [diff] [blame] | 524 | /* check whether syncpoint ID is valid */ |
| 525 | sp = host1x_syncpt_get(host1x, syncpt.id); |
| 526 | if (!sp) { |
| 527 | err = -ENOENT; |
| 528 | goto fail; |
| 529 | } |
| 530 | |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 531 | job->is_addr_reg = context->client->ops->is_addr_reg; |
Dmitry Osipenko | 0f563a4 | 2017-06-15 02:18:37 +0300 | [diff] [blame] | 532 | job->is_valid_class = context->client->ops->is_valid_class; |
Thierry Reding | c40f0f1 | 2013-10-10 11:00:33 +0200 | [diff] [blame] | 533 | job->syncpt_incrs = syncpt.incrs; |
| 534 | job->syncpt_id = syncpt.id; |
| 535 | job->timeout = 10000; |
| 536 | |
| 537 | if (args->timeout && args->timeout < 10000) |
| 538 | job->timeout = args->timeout; |
| 539 | |
| 540 | err = host1x_job_pin(job, context->client->base.dev); |
| 541 | if (err) |
| 542 | goto fail; |
| 543 | |
| 544 | err = host1x_job_submit(job); |
| 545 | if (err) |
| 546 | goto fail_submit; |
| 547 | |
| 548 | args->fence = job->syncpt_end; |
| 549 | |
| 550 | host1x_job_put(job); |
| 551 | return 0; |
| 552 | |
| 553 | fail_submit: |
| 554 | host1x_job_unpin(job); |
| 555 | fail: |
| 556 | host1x_job_put(job); |
| 557 | return err; |
| 558 | } |
| 559 | |
| 560 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 561 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 562 | static int tegra_gem_create(struct drm_device *drm, void *data, |
| 563 | struct drm_file *file) |
| 564 | { |
| 565 | struct drm_tegra_gem_create *args = data; |
| 566 | struct tegra_bo *bo; |
| 567 | |
Thierry Reding | 773af77 | 2013-10-04 22:34:01 +0200 | [diff] [blame] | 568 | bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 569 | &args->handle); |
| 570 | if (IS_ERR(bo)) |
| 571 | return PTR_ERR(bo); |
| 572 | |
| 573 | return 0; |
| 574 | } |
| 575 | |
| 576 | static int tegra_gem_mmap(struct drm_device *drm, void *data, |
| 577 | struct drm_file *file) |
| 578 | { |
| 579 | struct drm_tegra_gem_mmap *args = data; |
| 580 | struct drm_gem_object *gem; |
| 581 | struct tegra_bo *bo; |
| 582 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 583 | gem = drm_gem_object_lookup(file, args->handle); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 584 | if (!gem) |
| 585 | return -EINVAL; |
| 586 | |
| 587 | bo = to_tegra_bo(gem); |
| 588 | |
David Herrmann | 2bc7b0c | 2013-08-13 14:19:58 +0200 | [diff] [blame] | 589 | args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 590 | |
Daniel Vetter | 1153330 | 2015-11-23 10:32:40 +0100 | [diff] [blame] | 591 | drm_gem_object_unreference_unlocked(gem); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 592 | |
| 593 | return 0; |
| 594 | } |
| 595 | |
| 596 | static int tegra_syncpt_read(struct drm_device *drm, void *data, |
| 597 | struct drm_file *file) |
| 598 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 599 | struct host1x *host = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 600 | struct drm_tegra_syncpt_read *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 601 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 602 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 603 | sp = host1x_syncpt_get(host, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 604 | if (!sp) |
| 605 | return -EINVAL; |
| 606 | |
| 607 | args->value = host1x_syncpt_read_min(sp); |
| 608 | return 0; |
| 609 | } |
| 610 | |
| 611 | static int tegra_syncpt_incr(struct drm_device *drm, void *data, |
| 612 | struct drm_file *file) |
| 613 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 614 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 615 | struct drm_tegra_syncpt_incr *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 616 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 617 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 618 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 619 | if (!sp) |
| 620 | return -EINVAL; |
| 621 | |
Arto Merilainen | ebae30b | 2013-05-29 13:26:08 +0300 | [diff] [blame] | 622 | return host1x_syncpt_incr(sp); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 623 | } |
| 624 | |
| 625 | static int tegra_syncpt_wait(struct drm_device *drm, void *data, |
| 626 | struct drm_file *file) |
| 627 | { |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 628 | struct host1x *host1x = dev_get_drvdata(drm->dev->parent); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 629 | struct drm_tegra_syncpt_wait *args = data; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 630 | struct host1x_syncpt *sp; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 631 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 632 | sp = host1x_syncpt_get(host1x, args->id); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 633 | if (!sp) |
| 634 | return -EINVAL; |
| 635 | |
| 636 | return host1x_syncpt_wait(sp, args->thresh, args->timeout, |
| 637 | &args->value); |
| 638 | } |
| 639 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 640 | static int tegra_client_open(struct tegra_drm_file *fpriv, |
| 641 | struct tegra_drm_client *client, |
| 642 | struct tegra_drm_context *context) |
| 643 | { |
| 644 | int err; |
| 645 | |
| 646 | err = client->ops->open_channel(client, context); |
| 647 | if (err < 0) |
| 648 | return err; |
| 649 | |
Dmitry Osipenko | d6c153e | 2017-06-15 02:18:25 +0300 | [diff] [blame] | 650 | err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 651 | if (err < 0) { |
| 652 | client->ops->close_channel(context); |
| 653 | return err; |
| 654 | } |
| 655 | |
| 656 | context->client = client; |
| 657 | context->id = err; |
| 658 | |
| 659 | return 0; |
| 660 | } |
| 661 | |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 662 | static int tegra_open_channel(struct drm_device *drm, void *data, |
| 663 | struct drm_file *file) |
| 664 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 665 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 386a2a7 | 2013-09-24 13:22:17 +0200 | [diff] [blame] | 666 | struct tegra_drm *tegra = drm->dev_private; |
| 667 | struct drm_tegra_open_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 668 | struct tegra_drm_context *context; |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 669 | struct tegra_drm_client *client; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 670 | int err = -ENODEV; |
| 671 | |
| 672 | context = kzalloc(sizeof(*context), GFP_KERNEL); |
| 673 | if (!context) |
| 674 | return -ENOMEM; |
| 675 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 676 | mutex_lock(&fpriv->lock); |
| 677 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 678 | list_for_each_entry(client, &tegra->clients, list) |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 679 | if (client->base.class == args->client) { |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 680 | err = tegra_client_open(fpriv, client, context); |
| 681 | if (err < 0) |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 682 | break; |
| 683 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 684 | args->context = context->id; |
| 685 | break; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 686 | } |
| 687 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 688 | if (err < 0) |
| 689 | kfree(context); |
| 690 | |
| 691 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 692 | return err; |
| 693 | } |
| 694 | |
| 695 | static int tegra_close_channel(struct drm_device *drm, void *data, |
| 696 | struct drm_file *file) |
| 697 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 698 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 699 | struct drm_tegra_close_channel *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 700 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 701 | int err = 0; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 702 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 703 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 704 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 705 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 706 | if (!context) { |
| 707 | err = -EINVAL; |
| 708 | goto unlock; |
| 709 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 710 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 711 | idr_remove(&fpriv->contexts, context->id); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 712 | tegra_drm_context_free(context); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 713 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 714 | unlock: |
| 715 | mutex_unlock(&fpriv->lock); |
| 716 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 717 | } |
| 718 | |
| 719 | static int tegra_get_syncpt(struct drm_device *drm, void *data, |
| 720 | struct drm_file *file) |
| 721 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 722 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 723 | struct drm_tegra_get_syncpt *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 724 | struct tegra_drm_context *context; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 725 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 726 | int err = 0; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 727 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 728 | mutex_lock(&fpriv->lock); |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 729 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 730 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 731 | if (!context) { |
| 732 | err = -ENODEV; |
| 733 | goto unlock; |
| 734 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 735 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 736 | if (args->index >= context->client->base.num_syncpts) { |
| 737 | err = -EINVAL; |
| 738 | goto unlock; |
| 739 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 740 | |
Thierry Reding | 53fa7f7 | 2013-09-24 15:35:40 +0200 | [diff] [blame] | 741 | syncpt = context->client->base.syncpts[args->index]; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 742 | args->id = host1x_syncpt_id(syncpt); |
| 743 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 744 | unlock: |
| 745 | mutex_unlock(&fpriv->lock); |
| 746 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 747 | } |
| 748 | |
| 749 | static int tegra_submit(struct drm_device *drm, void *data, |
| 750 | struct drm_file *file) |
| 751 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 752 | struct tegra_drm_file *fpriv = file->driver_priv; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 753 | struct drm_tegra_submit *args = data; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 754 | struct tegra_drm_context *context; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 755 | int err; |
Thierry Reding | c88c363 | 2013-09-26 16:08:22 +0200 | [diff] [blame] | 756 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 757 | mutex_lock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 758 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 759 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 760 | if (!context) { |
| 761 | err = -ENODEV; |
| 762 | goto unlock; |
| 763 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 764 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 765 | err = context->client->ops->submit(context, args, drm, file); |
| 766 | |
| 767 | unlock: |
| 768 | mutex_unlock(&fpriv->lock); |
| 769 | return err; |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 770 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 771 | |
| 772 | static int tegra_get_syncpt_base(struct drm_device *drm, void *data, |
| 773 | struct drm_file *file) |
| 774 | { |
| 775 | struct tegra_drm_file *fpriv = file->driver_priv; |
| 776 | struct drm_tegra_get_syncpt_base *args = data; |
| 777 | struct tegra_drm_context *context; |
| 778 | struct host1x_syncpt_base *base; |
| 779 | struct host1x_syncpt *syncpt; |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 780 | int err = 0; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 781 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 782 | mutex_lock(&fpriv->lock); |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 783 | |
Dmitry Osipenko | 1066a89 | 2017-06-15 02:18:24 +0300 | [diff] [blame] | 784 | context = idr_find(&fpriv->contexts, args->context); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 785 | if (!context) { |
| 786 | err = -ENODEV; |
| 787 | goto unlock; |
| 788 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 789 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 790 | if (args->syncpt >= context->client->base.num_syncpts) { |
| 791 | err = -EINVAL; |
| 792 | goto unlock; |
| 793 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 794 | |
| 795 | syncpt = context->client->base.syncpts[args->syncpt]; |
| 796 | |
| 797 | base = host1x_syncpt_get_base(syncpt); |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 798 | if (!base) { |
| 799 | err = -ENXIO; |
| 800 | goto unlock; |
| 801 | } |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 802 | |
| 803 | args->id = host1x_syncpt_base_id(base); |
| 804 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 805 | unlock: |
| 806 | mutex_unlock(&fpriv->lock); |
| 807 | return err; |
Arto Merilainen | c54a169 | 2013-10-14 15:21:54 +0300 | [diff] [blame] | 808 | } |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 809 | |
| 810 | static int tegra_gem_set_tiling(struct drm_device *drm, void *data, |
| 811 | struct drm_file *file) |
| 812 | { |
| 813 | struct drm_tegra_gem_set_tiling *args = data; |
| 814 | enum tegra_bo_tiling_mode mode; |
| 815 | struct drm_gem_object *gem; |
| 816 | unsigned long value = 0; |
| 817 | struct tegra_bo *bo; |
| 818 | |
| 819 | switch (args->mode) { |
| 820 | case DRM_TEGRA_GEM_TILING_MODE_PITCH: |
| 821 | mode = TEGRA_BO_TILING_MODE_PITCH; |
| 822 | |
| 823 | if (args->value != 0) |
| 824 | return -EINVAL; |
| 825 | |
| 826 | break; |
| 827 | |
| 828 | case DRM_TEGRA_GEM_TILING_MODE_TILED: |
| 829 | mode = TEGRA_BO_TILING_MODE_TILED; |
| 830 | |
| 831 | if (args->value != 0) |
| 832 | return -EINVAL; |
| 833 | |
| 834 | break; |
| 835 | |
| 836 | case DRM_TEGRA_GEM_TILING_MODE_BLOCK: |
| 837 | mode = TEGRA_BO_TILING_MODE_BLOCK; |
| 838 | |
| 839 | if (args->value > 5) |
| 840 | return -EINVAL; |
| 841 | |
| 842 | value = args->value; |
| 843 | break; |
| 844 | |
| 845 | default: |
| 846 | return -EINVAL; |
| 847 | } |
| 848 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 849 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 850 | if (!gem) |
| 851 | return -ENOENT; |
| 852 | |
| 853 | bo = to_tegra_bo(gem); |
| 854 | |
| 855 | bo->tiling.mode = mode; |
| 856 | bo->tiling.value = value; |
| 857 | |
Daniel Vetter | 1153330 | 2015-11-23 10:32:40 +0100 | [diff] [blame] | 858 | drm_gem_object_unreference_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 859 | |
| 860 | return 0; |
| 861 | } |
| 862 | |
| 863 | static int tegra_gem_get_tiling(struct drm_device *drm, void *data, |
| 864 | struct drm_file *file) |
| 865 | { |
| 866 | struct drm_tegra_gem_get_tiling *args = data; |
| 867 | struct drm_gem_object *gem; |
| 868 | struct tegra_bo *bo; |
| 869 | int err = 0; |
| 870 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 871 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 872 | if (!gem) |
| 873 | return -ENOENT; |
| 874 | |
| 875 | bo = to_tegra_bo(gem); |
| 876 | |
| 877 | switch (bo->tiling.mode) { |
| 878 | case TEGRA_BO_TILING_MODE_PITCH: |
| 879 | args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; |
| 880 | args->value = 0; |
| 881 | break; |
| 882 | |
| 883 | case TEGRA_BO_TILING_MODE_TILED: |
| 884 | args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; |
| 885 | args->value = 0; |
| 886 | break; |
| 887 | |
| 888 | case TEGRA_BO_TILING_MODE_BLOCK: |
| 889 | args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; |
| 890 | args->value = bo->tiling.value; |
| 891 | break; |
| 892 | |
| 893 | default: |
| 894 | err = -EINVAL; |
| 895 | break; |
| 896 | } |
| 897 | |
Daniel Vetter | 1153330 | 2015-11-23 10:32:40 +0100 | [diff] [blame] | 898 | drm_gem_object_unreference_unlocked(gem); |
Thierry Reding | 7678d71 | 2014-06-03 14:56:57 +0200 | [diff] [blame] | 899 | |
| 900 | return err; |
| 901 | } |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 902 | |
| 903 | static int tegra_gem_set_flags(struct drm_device *drm, void *data, |
| 904 | struct drm_file *file) |
| 905 | { |
| 906 | struct drm_tegra_gem_set_flags *args = data; |
| 907 | struct drm_gem_object *gem; |
| 908 | struct tegra_bo *bo; |
| 909 | |
| 910 | if (args->flags & ~DRM_TEGRA_GEM_FLAGS) |
| 911 | return -EINVAL; |
| 912 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 913 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 914 | if (!gem) |
| 915 | return -ENOENT; |
| 916 | |
| 917 | bo = to_tegra_bo(gem); |
| 918 | bo->flags = 0; |
| 919 | |
| 920 | if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) |
| 921 | bo->flags |= TEGRA_BO_BOTTOM_UP; |
| 922 | |
Daniel Vetter | 1153330 | 2015-11-23 10:32:40 +0100 | [diff] [blame] | 923 | drm_gem_object_unreference_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 924 | |
| 925 | return 0; |
| 926 | } |
| 927 | |
| 928 | static int tegra_gem_get_flags(struct drm_device *drm, void *data, |
| 929 | struct drm_file *file) |
| 930 | { |
| 931 | struct drm_tegra_gem_get_flags *args = data; |
| 932 | struct drm_gem_object *gem; |
| 933 | struct tegra_bo *bo; |
| 934 | |
Chris Wilson | a8ad0bd | 2016-05-09 11:04:54 +0100 | [diff] [blame] | 935 | gem = drm_gem_object_lookup(file, args->handle); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 936 | if (!gem) |
| 937 | return -ENOENT; |
| 938 | |
| 939 | bo = to_tegra_bo(gem); |
| 940 | args->flags = 0; |
| 941 | |
| 942 | if (bo->flags & TEGRA_BO_BOTTOM_UP) |
| 943 | args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; |
| 944 | |
Daniel Vetter | 1153330 | 2015-11-23 10:32:40 +0100 | [diff] [blame] | 945 | drm_gem_object_unreference_unlocked(gem); |
Thierry Reding | 7b12908 | 2014-06-10 12:04:03 +0200 | [diff] [blame] | 946 | |
| 947 | return 0; |
| 948 | } |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 949 | #endif |
| 950 | |
Rob Clark | baa7094 | 2013-08-02 13:27:49 -0400 | [diff] [blame] | 951 | static const struct drm_ioctl_desc tegra_drm_ioctls[] = { |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 952 | #ifdef CONFIG_DRM_TEGRA_STAGING |
Daniel Vetter | f8c4714 | 2015-09-08 13:56:30 +0200 | [diff] [blame] | 953 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, 0), |
| 954 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, 0), |
| 955 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 0), |
| 956 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 0), |
| 957 | DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 0), |
| 958 | DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 0), |
| 959 | DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 0), |
| 960 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 0), |
| 961 | DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 0), |
| 962 | DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 0), |
| 963 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 0), |
| 964 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 0), |
| 965 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 0), |
| 966 | DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 0), |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 967 | #endif |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 968 | }; |
| 969 | |
| 970 | static const struct file_operations tegra_drm_fops = { |
| 971 | .owner = THIS_MODULE, |
| 972 | .open = drm_open, |
| 973 | .release = drm_release, |
| 974 | .unlocked_ioctl = drm_ioctl, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 975 | .mmap = tegra_drm_mmap, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 976 | .poll = drm_poll, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 977 | .read = drm_read, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 978 | .compat_ioctl = drm_compat_ioctl, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 979 | .llseek = noop_llseek, |
| 980 | }; |
| 981 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 982 | static int tegra_drm_context_cleanup(int id, void *p, void *data) |
| 983 | { |
| 984 | struct tegra_drm_context *context = p; |
| 985 | |
| 986 | tegra_drm_context_free(context); |
| 987 | |
| 988 | return 0; |
| 989 | } |
| 990 | |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 991 | static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 992 | { |
Thierry Reding | 08943e6 | 2013-09-26 16:08:18 +0200 | [diff] [blame] | 993 | struct tegra_drm_file *fpriv = file->driver_priv; |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 994 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 995 | mutex_lock(&fpriv->lock); |
| 996 | idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); |
| 997 | mutex_unlock(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 998 | |
Thierry Reding | bdd2f9c | 2017-03-09 20:04:55 +0100 | [diff] [blame] | 999 | idr_destroy(&fpriv->contexts); |
| 1000 | mutex_destroy(&fpriv->lock); |
Terje Bergstrom | d43f81c | 2013-03-22 16:34:09 +0200 | [diff] [blame] | 1001 | kfree(fpriv); |
Thierry Reding | 3c03c46 | 2012-11-28 12:00:18 +0100 | [diff] [blame] | 1002 | } |
| 1003 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1004 | #ifdef CONFIG_DEBUG_FS |
| 1005 | static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) |
| 1006 | { |
| 1007 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1008 | struct drm_device *drm = node->minor->dev; |
| 1009 | struct drm_framebuffer *fb; |
| 1010 | |
| 1011 | mutex_lock(&drm->mode_config.fb_lock); |
| 1012 | |
| 1013 | list_for_each_entry(fb, &drm->mode_config.fb_list, head) { |
| 1014 | seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", |
Ville Syrjälä | b00c600 | 2016-12-14 23:31:35 +0200 | [diff] [blame] | 1015 | fb->base.id, fb->width, fb->height, |
| 1016 | fb->format->depth, |
Ville Syrjälä | 272725c | 2016-12-14 23:32:20 +0200 | [diff] [blame] | 1017 | fb->format->cpp[0] * 8, |
Dave Airlie | 747a598 | 2016-04-15 15:10:35 +1000 | [diff] [blame] | 1018 | drm_framebuffer_read_refcount(fb)); |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1019 | } |
| 1020 | |
| 1021 | mutex_unlock(&drm->mode_config.fb_lock); |
| 1022 | |
| 1023 | return 0; |
| 1024 | } |
| 1025 | |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1026 | static int tegra_debugfs_iova(struct seq_file *s, void *data) |
| 1027 | { |
| 1028 | struct drm_info_node *node = (struct drm_info_node *)s->private; |
| 1029 | struct drm_device *drm = node->minor->dev; |
| 1030 | struct tegra_drm *tegra = drm->dev_private; |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1031 | struct drm_printer p = drm_seq_file_printer(s); |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1032 | |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 1033 | mutex_lock(&tegra->mm_lock); |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1034 | drm_mm_print(&tegra->mm, &p); |
Thierry Reding | 347ad49d | 2017-03-09 20:04:56 +0100 | [diff] [blame] | 1035 | mutex_unlock(&tegra->mm_lock); |
Daniel Vetter | b5c3714 | 2016-12-29 12:09:24 +0100 | [diff] [blame] | 1036 | |
| 1037 | return 0; |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1038 | } |
| 1039 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1040 | static struct drm_info_list tegra_debugfs_list[] = { |
| 1041 | { "framebuffers", tegra_debugfs_framebuffers, 0 }, |
Thierry Reding | 28c2337 | 2015-01-23 09:16:03 +0100 | [diff] [blame] | 1042 | { "iova", tegra_debugfs_iova, 0 }, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1043 | }; |
| 1044 | |
| 1045 | static int tegra_debugfs_init(struct drm_minor *minor) |
| 1046 | { |
| 1047 | return drm_debugfs_create_files(tegra_debugfs_list, |
| 1048 | ARRAY_SIZE(tegra_debugfs_list), |
| 1049 | minor->debugfs_root, minor); |
| 1050 | } |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1051 | #endif |
| 1052 | |
Thierry Reding | 9b57f5f | 2013-11-08 13:17:14 +0100 | [diff] [blame] | 1053 | static struct drm_driver tegra_drm_driver = { |
Thierry Reding | ad90659 | 2015-09-24 18:38:09 +0200 | [diff] [blame] | 1054 | .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME | |
| 1055 | DRIVER_ATOMIC, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1056 | .load = tegra_drm_load, |
| 1057 | .unload = tegra_drm_unload, |
| 1058 | .open = tegra_drm_open, |
Daniel Vetter | bda0ecc | 2017-05-08 10:26:31 +0200 | [diff] [blame] | 1059 | .postclose = tegra_drm_postclose, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1060 | .lastclose = tegra_drm_lastclose, |
| 1061 | |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1062 | #if defined(CONFIG_DEBUG_FS) |
| 1063 | .debugfs_init = tegra_debugfs_init, |
Thierry Reding | e450fcc | 2013-02-13 16:13:16 +0100 | [diff] [blame] | 1064 | #endif |
| 1065 | |
Daniel Vetter | 1ddbdbd | 2016-04-26 19:30:00 +0200 | [diff] [blame] | 1066 | .gem_free_object_unlocked = tegra_bo_free_object, |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1067 | .gem_vm_ops = &tegra_bo_vm_ops, |
Thierry Reding | 3800391 | 2013-12-12 10:00:43 +0100 | [diff] [blame] | 1068 | |
| 1069 | .prime_handle_to_fd = drm_gem_prime_handle_to_fd, |
| 1070 | .prime_fd_to_handle = drm_gem_prime_fd_to_handle, |
| 1071 | .gem_prime_export = tegra_gem_prime_export, |
| 1072 | .gem_prime_import = tegra_gem_prime_import, |
| 1073 | |
Arto Merilainen | de2ba66 | 2013-03-22 16:34:08 +0200 | [diff] [blame] | 1074 | .dumb_create = tegra_bo_dumb_create, |
| 1075 | .dumb_map_offset = tegra_bo_dumb_map_offset, |
Daniel Vetter | 43387b3 | 2013-07-16 09:12:04 +0200 | [diff] [blame] | 1076 | .dumb_destroy = drm_gem_dumb_destroy, |
Thierry Reding | d8f4a9e | 2012-11-15 21:28:22 +0000 | [diff] [blame] | 1077 | |
| 1078 | .ioctls = tegra_drm_ioctls, |
| 1079 | .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), |
| 1080 | .fops = &tegra_drm_fops, |
| 1081 | |
| 1082 | .name = DRIVER_NAME, |
| 1083 | .desc = DRIVER_DESC, |
| 1084 | .date = DRIVER_DATE, |
| 1085 | .major = DRIVER_MAJOR, |
| 1086 | .minor = DRIVER_MINOR, |
| 1087 | .patchlevel = DRIVER_PATCHLEVEL, |
| 1088 | }; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1089 | |
| 1090 | int tegra_drm_register_client(struct tegra_drm *tegra, |
| 1091 | struct tegra_drm_client *client) |
| 1092 | { |
| 1093 | mutex_lock(&tegra->clients_lock); |
| 1094 | list_add_tail(&client->list, &tegra->clients); |
| 1095 | mutex_unlock(&tegra->clients_lock); |
| 1096 | |
| 1097 | return 0; |
| 1098 | } |
| 1099 | |
| 1100 | int tegra_drm_unregister_client(struct tegra_drm *tegra, |
| 1101 | struct tegra_drm_client *client) |
| 1102 | { |
| 1103 | mutex_lock(&tegra->clients_lock); |
| 1104 | list_del_init(&client->list); |
| 1105 | mutex_unlock(&tegra->clients_lock); |
| 1106 | |
| 1107 | return 0; |
| 1108 | } |
| 1109 | |
Mikko Perttunen | ad92601 | 2016-12-14 13:16:11 +0200 | [diff] [blame] | 1110 | void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, |
| 1111 | dma_addr_t *dma) |
| 1112 | { |
| 1113 | struct iova *alloc; |
| 1114 | void *virt; |
| 1115 | gfp_t gfp; |
| 1116 | int err; |
| 1117 | |
| 1118 | if (tegra->domain) |
| 1119 | size = iova_align(&tegra->carveout.domain, size); |
| 1120 | else |
| 1121 | size = PAGE_ALIGN(size); |
| 1122 | |
| 1123 | gfp = GFP_KERNEL | __GFP_ZERO; |
| 1124 | if (!tegra->domain) { |
| 1125 | /* |
| 1126 | * Many units only support 32-bit addresses, even on 64-bit |
| 1127 | * SoCs. If there is no IOMMU to translate into a 32-bit IO |
| 1128 | * virtual address space, force allocations to be in the |
| 1129 | * lower 32-bit range. |
| 1130 | */ |
| 1131 | gfp |= GFP_DMA; |
| 1132 | } |
| 1133 | |
| 1134 | virt = (void *)__get_free_pages(gfp, get_order(size)); |
| 1135 | if (!virt) |
| 1136 | return ERR_PTR(-ENOMEM); |
| 1137 | |
| 1138 | if (!tegra->domain) { |
| 1139 | /* |
| 1140 | * If IOMMU is disabled, devices address physical memory |
| 1141 | * directly. |
| 1142 | */ |
| 1143 | *dma = virt_to_phys(virt); |
| 1144 | return virt; |
| 1145 | } |
| 1146 | |
| 1147 | alloc = alloc_iova(&tegra->carveout.domain, |
| 1148 | size >> tegra->carveout.shift, |
| 1149 | tegra->carveout.limit, true); |
| 1150 | if (!alloc) { |
| 1151 | err = -EBUSY; |
| 1152 | goto free_pages; |
| 1153 | } |
| 1154 | |
| 1155 | *dma = iova_dma_addr(&tegra->carveout.domain, alloc); |
| 1156 | err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), |
| 1157 | size, IOMMU_READ | IOMMU_WRITE); |
| 1158 | if (err < 0) |
| 1159 | goto free_iova; |
| 1160 | |
| 1161 | return virt; |
| 1162 | |
| 1163 | free_iova: |
| 1164 | __free_iova(&tegra->carveout.domain, alloc); |
| 1165 | free_pages: |
| 1166 | free_pages((unsigned long)virt, get_order(size)); |
| 1167 | |
| 1168 | return ERR_PTR(err); |
| 1169 | } |
| 1170 | |
| 1171 | void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, |
| 1172 | dma_addr_t dma) |
| 1173 | { |
| 1174 | if (tegra->domain) |
| 1175 | size = iova_align(&tegra->carveout.domain, size); |
| 1176 | else |
| 1177 | size = PAGE_ALIGN(size); |
| 1178 | |
| 1179 | if (tegra->domain) { |
| 1180 | iommu_unmap(tegra->domain, dma, size); |
| 1181 | free_iova(&tegra->carveout.domain, |
| 1182 | iova_pfn(&tegra->carveout.domain, dma)); |
| 1183 | } |
| 1184 | |
| 1185 | free_pages((unsigned long)virt, get_order(size)); |
| 1186 | } |
| 1187 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1188 | static int host1x_drm_probe(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1189 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1190 | struct drm_driver *driver = &tegra_drm_driver; |
| 1191 | struct drm_device *drm; |
| 1192 | int err; |
| 1193 | |
| 1194 | drm = drm_dev_alloc(driver, &dev->dev); |
Tom Gundersen | 0f28860 | 2016-09-21 16:59:19 +0200 | [diff] [blame] | 1195 | if (IS_ERR(drm)) |
| 1196 | return PTR_ERR(drm); |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1197 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1198 | dev_set_drvdata(&dev->dev, drm); |
| 1199 | |
| 1200 | err = drm_dev_register(drm, 0); |
| 1201 | if (err < 0) |
| 1202 | goto unref; |
| 1203 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1204 | return 0; |
| 1205 | |
| 1206 | unref: |
| 1207 | drm_dev_unref(drm); |
| 1208 | return err; |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1209 | } |
| 1210 | |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1211 | static int host1x_drm_remove(struct host1x_device *dev) |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1212 | { |
Thierry Reding | 9910f5c | 2014-05-22 09:57:15 +0200 | [diff] [blame] | 1213 | struct drm_device *drm = dev_get_drvdata(&dev->dev); |
| 1214 | |
| 1215 | drm_dev_unregister(drm); |
| 1216 | drm_dev_unref(drm); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1217 | |
| 1218 | return 0; |
| 1219 | } |
| 1220 | |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1221 | #ifdef CONFIG_PM_SLEEP |
| 1222 | static int host1x_drm_suspend(struct device *dev) |
| 1223 | { |
| 1224 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1225 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1226 | |
| 1227 | drm_kms_helper_poll_disable(drm); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1228 | tegra_drm_fb_suspend(drm); |
| 1229 | |
| 1230 | tegra->state = drm_atomic_helper_suspend(drm); |
| 1231 | if (IS_ERR(tegra->state)) { |
| 1232 | tegra_drm_fb_resume(drm); |
| 1233 | drm_kms_helper_poll_enable(drm); |
| 1234 | return PTR_ERR(tegra->state); |
| 1235 | } |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1236 | |
| 1237 | return 0; |
| 1238 | } |
| 1239 | |
| 1240 | static int host1x_drm_resume(struct device *dev) |
| 1241 | { |
| 1242 | struct drm_device *drm = dev_get_drvdata(dev); |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1243 | struct tegra_drm *tegra = drm->dev_private; |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1244 | |
Thierry Reding | 986c58d | 2015-08-11 13:11:49 +0200 | [diff] [blame] | 1245 | drm_atomic_helper_resume(drm, tegra->state); |
| 1246 | tegra_drm_fb_resume(drm); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1247 | drm_kms_helper_poll_enable(drm); |
| 1248 | |
| 1249 | return 0; |
| 1250 | } |
| 1251 | #endif |
| 1252 | |
Thierry Reding | a13f1dc | 2015-08-11 13:22:44 +0200 | [diff] [blame] | 1253 | static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, |
| 1254 | host1x_drm_resume); |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1255 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1256 | static const struct of_device_id host1x_drm_subdevs[] = { |
| 1257 | { .compatible = "nvidia,tegra20-dc", }, |
| 1258 | { .compatible = "nvidia,tegra20-hdmi", }, |
| 1259 | { .compatible = "nvidia,tegra20-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1260 | { .compatible = "nvidia,tegra20-gr3d", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1261 | { .compatible = "nvidia,tegra30-dc", }, |
| 1262 | { .compatible = "nvidia,tegra30-hdmi", }, |
| 1263 | { .compatible = "nvidia,tegra30-gr2d", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1264 | { .compatible = "nvidia,tegra30-gr3d", }, |
Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1265 | { .compatible = "nvidia,tegra114-dsi", }, |
Mikko Perttunen | 7d1d28a | 2013-09-30 16:54:47 +0200 | [diff] [blame] | 1266 | { .compatible = "nvidia,tegra114-hdmi", }, |
Thierry Reding | 5f60ed0 | 2013-02-28 08:08:01 +0100 | [diff] [blame] | 1267 | { .compatible = "nvidia,tegra114-gr3d", }, |
Thierry Reding | 8620fc6 | 2013-12-12 11:03:59 +0100 | [diff] [blame] | 1268 | { .compatible = "nvidia,tegra124-dc", }, |
Thierry Reding | 6b6b604 | 2013-11-15 16:06:05 +0100 | [diff] [blame] | 1269 | { .compatible = "nvidia,tegra124-sor", }, |
Thierry Reding | fb7be70 | 2013-11-15 16:07:32 +0100 | [diff] [blame] | 1270 | { .compatible = "nvidia,tegra124-hdmi", }, |
Thierry Reding | 7d33858 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1271 | { .compatible = "nvidia,tegra124-dsi", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1272 | { .compatible = "nvidia,tegra124-vic", }, |
Thierry Reding | c06c793 | 2015-04-10 11:35:21 +0200 | [diff] [blame] | 1273 | { .compatible = "nvidia,tegra132-dsi", }, |
Thierry Reding | 5b4f516 | 2015-03-27 10:31:58 +0100 | [diff] [blame] | 1274 | { .compatible = "nvidia,tegra210-dc", }, |
Thierry Reding | ddfb406 | 2015-04-08 16:56:22 +0200 | [diff] [blame] | 1275 | { .compatible = "nvidia,tegra210-dsi", }, |
Thierry Reding | 3309ac8 | 2015-07-30 10:32:46 +0200 | [diff] [blame] | 1276 | { .compatible = "nvidia,tegra210-sor", }, |
Thierry Reding | 459cc2c | 2015-07-30 10:34:24 +0200 | [diff] [blame] | 1277 | { .compatible = "nvidia,tegra210-sor1", }, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1278 | { .compatible = "nvidia,tegra210-vic", }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1279 | { /* sentinel */ } |
| 1280 | }; |
| 1281 | |
| 1282 | static struct host1x_driver host1x_drm_driver = { |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1283 | .driver = { |
| 1284 | .name = "drm", |
Thierry Reding | 359ae68 | 2014-12-18 17:15:25 +0100 | [diff] [blame] | 1285 | .pm = &host1x_drm_pm_ops, |
Thierry Reding | f4c5cf8 | 2014-12-18 15:29:14 +0100 | [diff] [blame] | 1286 | }, |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1287 | .probe = host1x_drm_probe, |
| 1288 | .remove = host1x_drm_remove, |
| 1289 | .subdevs = host1x_drm_subdevs, |
| 1290 | }; |
| 1291 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1292 | static struct platform_driver * const drivers[] = { |
| 1293 | &tegra_dc_driver, |
| 1294 | &tegra_hdmi_driver, |
| 1295 | &tegra_dsi_driver, |
| 1296 | &tegra_dpaux_driver, |
| 1297 | &tegra_sor_driver, |
| 1298 | &tegra_gr2d_driver, |
| 1299 | &tegra_gr3d_driver, |
Arto Merilainen | 0ae797a | 2016-12-14 13:16:13 +0200 | [diff] [blame] | 1300 | &tegra_vic_driver, |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1301 | }; |
| 1302 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1303 | static int __init host1x_drm_init(void) |
| 1304 | { |
| 1305 | int err; |
| 1306 | |
| 1307 | err = host1x_driver_register(&host1x_drm_driver); |
| 1308 | if (err < 0) |
| 1309 | return err; |
| 1310 | |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1311 | err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1312 | if (err < 0) |
| 1313 | goto unregister_host1x; |
| 1314 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1315 | return 0; |
| 1316 | |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1317 | unregister_host1x: |
| 1318 | host1x_driver_unregister(&host1x_drm_driver); |
| 1319 | return err; |
| 1320 | } |
| 1321 | module_init(host1x_drm_init); |
| 1322 | |
| 1323 | static void __exit host1x_drm_exit(void) |
| 1324 | { |
Thierry Reding | 473112e | 2015-09-10 16:07:14 +0200 | [diff] [blame] | 1325 | platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); |
Thierry Reding | 776dc38 | 2013-10-14 14:43:22 +0200 | [diff] [blame] | 1326 | host1x_driver_unregister(&host1x_drm_driver); |
| 1327 | } |
| 1328 | module_exit(host1x_drm_exit); |
| 1329 | |
| 1330 | MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); |
| 1331 | MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); |
| 1332 | MODULE_LICENSE("GPL v2"); |