Blame - drivers/media/dvb/frontends/drxk_map.h - kernel/msm-4.19

Ralph Metzler

43dd07f

2011-07-03 13:42:18 -0300

[diff] [blame^]

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#ifndef __DRXK_MAP__H__

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#define __DRXK_MAP__H__ 1

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#define AUD_COMM_EXEC__A 0x1000000

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#define AUD_COMM_EXEC__W 2

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#define AUD_COMM_EXEC__M 0x3

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#define AUD_COMM_EXEC__PRE 0x0

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#define AUD_COMM_EXEC_STOP 0x0

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#define FEC_COMM_EXEC__A 0x1C00000

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#define FEC_COMM_EXEC__W 2

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#define FEC_COMM_EXEC__M 0x3

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#define FEC_COMM_EXEC__PRE 0x0

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#define FEC_COMM_EXEC_STOP 0x0

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#define FEC_COMM_EXEC_ACTIVE 0x1

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#define FEC_COMM_EXEC_HOLD 0x2

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#define FEC_COMM_MB__A 0x1C00002

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#define FEC_COMM_MB__W 16

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#define FEC_COMM_MB__M 0xFFFF

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#define FEC_COMM_MB__PRE 0x0

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#define FEC_COMM_INT_REQ__A 0x1C00003

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#define FEC_COMM_INT_REQ__W 16

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#define FEC_COMM_INT_REQ__M 0xFFFF

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#define FEC_COMM_INT_REQ__PRE 0x0

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#define FEC_COMM_INT_REQ_OC_REQ__B 0

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#define FEC_COMM_INT_REQ_OC_REQ__W 1

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#define FEC_COMM_INT_REQ_OC_REQ__M 0x1

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#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x0

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#define FEC_COMM_INT_REQ_RS_REQ__B 1

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#define FEC_COMM_INT_REQ_RS_REQ__W 1

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#define FEC_COMM_INT_REQ_RS_REQ__M 0x2

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#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x0

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#define FEC_COMM_INT_REQ_DI_REQ__B 2

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#define FEC_COMM_INT_REQ_DI_REQ__W 1

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#define FEC_COMM_INT_REQ_DI_REQ__M 0x4

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#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x0

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#define FEC_COMM_INT_STA__A 0x1C00005

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#define FEC_COMM_INT_STA__W 16

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#define FEC_COMM_INT_STA__M 0xFFFF

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#define FEC_COMM_INT_STA__PRE 0x0

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#define FEC_COMM_INT_MSK__A 0x1C00006

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#define FEC_COMM_INT_MSK__W 16

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#define FEC_COMM_INT_MSK__M 0xFFFF

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#define FEC_COMM_INT_MSK__PRE 0x0

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#define FEC_COMM_INT_STM__A 0x1C00007

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#define FEC_COMM_INT_STM__W 16

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#define FEC_COMM_INT_STM__M 0xFFFF

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#define FEC_COMM_INT_STM__PRE 0x0

#define FEC_TOP_COMM_EXEC__A 0x1C10000

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#define FEC_TOP_COMM_EXEC__W 2

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#define FEC_TOP_COMM_EXEC__M 0x3

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#define FEC_TOP_COMM_EXEC__PRE 0x0

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#define FEC_TOP_COMM_EXEC_STOP 0x0

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#define FEC_TOP_COMM_EXEC_ACTIVE 0x1

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#define FEC_TOP_COMM_EXEC_HOLD 0x2

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#define FEC_TOP_ANNEX__A 0x1C10010

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#define FEC_TOP_ANNEX__W 2

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#define FEC_TOP_ANNEX__M 0x3

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#define FEC_TOP_ANNEX__PRE 0x0

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#define FEC_TOP_ANNEX_A 0x0

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#define FEC_TOP_ANNEX_B 0x1

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#define FEC_TOP_ANNEX_C 0x2

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#define FEC_TOP_ANNEX_D 0x3

#define FEC_DI_COMM_EXEC__A 0x1C20000

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#define FEC_DI_COMM_EXEC__W 2

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#define FEC_DI_COMM_EXEC__M 0x3

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#define FEC_DI_COMM_EXEC__PRE 0x0

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#define FEC_DI_COMM_EXEC_STOP 0x0

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#define FEC_DI_COMM_EXEC_ACTIVE 0x1

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#define FEC_DI_COMM_EXEC_HOLD 0x2

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#define FEC_DI_COMM_MB__A 0x1C20002

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#define FEC_DI_COMM_MB__W 2

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#define FEC_DI_COMM_MB__M 0x3

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#define FEC_DI_COMM_MB__PRE 0x0

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#define FEC_DI_COMM_MB_CTL__B 0

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#define FEC_DI_COMM_MB_CTL__W 1

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#define FEC_DI_COMM_MB_CTL__M 0x1

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#define FEC_DI_COMM_MB_CTL__PRE 0x0

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#define FEC_DI_COMM_MB_CTL_OFF 0x0

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#define FEC_DI_COMM_MB_CTL_ON 0x1

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#define FEC_DI_COMM_MB_OBS__B 1

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#define FEC_DI_COMM_MB_OBS__W 1

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#define FEC_DI_COMM_MB_OBS__M 0x2

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#define FEC_DI_COMM_MB_OBS__PRE 0x0

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#define FEC_DI_COMM_MB_OBS_OFF 0x0

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#define FEC_DI_COMM_MB_OBS_ON 0x2

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#define FEC_DI_COMM_INT_REQ__A 0x1C20003

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#define FEC_DI_COMM_INT_REQ__W 1

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#define FEC_DI_COMM_INT_REQ__M 0x1

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#define FEC_DI_COMM_INT_REQ__PRE 0x0

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#define FEC_DI_COMM_INT_STA__A 0x1C20005

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#define FEC_DI_COMM_INT_STA__W 2

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#define FEC_DI_COMM_INT_STA__M 0x3

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#define FEC_DI_COMM_INT_STA__PRE 0x0

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#define FEC_DI_COMM_INT_STA_STAT_INT__B 0

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#define FEC_DI_COMM_INT_STA_STAT_INT__W 1

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#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x1

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#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x0

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#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 1

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#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 1

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#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x2

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#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x0

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#define FEC_DI_COMM_INT_MSK__A 0x1C20006

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#define FEC_DI_COMM_INT_MSK__W 2

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#define FEC_DI_COMM_INT_MSK__M 0x3

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#define FEC_DI_COMM_INT_MSK__PRE 0x0

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#define FEC_DI_COMM_INT_MSK_STAT_INT__B 0

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#define FEC_DI_COMM_INT_MSK_STAT_INT__W 1

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#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x1

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#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x0

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#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 1

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#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 1

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#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x2

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#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x0

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#define FEC_DI_COMM_INT_STM__A 0x1C20007

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#define FEC_DI_COMM_INT_STM__W 2

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#define FEC_DI_COMM_INT_STM__M 0x3

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#define FEC_DI_COMM_INT_STM__PRE 0x0

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#define FEC_DI_COMM_INT_STM_STAT_INT__B 0

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#define FEC_DI_COMM_INT_STM_STAT_INT__W 1

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#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x1

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#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x0

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#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 1

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#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 1

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#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x2

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#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x0

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#define FEC_DI_STATUS__A 0x1C20010

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#define FEC_DI_STATUS__W 1

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#define FEC_DI_STATUS__M 0x1

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#define FEC_DI_STATUS__PRE 0x0

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#define FEC_DI_MODE__A 0x1C20011

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#define FEC_DI_MODE__W 3

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#define FEC_DI_MODE__M 0x7

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#define FEC_DI_MODE__PRE 0x0

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#define FEC_DI_MODE_NO_SYNC__B 0

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#define FEC_DI_MODE_NO_SYNC__W 1

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#define FEC_DI_MODE_NO_SYNC__M 0x1

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#define FEC_DI_MODE_NO_SYNC__PRE 0x0

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#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 1

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#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 1

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#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x2

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#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x0

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#define FEC_DI_MODE_IGNORE_TIMEOUT__B 2

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#define FEC_DI_MODE_IGNORE_TIMEOUT__W 1

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#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x4

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#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x0

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#define FEC_DI_CONTROL_WORD__A 0x1C20012

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#define FEC_DI_CONTROL_WORD__W 4

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#define FEC_DI_CONTROL_WORD__M 0xF

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#define FEC_DI_CONTROL_WORD__PRE 0x0

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#define FEC_DI_RESTART__A 0x1C20013

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#define FEC_DI_RESTART__W 1

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#define FEC_DI_RESTART__M 0x1

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#define FEC_DI_RESTART__PRE 0x0

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#define FEC_DI_TIMEOUT_LO__A 0x1C20014

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#define FEC_DI_TIMEOUT_LO__W 16

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#define FEC_DI_TIMEOUT_LO__M 0xFFFF

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#define FEC_DI_TIMEOUT_LO__PRE 0x0

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#define FEC_DI_TIMEOUT_HI__A 0x1C20015

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#define FEC_DI_TIMEOUT_HI__W 8

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#define FEC_DI_TIMEOUT_HI__M 0xFF

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#define FEC_DI_TIMEOUT_HI__PRE 0xA

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#define FEC_DI_INPUT_CTL__A 0x1C20016

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#define FEC_DI_INPUT_CTL__W 1

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#define FEC_DI_INPUT_CTL__M 0x1

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#define FEC_DI_INPUT_CTL__PRE 0x0

#define FEC_RS_COMM_EXEC__A 0x1C30000

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#define FEC_RS_COMM_EXEC__W 2

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#define FEC_RS_COMM_EXEC__M 0x3

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#define FEC_RS_COMM_EXEC__PRE 0x0

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#define FEC_RS_COMM_EXEC_STOP 0x0

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#define FEC_RS_COMM_EXEC_ACTIVE 0x1

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#define FEC_RS_COMM_EXEC_HOLD 0x2

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#define FEC_RS_COMM_MB__A 0x1C30002

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#define FEC_RS_COMM_MB__W 2

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#define FEC_RS_COMM_MB__M 0x3

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#define FEC_RS_COMM_MB__PRE 0x0

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#define FEC_RS_COMM_MB_CTL__B 0

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#define FEC_RS_COMM_MB_CTL__W 1

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#define FEC_RS_COMM_MB_CTL__M 0x1

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#define FEC_RS_COMM_MB_CTL__PRE 0x0

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#define FEC_RS_COMM_MB_CTL_OFF 0x0

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#define FEC_RS_COMM_MB_CTL_ON 0x1

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#define FEC_RS_COMM_MB_OBS__B 1

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#define FEC_RS_COMM_MB_OBS__W 1

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#define FEC_RS_COMM_MB_OBS__M 0x2

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#define FEC_RS_COMM_MB_OBS__PRE 0x0

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#define FEC_RS_COMM_MB_OBS_OFF 0x0

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#define FEC_RS_COMM_MB_OBS_ON 0x2

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#define FEC_RS_COMM_INT_REQ__A 0x1C30003

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#define FEC_RS_COMM_INT_REQ__W 1

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#define FEC_RS_COMM_INT_REQ__M 0x1

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#define FEC_RS_COMM_INT_REQ__PRE 0x0

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#define FEC_RS_COMM_INT_STA__A 0x1C30005

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#define FEC_RS_COMM_INT_STA__W 2

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#define FEC_RS_COMM_INT_STA__M 0x3

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#define FEC_RS_COMM_INT_STA__PRE 0x0

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#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 0

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#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 1

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#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x1

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#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x0

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#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 1

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#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 1

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#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x2

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#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x0

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#define FEC_RS_COMM_INT_MSK__A 0x1C30006

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#define FEC_RS_COMM_INT_MSK__W 2

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#define FEC_RS_COMM_INT_MSK__M 0x3

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#define FEC_RS_COMM_INT_MSK__PRE 0x0

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#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 0

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#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 1

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#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x1

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#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x0

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#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 1

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#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 1

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#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x2

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#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x0

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#define FEC_RS_COMM_INT_STM__A 0x1C30007

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#define FEC_RS_COMM_INT_STM__W 2

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#define FEC_RS_COMM_INT_STM__M 0x3

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#define FEC_RS_COMM_INT_STM__PRE 0x0

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#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 0

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#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 1

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#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x1

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#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x0

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#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 1

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#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 1

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#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x2

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#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x0

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#define FEC_RS_STATUS__A 0x1C30010

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#define FEC_RS_STATUS__W 1

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#define FEC_RS_STATUS__M 0x1

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#define FEC_RS_STATUS__PRE 0x0

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#define FEC_RS_MODE__A 0x1C30011

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#define FEC_RS_MODE__W 1

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#define FEC_RS_MODE__M 0x1

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#define FEC_RS_MODE__PRE 0x0

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#define FEC_RS_MODE_BYPASS__B 0

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#define FEC_RS_MODE_BYPASS__W 1

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#define FEC_RS_MODE_BYPASS__M 0x1

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#define FEC_RS_MODE_BYPASS__PRE 0x0

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#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C30012

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#define FEC_RS_MEASUREMENT_PERIOD__W 16

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#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF

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#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x993

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#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 0

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#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 16

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#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF

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#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x993

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#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C30013

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#define FEC_RS_MEASUREMENT_PRESCALE__W 16

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#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF

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#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x1

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#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 0

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#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 16

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#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF

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#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x1

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#define FEC_RS_NR_BIT_ERRORS__A 0x1C30014

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#define FEC_RS_NR_BIT_ERRORS__W 16

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#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF

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#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF

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#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 0

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#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 12

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#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF

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#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF

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#define FEC_RS_NR_BIT_ERRORS_EXP__B 12

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#define FEC_RS_NR_BIT_ERRORS_EXP__W 4

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#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF000

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#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF000

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#define FEC_RS_NR_SYMBOL_ERRORS__A 0x1C30015

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#define FEC_RS_NR_SYMBOL_ERRORS__W 16

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#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF

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#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF

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#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 0

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#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 12

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#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF

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#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF

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#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 12

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#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 4

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#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF000

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#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF000

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#define FEC_RS_NR_PACKET_ERRORS__A 0x1C30016

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#define FEC_RS_NR_PACKET_ERRORS__W 16

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#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF

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#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF

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#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 0

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#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 12

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#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF

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#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF

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#define FEC_RS_NR_PACKET_ERRORS_EXP__B 12

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#define FEC_RS_NR_PACKET_ERRORS_EXP__W 4

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#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF000

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#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF000

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#define FEC_RS_NR_FAILURES__A 0x1C30017

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#define FEC_RS_NR_FAILURES__W 16

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#define FEC_RS_NR_FAILURES__M 0xFFFF

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#define FEC_RS_NR_FAILURES__PRE 0x0

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#define FEC_RS_NR_FAILURES_FIXED_MANT__B 0

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#define FEC_RS_NR_FAILURES_FIXED_MANT__W 12

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#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF

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#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x0

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#define FEC_RS_NR_FAILURES_EXP__B 12

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#define FEC_RS_NR_FAILURES_EXP__W 4

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#define FEC_RS_NR_FAILURES_EXP__M 0xF000

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#define FEC_RS_NR_FAILURES_EXP__PRE 0x0

#define FEC_OC_COMM_EXEC__A 0x1C40000

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#define FEC_OC_COMM_EXEC__W 2

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#define FEC_OC_COMM_EXEC__M 0x3

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#define FEC_OC_COMM_EXEC__PRE 0x0

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#define FEC_OC_COMM_EXEC_STOP 0x0

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#define FEC_OC_COMM_EXEC_ACTIVE 0x1

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#define FEC_OC_COMM_EXEC_HOLD 0x2

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#define FEC_OC_COMM_MB__A 0x1C40002

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#define FEC_OC_COMM_MB__W 2

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#define FEC_OC_COMM_MB__M 0x3

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#define FEC_OC_COMM_MB__PRE 0x0

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#define FEC_OC_COMM_MB_CTL__B 0

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#define FEC_OC_COMM_MB_CTL__W 1

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#define FEC_OC_COMM_MB_CTL__M 0x1

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#define FEC_OC_COMM_MB_CTL__PRE 0x0

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#define FEC_OC_COMM_MB_CTL_OFF 0x0

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#define FEC_OC_COMM_MB_CTL_ON 0x1

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#define FEC_OC_COMM_MB_OBS__B 1

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#define FEC_OC_COMM_MB_OBS__W 1

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#define FEC_OC_COMM_MB_OBS__M 0x2

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#define FEC_OC_COMM_MB_OBS__PRE 0x0

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#define FEC_OC_COMM_MB_OBS_OFF 0x0

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#define FEC_OC_COMM_MB_OBS_ON 0x2

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#define FEC_OC_COMM_INT_REQ__A 0x1C40003

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#define FEC_OC_COMM_INT_REQ__W 1

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#define FEC_OC_COMM_INT_REQ__M 0x1

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#define FEC_OC_COMM_INT_REQ__PRE 0x0

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#define FEC_OC_COMM_INT_STA__A 0x1C40005

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#define FEC_OC_COMM_INT_STA__W 8

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#define FEC_OC_COMM_INT_STA__M 0xFF

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#define FEC_OC_COMM_INT_STA__PRE 0x0

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#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 0

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#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 1

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#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x1

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#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x0

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#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 1

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#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 1

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#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x2

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#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x0

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#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 2

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#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 1

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#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x4

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#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x0

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#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 3

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#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 1

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#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x8

414

#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x0

415

416

#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 4

417

#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 1

418

#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x10

419

#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x0

420

421

#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 5

422

#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 1

423

#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x20

424

#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x0

425

426

#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 6

427

#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 1

428

#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x40

429

#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x0

430

431

#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 7

432

#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 1

433

#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x80

434

#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x0

435

436

#define FEC_OC_COMM_INT_MSK__A 0x1C40006

437

#define FEC_OC_COMM_INT_MSK__W 8

438

#define FEC_OC_COMM_INT_MSK__M 0xFF

439

#define FEC_OC_COMM_INT_MSK__PRE 0x0

440

#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 0

441

#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 1

442

#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x1

443

#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x0

444

#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 1

445

#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 1

446

#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x2

447

#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x0

448

#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 2

449

#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 1

450

#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x4

451

#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x0

452

#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 3

453

#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 1

454

#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x8

455

#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x0

456

#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 4

457

#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 1

458

#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x10

459

#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x0

460

#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 5

461

#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 1

462

#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x20

463

#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x0

464

#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 6

465

#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 1

466

#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x40

467

#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x0

468

#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 7

469

#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 1

470

#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x80

471

#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x0

472

473

#define FEC_OC_COMM_INT_STM__A 0x1C40007

474

#define FEC_OC_COMM_INT_STM__W 8

475

#define FEC_OC_COMM_INT_STM__M 0xFF

476

#define FEC_OC_COMM_INT_STM__PRE 0x0

477

#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 0

478

#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 1

479

#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x1

480

#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x0

481

#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 1

482

#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 1

483

#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x2

484

#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x0

485

#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 2

486

#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 1

487

#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x4

488

#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x0

489

#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 3

490

#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 1

491

#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x8

492

#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x0

493

#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 4

494

#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 1

495

#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x10

496

#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x0

497

#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 5

498

#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 1

499

#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x20

500

#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x0

501

#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 6

502

#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 1

503

#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x40

504

#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x0

505

#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 7

506

#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 1

507

#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x80

508

#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x0

509

510

#define FEC_OC_STATUS__A 0x1C40010

511

#define FEC_OC_STATUS__W 5

512

#define FEC_OC_STATUS__M 0x1F

513

#define FEC_OC_STATUS__PRE 0x0

514

515

#define FEC_OC_STATUS_DPR_STATUS__B 0

516

#define FEC_OC_STATUS_DPR_STATUS__W 1

517

#define FEC_OC_STATUS_DPR_STATUS__M 0x1

518

#define FEC_OC_STATUS_DPR_STATUS__PRE 0x0

519

520

#define FEC_OC_STATUS_SNC_STATUS__B 1

521

#define FEC_OC_STATUS_SNC_STATUS__W 2

522

#define FEC_OC_STATUS_SNC_STATUS__M 0x6

523

#define FEC_OC_STATUS_SNC_STATUS__PRE 0x0

524

#define FEC_OC_STATUS_SNC_STATUS_HUNTING 0x0

525

#define FEC_OC_STATUS_SNC_STATUS_TRACKING 0x2

526

#define FEC_OC_STATUS_SNC_STATUS_LOCKED 0x4

527

528

#define FEC_OC_STATUS_FIFO_FULL__B 3

529

#define FEC_OC_STATUS_FIFO_FULL__W 1

530

#define FEC_OC_STATUS_FIFO_FULL__M 0x8

531

#define FEC_OC_STATUS_FIFO_FULL__PRE 0x0

532

533

#define FEC_OC_STATUS_FIFO_EMPTY__B 4

534

#define FEC_OC_STATUS_FIFO_EMPTY__W 1

535

#define FEC_OC_STATUS_FIFO_EMPTY__M 0x10

536

#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x0

537

538

#define FEC_OC_MODE__A 0x1C40011

539

#define FEC_OC_MODE__W 4

540

#define FEC_OC_MODE__M 0xF

541

#define FEC_OC_MODE__PRE 0x0

542

543

#define FEC_OC_MODE_PARITY__B 0

544

#define FEC_OC_MODE_PARITY__W 1

545

#define FEC_OC_MODE_PARITY__M 0x1

546

#define FEC_OC_MODE_PARITY__PRE 0x0

547

548

#define FEC_OC_MODE_TRANSPARENT__B 1

549

#define FEC_OC_MODE_TRANSPARENT__W 1

550

#define FEC_OC_MODE_TRANSPARENT__M 0x2

551

#define FEC_OC_MODE_TRANSPARENT__PRE 0x0

552

553

#define FEC_OC_MODE_CLEAR__B 2

554

#define FEC_OC_MODE_CLEAR__W 1

555

#define FEC_OC_MODE_CLEAR__M 0x4

556

#define FEC_OC_MODE_CLEAR__PRE 0x0

557

558

#define FEC_OC_MODE_RETAIN_FRAMING__B 3

559

#define FEC_OC_MODE_RETAIN_FRAMING__W 1

560

#define FEC_OC_MODE_RETAIN_FRAMING__M 0x8

561

#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x0

562

563

#define FEC_OC_DPR_MODE__A 0x1C40012

564

#define FEC_OC_DPR_MODE__W 2

565

#define FEC_OC_DPR_MODE__M 0x3

566

#define FEC_OC_DPR_MODE__PRE 0x0

567

568

#define FEC_OC_DPR_MODE_ERR_DISABLE__B 0

569

#define FEC_OC_DPR_MODE_ERR_DISABLE__W 1

570

#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x1

571

#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x0

572

573

#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 1

574

#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 1

575

#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x2

576

#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x0

577

578

579

#define FEC_OC_DPR_UNLOCK__A 0x1C40013

580

#define FEC_OC_DPR_UNLOCK__W 1

581

#define FEC_OC_DPR_UNLOCK__M 0x1

582

#define FEC_OC_DPR_UNLOCK__PRE 0x0

583

#define FEC_OC_DTO_MODE__A 0x1C40014

584

#define FEC_OC_DTO_MODE__W 3

585

#define FEC_OC_DTO_MODE__M 0x7

586

#define FEC_OC_DTO_MODE__PRE 0x0

587

588

#define FEC_OC_DTO_MODE_DYNAMIC__B 0

589

#define FEC_OC_DTO_MODE_DYNAMIC__W 1

590

#define FEC_OC_DTO_MODE_DYNAMIC__M 0x1

591

#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x0

592

593

#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 1

594

#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 1

595

#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x2

596

#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x0

597

598

#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 2

599

#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 1

600

#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x4

601

#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x0

602

603

604

#define FEC_OC_DTO_PERIOD__A 0x1C40015

605

#define FEC_OC_DTO_PERIOD__W 8

606

#define FEC_OC_DTO_PERIOD__M 0xFF

607

#define FEC_OC_DTO_PERIOD__PRE 0x0

608

#define FEC_OC_DTO_RATE_LO__A 0x1C40016

609

#define FEC_OC_DTO_RATE_LO__W 16

610

#define FEC_OC_DTO_RATE_LO__M 0xFFFF

611

#define FEC_OC_DTO_RATE_LO__PRE 0x0

612

613

#define FEC_OC_DTO_RATE_LO_RATE_LO__B 0

614

#define FEC_OC_DTO_RATE_LO_RATE_LO__W 16

615

#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF

616

#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x0

617

618

#define FEC_OC_DTO_RATE_HI__A 0x1C40017

619

#define FEC_OC_DTO_RATE_HI__W 10

620

#define FEC_OC_DTO_RATE_HI__M 0x3FF

621

#define FEC_OC_DTO_RATE_HI__PRE 0xC0

622

623

#define FEC_OC_DTO_RATE_HI_RATE_HI__B 0

624

#define FEC_OC_DTO_RATE_HI_RATE_HI__W 10

625

#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF

626

#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC0

627

628

#define FEC_OC_DTO_BURST_LEN__A 0x1C40018

629

#define FEC_OC_DTO_BURST_LEN__W 8

630

#define FEC_OC_DTO_BURST_LEN__M 0xFF

631

#define FEC_OC_DTO_BURST_LEN__PRE 0xBC

632

633

#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 0

634

#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 8

635

#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF

636

#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC

637

638

#define FEC_OC_FCT_MODE__A 0x1C4001A

639

#define FEC_OC_FCT_MODE__W 2

640

#define FEC_OC_FCT_MODE__M 0x3

641

#define FEC_OC_FCT_MODE__PRE 0x0

642

643

#define FEC_OC_FCT_MODE_RAT_ENA__B 0

644

#define FEC_OC_FCT_MODE_RAT_ENA__W 1

645

#define FEC_OC_FCT_MODE_RAT_ENA__M 0x1

646

#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x0

647

648

#define FEC_OC_FCT_MODE_VIRT_ENA__B 1

649

#define FEC_OC_FCT_MODE_VIRT_ENA__W 1

650

#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x2

651

#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x0

652

653

#define FEC_OC_FCT_USAGE__A 0x1C4001B

654

#define FEC_OC_FCT_USAGE__W 3

655

#define FEC_OC_FCT_USAGE__M 0x7

656

#define FEC_OC_FCT_USAGE__PRE 0x7

657

658

#define FEC_OC_FCT_USAGE_USAGE__B 0

659

#define FEC_OC_FCT_USAGE_USAGE__W 3

660

#define FEC_OC_FCT_USAGE_USAGE__M 0x7

661

#define FEC_OC_FCT_USAGE_USAGE__PRE 0x7

662

663

#define FEC_OC_FCT_OCCUPATION__A 0x1C4001C

664

#define FEC_OC_FCT_OCCUPATION__W 12

665

#define FEC_OC_FCT_OCCUPATION__M 0xFFF

666

#define FEC_OC_FCT_OCCUPATION__PRE 0x0

667

668

#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 0

669

#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 12

670

#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF

671

#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x0

672

673

#define FEC_OC_TMD_MODE__A 0x1C4001E

674

#define FEC_OC_TMD_MODE__W 3

675

#define FEC_OC_TMD_MODE__M 0x7

676

#define FEC_OC_TMD_MODE__PRE 0x4

677

678

#define FEC_OC_TMD_MODE_MODE__B 0

679

#define FEC_OC_TMD_MODE_MODE__W 3

680

#define FEC_OC_TMD_MODE_MODE__M 0x7

681

#define FEC_OC_TMD_MODE_MODE__PRE 0x4

682

683

#define FEC_OC_TMD_COUNT__A 0x1C4001F

684

#define FEC_OC_TMD_COUNT__W 10

685

#define FEC_OC_TMD_COUNT__M 0x3FF

686

#define FEC_OC_TMD_COUNT__PRE 0x1F4

687

688

#define FEC_OC_TMD_COUNT_COUNT__B 0

689

#define FEC_OC_TMD_COUNT_COUNT__W 10

690

#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF

691

#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F4

692

693

#define FEC_OC_TMD_HI_MARGIN__A 0x1C40020

694

#define FEC_OC_TMD_HI_MARGIN__W 11

695

#define FEC_OC_TMD_HI_MARGIN__M 0x7FF

696

#define FEC_OC_TMD_HI_MARGIN__PRE 0x500

697

698

#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 0

699

#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 11

700

#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF

701

#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x500

702

703

#define FEC_OC_TMD_LO_MARGIN__A 0x1C40021

704

#define FEC_OC_TMD_LO_MARGIN__W 11

705

#define FEC_OC_TMD_LO_MARGIN__M 0x7FF

706

#define FEC_OC_TMD_LO_MARGIN__PRE 0x300

707

708

#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 0

709

#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 11

710

#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF

711

#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x300

712

713

#define FEC_OC_TMD_CTL_UPD_RATE__A 0x1C40022

714

#define FEC_OC_TMD_CTL_UPD_RATE__W 4

715

#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF

716

#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x1

717

718

#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 0

719

#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 4

720

#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF

721

#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x1

722

723

#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C40023

724

#define FEC_OC_TMD_INT_UPD_RATE__W 4

725

#define FEC_OC_TMD_INT_UPD_RATE__M 0xF

726

#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x4

727

728

#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 0

729

#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 4

730

#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF

731

#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x4

732

733

#define FEC_OC_AVR_PARM_A__A 0x1C40026

734

#define FEC_OC_AVR_PARM_A__W 4

735

#define FEC_OC_AVR_PARM_A__M 0xF

736

#define FEC_OC_AVR_PARM_A__PRE 0x6

737

738

#define FEC_OC_AVR_PARM_A_PARM__B 0

739

#define FEC_OC_AVR_PARM_A_PARM__W 4

740

#define FEC_OC_AVR_PARM_A_PARM__M 0xF

741

#define FEC_OC_AVR_PARM_A_PARM__PRE 0x6

742

743

#define FEC_OC_AVR_PARM_B__A 0x1C40027

744

#define FEC_OC_AVR_PARM_B__W 4

745

#define FEC_OC_AVR_PARM_B__M 0xF

746

#define FEC_OC_AVR_PARM_B__PRE 0x4

747

748

#define FEC_OC_AVR_PARM_B_PARM__B 0

749

#define FEC_OC_AVR_PARM_B_PARM__W 4

750

#define FEC_OC_AVR_PARM_B_PARM__M 0xF

751

#define FEC_OC_AVR_PARM_B_PARM__PRE 0x4

752

753

#define FEC_OC_AVR_AVG_LO__A 0x1C40028

754

#define FEC_OC_AVR_AVG_LO__W 16

755

#define FEC_OC_AVR_AVG_LO__M 0xFFFF

756

#define FEC_OC_AVR_AVG_LO__PRE 0x0

757

758

#define FEC_OC_AVR_AVG_LO_AVG_LO__B 0

759

#define FEC_OC_AVR_AVG_LO_AVG_LO__W 16

760

#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF

761

#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x0

762

763

#define FEC_OC_AVR_AVG_HI__A 0x1C40029

764

#define FEC_OC_AVR_AVG_HI__W 6

765

#define FEC_OC_AVR_AVG_HI__M 0x3F

766

#define FEC_OC_AVR_AVG_HI__PRE 0x0

767

768

#define FEC_OC_AVR_AVG_HI_AVG_HI__B 0

769

#define FEC_OC_AVR_AVG_HI_AVG_HI__W 6

770

#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F

771

#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x0

772

773

#define FEC_OC_RCN_MODE__A 0x1C4002C

774

#define FEC_OC_RCN_MODE__W 5

775

#define FEC_OC_RCN_MODE__M 0x1F

776

#define FEC_OC_RCN_MODE__PRE 0x1F

777

778

#define FEC_OC_RCN_MODE_MODE__B 0

779

#define FEC_OC_RCN_MODE_MODE__W 5

780

#define FEC_OC_RCN_MODE_MODE__M 0x1F

781

#define FEC_OC_RCN_MODE_MODE__PRE 0x1F

782

783

#define FEC_OC_RCN_OCC_SETTLE__A 0x1C4002D

784

#define FEC_OC_RCN_OCC_SETTLE__W 11

785

#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF

786

#define FEC_OC_RCN_OCC_SETTLE__PRE 0x400

787

788

#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 0

789

#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 11

790

#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF

791

#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x400

792

793

#define FEC_OC_RCN_GAIN__A 0x1C4002E

794

#define FEC_OC_RCN_GAIN__W 4

795

#define FEC_OC_RCN_GAIN__M 0xF

796

#define FEC_OC_RCN_GAIN__PRE 0xC

797

798

#define FEC_OC_RCN_GAIN_GAIN__B 0

799

#define FEC_OC_RCN_GAIN_GAIN__W 4

800

#define FEC_OC_RCN_GAIN_GAIN__M 0xF

801

#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC

802

803

#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C40030

804

#define FEC_OC_RCN_CTL_RATE_LO__W 16

805

#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF

806

#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x0

807

808

#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 0

809

#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 16

810

#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF

811

#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x0

812

813

#define FEC_OC_RCN_CTL_RATE_HI__A 0x1C40031

814

#define FEC_OC_RCN_CTL_RATE_HI__W 8

815

#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF

816

#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC0

817

818

#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 0

819

#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 8

820

#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF

821

#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC0

822

823

#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C40032

824

#define FEC_OC_RCN_CTL_STEP_LO__W 16

825

#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF

826

#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x0

827

828

#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 0

829

#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 16

830

#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF

831

#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x0

832

833

#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C40033

834

#define FEC_OC_RCN_CTL_STEP_HI__W 8

835

#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF

836

#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x8

837

838

#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 0

839

#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 8

840

#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF

841

#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x8

842

843

#define FEC_OC_RCN_DTO_OFS_LO__A 0x1C40034

844

#define FEC_OC_RCN_DTO_OFS_LO__W 16

845

#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF

846

#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x0

847

848

#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 0

849

#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 16

850

#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF

851

#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x0

852

853

#define FEC_OC_RCN_DTO_OFS_HI__A 0x1C40035

854

#define FEC_OC_RCN_DTO_OFS_HI__W 8

855

#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF

856

#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x0

857

858

#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 0

859

#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 8

860

#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF

861

#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x0

862

863

#define FEC_OC_RCN_DTO_RATE_LO__A 0x1C40036

864

#define FEC_OC_RCN_DTO_RATE_LO__W 16

865

#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF

866

#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x0

867

868

#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 0

869

#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 16

870

#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF

871

#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x0

872

873

#define FEC_OC_RCN_DTO_RATE_HI__A 0x1C40037

874

#define FEC_OC_RCN_DTO_RATE_HI__W 8

875

#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF

876

#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x0

877

878

#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 0

879

#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 8

880

#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF

881

#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x0

882

883

#define FEC_OC_RCN_RATE_CLIP_LO__A 0x1C40038

884

#define FEC_OC_RCN_RATE_CLIP_LO__W 16

885

#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF

886

#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x0

887

888

#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 0

889

#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 16

890

#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF

891

#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x0

892

893

#define FEC_OC_RCN_RATE_CLIP_HI__A 0x1C40039

894

#define FEC_OC_RCN_RATE_CLIP_HI__W 8

895

#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF

896

#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF0

897

898

#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 0

899

#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 8

900

#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF

901

#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF0

902

903

#define FEC_OC_RCN_DYN_RATE_LO__A 0x1C4003A

904

#define FEC_OC_RCN_DYN_RATE_LO__W 16

905

#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF

906

#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x0

907

908

#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 0

909

#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 16

910

#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF

911

#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x0

912

913

#define FEC_OC_RCN_DYN_RATE_HI__A 0x1C4003B

914

#define FEC_OC_RCN_DYN_RATE_HI__W 8

915

#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF

916

#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x0

917

918

#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 0

919

#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 8

920

#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF

921

#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x0

922

923

#define FEC_OC_SNC_MODE__A 0x1C40040

924

#define FEC_OC_SNC_MODE__W 5

925

#define FEC_OC_SNC_MODE__M 0x1F

926

#define FEC_OC_SNC_MODE__PRE 0x0

927

928

#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 0

929

#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 1

930

#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x1

931

#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x0

932

933

#define FEC_OC_SNC_MODE_ERROR_CTL__B 1

934

#define FEC_OC_SNC_MODE_ERROR_CTL__W 2

935

#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x6

936

#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x0

937

938

#define FEC_OC_SNC_MODE_CORR_DISABLE__B 3

939

#define FEC_OC_SNC_MODE_CORR_DISABLE__W 1

940

#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x8

941

#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x0

942

943

#define FEC_OC_SNC_MODE_SHUTDOWN__B 4

944

#define FEC_OC_SNC_MODE_SHUTDOWN__W 1

945

#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x10

946

#define FEC_OC_SNC_MODE_SHUTDOWN__PRE 0x0

947

948

#define FEC_OC_SNC_LWM__A 0x1C40041

949

#define FEC_OC_SNC_LWM__W 4

950

#define FEC_OC_SNC_LWM__M 0xF

951

#define FEC_OC_SNC_LWM__PRE 0x3

952

953

#define FEC_OC_SNC_LWM_MARK__B 0

954

#define FEC_OC_SNC_LWM_MARK__W 4

955

#define FEC_OC_SNC_LWM_MARK__M 0xF

956

#define FEC_OC_SNC_LWM_MARK__PRE 0x3

957

958

#define FEC_OC_SNC_HWM__A 0x1C40042

959

#define FEC_OC_SNC_HWM__W 4

960

#define FEC_OC_SNC_HWM__M 0xF

961

#define FEC_OC_SNC_HWM__PRE 0x5

962

963

#define FEC_OC_SNC_HWM_MARK__B 0

964

#define FEC_OC_SNC_HWM_MARK__W 4

965

#define FEC_OC_SNC_HWM_MARK__M 0xF

966

#define FEC_OC_SNC_HWM_MARK__PRE 0x5

967

968

#define FEC_OC_SNC_UNLOCK__A 0x1C40043

969

#define FEC_OC_SNC_UNLOCK__W 1

970

#define FEC_OC_SNC_UNLOCK__M 0x1

971

#define FEC_OC_SNC_UNLOCK__PRE 0x0

972

973

#define FEC_OC_SNC_UNLOCK_RESTART__B 0

974

#define FEC_OC_SNC_UNLOCK_RESTART__W 1

975

#define FEC_OC_SNC_UNLOCK_RESTART__M 0x1

976

#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x0

977

978

#define FEC_OC_SNC_LOCK_COUNT__A 0x1C40044

979

#define FEC_OC_SNC_LOCK_COUNT__W 12

980

#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF

981

#define FEC_OC_SNC_LOCK_COUNT__PRE 0x0

982

983

#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 0

984

#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 12

985

#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF

986

#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x0

987

988

#define FEC_OC_SNC_FAIL_COUNT__A 0x1C40045

989

#define FEC_OC_SNC_FAIL_COUNT__W 12

990

#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF

991

#define FEC_OC_SNC_FAIL_COUNT__PRE 0x0

992

993

#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 0

994

#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 12

995

#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF

996

#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x0

997

998

#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C40046

999

#define FEC_OC_SNC_FAIL_PERIOD__W 16

1000

#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF

1001

#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x1171

1002

1003

#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 0

1004

#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 16

1005

#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF

1006

#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x1171

1007

1008

#define FEC_OC_EMS_MODE__A 0x1C40047

1009

#define FEC_OC_EMS_MODE__W 2

1010

#define FEC_OC_EMS_MODE__M 0x3

1011

#define FEC_OC_EMS_MODE__PRE 0x0

1012

1013

#define FEC_OC_EMS_MODE_MODE__B 0

1014

#define FEC_OC_EMS_MODE_MODE__W 2

1015

#define FEC_OC_EMS_MODE_MODE__M 0x3

1016

#define FEC_OC_EMS_MODE_MODE__PRE 0x0

1017

1018

#define FEC_OC_IPR_MODE__A 0x1C40048

1019

#define FEC_OC_IPR_MODE__W 12

1020

#define FEC_OC_IPR_MODE__M 0xFFF

1021

#define FEC_OC_IPR_MODE__PRE 0x0

1022

1023

#define FEC_OC_IPR_MODE_SERIAL__B 0

1024

#define FEC_OC_IPR_MODE_SERIAL__W 1

1025

#define FEC_OC_IPR_MODE_SERIAL__M 0x1

1026

#define FEC_OC_IPR_MODE_SERIAL__PRE 0x0

1027

1028

#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 1

1029

#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 1

1030

#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x2

1031

#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x0

1032

1033

#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 2

1034

#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 1

1035

#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x4

1036

#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x0

1037

1038

#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 3

1039

#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 1

1040

#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x8

1041

#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x0

1042

1043

#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 4

1044

#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 1

1045

#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x10

1046

#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x0

1047

1048

#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 5

1049

#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 1

1050

#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x20

1051

#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x0

1052

1053

#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 6

1054

#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 1

1055

#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x40

1056

#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x0

1057

1058

#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 7

1059

#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 1

1060

#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x80

1061

#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x0

1062

1063

#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 8

1064

#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 1

1065

#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x100

1066

#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x0

1067

1068

#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 9

1069

#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 1

1070

#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x200

1071

#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x0

1072

1073

#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 10

1074

#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 1

1075

#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x400

1076

#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x0

1077

1078

#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 11

1079

#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 1

1080

#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x800

1081

#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x0

1082

1083

#define FEC_OC_IPR_INVERT__A 0x1C40049

1084

#define FEC_OC_IPR_INVERT__W 12

1085

#define FEC_OC_IPR_INVERT__M 0xFFF

1086

#define FEC_OC_IPR_INVERT__PRE 0x0

1087

1088

#define FEC_OC_IPR_INVERT_MD0__B 0

1089

#define FEC_OC_IPR_INVERT_MD0__W 1

1090

#define FEC_OC_IPR_INVERT_MD0__M 0x1

1091

#define FEC_OC_IPR_INVERT_MD0__PRE 0x0

1092

1093

#define FEC_OC_IPR_INVERT_MD1__B 1

1094

#define FEC_OC_IPR_INVERT_MD1__W 1

1095

#define FEC_OC_IPR_INVERT_MD1__M 0x2

1096

#define FEC_OC_IPR_INVERT_MD1__PRE 0x0

1097

1098

#define FEC_OC_IPR_INVERT_MD2__B 2

1099

#define FEC_OC_IPR_INVERT_MD2__W 1

1100

#define FEC_OC_IPR_INVERT_MD2__M 0x4

1101

#define FEC_OC_IPR_INVERT_MD2__PRE 0x0

1102

1103

#define FEC_OC_IPR_INVERT_MD3__B 3

1104

#define FEC_OC_IPR_INVERT_MD3__W 1

1105

#define FEC_OC_IPR_INVERT_MD3__M 0x8

1106

#define FEC_OC_IPR_INVERT_MD3__PRE 0x0

1107

1108

#define FEC_OC_IPR_INVERT_MD4__B 4

1109

#define FEC_OC_IPR_INVERT_MD4__W 1

1110

#define FEC_OC_IPR_INVERT_MD4__M 0x10

1111

#define FEC_OC_IPR_INVERT_MD4__PRE 0x0

1112

1113

#define FEC_OC_IPR_INVERT_MD5__B 5

1114

#define FEC_OC_IPR_INVERT_MD5__W 1

1115

#define FEC_OC_IPR_INVERT_MD5__M 0x20

1116

#define FEC_OC_IPR_INVERT_MD5__PRE 0x0

1117

1118

#define FEC_OC_IPR_INVERT_MD6__B 6

1119

#define FEC_OC_IPR_INVERT_MD6__W 1

1120

#define FEC_OC_IPR_INVERT_MD6__M 0x40

1121

#define FEC_OC_IPR_INVERT_MD6__PRE 0x0

1122

1123

#define FEC_OC_IPR_INVERT_MD7__B 7

1124

#define FEC_OC_IPR_INVERT_MD7__W 1

1125

#define FEC_OC_IPR_INVERT_MD7__M 0x80

1126

#define FEC_OC_IPR_INVERT_MD7__PRE 0x0

1127

1128

#define FEC_OC_IPR_INVERT_MERR__B 8

1129

#define FEC_OC_IPR_INVERT_MERR__W 1

1130

#define FEC_OC_IPR_INVERT_MERR__M 0x100

1131

#define FEC_OC_IPR_INVERT_MERR__PRE 0x0

1132

1133

#define FEC_OC_IPR_INVERT_MSTRT__B 9

1134

#define FEC_OC_IPR_INVERT_MSTRT__W 1

1135

#define FEC_OC_IPR_INVERT_MSTRT__M 0x200

1136

#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x0

1137

1138

#define FEC_OC_IPR_INVERT_MVAL__B 10

1139

#define FEC_OC_IPR_INVERT_MVAL__W 1

1140

#define FEC_OC_IPR_INVERT_MVAL__M 0x400

1141

#define FEC_OC_IPR_INVERT_MVAL__PRE 0x0

1142

1143

#define FEC_OC_IPR_INVERT_MCLK__B 11

1144

#define FEC_OC_IPR_INVERT_MCLK__W 1

1145

#define FEC_OC_IPR_INVERT_MCLK__M 0x800

1146

#define FEC_OC_IPR_INVERT_MCLK__PRE 0x0

1147

1148

#define FEC_OC_OCR_MODE__A 0x1C40050

1149

#define FEC_OC_OCR_MODE__W 4

1150

#define FEC_OC_OCR_MODE__M 0xF

1151

#define FEC_OC_OCR_MODE__PRE 0x0

1152

1153

#define FEC_OC_OCR_MODE_MB_SELECT__B 0

1154

#define FEC_OC_OCR_MODE_MB_SELECT__W 1

1155

#define FEC_OC_OCR_MODE_MB_SELECT__M 0x1

1156

#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x0

1157

1158

#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 1

1159

#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 1

1160

#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x2

1161

#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x0

1162

1163

#define FEC_OC_OCR_MODE_GRAB_SELECT__B 2

1164

#define FEC_OC_OCR_MODE_GRAB_SELECT__W 1

1165

#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x4

1166

#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x0

1167

1168

#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 3

1169

#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 1

1170

#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x8

1171

#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x0

1172

1173

#define FEC_OC_OCR_RATE__A 0x1C40051

1174

#define FEC_OC_OCR_RATE__W 4

1175

#define FEC_OC_OCR_RATE__M 0xF

1176

#define FEC_OC_OCR_RATE__PRE 0x0

1177

1178

#define FEC_OC_OCR_RATE_RATE__B 0

1179

#define FEC_OC_OCR_RATE_RATE__W 4

1180

#define FEC_OC_OCR_RATE_RATE__M 0xF

1181

#define FEC_OC_OCR_RATE_RATE__PRE 0x0

1182

1183

#define FEC_OC_OCR_INVERT__A 0x1C40052

1184

#define FEC_OC_OCR_INVERT__W 12

1185

#define FEC_OC_OCR_INVERT__M 0xFFF

1186

#define FEC_OC_OCR_INVERT__PRE 0x800

1187

1188

#define FEC_OC_OCR_INVERT_INVERT__B 0

1189

#define FEC_OC_OCR_INVERT_INVERT__W 12

1190

#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF

1191

#define FEC_OC_OCR_INVERT_INVERT__PRE 0x800

1192

1193

#define FEC_OC_OCR_GRAB_COUNT__A 0x1C40053

1194

#define FEC_OC_OCR_GRAB_COUNT__W 16

1195

#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF

1196

#define FEC_OC_OCR_GRAB_COUNT__PRE 0x0

1197

1198

#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 0

1199

#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 16

1200

#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF

1201

#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x0

1202

1203

#define FEC_OC_OCR_GRAB_SYNC__A 0x1C40054

1204

#define FEC_OC_OCR_GRAB_SYNC__W 8

1205

#define FEC_OC_OCR_GRAB_SYNC__M 0xFF

1206

#define FEC_OC_OCR_GRAB_SYNC__PRE 0x0

1207

1208

#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 0

1209

#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 3

1210

#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x7

1211

#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x0

1212

1213

#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 3

1214

#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 4

1215

#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x78

1216

#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x0

1217

1218

#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 7

1219

#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 1

1220

#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x80

1221

#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x0

1222

1223

#define FEC_OC_OCR_GRAB_RD0__A 0x1C40055

1224

#define FEC_OC_OCR_GRAB_RD0__W 10

1225

#define FEC_OC_OCR_GRAB_RD0__M 0x3FF

1226

#define FEC_OC_OCR_GRAB_RD0__PRE 0x0

1227

1228

#define FEC_OC_OCR_GRAB_RD0_DATA__B 0

1229

#define FEC_OC_OCR_GRAB_RD0_DATA__W 10

1230

#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF

1231

#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x0

1232

1233

#define FEC_OC_OCR_GRAB_RD1__A 0x1C40056

1234

#define FEC_OC_OCR_GRAB_RD1__W 10

1235

#define FEC_OC_OCR_GRAB_RD1__M 0x3FF

1236

#define FEC_OC_OCR_GRAB_RD1__PRE 0x0

1237

1238

#define FEC_OC_OCR_GRAB_RD1_DATA__B 0

1239

#define FEC_OC_OCR_GRAB_RD1_DATA__W 10

1240

#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF

1241

#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x0

1242

1243

#define FEC_OC_OCR_GRAB_RD2__A 0x1C40057

1244

#define FEC_OC_OCR_GRAB_RD2__W 10

1245

#define FEC_OC_OCR_GRAB_RD2__M 0x3FF

1246

#define FEC_OC_OCR_GRAB_RD2__PRE 0x0

1247

1248

#define FEC_OC_OCR_GRAB_RD2_DATA__B 0

1249

#define FEC_OC_OCR_GRAB_RD2_DATA__W 10

1250

#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF

1251

#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x0

1252

1253

#define FEC_OC_OCR_GRAB_RD3__A 0x1C40058

1254

#define FEC_OC_OCR_GRAB_RD3__W 10

1255

#define FEC_OC_OCR_GRAB_RD3__M 0x3FF

1256

#define FEC_OC_OCR_GRAB_RD3__PRE 0x0

1257

1258

#define FEC_OC_OCR_GRAB_RD3_DATA__B 0

1259

#define FEC_OC_OCR_GRAB_RD3_DATA__W 10

1260

#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF

1261

#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x0

1262

1263

#define FEC_OC_OCR_GRAB_RD4__A 0x1C40059

1264

#define FEC_OC_OCR_GRAB_RD4__W 10

1265

#define FEC_OC_OCR_GRAB_RD4__M 0x3FF

1266

#define FEC_OC_OCR_GRAB_RD4__PRE 0x0

1267

1268

#define FEC_OC_OCR_GRAB_RD4_DATA__B 0

1269

#define FEC_OC_OCR_GRAB_RD4_DATA__W 10

1270

#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF

1271

#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x0

1272

1273

#define FEC_OC_OCR_GRAB_RD5__A 0x1C4005A

1274

#define FEC_OC_OCR_GRAB_RD5__W 10

1275

#define FEC_OC_OCR_GRAB_RD5__M 0x3FF

1276

#define FEC_OC_OCR_GRAB_RD5__PRE 0x0

1277

1278

#define FEC_OC_OCR_GRAB_RD5_DATA__B 0

1279

#define FEC_OC_OCR_GRAB_RD5_DATA__W 10

1280

#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF

1281

#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x0

#define FEC_DI_RAM__A 0x1C50000

#define FEC_RS_RAM__A 0x1C60000

#define FEC_OC_RAM__A 0x1C70000

#define IQM_COMM_EXEC__A 0x1800000

1300

#define IQM_COMM_EXEC__W 2

1301

#define IQM_COMM_EXEC__M 0x3

1302

#define IQM_COMM_EXEC__PRE 0x0

1303

#define IQM_COMM_EXEC_B__B 0

1304

#define IQM_COMM_EXEC_B__W 2

1305

#define IQM_COMM_EXEC_B__M 0x3

1306

#define IQM_COMM_EXEC_B__PRE 0x0

1307

#define IQM_COMM_EXEC_B_STOP 0x0

1308

#define IQM_COMM_EXEC_B_ACTIVE 0x1

1309

#define IQM_COMM_EXEC_B_HOLD 0x2

1310

1311

#define IQM_COMM_MB__A 0x1800002

1312

#define IQM_COMM_MB__W 16

1313

#define IQM_COMM_MB__M 0xFFFF

1314

#define IQM_COMM_MB__PRE 0x0

1315

#define IQM_COMM_MB_B__B 0

1316

#define IQM_COMM_MB_B__W 16

1317

#define IQM_COMM_MB_B__M 0xFFFF

1318

#define IQM_COMM_MB_B__PRE 0x0

1319

1320

#define IQM_COMM_INT_REQ__A 0x1800003

1321

#define IQM_COMM_INT_REQ__W 3

1322

#define IQM_COMM_INT_REQ__M 0x7

1323

#define IQM_COMM_INT_REQ__PRE 0x0

1324

1325

#define IQM_COMM_INT_REQ_AF_REQ__B 0

1326

#define IQM_COMM_INT_REQ_AF_REQ__W 1

1327

#define IQM_COMM_INT_REQ_AF_REQ__M 0x1

1328

#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x0

1329

1330

#define IQM_COMM_INT_REQ_CF_REQ__B 1

1331

#define IQM_COMM_INT_REQ_CF_REQ__W 1

1332

#define IQM_COMM_INT_REQ_CF_REQ__M 0x2

1333

#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x0

1334

1335

#define IQM_COMM_INT_REQ_CW_REQ__B 2

1336

#define IQM_COMM_INT_REQ_CW_REQ__W 1

1337

#define IQM_COMM_INT_REQ_CW_REQ__M 0x4

1338

#define IQM_COMM_INT_REQ_CW_REQ__PRE 0x0

1339

1340

#define IQM_COMM_INT_STA__A 0x1800005

1341

#define IQM_COMM_INT_STA__W 16

1342

#define IQM_COMM_INT_STA__M 0xFFFF

1343

#define IQM_COMM_INT_STA__PRE 0x0

1344

#define IQM_COMM_INT_STA_B__B 0

1345

#define IQM_COMM_INT_STA_B__W 16

1346

#define IQM_COMM_INT_STA_B__M 0xFFFF

1347

#define IQM_COMM_INT_STA_B__PRE 0x0

1348

1349

#define IQM_COMM_INT_MSK__A 0x1800006

1350

#define IQM_COMM_INT_MSK__W 16

1351

#define IQM_COMM_INT_MSK__M 0xFFFF

1352

#define IQM_COMM_INT_MSK__PRE 0x0

1353

#define IQM_COMM_INT_MSK_B__B 0

1354

#define IQM_COMM_INT_MSK_B__W 16

1355

#define IQM_COMM_INT_MSK_B__M 0xFFFF

1356

#define IQM_COMM_INT_MSK_B__PRE 0x0

1357

1358

#define IQM_COMM_INT_STM__A 0x1800007

1359

#define IQM_COMM_INT_STM__W 16

1360

#define IQM_COMM_INT_STM__M 0xFFFF

1361

#define IQM_COMM_INT_STM__PRE 0x0

1362

#define IQM_COMM_INT_STM_B__B 0

1363

#define IQM_COMM_INT_STM_B__W 16

1364

#define IQM_COMM_INT_STM_B__M 0xFFFF

1365

#define IQM_COMM_INT_STM_B__PRE 0x0

#define IQM_FS_COMM_EXEC__A 0x1820000

1370

#define IQM_FS_COMM_EXEC__W 2

1371

#define IQM_FS_COMM_EXEC__M 0x3

1372

#define IQM_FS_COMM_EXEC__PRE 0x0

1373

#define IQM_FS_COMM_EXEC_STOP 0x0

1374

#define IQM_FS_COMM_EXEC_ACTIVE 0x1

1375

#define IQM_FS_COMM_EXEC_HOLD 0x2

1376

1377

#define IQM_FS_COMM_MB__A 0x1820002

1378

#define IQM_FS_COMM_MB__W 4

1379

#define IQM_FS_COMM_MB__M 0xF

1380

#define IQM_FS_COMM_MB__PRE 0x0

1381

#define IQM_FS_COMM_MB_CTL__B 0

1382

#define IQM_FS_COMM_MB_CTL__W 1

1383

#define IQM_FS_COMM_MB_CTL__M 0x1

1384

#define IQM_FS_COMM_MB_CTL__PRE 0x0

1385

#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x0

1386

#define IQM_FS_COMM_MB_CTL_CTL_ON 0x1

1387

#define IQM_FS_COMM_MB_OBS__B 1

1388

#define IQM_FS_COMM_MB_OBS__W 1

1389

#define IQM_FS_COMM_MB_OBS__M 0x2

1390

#define IQM_FS_COMM_MB_OBS__PRE 0x0

1391

#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x0

1392

#define IQM_FS_COMM_MB_OBS_OBS_ON 0x2

1393

#define IQM_FS_COMM_MB_CTL_MUX__B 2

1394

#define IQM_FS_COMM_MB_CTL_MUX__W 1

1395

#define IQM_FS_COMM_MB_CTL_MUX__M 0x4

1396

#define IQM_FS_COMM_MB_CTL_MUX__PRE 0x0

1397

#define IQM_FS_COMM_MB_OBS_MUX__B 3

1398

#define IQM_FS_COMM_MB_OBS_MUX__W 1

1399

#define IQM_FS_COMM_MB_OBS_MUX__M 0x8

1400

#define IQM_FS_COMM_MB_OBS_MUX__PRE 0x0

1401

1402

#define IQM_FS_RATE_OFS_LO__A 0x1820010

1403

#define IQM_FS_RATE_OFS_LO__W 16

1404

#define IQM_FS_RATE_OFS_LO__M 0xFFFF

1405

#define IQM_FS_RATE_OFS_LO__PRE 0x0

1406

#define IQM_FS_RATE_OFS_LO_B__B 0

1407

#define IQM_FS_RATE_OFS_LO_B__W 16

1408

#define IQM_FS_RATE_OFS_LO_B__M 0xFFFF

1409

#define IQM_FS_RATE_OFS_LO_B__PRE 0x0

1410

1411

#define IQM_FS_RATE_OFS_HI__A 0x1820011

1412

#define IQM_FS_RATE_OFS_HI__W 12

1413

#define IQM_FS_RATE_OFS_HI__M 0xFFF

1414

#define IQM_FS_RATE_OFS_HI__PRE 0x0

1415

#define IQM_FS_RATE_OFS_HI_B__B 0

1416

#define IQM_FS_RATE_OFS_HI_B__W 12

1417

#define IQM_FS_RATE_OFS_HI_B__M 0xFFF

1418

#define IQM_FS_RATE_OFS_HI_B__PRE 0x0

1419

1420

#define IQM_FS_RATE_LO__A 0x1820012

1421

#define IQM_FS_RATE_LO__W 16

1422

#define IQM_FS_RATE_LO__M 0xFFFF

1423

#define IQM_FS_RATE_LO__PRE 0x0

1424

#define IQM_FS_RATE_LO_B__B 0

1425

#define IQM_FS_RATE_LO_B__W 16

1426

#define IQM_FS_RATE_LO_B__M 0xFFFF

1427

#define IQM_FS_RATE_LO_B__PRE 0x0

1428

1429

#define IQM_FS_RATE_HI__A 0x1820013

1430

#define IQM_FS_RATE_HI__W 12

1431

#define IQM_FS_RATE_HI__M 0xFFF

1432

#define IQM_FS_RATE_HI__PRE 0x0

1433

#define IQM_FS_RATE_HI_B__B 0

1434

#define IQM_FS_RATE_HI_B__W 12

1435

#define IQM_FS_RATE_HI_B__M 0xFFF

1436

#define IQM_FS_RATE_HI_B__PRE 0x0

1437

1438

#define IQM_FS_ADJ_SEL__A 0x1820014

1439

#define IQM_FS_ADJ_SEL__W 2

1440

#define IQM_FS_ADJ_SEL__M 0x3

1441

#define IQM_FS_ADJ_SEL__PRE 0x0

1442

1443

#define IQM_FS_ADJ_SEL_B__B 0

1444

#define IQM_FS_ADJ_SEL_B__W 2

1445

#define IQM_FS_ADJ_SEL_B__M 0x3

1446

#define IQM_FS_ADJ_SEL_B__PRE 0x0

1447

#define IQM_FS_ADJ_SEL_B_OFF 0x0

1448

#define IQM_FS_ADJ_SEL_B_QAM 0x1

1449

#define IQM_FS_ADJ_SEL_B_VSB 0x2

#define IQM_FD_COMM_EXEC__A 0x1830000

1454

#define IQM_FD_COMM_EXEC__W 2

1455

#define IQM_FD_COMM_EXEC__M 0x3

1456

#define IQM_FD_COMM_EXEC__PRE 0x0

1457

#define IQM_FD_COMM_EXEC_STOP 0x0

1458

#define IQM_FD_COMM_EXEC_ACTIVE 0x1

1459

#define IQM_FD_COMM_EXEC_HOLD 0x2

1460

1461

#define IQM_FD_COMM_MB__A 0x1830002

1462

#define IQM_FD_COMM_MB__W 2

1463

#define IQM_FD_COMM_MB__M 0x3

1464

#define IQM_FD_COMM_MB__PRE 0x0

1465

#define IQM_FD_COMM_MB_CTL__B 0

1466

#define IQM_FD_COMM_MB_CTL__W 1

1467

#define IQM_FD_COMM_MB_CTL__M 0x1

1468

#define IQM_FD_COMM_MB_CTL__PRE 0x0

1469

#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x0

1470

#define IQM_FD_COMM_MB_CTL_CTL_ON 0x1

1471

#define IQM_FD_COMM_MB_OBS__B 1

1472

#define IQM_FD_COMM_MB_OBS__W 1

1473

#define IQM_FD_COMM_MB_OBS__M 0x2

1474

#define IQM_FD_COMM_MB_OBS__PRE 0x0

1475

#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x0

1476

#define IQM_FD_COMM_MB_OBS_OBS_ON 0x2

1477

1478

#define IQM_FD_RATESEL__A 0x1830010

1479

#define IQM_FD_RATESEL__W 2

1480

#define IQM_FD_RATESEL__M 0x3

1481

#define IQM_FD_RATESEL__PRE 0x0

1482

#define IQM_FD_RATESEL_B__B 0

1483

#define IQM_FD_RATESEL_B__W 2

1484

#define IQM_FD_RATESEL_B__M 0x3

1485

#define IQM_FD_RATESEL_B__PRE 0x0

1486

#define IQM_FD_RATESEL_B_DS0 0x0

1487

#define IQM_FD_RATESEL_B_DS1 0x1

1488

#define IQM_FD_RATESEL_B_DS2 0x2

1489

#define IQM_FD_RATESEL_B_DS3 0x3

#define IQM_RC_COMM_EXEC__A 0x1840000

1494

#define IQM_RC_COMM_EXEC__W 2

1495

#define IQM_RC_COMM_EXEC__M 0x3

1496

#define IQM_RC_COMM_EXEC__PRE 0x0

1497

#define IQM_RC_COMM_EXEC_STOP 0x0

1498

#define IQM_RC_COMM_EXEC_ACTIVE 0x1

1499

#define IQM_RC_COMM_EXEC_HOLD 0x2

1500

1501

#define IQM_RC_COMM_MB__A 0x1840002

1502

#define IQM_RC_COMM_MB__W 2

1503

#define IQM_RC_COMM_MB__M 0x3

1504

#define IQM_RC_COMM_MB__PRE 0x0

1505

#define IQM_RC_COMM_MB_CTL__B 0

1506

#define IQM_RC_COMM_MB_CTL__W 1

1507

#define IQM_RC_COMM_MB_CTL__M 0x1

1508

#define IQM_RC_COMM_MB_CTL__PRE 0x0

1509

#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x0

1510

#define IQM_RC_COMM_MB_CTL_CTL_ON 0x1

1511

#define IQM_RC_COMM_MB_OBS__B 1

1512

#define IQM_RC_COMM_MB_OBS__W 1

1513

#define IQM_RC_COMM_MB_OBS__M 0x2

1514

#define IQM_RC_COMM_MB_OBS__PRE 0x0

1515

#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x0

1516

#define IQM_RC_COMM_MB_OBS_OBS_ON 0x2

1517

1518

#define IQM_RC_RATE_OFS_LO__A 0x1840010

1519

#define IQM_RC_RATE_OFS_LO__W 16

1520

#define IQM_RC_RATE_OFS_LO__M 0xFFFF

1521

#define IQM_RC_RATE_OFS_LO__PRE 0x0

1522

#define IQM_RC_RATE_OFS_LO_B__B 0

1523

#define IQM_RC_RATE_OFS_LO_B__W 16

1524

#define IQM_RC_RATE_OFS_LO_B__M 0xFFFF

1525

#define IQM_RC_RATE_OFS_LO_B__PRE 0x0

1526

1527

#define IQM_RC_RATE_OFS_HI__A 0x1840011

1528

#define IQM_RC_RATE_OFS_HI__W 8

1529

#define IQM_RC_RATE_OFS_HI__M 0xFF

1530

#define IQM_RC_RATE_OFS_HI__PRE 0x0

1531

#define IQM_RC_RATE_OFS_HI_B__B 0

1532

#define IQM_RC_RATE_OFS_HI_B__W 8

1533

#define IQM_RC_RATE_OFS_HI_B__M 0xFF

1534

#define IQM_RC_RATE_OFS_HI_B__PRE 0x0

1535

1536

#define IQM_RC_RATE_LO__A 0x1840012

1537

#define IQM_RC_RATE_LO__W 16

1538

#define IQM_RC_RATE_LO__M 0xFFFF

1539

#define IQM_RC_RATE_LO__PRE 0x0

1540

#define IQM_RC_RATE_LO_B__B 0

1541

#define IQM_RC_RATE_LO_B__W 16

1542

#define IQM_RC_RATE_LO_B__M 0xFFFF

1543

#define IQM_RC_RATE_LO_B__PRE 0x0

1544

1545

#define IQM_RC_RATE_HI__A 0x1840013

1546

#define IQM_RC_RATE_HI__W 8

1547

#define IQM_RC_RATE_HI__M 0xFF

1548

#define IQM_RC_RATE_HI__PRE 0x0

1549

#define IQM_RC_RATE_HI_B__B 0

1550

#define IQM_RC_RATE_HI_B__W 8

1551

#define IQM_RC_RATE_HI_B__M 0xFF

1552

#define IQM_RC_RATE_HI_B__PRE 0x0

1553

1554

#define IQM_RC_ADJ_SEL__A 0x1840014

1555

#define IQM_RC_ADJ_SEL__W 2

1556

#define IQM_RC_ADJ_SEL__M 0x3

1557

#define IQM_RC_ADJ_SEL__PRE 0x0

1558

1559

#define IQM_RC_ADJ_SEL_B__B 0

1560

#define IQM_RC_ADJ_SEL_B__W 2

1561

#define IQM_RC_ADJ_SEL_B__M 0x3

1562

#define IQM_RC_ADJ_SEL_B__PRE 0x0

1563

#define IQM_RC_ADJ_SEL_B_OFF 0x0

1564

#define IQM_RC_ADJ_SEL_B_QAM 0x1

1565

#define IQM_RC_ADJ_SEL_B_VSB 0x2

1566

1567

#define IQM_RC_CROUT_ENA__A 0x1840015

1568

#define IQM_RC_CROUT_ENA__W 1

1569

#define IQM_RC_CROUT_ENA__M 0x1

1570

#define IQM_RC_CROUT_ENA__PRE 0x0

1571

1572

#define IQM_RC_CROUT_ENA_ENA__B 0

1573

#define IQM_RC_CROUT_ENA_ENA__W 1

1574

#define IQM_RC_CROUT_ENA_ENA__M 0x1

1575

#define IQM_RC_CROUT_ENA_ENA__PRE 0x0

1576

1577

#define IQM_RC_STRETCH__A 0x1840016

1578

#define IQM_RC_STRETCH__W 5

1579

#define IQM_RC_STRETCH__M 0x1F

1580

#define IQM_RC_STRETCH__PRE 0x0

1581

1582

#define IQM_RC_STRETCH_B__B 0

1583

#define IQM_RC_STRETCH_B__W 5

1584

#define IQM_RC_STRETCH_B__M 0x1F

1585

#define IQM_RC_STRETCH_B__PRE 0x0

#define IQM_RT_COMM_EXEC__A 0x1850000

1590

#define IQM_RT_COMM_EXEC__W 2

1591

#define IQM_RT_COMM_EXEC__M 0x3

1592

#define IQM_RT_COMM_EXEC__PRE 0x0

1593

#define IQM_RT_COMM_EXEC_STOP 0x0

1594

#define IQM_RT_COMM_EXEC_ACTIVE 0x1

1595

#define IQM_RT_COMM_EXEC_HOLD 0x2

1596

1597

#define IQM_RT_COMM_MB__A 0x1850002

1598

#define IQM_RT_COMM_MB__W 2

1599

#define IQM_RT_COMM_MB__M 0x3

1600

#define IQM_RT_COMM_MB__PRE 0x0

1601

#define IQM_RT_COMM_MB_CTL__B 0

1602

#define IQM_RT_COMM_MB_CTL__W 1

1603

#define IQM_RT_COMM_MB_CTL__M 0x1

1604

#define IQM_RT_COMM_MB_CTL__PRE 0x0

1605

#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x0

1606

#define IQM_RT_COMM_MB_CTL_CTL_ON 0x1

1607

#define IQM_RT_COMM_MB_OBS__B 1

1608

#define IQM_RT_COMM_MB_OBS__W 1

1609

#define IQM_RT_COMM_MB_OBS__M 0x2

1610

#define IQM_RT_COMM_MB_OBS__PRE 0x0

1611

#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x0

1612

#define IQM_RT_COMM_MB_OBS_OBS_ON 0x2

1613

1614

#define IQM_RT_ACTIVE__A 0x1850010

1615

#define IQM_RT_ACTIVE__W 2

1616

#define IQM_RT_ACTIVE__M 0x3

1617

#define IQM_RT_ACTIVE__PRE 0x0

1618

1619

#define IQM_RT_ACTIVE_ACTIVE_RT__B 0

1620

#define IQM_RT_ACTIVE_ACTIVE_RT__W 1

1621

#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x1

1622

#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x0

1623

#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x0

1624

#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x1

1625

1626

#define IQM_RT_ACTIVE_ACTIVE_CR__B 1

1627

#define IQM_RT_ACTIVE_ACTIVE_CR__W 1

1628

#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x2

1629

#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x0

1630

#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x0

1631

#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x2

1632

1633

1634

#define IQM_RT_LO_INCR__A 0x1850011

1635

#define IQM_RT_LO_INCR__W 12

1636

#define IQM_RT_LO_INCR__M 0xFFF

1637

#define IQM_RT_LO_INCR__PRE 0x588

1638

#define IQM_RT_LO_INCR_FM 0x0

1639

#define IQM_RT_LO_INCR_MN 0x588

1640

1641

#define IQM_RT_ROT_BP__A 0x1850012

1642

#define IQM_RT_ROT_BP__W 3

1643

#define IQM_RT_ROT_BP__M 0x7

1644

#define IQM_RT_ROT_BP__PRE 0x0

1645

1646

#define IQM_RT_ROT_BP_ROT_OFF__B 0

1647

#define IQM_RT_ROT_BP_ROT_OFF__W 1

1648

#define IQM_RT_ROT_BP_ROT_OFF__M 0x1

1649

#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x0

1650

#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x0

1651

#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x1

1652

1653

#define IQM_RT_ROT_BP_ROT_BPF__B 1

1654

#define IQM_RT_ROT_BP_ROT_BPF__W 1

1655

#define IQM_RT_ROT_BP_ROT_BPF__M 0x2

1656

#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x0

1657

1658

#define IQM_RT_ROT_BP_MIX_BP__B 2

1659

#define IQM_RT_ROT_BP_MIX_BP__W 1

1660

#define IQM_RT_ROT_BP_MIX_BP__M 0x4

1661

#define IQM_RT_ROT_BP_MIX_BP__PRE 0x0

1662

1663

1664

#define IQM_RT_LP_BP__A 0x1850013

1665

#define IQM_RT_LP_BP__W 1

1666

#define IQM_RT_LP_BP__M 0x1

1667

#define IQM_RT_LP_BP__PRE 0x0

1668

1669

#define IQM_RT_DELAY__A 0x1850014

1670

#define IQM_RT_DELAY__W 7

1671

#define IQM_RT_DELAY__M 0x7F

1672

#define IQM_RT_DELAY__PRE 0x45

#define IQM_CF_COMM_EXEC__A 0x1860000

1677

#define IQM_CF_COMM_EXEC__W 2

1678

#define IQM_CF_COMM_EXEC__M 0x3

1679

#define IQM_CF_COMM_EXEC__PRE 0x0

1680

#define IQM_CF_COMM_EXEC_STOP 0x0

1681

#define IQM_CF_COMM_EXEC_ACTIVE 0x1

1682

#define IQM_CF_COMM_EXEC_HOLD 0x2

1683

1684

#define IQM_CF_COMM_MB__A 0x1860002

1685

#define IQM_CF_COMM_MB__W 2

1686

#define IQM_CF_COMM_MB__M 0x3

1687

#define IQM_CF_COMM_MB__PRE 0x0

1688

#define IQM_CF_COMM_MB_CTL__B 0

1689

#define IQM_CF_COMM_MB_CTL__W 1

1690

#define IQM_CF_COMM_MB_CTL__M 0x1

1691

#define IQM_CF_COMM_MB_CTL__PRE 0x0

1692

#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x0

1693

#define IQM_CF_COMM_MB_CTL_CTL_ON 0x1

1694

#define IQM_CF_COMM_MB_OBS__B 1

1695

#define IQM_CF_COMM_MB_OBS__W 1

1696

#define IQM_CF_COMM_MB_OBS__M 0x2

1697

#define IQM_CF_COMM_MB_OBS__PRE 0x0

1698

#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x0

1699

#define IQM_CF_COMM_MB_OBS_OBS_ON 0x2

1700

1701

#define IQM_CF_COMM_INT_REQ__A 0x1860003

1702

#define IQM_CF_COMM_INT_REQ__W 1

1703

#define IQM_CF_COMM_INT_REQ__M 0x1

1704

#define IQM_CF_COMM_INT_REQ__PRE 0x0

1705

#define IQM_CF_COMM_INT_STA__A 0x1860005

1706

#define IQM_CF_COMM_INT_STA__W 2

1707

#define IQM_CF_COMM_INT_STA__M 0x3

1708

#define IQM_CF_COMM_INT_STA__PRE 0x0

1709

#define IQM_CF_COMM_INT_STA_PM__B 0

1710

#define IQM_CF_COMM_INT_STA_PM__W 1

1711

#define IQM_CF_COMM_INT_STA_PM__M 0x1

1712

#define IQM_CF_COMM_INT_STA_PM__PRE 0x0

1713

#define IQM_CF_COMM_INT_STA_INC__B 1

1714

#define IQM_CF_COMM_INT_STA_INC__W 1

1715

#define IQM_CF_COMM_INT_STA_INC__M 0x2

1716

#define IQM_CF_COMM_INT_STA_INC__PRE 0x0

1717

1718

#define IQM_CF_COMM_INT_MSK__A 0x1860006

1719

#define IQM_CF_COMM_INT_MSK__W 2

1720

#define IQM_CF_COMM_INT_MSK__M 0x3

1721

#define IQM_CF_COMM_INT_MSK__PRE 0x0

1722

#define IQM_CF_COMM_INT_MSK_PM__B 0

1723

#define IQM_CF_COMM_INT_MSK_PM__W 1

1724

#define IQM_CF_COMM_INT_MSK_PM__M 0x1

1725

#define IQM_CF_COMM_INT_MSK_PM__PRE 0x0

1726

#define IQM_CF_COMM_INT_MSK_INC__B 1

1727

#define IQM_CF_COMM_INT_MSK_INC__W 1

1728

#define IQM_CF_COMM_INT_MSK_INC__M 0x2

1729

#define IQM_CF_COMM_INT_MSK_INC__PRE 0x0

1730

1731

#define IQM_CF_COMM_INT_STM__A 0x1860007

1732

#define IQM_CF_COMM_INT_STM__W 2

1733

#define IQM_CF_COMM_INT_STM__M 0x3

1734

#define IQM_CF_COMM_INT_STM__PRE 0x0

1735

#define IQM_CF_COMM_INT_STM_PM__B 0

1736

#define IQM_CF_COMM_INT_STM_PM__W 1

1737

#define IQM_CF_COMM_INT_STM_PM__M 0x1

1738

#define IQM_CF_COMM_INT_STM_PM__PRE 0x0

1739

#define IQM_CF_COMM_INT_STM_INC__B 1

1740

#define IQM_CF_COMM_INT_STM_INC__W 1

1741

#define IQM_CF_COMM_INT_STM_INC__M 0x2

1742

#define IQM_CF_COMM_INT_STM_INC__PRE 0x0

1743

1744

#define IQM_CF_SYMMETRIC__A 0x1860010

1745

#define IQM_CF_SYMMETRIC__W 2

1746

#define IQM_CF_SYMMETRIC__M 0x3

1747

#define IQM_CF_SYMMETRIC__PRE 0x0

1748

1749

#define IQM_CF_SYMMETRIC_RE__B 0

1750

#define IQM_CF_SYMMETRIC_RE__W 1

1751

#define IQM_CF_SYMMETRIC_RE__M 0x1

1752

#define IQM_CF_SYMMETRIC_RE__PRE 0x0

1753

1754

#define IQM_CF_SYMMETRIC_IM__B 1

1755

#define IQM_CF_SYMMETRIC_IM__W 1

1756

#define IQM_CF_SYMMETRIC_IM__M 0x2

1757

#define IQM_CF_SYMMETRIC_IM__PRE 0x0

1758

1759

#define IQM_CF_MIDTAP__A 0x1860011

1760

#define IQM_CF_MIDTAP__W 3

1761

#define IQM_CF_MIDTAP__M 0x7

1762

#define IQM_CF_MIDTAP__PRE 0x3

1763

1764

#define IQM_CF_MIDTAP_RE__B 0

1765

#define IQM_CF_MIDTAP_RE__W 1

1766

#define IQM_CF_MIDTAP_RE__M 0x1

1767

#define IQM_CF_MIDTAP_RE__PRE 0x1

1768

1769

#define IQM_CF_MIDTAP_IM__B 1

1770

#define IQM_CF_MIDTAP_IM__W 1

1771

#define IQM_CF_MIDTAP_IM__M 0x2

1772

#define IQM_CF_MIDTAP_IM__PRE 0x2

1773

1774

#define IQM_CF_MIDTAP_SCALE__B 2

1775

#define IQM_CF_MIDTAP_SCALE__W 1

1776

#define IQM_CF_MIDTAP_SCALE__M 0x4

1777

#define IQM_CF_MIDTAP_SCALE__PRE 0x0

1778

1779

#define IQM_CF_OUT_ENA__A 0x1860012

1780

#define IQM_CF_OUT_ENA__W 3

1781

#define IQM_CF_OUT_ENA__M 0x7

1782

#define IQM_CF_OUT_ENA__PRE 0x0

1783

1784

#define IQM_CF_OUT_ENA_ATV__B 0

1785

#define IQM_CF_OUT_ENA_ATV__W 1

1786

#define IQM_CF_OUT_ENA_ATV__M 0x1

1787

#define IQM_CF_OUT_ENA_ATV__PRE 0x0

1788

1789

#define IQM_CF_OUT_ENA_QAM__B 1

1790

#define IQM_CF_OUT_ENA_QAM__W 1

1791

#define IQM_CF_OUT_ENA_QAM__M 0x2

1792

#define IQM_CF_OUT_ENA_QAM__PRE 0x0

1793

1794

#define IQM_CF_OUT_ENA_OFDM__B 2

1795

#define IQM_CF_OUT_ENA_OFDM__W 1

1796

#define IQM_CF_OUT_ENA_OFDM__M 0x4

1797

#define IQM_CF_OUT_ENA_OFDM__PRE 0x0

1798

1799

#define IQM_CF_ADJ_SEL__A 0x1860013

1800

#define IQM_CF_ADJ_SEL__W 2

1801

#define IQM_CF_ADJ_SEL__M 0x3

1802

#define IQM_CF_ADJ_SEL__PRE 0x0

1803

1804

#define IQM_CF_ADJ_SEL_B__B 0

1805

#define IQM_CF_ADJ_SEL_B__W 2

1806

#define IQM_CF_ADJ_SEL_B__M 0x3

1807

#define IQM_CF_ADJ_SEL_B__PRE 0x0

1808

1809

#define IQM_CF_SCALE__A 0x1860014

1810

#define IQM_CF_SCALE__W 14

1811

#define IQM_CF_SCALE__M 0x3FFF

1812

#define IQM_CF_SCALE__PRE 0x400

1813

#define IQM_CF_SCALE_B__B 0

1814

#define IQM_CF_SCALE_B__W 14

1815

#define IQM_CF_SCALE_B__M 0x3FFF

1816

#define IQM_CF_SCALE_B__PRE 0x400

1817

1818

#define IQM_CF_SCALE_SH__A 0x1860015

1819

#define IQM_CF_SCALE_SH__W 2

1820

#define IQM_CF_SCALE_SH__M 0x3

1821

#define IQM_CF_SCALE_SH__PRE 0x0

1822

1823

#define IQM_CF_SCALE_SH_B__B 0

1824

#define IQM_CF_SCALE_SH_B__W 2

1825

#define IQM_CF_SCALE_SH_B__M 0x3

1826

#define IQM_CF_SCALE_SH_B__PRE 0x0

1827

1828

#define IQM_CF_AMP__A 0x1860016

1829

#define IQM_CF_AMP__W 14

1830

#define IQM_CF_AMP__M 0x3FFF

1831

#define IQM_CF_AMP__PRE 0x0

1832

1833

#define IQM_CF_AMP_B__B 0

1834

#define IQM_CF_AMP_B__W 14

1835

#define IQM_CF_AMP_B__M 0x3FFF

1836

#define IQM_CF_AMP_B__PRE 0x0

1837

1838

#define IQM_CF_POW_MEAS_LEN__A 0x1860017

1839

#define IQM_CF_POW_MEAS_LEN__W 3

1840

#define IQM_CF_POW_MEAS_LEN__M 0x7

1841

#define IQM_CF_POW_MEAS_LEN__PRE 0x2

1842

1843

#define IQM_CF_POW_MEAS_LEN_B__B 0

1844

#define IQM_CF_POW_MEAS_LEN_B__W 3

1845

#define IQM_CF_POW_MEAS_LEN_B__M 0x7

1846

#define IQM_CF_POW_MEAS_LEN_B__PRE 0x2

1847

1848

#define IQM_CF_POW__A 0x1860018

1849

#define IQM_CF_POW__W 16

1850

#define IQM_CF_POW__M 0xFFFF

1851

#define IQM_CF_POW__PRE 0x2

1852

#define IQM_CF_POW_B__B 0

1853

#define IQM_CF_POW_B__W 16

1854

#define IQM_CF_POW_B__M 0xFFFF

1855

#define IQM_CF_POW_B__PRE 0x2

1856

1857

#define IQM_CF_DS_ENA__A 0x1860019

1858

#define IQM_CF_DS_ENA__W 3

1859

#define IQM_CF_DS_ENA__M 0x7

1860

#define IQM_CF_DS_ENA__PRE 0x4

1861

1862

#define IQM_CF_DS_ENA_ATV__B 0

1863

#define IQM_CF_DS_ENA_ATV__W 1

1864

#define IQM_CF_DS_ENA_ATV__M 0x1

1865

#define IQM_CF_DS_ENA_ATV__PRE 0x0

1866

1867

#define IQM_CF_DS_ENA_QAM__B 1

1868

#define IQM_CF_DS_ENA_QAM__W 1

1869

#define IQM_CF_DS_ENA_QAM__M 0x2

1870

#define IQM_CF_DS_ENA_QAM__PRE 0x0

1871

1872

#define IQM_CF_DS_ENA_VSB__B 2

1873

#define IQM_CF_DS_ENA_VSB__W 1

1874

#define IQM_CF_DS_ENA_VSB__M 0x4

1875

#define IQM_CF_DS_ENA_VSB__PRE 0x4

1876

1877

1878

#define IQM_CF_POW_UPD__A 0x186001A

1879

#define IQM_CF_POW_UPD__W 1

1880

#define IQM_CF_POW_UPD__M 0x1

1881

#define IQM_CF_POW_UPD__PRE 0x0

1882

#define IQM_CF_TAP_RE0__A 0x1860020

1883

#define IQM_CF_TAP_RE0__W 7

1884

#define IQM_CF_TAP_RE0__M 0x7F

1885

#define IQM_CF_TAP_RE0__PRE 0x2

1886

#define IQM_CF_TAP_RE0_B__B 0

1887

#define IQM_CF_TAP_RE0_B__W 7

1888

#define IQM_CF_TAP_RE0_B__M 0x7F

1889

#define IQM_CF_TAP_RE0_B__PRE 0x2

1890

1891

#define IQM_CF_TAP_RE1__A 0x1860021

1892

#define IQM_CF_TAP_RE1__W 7

1893

#define IQM_CF_TAP_RE1__M 0x7F

1894

#define IQM_CF_TAP_RE1__PRE 0x2

1895

#define IQM_CF_TAP_RE1_B__B 0

1896

#define IQM_CF_TAP_RE1_B__W 7

1897

#define IQM_CF_TAP_RE1_B__M 0x7F

1898

#define IQM_CF_TAP_RE1_B__PRE 0x2

1899

1900

#define IQM_CF_TAP_RE2__A 0x1860022

1901

#define IQM_CF_TAP_RE2__W 7

1902

#define IQM_CF_TAP_RE2__M 0x7F

1903

#define IQM_CF_TAP_RE2__PRE 0x2

1904

#define IQM_CF_TAP_RE2_B__B 0

1905

#define IQM_CF_TAP_RE2_B__W 7

1906

#define IQM_CF_TAP_RE2_B__M 0x7F

1907

#define IQM_CF_TAP_RE2_B__PRE 0x2

1908

1909

#define IQM_CF_TAP_RE3__A 0x1860023

1910

#define IQM_CF_TAP_RE3__W 7

1911

#define IQM_CF_TAP_RE3__M 0x7F

1912

#define IQM_CF_TAP_RE3__PRE 0x2

1913

#define IQM_CF_TAP_RE3_B__B 0

1914

#define IQM_CF_TAP_RE3_B__W 7

1915

#define IQM_CF_TAP_RE3_B__M 0x7F

1916

#define IQM_CF_TAP_RE3_B__PRE 0x2

1917

1918

#define IQM_CF_TAP_RE4__A 0x1860024

1919

#define IQM_CF_TAP_RE4__W 7

1920

#define IQM_CF_TAP_RE4__M 0x7F

1921

#define IQM_CF_TAP_RE4__PRE 0x2

1922

#define IQM_CF_TAP_RE4_B__B 0

1923

#define IQM_CF_TAP_RE4_B__W 7

1924

#define IQM_CF_TAP_RE4_B__M 0x7F

1925

#define IQM_CF_TAP_RE4_B__PRE 0x2

1926

1927

#define IQM_CF_TAP_RE5__A 0x1860025

1928

#define IQM_CF_TAP_RE5__W 7

1929

#define IQM_CF_TAP_RE5__M 0x7F

1930

#define IQM_CF_TAP_RE5__PRE 0x2

1931

#define IQM_CF_TAP_RE5_B__B 0

1932

#define IQM_CF_TAP_RE5_B__W 7

1933

#define IQM_CF_TAP_RE5_B__M 0x7F

1934

#define IQM_CF_TAP_RE5_B__PRE 0x2

1935

1936

#define IQM_CF_TAP_RE6__A 0x1860026

1937

#define IQM_CF_TAP_RE6__W 7

1938

#define IQM_CF_TAP_RE6__M 0x7F

1939

#define IQM_CF_TAP_RE6__PRE 0x2

1940

#define IQM_CF_TAP_RE6_B__B 0

1941

#define IQM_CF_TAP_RE6_B__W 7

1942

#define IQM_CF_TAP_RE6_B__M 0x7F

1943

#define IQM_CF_TAP_RE6_B__PRE 0x2

1944

1945

#define IQM_CF_TAP_RE7__A 0x1860027

1946

#define IQM_CF_TAP_RE7__W 9

1947

#define IQM_CF_TAP_RE7__M 0x1FF

1948

#define IQM_CF_TAP_RE7__PRE 0x2

1949

#define IQM_CF_TAP_RE7_B__B 0

1950

#define IQM_CF_TAP_RE7_B__W 9

1951

#define IQM_CF_TAP_RE7_B__M 0x1FF

1952

#define IQM_CF_TAP_RE7_B__PRE 0x2

1953

1954

#define IQM_CF_TAP_RE8__A 0x1860028

1955

#define IQM_CF_TAP_RE8__W 9

1956

#define IQM_CF_TAP_RE8__M 0x1FF

1957

#define IQM_CF_TAP_RE8__PRE 0x2

1958

#define IQM_CF_TAP_RE8_B__B 0

1959

#define IQM_CF_TAP_RE8_B__W 9

1960

#define IQM_CF_TAP_RE8_B__M 0x1FF

1961

#define IQM_CF_TAP_RE8_B__PRE 0x2

1962

1963

#define IQM_CF_TAP_RE9__A 0x1860029

1964

#define IQM_CF_TAP_RE9__W 9

1965

#define IQM_CF_TAP_RE9__M 0x1FF

1966

#define IQM_CF_TAP_RE9__PRE 0x2

1967

#define IQM_CF_TAP_RE9_B__B 0

1968

#define IQM_CF_TAP_RE9_B__W 9

1969

#define IQM_CF_TAP_RE9_B__M 0x1FF

1970

#define IQM_CF_TAP_RE9_B__PRE 0x2

1971

1972

#define IQM_CF_TAP_RE10__A 0x186002A

1973

#define IQM_CF_TAP_RE10__W 9

1974

#define IQM_CF_TAP_RE10__M 0x1FF

1975

#define IQM_CF_TAP_RE10__PRE 0x2

1976

#define IQM_CF_TAP_RE10_B__B 0

1977

#define IQM_CF_TAP_RE10_B__W 9

1978

#define IQM_CF_TAP_RE10_B__M 0x1FF

1979

#define IQM_CF_TAP_RE10_B__PRE 0x2

1980

1981

#define IQM_CF_TAP_RE11__A 0x186002B

1982

#define IQM_CF_TAP_RE11__W 9

1983

#define IQM_CF_TAP_RE11__M 0x1FF

1984

#define IQM_CF_TAP_RE11__PRE 0x2

1985

#define IQM_CF_TAP_RE11_B__B 0

1986

#define IQM_CF_TAP_RE11_B__W 9

1987

#define IQM_CF_TAP_RE11_B__M 0x1FF

1988

#define IQM_CF_TAP_RE11_B__PRE 0x2

1989

1990

#define IQM_CF_TAP_RE12__A 0x186002C

1991

#define IQM_CF_TAP_RE12__W 9

1992

#define IQM_CF_TAP_RE12__M 0x1FF

1993

#define IQM_CF_TAP_RE12__PRE 0x2

1994

#define IQM_CF_TAP_RE12_B__B 0

1995

#define IQM_CF_TAP_RE12_B__W 9

1996

#define IQM_CF_TAP_RE12_B__M 0x1FF

1997

#define IQM_CF_TAP_RE12_B__PRE 0x2

1998

1999

#define IQM_CF_TAP_RE13__A 0x186002D

2000

#define IQM_CF_TAP_RE13__W 9

2001

#define IQM_CF_TAP_RE13__M 0x1FF

2002

#define IQM_CF_TAP_RE13__PRE 0x2

2003

#define IQM_CF_TAP_RE13_B__B 0

2004

#define IQM_CF_TAP_RE13_B__W 9

2005

#define IQM_CF_TAP_RE13_B__M 0x1FF

2006

#define IQM_CF_TAP_RE13_B__PRE 0x2

2007

2008

#define IQM_CF_TAP_RE14__A 0x186002E

2009

#define IQM_CF_TAP_RE14__W 9

2010

#define IQM_CF_TAP_RE14__M 0x1FF

2011

#define IQM_CF_TAP_RE14__PRE 0x2

2012

#define IQM_CF_TAP_RE14_B__B 0

2013

#define IQM_CF_TAP_RE14_B__W 9

2014

#define IQM_CF_TAP_RE14_B__M 0x1FF

2015

#define IQM_CF_TAP_RE14_B__PRE 0x2

2016

2017

#define IQM_CF_TAP_RE15__A 0x186002F

2018

#define IQM_CF_TAP_RE15__W 9

2019

#define IQM_CF_TAP_RE15__M 0x1FF

2020

#define IQM_CF_TAP_RE15__PRE 0x2

2021

#define IQM_CF_TAP_RE15_B__B 0

2022

#define IQM_CF_TAP_RE15_B__W 9

2023

#define IQM_CF_TAP_RE15_B__M 0x1FF

2024

#define IQM_CF_TAP_RE15_B__PRE 0x2

2025

2026

#define IQM_CF_TAP_RE16__A 0x1860030

2027

#define IQM_CF_TAP_RE16__W 9

2028

#define IQM_CF_TAP_RE16__M 0x1FF

2029

#define IQM_CF_TAP_RE16__PRE 0x2

2030

#define IQM_CF_TAP_RE16_B__B 0

2031

#define IQM_CF_TAP_RE16_B__W 9

2032

#define IQM_CF_TAP_RE16_B__M 0x1FF

2033

#define IQM_CF_TAP_RE16_B__PRE 0x2

2034

2035

#define IQM_CF_TAP_RE17__A 0x1860031

2036

#define IQM_CF_TAP_RE17__W 9

2037

#define IQM_CF_TAP_RE17__M 0x1FF

2038

#define IQM_CF_TAP_RE17__PRE 0x2

2039

#define IQM_CF_TAP_RE17_B__B 0

2040

#define IQM_CF_TAP_RE17_B__W 9

2041

#define IQM_CF_TAP_RE17_B__M 0x1FF

2042

#define IQM_CF_TAP_RE17_B__PRE 0x2

2043

2044

#define IQM_CF_TAP_RE18__A 0x1860032

2045

#define IQM_CF_TAP_RE18__W 9

2046

#define IQM_CF_TAP_RE18__M 0x1FF

2047

#define IQM_CF_TAP_RE18__PRE 0x2

2048

#define IQM_CF_TAP_RE18_B__B 0

2049

#define IQM_CF_TAP_RE18_B__W 9

2050

#define IQM_CF_TAP_RE18_B__M 0x1FF

2051

#define IQM_CF_TAP_RE18_B__PRE 0x2

2052

2053

#define IQM_CF_TAP_RE19__A 0x1860033

2054

#define IQM_CF_TAP_RE19__W 9

2055

#define IQM_CF_TAP_RE19__M 0x1FF

2056

#define IQM_CF_TAP_RE19__PRE 0x2

2057

#define IQM_CF_TAP_RE19_B__B 0

2058

#define IQM_CF_TAP_RE19_B__W 9

2059

#define IQM_CF_TAP_RE19_B__M 0x1FF

2060

#define IQM_CF_TAP_RE19_B__PRE 0x2

2061

2062

#define IQM_CF_TAP_RE20__A 0x1860034

2063

#define IQM_CF_TAP_RE20__W 9

2064

#define IQM_CF_TAP_RE20__M 0x1FF

2065

#define IQM_CF_TAP_RE20__PRE 0x2

2066

#define IQM_CF_TAP_RE20_B__B 0

2067

#define IQM_CF_TAP_RE20_B__W 9

2068

#define IQM_CF_TAP_RE20_B__M 0x1FF

2069

#define IQM_CF_TAP_RE20_B__PRE 0x2

2070

2071

#define IQM_CF_TAP_RE21__A 0x1860035

2072

#define IQM_CF_TAP_RE21__W 11

2073

#define IQM_CF_TAP_RE21__M 0x7FF

2074

#define IQM_CF_TAP_RE21__PRE 0x2

2075

#define IQM_CF_TAP_RE21_B__B 0

2076

#define IQM_CF_TAP_RE21_B__W 11

2077

#define IQM_CF_TAP_RE21_B__M 0x7FF

2078

#define IQM_CF_TAP_RE21_B__PRE 0x2

2079

2080

#define IQM_CF_TAP_RE22__A 0x1860036

2081

#define IQM_CF_TAP_RE22__W 11

2082

#define IQM_CF_TAP_RE22__M 0x7FF

2083

#define IQM_CF_TAP_RE22__PRE 0x2

2084

#define IQM_CF_TAP_RE22_B__B 0

2085

#define IQM_CF_TAP_RE22_B__W 11

2086

#define IQM_CF_TAP_RE22_B__M 0x7FF

2087

#define IQM_CF_TAP_RE22_B__PRE 0x2

2088

2089

#define IQM_CF_TAP_RE23__A 0x1860037

2090

#define IQM_CF_TAP_RE23__W 11

2091

#define IQM_CF_TAP_RE23__M 0x7FF

2092

#define IQM_CF_TAP_RE23__PRE 0x2

2093

#define IQM_CF_TAP_RE23_B__B 0

2094

#define IQM_CF_TAP_RE23_B__W 11

2095

#define IQM_CF_TAP_RE23_B__M 0x7FF

2096

#define IQM_CF_TAP_RE23_B__PRE 0x2

2097

2098

#define IQM_CF_TAP_RE24__A 0x1860038

2099

#define IQM_CF_TAP_RE24__W 11

2100

#define IQM_CF_TAP_RE24__M 0x7FF

2101

#define IQM_CF_TAP_RE24__PRE 0x2

2102

#define IQM_CF_TAP_RE24_B__B 0

2103

#define IQM_CF_TAP_RE24_B__W 11

2104

#define IQM_CF_TAP_RE24_B__M 0x7FF

2105

#define IQM_CF_TAP_RE24_B__PRE 0x2

2106

2107

#define IQM_CF_TAP_RE25__A 0x1860039

2108

#define IQM_CF_TAP_RE25__W 11

2109

#define IQM_CF_TAP_RE25__M 0x7FF

2110

#define IQM_CF_TAP_RE25__PRE 0x2

2111

#define IQM_CF_TAP_RE25_B__B 0

2112

#define IQM_CF_TAP_RE25_B__W 11

2113

#define IQM_CF_TAP_RE25_B__M 0x7FF

2114

#define IQM_CF_TAP_RE25_B__PRE 0x2

2115

2116

#define IQM_CF_TAP_RE26__A 0x186003A

2117

#define IQM_CF_TAP_RE26__W 11

2118

#define IQM_CF_TAP_RE26__M 0x7FF

2119

#define IQM_CF_TAP_RE26__PRE 0x2

2120

#define IQM_CF_TAP_RE26_B__B 0

2121

#define IQM_CF_TAP_RE26_B__W 11

2122

#define IQM_CF_TAP_RE26_B__M 0x7FF

2123

#define IQM_CF_TAP_RE26_B__PRE 0x2

2124

2125

#define IQM_CF_TAP_RE27__A 0x186003B

2126

#define IQM_CF_TAP_RE27__W 11

2127

#define IQM_CF_TAP_RE27__M 0x7FF

2128

#define IQM_CF_TAP_RE27__PRE 0x2

2129

#define IQM_CF_TAP_RE27_B__B 0

2130

#define IQM_CF_TAP_RE27_B__W 11

2131

#define IQM_CF_TAP_RE27_B__M 0x7FF

2132

#define IQM_CF_TAP_RE27_B__PRE 0x2

2133

2134

#define IQM_CF_TAP_IM0__A 0x1860040

2135

#define IQM_CF_TAP_IM0__W 7

2136

#define IQM_CF_TAP_IM0__M 0x7F

2137

#define IQM_CF_TAP_IM0__PRE 0x2

2138

#define IQM_CF_TAP_IM0_B__B 0

2139

#define IQM_CF_TAP_IM0_B__W 7

2140

#define IQM_CF_TAP_IM0_B__M 0x7F

2141

#define IQM_CF_TAP_IM0_B__PRE 0x2

2142

2143

#define IQM_CF_TAP_IM1__A 0x1860041

2144

#define IQM_CF_TAP_IM1__W 7

2145

#define IQM_CF_TAP_IM1__M 0x7F

2146

#define IQM_CF_TAP_IM1__PRE 0x2

2147

#define IQM_CF_TAP_IM1_B__B 0

2148

#define IQM_CF_TAP_IM1_B__W 7

2149

#define IQM_CF_TAP_IM1_B__M 0x7F

2150

#define IQM_CF_TAP_IM1_B__PRE 0x2

2151

2152

#define IQM_CF_TAP_IM2__A 0x1860042

2153

#define IQM_CF_TAP_IM2__W 7

2154

#define IQM_CF_TAP_IM2__M 0x7F

2155

#define IQM_CF_TAP_IM2__PRE 0x2

2156

#define IQM_CF_TAP_IM2_B__B 0

2157

#define IQM_CF_TAP_IM2_B__W 7

2158

#define IQM_CF_TAP_IM2_B__M 0x7F

2159

#define IQM_CF_TAP_IM2_B__PRE 0x2

2160

2161

#define IQM_CF_TAP_IM3__A 0x1860043

2162

#define IQM_CF_TAP_IM3__W 7

2163

#define IQM_CF_TAP_IM3__M 0x7F

2164

#define IQM_CF_TAP_IM3__PRE 0x2

2165

#define IQM_CF_TAP_IM3_B__B 0

2166

#define IQM_CF_TAP_IM3_B__W 7

2167

#define IQM_CF_TAP_IM3_B__M 0x7F

2168

#define IQM_CF_TAP_IM3_B__PRE 0x2

2169

2170

#define IQM_CF_TAP_IM4__A 0x1860044

2171

#define IQM_CF_TAP_IM4__W 7

2172

#define IQM_CF_TAP_IM4__M 0x7F

2173

#define IQM_CF_TAP_IM4__PRE 0x2

2174

#define IQM_CF_TAP_IM4_B__B 0

2175

#define IQM_CF_TAP_IM4_B__W 7

2176

#define IQM_CF_TAP_IM4_B__M 0x7F

2177

#define IQM_CF_TAP_IM4_B__PRE 0x2

2178

2179

#define IQM_CF_TAP_IM5__A 0x1860045

2180

#define IQM_CF_TAP_IM5__W 7

2181

#define IQM_CF_TAP_IM5__M 0x7F

2182

#define IQM_CF_TAP_IM5__PRE 0x2

2183

#define IQM_CF_TAP_IM5_B__B 0

2184

#define IQM_CF_TAP_IM5_B__W 7

2185

#define IQM_CF_TAP_IM5_B__M 0x7F

2186

#define IQM_CF_TAP_IM5_B__PRE 0x2

2187

2188

#define IQM_CF_TAP_IM6__A 0x1860046

2189

#define IQM_CF_TAP_IM6__W 7

2190

#define IQM_CF_TAP_IM6__M 0x7F

2191

#define IQM_CF_TAP_IM6__PRE 0x2

2192

#define IQM_CF_TAP_IM6_B__B 0

2193

#define IQM_CF_TAP_IM6_B__W 7

2194

#define IQM_CF_TAP_IM6_B__M 0x7F

2195

#define IQM_CF_TAP_IM6_B__PRE 0x2

2196

2197

#define IQM_CF_TAP_IM7__A 0x1860047

2198

#define IQM_CF_TAP_IM7__W 9

2199

#define IQM_CF_TAP_IM7__M 0x1FF

2200

#define IQM_CF_TAP_IM7__PRE 0x2

2201

#define IQM_CF_TAP_IM7_B__B 0

2202

#define IQM_CF_TAP_IM7_B__W 9

2203

#define IQM_CF_TAP_IM7_B__M 0x1FF

2204

#define IQM_CF_TAP_IM7_B__PRE 0x2

2205

2206

#define IQM_CF_TAP_IM8__A 0x1860048

2207

#define IQM_CF_TAP_IM8__W 9

2208

#define IQM_CF_TAP_IM8__M 0x1FF

2209

#define IQM_CF_TAP_IM8__PRE 0x2

2210

#define IQM_CF_TAP_IM8_B__B 0

2211

#define IQM_CF_TAP_IM8_B__W 9

2212

#define IQM_CF_TAP_IM8_B__M 0x1FF

2213

#define IQM_CF_TAP_IM8_B__PRE 0x2

2214

2215

#define IQM_CF_TAP_IM9__A 0x1860049

2216

#define IQM_CF_TAP_IM9__W 9

2217

#define IQM_CF_TAP_IM9__M 0x1FF

2218

#define IQM_CF_TAP_IM9__PRE 0x2

2219

#define IQM_CF_TAP_IM9_B__B 0

2220

#define IQM_CF_TAP_IM9_B__W 9

2221

#define IQM_CF_TAP_IM9_B__M 0x1FF

2222

#define IQM_CF_TAP_IM9_B__PRE 0x2

2223

2224

#define IQM_CF_TAP_IM10__A 0x186004A

2225

#define IQM_CF_TAP_IM10__W 9

2226

#define IQM_CF_TAP_IM10__M 0x1FF

2227

#define IQM_CF_TAP_IM10__PRE 0x2

2228

#define IQM_CF_TAP_IM10_B__B 0

2229

#define IQM_CF_TAP_IM10_B__W 9

2230

#define IQM_CF_TAP_IM10_B__M 0x1FF

2231

#define IQM_CF_TAP_IM10_B__PRE 0x2

2232

2233

#define IQM_CF_TAP_IM11__A 0x186004B

2234

#define IQM_CF_TAP_IM11__W 9

2235

#define IQM_CF_TAP_IM11__M 0x1FF

2236

#define IQM_CF_TAP_IM11__PRE 0x2

2237

#define IQM_CF_TAP_IM11_B__B 0

2238

#define IQM_CF_TAP_IM11_B__W 9

2239

#define IQM_CF_TAP_IM11_B__M 0x1FF

2240

#define IQM_CF_TAP_IM11_B__PRE 0x2

2241

2242

#define IQM_CF_TAP_IM12__A 0x186004C

2243

#define IQM_CF_TAP_IM12__W 9

2244

#define IQM_CF_TAP_IM12__M 0x1FF

2245

#define IQM_CF_TAP_IM12__PRE 0x2

2246

#define IQM_CF_TAP_IM12_B__B 0

2247

#define IQM_CF_TAP_IM12_B__W 9

2248

#define IQM_CF_TAP_IM12_B__M 0x1FF

2249

#define IQM_CF_TAP_IM12_B__PRE 0x2

2250

2251

#define IQM_CF_TAP_IM13__A 0x186004D

2252

#define IQM_CF_TAP_IM13__W 9

2253

#define IQM_CF_TAP_IM13__M 0x1FF

2254

#define IQM_CF_TAP_IM13__PRE 0x2

2255

#define IQM_CF_TAP_IM13_B__B 0

2256

#define IQM_CF_TAP_IM13_B__W 9

2257

#define IQM_CF_TAP_IM13_B__M 0x1FF

2258

#define IQM_CF_TAP_IM13_B__PRE 0x2

2259

2260

#define IQM_CF_TAP_IM14__A 0x186004E

2261

#define IQM_CF_TAP_IM14__W 9

2262

#define IQM_CF_TAP_IM14__M 0x1FF

2263

#define IQM_CF_TAP_IM14__PRE 0x2

2264

#define IQM_CF_TAP_IM14_B__B 0

2265

#define IQM_CF_TAP_IM14_B__W 9

2266

#define IQM_CF_TAP_IM14_B__M 0x1FF

2267

#define IQM_CF_TAP_IM14_B__PRE 0x2

2268

2269

#define IQM_CF_TAP_IM15__A 0x186004F

2270

#define IQM_CF_TAP_IM15__W 9

2271

#define IQM_CF_TAP_IM15__M 0x1FF

2272

#define IQM_CF_TAP_IM15__PRE 0x2

2273

#define IQM_CF_TAP_IM15_B__B 0

2274

#define IQM_CF_TAP_IM15_B__W 9

2275

#define IQM_CF_TAP_IM15_B__M 0x1FF

2276

#define IQM_CF_TAP_IM15_B__PRE 0x2

2277

2278

#define IQM_CF_TAP_IM16__A 0x1860050

2279

#define IQM_CF_TAP_IM16__W 9

2280

#define IQM_CF_TAP_IM16__M 0x1FF

2281

#define IQM_CF_TAP_IM16__PRE 0x2

2282

#define IQM_CF_TAP_IM16_B__B 0

2283

#define IQM_CF_TAP_IM16_B__W 9

2284

#define IQM_CF_TAP_IM16_B__M 0x1FF

2285

#define IQM_CF_TAP_IM16_B__PRE 0x2

2286

2287

#define IQM_CF_TAP_IM17__A 0x1860051

2288

#define IQM_CF_TAP_IM17__W 9

2289

#define IQM_CF_TAP_IM17__M 0x1FF

2290

#define IQM_CF_TAP_IM17__PRE 0x2

2291

#define IQM_CF_TAP_IM17_B__B 0

2292

#define IQM_CF_TAP_IM17_B__W 9

2293

#define IQM_CF_TAP_IM17_B__M 0x1FF

2294

#define IQM_CF_TAP_IM17_B__PRE 0x2

2295

2296

#define IQM_CF_TAP_IM18__A 0x1860052

2297

#define IQM_CF_TAP_IM18__W 9

2298

#define IQM_CF_TAP_IM18__M 0x1FF

2299

#define IQM_CF_TAP_IM18__PRE 0x2

2300

#define IQM_CF_TAP_IM18_B__B 0

2301

#define IQM_CF_TAP_IM18_B__W 9

2302

#define IQM_CF_TAP_IM18_B__M 0x1FF

2303

#define IQM_CF_TAP_IM18_B__PRE 0x2

2304

2305

#define IQM_CF_TAP_IM19__A 0x1860053

2306

#define IQM_CF_TAP_IM19__W 9

2307

#define IQM_CF_TAP_IM19__M 0x1FF

2308

#define IQM_CF_TAP_IM19__PRE 0x2

2309

#define IQM_CF_TAP_IM19_B__B 0

2310

#define IQM_CF_TAP_IM19_B__W 9

2311

#define IQM_CF_TAP_IM19_B__M 0x1FF

2312

#define IQM_CF_TAP_IM19_B__PRE 0x2

2313

2314

#define IQM_CF_TAP_IM20__A 0x1860054

2315

#define IQM_CF_TAP_IM20__W 9

2316

#define IQM_CF_TAP_IM20__M 0x1FF

2317

#define IQM_CF_TAP_IM20__PRE 0x2

2318

#define IQM_CF_TAP_IM20_B__B 0

2319

#define IQM_CF_TAP_IM20_B__W 9

2320

#define IQM_CF_TAP_IM20_B__M 0x1FF

2321

#define IQM_CF_TAP_IM20_B__PRE 0x2

2322

2323

#define IQM_CF_TAP_IM21__A 0x1860055

2324

#define IQM_CF_TAP_IM21__W 11

2325

#define IQM_CF_TAP_IM21__M 0x7FF

2326

#define IQM_CF_TAP_IM21__PRE 0x2

2327

#define IQM_CF_TAP_IM21_B__B 0

2328

#define IQM_CF_TAP_IM21_B__W 11

2329

#define IQM_CF_TAP_IM21_B__M 0x7FF

2330

#define IQM_CF_TAP_IM21_B__PRE 0x2

2331

2332

#define IQM_CF_TAP_IM22__A 0x1860056

2333

#define IQM_CF_TAP_IM22__W 11

2334

#define IQM_CF_TAP_IM22__M 0x7FF

2335

#define IQM_CF_TAP_IM22__PRE 0x2

2336

#define IQM_CF_TAP_IM22_B__B 0

2337

#define IQM_CF_TAP_IM22_B__W 11

2338

#define IQM_CF_TAP_IM22_B__M 0x7FF

2339

#define IQM_CF_TAP_IM22_B__PRE 0x2

2340

2341

#define IQM_CF_TAP_IM23__A 0x1860057

2342

#define IQM_CF_TAP_IM23__W 11

2343

#define IQM_CF_TAP_IM23__M 0x7FF

2344

#define IQM_CF_TAP_IM23__PRE 0x2

2345

#define IQM_CF_TAP_IM23_B__B 0

2346

#define IQM_CF_TAP_IM23_B__W 11

2347

#define IQM_CF_TAP_IM23_B__M 0x7FF

2348

#define IQM_CF_TAP_IM23_B__PRE 0x2

2349

2350

#define IQM_CF_TAP_IM24__A 0x1860058

2351

#define IQM_CF_TAP_IM24__W 11

2352

#define IQM_CF_TAP_IM24__M 0x7FF

2353

#define IQM_CF_TAP_IM24__PRE 0x2

2354

#define IQM_CF_TAP_IM24_B__B 0

2355

#define IQM_CF_TAP_IM24_B__W 11

2356

#define IQM_CF_TAP_IM24_B__M 0x7FF

2357

#define IQM_CF_TAP_IM24_B__PRE 0x2

2358

2359

#define IQM_CF_TAP_IM25__A 0x1860059

2360

#define IQM_CF_TAP_IM25__W 11

2361

#define IQM_CF_TAP_IM25__M 0x7FF

2362

#define IQM_CF_TAP_IM25__PRE 0x2

2363

#define IQM_CF_TAP_IM25_B__B 0

2364

#define IQM_CF_TAP_IM25_B__W 11

2365

#define IQM_CF_TAP_IM25_B__M 0x7FF

2366

#define IQM_CF_TAP_IM25_B__PRE 0x2

2367

2368

#define IQM_CF_TAP_IM26__A 0x186005A

2369

#define IQM_CF_TAP_IM26__W 11

2370

#define IQM_CF_TAP_IM26__M 0x7FF

2371

#define IQM_CF_TAP_IM26__PRE 0x2

2372

#define IQM_CF_TAP_IM26_B__B 0

2373

#define IQM_CF_TAP_IM26_B__W 11

2374

#define IQM_CF_TAP_IM26_B__M 0x7FF

2375

#define IQM_CF_TAP_IM26_B__PRE 0x2

2376

2377

#define IQM_CF_TAP_IM27__A 0x186005B

2378

#define IQM_CF_TAP_IM27__W 11

2379

#define IQM_CF_TAP_IM27__M 0x7FF

2380

#define IQM_CF_TAP_IM27__PRE 0x2

2381

#define IQM_CF_TAP_IM27_B__B 0

2382

#define IQM_CF_TAP_IM27_B__W 11

2383

#define IQM_CF_TAP_IM27_B__M 0x7FF

2384

#define IQM_CF_TAP_IM27_B__PRE 0x2

2385

2386

2387

#define IQM_CF_CLP_VAL__A 0x1860060

2388

#define IQM_CF_CLP_VAL__W 9

2389

#define IQM_CF_CLP_VAL__M 0x1FF

2390

#define IQM_CF_CLP_VAL__PRE 0x3C

2391

2392

#define IQM_CF_DATATH__A 0x1860061

2393

#define IQM_CF_DATATH__W 10

2394

#define IQM_CF_DATATH__M 0x3FF

2395

#define IQM_CF_DATATH__PRE 0x180

2396

2397

#define IQM_CF_PKDTH__A 0x1860062

2398

#define IQM_CF_PKDTH__W 5

2399

#define IQM_CF_PKDTH__M 0x1F

2400

#define IQM_CF_PKDTH__PRE 0x1

2401

2402

#define IQM_CF_WND_LEN__A 0x1860063

2403

#define IQM_CF_WND_LEN__W 4

2404

#define IQM_CF_WND_LEN__M 0xF

2405

#define IQM_CF_WND_LEN__PRE 0x1

2406

2407

#define IQM_CF_DET_LCT__A 0x1860064

2408

#define IQM_CF_DET_LCT__W 1

2409

#define IQM_CF_DET_LCT__M 0x1

2410

#define IQM_CF_DET_LCT__PRE 0x1

2411

2412

#define IQM_CF_SNS_LEN__A 0x1860065

2413

#define IQM_CF_SNS_LEN__W 16

2414

#define IQM_CF_SNS_LEN__M 0xFFFF

2415

#define IQM_CF_SNS_LEN__PRE 0x0

2416

2417

#define IQM_CF_SNS_SENSE__A 0x1860066

2418

#define IQM_CF_SNS_SENSE__W 16

2419

#define IQM_CF_SNS_SENSE__M 0xFFFF

2420

#define IQM_CF_SNS_SENSE__PRE 0x0

2421

2422

#define IQM_CF_BYPASSDET__A 0x1860067

2423

#define IQM_CF_BYPASSDET__W 1

2424

#define IQM_CF_BYPASSDET__M 0x1

2425

#define IQM_CF_BYPASSDET__PRE 0x0

2426

2427

#define IQM_CF_UPD_ENA__A 0x1860068

2428

#define IQM_CF_UPD_ENA__W 1

2429

#define IQM_CF_UPD_ENA__M 0x1

2430

#define IQM_CF_UPD_ENA__PRE 0x0

2431

#define IQM_CF_UPD_ENA_DISABLE 0x0

2432

#define IQM_CF_UPD_ENA_ENABLE 0x1

#define IQM_AF_COMM_EXEC__A 0x1870000

2437

#define IQM_AF_COMM_EXEC__W 2

2438

#define IQM_AF_COMM_EXEC__M 0x3

2439

#define IQM_AF_COMM_EXEC__PRE 0x0

2440

#define IQM_AF_COMM_EXEC_STOP 0x0

2441

#define IQM_AF_COMM_EXEC_ACTIVE 0x1

2442

#define IQM_AF_COMM_EXEC_HOLD 0x2

2443

2444

#define IQM_AF_COMM_MB__A 0x1870002

2445

#define IQM_AF_COMM_MB__W 8

2446

#define IQM_AF_COMM_MB__M 0xFF

2447

#define IQM_AF_COMM_MB__PRE 0x0

2448

#define IQM_AF_COMM_MB_CTL__B 0

2449

#define IQM_AF_COMM_MB_CTL__W 1

2450

#define IQM_AF_COMM_MB_CTL__M 0x1

2451

#define IQM_AF_COMM_MB_CTL__PRE 0x0

2452

#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x0

2453

#define IQM_AF_COMM_MB_CTL_CTL_ON 0x1

2454

#define IQM_AF_COMM_MB_OBS__B 1

2455

#define IQM_AF_COMM_MB_OBS__W 1

2456

#define IQM_AF_COMM_MB_OBS__M 0x2

2457

#define IQM_AF_COMM_MB_OBS__PRE 0x0

2458

#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x0

2459

#define IQM_AF_COMM_MB_OBS_OBS_ON 0x2

2460

#define IQM_AF_COMM_MB_MUX_CTRL__B 2

2461

#define IQM_AF_COMM_MB_MUX_CTRL__W 3

2462

#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C

2463

#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x0

2464

#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x0

2465

#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x4

2466

#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x8

2467

#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC

2468

#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x10

2469

#define IQM_AF_COMM_MB_MUX_CTRL_CMP_ERR_DN 0x14

2470

#define IQM_AF_COMM_MB_MUX_OBS__B 5

2471

#define IQM_AF_COMM_MB_MUX_OBS__W 3

2472

#define IQM_AF_COMM_MB_MUX_OBS__M 0xE0

2473

#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x0

2474

#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x0

2475

#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x20

2476

#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x40

2477

#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x60

2478

#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x80

2479

#define IQM_AF_COMM_MB_MUX_OBS_CMP_ERR_DN 0xA0

2480

2481

#define IQM_AF_COMM_INT_REQ__A 0x1870003

2482

#define IQM_AF_COMM_INT_REQ__W 1

2483

#define IQM_AF_COMM_INT_REQ__M 0x1

2484

#define IQM_AF_COMM_INT_REQ__PRE 0x0

2485

#define IQM_AF_COMM_INT_STA__A 0x1870005

2486

#define IQM_AF_COMM_INT_STA__W 3

2487

#define IQM_AF_COMM_INT_STA__M 0x7

2488

#define IQM_AF_COMM_INT_STA__PRE 0x0

2489

#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 0

2490

#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 1

2491

#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x1

2492

#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x0

2493

#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 1

2494

#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 1

2495

#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x2

2496

#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x0

2497

#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__B 2

2498

#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__W 1

2499

#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__M 0x4

2500

#define IQM_AF_COMM_INT_STA_ISNS_INT_STA__PRE 0x0

2501

2502

#define IQM_AF_COMM_INT_MSK__A 0x1870006

2503

#define IQM_AF_COMM_INT_MSK__W 3

2504

#define IQM_AF_COMM_INT_MSK__M 0x7

2505

#define IQM_AF_COMM_INT_MSK__PRE 0x0

2506

#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 0

2507

#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 1

2508

#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x1

2509

#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x0

2510

#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 1

2511

#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 1

2512

#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x2

2513

#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x0

2514

#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__B 2

2515

#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__W 1

2516

#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__M 0x4

2517

#define IQM_AF_COMM_INT_MSK_ISNS_INT_MSK__PRE 0x0

2518

2519

#define IQM_AF_COMM_INT_STM__A 0x1870007

2520

#define IQM_AF_COMM_INT_STM__W 3

2521

#define IQM_AF_COMM_INT_STM__M 0x7

2522

#define IQM_AF_COMM_INT_STM__PRE 0x0

2523

#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 0

2524

#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 1

2525

#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x1

2526

#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x0

2527

#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 1

2528

#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 1

2529

#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x2

2530

#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x0

2531

#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__B 2

2532

#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__W 1

2533

#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__M 0x4

2534

#define IQM_AF_COMM_INT_STM_ISNS_INT_STA__PRE 0x0

2535

2536

2537

#define IQM_AF_FDB_SEL__A 0x1870010

2538

#define IQM_AF_FDB_SEL__W 2

2539

#define IQM_AF_FDB_SEL__M 0x3

2540

#define IQM_AF_FDB_SEL__PRE 0x0

2541

#define IQM_AF_CLKNEG__A 0x1870012

2542

#define IQM_AF_CLKNEG__W 2

2543

#define IQM_AF_CLKNEG__M 0x3

2544

#define IQM_AF_CLKNEG__PRE 0x0

2545

2546

#define IQM_AF_CLKNEG_CLKNEGPEAK__B 0

2547

#define IQM_AF_CLKNEG_CLKNEGPEAK__W 1

2548

#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x1

2549

#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x0

2550

#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x0

2551

#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x1

2552

2553

#define IQM_AF_CLKNEG_CLKNEGDATA__B 1

2554

#define IQM_AF_CLKNEG_CLKNEGDATA__W 1

2555

#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2

2556

#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x0

2557

#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0

2558

#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2

2559

2560

2561

#define IQM_AF_MON_IN_MUX__A 0x1870013

2562

#define IQM_AF_MON_IN_MUX__W 2

2563

#define IQM_AF_MON_IN_MUX__M 0x3

2564

#define IQM_AF_MON_IN_MUX__PRE 0x0

2565

2566

#define IQM_AF_MON_IN5__A 0x1870014

2567

#define IQM_AF_MON_IN5__W 10

2568

#define IQM_AF_MON_IN5__M 0x3FF

2569

#define IQM_AF_MON_IN5__PRE 0x0

2570

2571

#define IQM_AF_MON_IN4__A 0x1870015

2572

#define IQM_AF_MON_IN4__W 10

2573

#define IQM_AF_MON_IN4__M 0x3FF

2574

#define IQM_AF_MON_IN4__PRE 0x0

2575

2576

#define IQM_AF_MON_IN3__A 0x1870016

2577

#define IQM_AF_MON_IN3__W 10

2578

#define IQM_AF_MON_IN3__M 0x3FF

2579

#define IQM_AF_MON_IN3__PRE 0x0

2580

2581

#define IQM_AF_MON_IN2__A 0x1870017

2582

#define IQM_AF_MON_IN2__W 10

2583

#define IQM_AF_MON_IN2__M 0x3FF

2584

#define IQM_AF_MON_IN2__PRE 0x0

2585

2586

#define IQM_AF_MON_IN1__A 0x1870018

2587

#define IQM_AF_MON_IN1__W 10

2588

#define IQM_AF_MON_IN1__M 0x3FF

2589

#define IQM_AF_MON_IN1__PRE 0x0

2590

2591

#define IQM_AF_MON_IN0__A 0x1870019

2592

#define IQM_AF_MON_IN0__W 10

2593

#define IQM_AF_MON_IN0__M 0x3FF

2594

#define IQM_AF_MON_IN0__PRE 0x0

2595

2596

#define IQM_AF_MON_IN_VAL__A 0x187001A

2597

#define IQM_AF_MON_IN_VAL__W 1

2598

#define IQM_AF_MON_IN_VAL__M 0x1

2599

#define IQM_AF_MON_IN_VAL__PRE 0x0

2600

2601

#define IQM_AF_START_LOCK__A 0x187001B

2602

#define IQM_AF_START_LOCK__W 1

2603

#define IQM_AF_START_LOCK__M 0x1

2604

#define IQM_AF_START_LOCK__PRE 0x0

2605

2606

#define IQM_AF_PHASE0__A 0x187001C

2607

#define IQM_AF_PHASE0__W 7

2608

#define IQM_AF_PHASE0__M 0x7F

2609

#define IQM_AF_PHASE0__PRE 0x0

2610

2611

#define IQM_AF_PHASE1__A 0x187001D

2612

#define IQM_AF_PHASE1__W 7

2613

#define IQM_AF_PHASE1__M 0x7F

2614

#define IQM_AF_PHASE1__PRE 0x0

2615

2616

#define IQM_AF_PHASE2__A 0x187001E

2617

#define IQM_AF_PHASE2__W 7

2618

#define IQM_AF_PHASE2__M 0x7F

2619

#define IQM_AF_PHASE2__PRE 0x0

2620

2621

#define IQM_AF_SCU_PHASE__A 0x187001F

2622

#define IQM_AF_SCU_PHASE__W 2

2623

#define IQM_AF_SCU_PHASE__M 0x3

2624

#define IQM_AF_SCU_PHASE__PRE 0x0

2625

2626

#define IQM_AF_SYNC_SEL__A 0x1870020

2627

#define IQM_AF_SYNC_SEL__W 2

2628

#define IQM_AF_SYNC_SEL__M 0x3

2629

#define IQM_AF_SYNC_SEL__PRE 0x0

2630

#define IQM_AF_ADC_CONF__A 0x1870021

2631

#define IQM_AF_ADC_CONF__W 4

2632

#define IQM_AF_ADC_CONF__M 0xF

2633

#define IQM_AF_ADC_CONF__PRE 0x0

2634

2635

#define IQM_AF_ADC_CONF_ADC_SIGN__B 0

2636

#define IQM_AF_ADC_CONF_ADC_SIGN__W 1

2637

#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x1

2638

#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x0

2639

#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x0

2640

#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x1

2641

2642

#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 1

2643

#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 1

2644

#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x2

2645

#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x0

2646

#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x0

2647

#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x2

2648

2649

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 2

2650

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 1

2651

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x4

2652

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x0

2653

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x0

2654

#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x4

2655

2656

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 3

2657

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 1

2658

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x8

2659

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x0

2660

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x0

2661

#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x8

2662

2663

2664

#define IQM_AF_CLP_CLIP__A 0x1870022

2665

#define IQM_AF_CLP_CLIP__W 16

2666

#define IQM_AF_CLP_CLIP__M 0xFFFF

2667

#define IQM_AF_CLP_CLIP__PRE 0x0

2668

2669

#define IQM_AF_CLP_LEN__A 0x1870023

2670

#define IQM_AF_CLP_LEN__W 16

2671

#define IQM_AF_CLP_LEN__M 0xFFFF

2672

#define IQM_AF_CLP_LEN__PRE 0x0

2673

2674

#define IQM_AF_CLP_TH__A 0x1870024

2675

#define IQM_AF_CLP_TH__W 9

2676

#define IQM_AF_CLP_TH__M 0x1FF

2677

#define IQM_AF_CLP_TH__PRE 0x0

2678

2679

#define IQM_AF_DCF_BYPASS__A 0x1870025

2680

#define IQM_AF_DCF_BYPASS__W 1

2681

#define IQM_AF_DCF_BYPASS__M 0x1

2682

#define IQM_AF_DCF_BYPASS__PRE 0x0

2683

#define IQM_AF_DCF_BYPASS_ACTIVE 0x0

2684

#define IQM_AF_DCF_BYPASS_BYPASS 0x1

2685

2686

2687

#define IQM_AF_SNS_LEN__A 0x1870026

2688

#define IQM_AF_SNS_LEN__W 16

2689

#define IQM_AF_SNS_LEN__M 0xFFFF

2690

#define IQM_AF_SNS_LEN__PRE 0x0

2691

2692

#define IQM_AF_SNS_SENSE__A 0x1870027

2693

#define IQM_AF_SNS_SENSE__W 16

2694

#define IQM_AF_SNS_SENSE__M 0xFFFF

2695

#define IQM_AF_SNS_SENSE__PRE 0x0

2696

2697

#define IQM_AF_AGC_IF__A 0x1870028

2698

#define IQM_AF_AGC_IF__W 15

2699

#define IQM_AF_AGC_IF__M 0x7FFF

2700

#define IQM_AF_AGC_IF__PRE 0x0

2701

2702

#define IQM_AF_AGC_RF__A 0x1870029

2703

#define IQM_AF_AGC_RF__W 15

2704

#define IQM_AF_AGC_RF__M 0x7FFF

2705

#define IQM_AF_AGC_RF__PRE 0x0

2706

2707

#define IQM_AF_PDREF__A 0x187002B

2708

#define IQM_AF_PDREF__W 5

2709

#define IQM_AF_PDREF__M 0x1F

2710

#define IQM_AF_PDREF__PRE 0x0

2711

#define IQM_AF_STDBY__A 0x187002C

2712

#define IQM_AF_STDBY__W 6

2713

#define IQM_AF_STDBY__M 0x3F

2714

#define IQM_AF_STDBY__PRE 0x3E

2715

2716

#define IQM_AF_STDBY_STDBY_BIAS__B 0

2717

#define IQM_AF_STDBY_STDBY_BIAS__W 1

2718

#define IQM_AF_STDBY_STDBY_BIAS__M 0x1

2719

#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x0

2720

#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x0

2721

#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x1

2722

2723

#define IQM_AF_STDBY_STDBY_ADC__B 1

2724

#define IQM_AF_STDBY_STDBY_ADC__W 1

2725

#define IQM_AF_STDBY_STDBY_ADC__M 0x2

2726

#define IQM_AF_STDBY_STDBY_ADC__PRE 0x2

2727

#define IQM_AF_STDBY_STDBY_ADC_ACTIVE 0x0

2728

#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2

2729

2730

#define IQM_AF_STDBY_STDBY_AMP__B 2

2731

#define IQM_AF_STDBY_STDBY_AMP__W 1

2732

#define IQM_AF_STDBY_STDBY_AMP__M 0x4

2733

#define IQM_AF_STDBY_STDBY_AMP__PRE 0x4

2734

#define IQM_AF_STDBY_STDBY_AMP_ACTIVE 0x0

2735

#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4

2736

2737

#define IQM_AF_STDBY_STDBY_PD__B 3

2738

#define IQM_AF_STDBY_STDBY_PD__W 1

2739

#define IQM_AF_STDBY_STDBY_PD__M 0x8

2740

#define IQM_AF_STDBY_STDBY_PD__PRE 0x8

2741

#define IQM_AF_STDBY_STDBY_PD_ACTIVE 0x0

2742

#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8

2743

2744

#define IQM_AF_STDBY_STDBY_TAGC_IF__B 4

2745

#define IQM_AF_STDBY_STDBY_TAGC_IF__W 1

2746

#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x10

2747

#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x10

2748

#define IQM_AF_STDBY_STDBY_TAGC_IF_ACTIVE 0x0

2749

#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10

2750

2751

#define IQM_AF_STDBY_STDBY_TAGC_RF__B 5

2752

#define IQM_AF_STDBY_STDBY_TAGC_RF__W 1

2753

#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x20

2754

#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x20

2755

#define IQM_AF_STDBY_STDBY_TAGC_RF_ACTIVE 0x0

2756

#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20

2757

2758

2759

#define IQM_AF_AMUX__A 0x187002D

2760

#define IQM_AF_AMUX__W 1

2761

#define IQM_AF_AMUX__M 0x1

2762

#define IQM_AF_AMUX__PRE 0x0

2763

#define IQM_AF_AMUX_SIGNAL2LOWPASS 0x0

2764

#define IQM_AF_AMUX_SIGNAL2ADC 0x1

2765

2766

2767

#define IQM_AF_TST_AFEMAIN__A 0x187002E

2768

#define IQM_AF_TST_AFEMAIN__W 8

2769

#define IQM_AF_TST_AFEMAIN__M 0xFF

2770

#define IQM_AF_TST_AFEMAIN__PRE 0x0

2771

2772

#define IQM_AF_UPD_SEL__A 0x187002F

2773

#define IQM_AF_UPD_SEL__W 1

2774

#define IQM_AF_UPD_SEL__M 0x1

2775

#define IQM_AF_UPD_SEL__PRE 0x0

2776

2777

#define IQM_AF_INC_DATATH__A 0x1870030

2778

#define IQM_AF_INC_DATATH__W 9

2779

#define IQM_AF_INC_DATATH__M 0x1FF

2780

#define IQM_AF_INC_DATATH__PRE 0x180

2781

2782

#define IQM_AF_INC_PKDTH__A 0x1870031

2783

#define IQM_AF_INC_PKDTH__W 5

2784

#define IQM_AF_INC_PKDTH__M 0x1F

2785

#define IQM_AF_INC_PKDTH__PRE 0x3

2786

2787

#define IQM_AF_INC_WND_LEN__A 0x1870032

2788

#define IQM_AF_INC_WND_LEN__W 4

2789

#define IQM_AF_INC_WND_LEN__M 0xF

2790

#define IQM_AF_INC_WND_LEN__PRE 0xA

2791

2792

#define IQM_AF_INC_DLY__A 0x1870033

2793

#define IQM_AF_INC_DLY__W 7

2794

#define IQM_AF_INC_DLY__M 0x7F

2795

#define IQM_AF_INC_DLY__PRE 0x14

2796

2797

#define IQM_AF_INC_LCT__A 0x1870034

2798

#define IQM_AF_INC_LCT__W 1

2799

#define IQM_AF_INC_LCT__M 0x1

2800

#define IQM_AF_INC_LCT__PRE 0x1

2801

2802

#define IQM_AF_INC_CLP_VAL__A 0x1870035

2803

#define IQM_AF_INC_CLP_VAL__W 9

2804

#define IQM_AF_INC_CLP_VAL__M 0x1FF

2805

#define IQM_AF_INC_CLP_VAL__PRE 0x3C

2806

2807

#define IQM_AF_INC_BYPASS__A 0x1870036

2808

#define IQM_AF_INC_BYPASS__W 1

2809

#define IQM_AF_INC_BYPASS__M 0x1

2810

#define IQM_AF_INC_BYPASS__PRE 0x1

2811

2812

#define IQM_AF_INC_MODE_SEL__A 0x1870037

2813

#define IQM_AF_INC_MODE_SEL__W 2

2814

#define IQM_AF_INC_MODE_SEL__M 0x3

2815

#define IQM_AF_INC_MODE_SEL__PRE 0x1

2816

2817

#define IQM_AF_INC_A_DLY__A 0x1870038

2818

#define IQM_AF_INC_A_DLY__W 6

2819

#define IQM_AF_INC_A_DLY__M 0x3F

2820

#define IQM_AF_INC_A_DLY__PRE 0xF

2821

2822

#define IQM_AF_ISNS_LEN__A 0x1870039

2823

#define IQM_AF_ISNS_LEN__W 16

2824

#define IQM_AF_ISNS_LEN__M 0xFFFF

2825

#define IQM_AF_ISNS_LEN__PRE 0x0

2826

2827

#define IQM_AF_ISNS_SENSE__A 0x187003A

2828

#define IQM_AF_ISNS_SENSE__W 16

2829

#define IQM_AF_ISNS_SENSE__M 0xFFFF

2830

#define IQM_AF_ISNS_SENSE__PRE 0x0

2831

#define IQM_AF_CMP_STATE__A 0x187003B

2832

#define IQM_AF_CMP_STATE__W 7

2833

#define IQM_AF_CMP_STATE__M 0x7F

2834

#define IQM_AF_CMP_STATE__PRE 0x0

2835

2836

#define IQM_AF_CMP_STATE_STATE__B 0

2837

#define IQM_AF_CMP_STATE_STATE__W 2

2838

#define IQM_AF_CMP_STATE_STATE__M 0x3

2839

#define IQM_AF_CMP_STATE_STATE__PRE 0x0

2840

2841

#define IQM_AF_CMP_STATE_ENABLE_CORING__B 2

2842

#define IQM_AF_CMP_STATE_ENABLE_CORING__W 1

2843

#define IQM_AF_CMP_STATE_ENABLE_CORING__M 0x4

2844

#define IQM_AF_CMP_STATE_ENABLE_CORING__PRE 0x0

2845

2846

#define IQM_AF_CMP_STATE_FILTERGAIN__B 3

2847

#define IQM_AF_CMP_STATE_FILTERGAIN__W 2

2848

#define IQM_AF_CMP_STATE_FILTERGAIN__M 0x18

2849

#define IQM_AF_CMP_STATE_FILTERGAIN__PRE 0x0

2850

#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER128 0x0

2851

#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER64 0x8

2852

#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER32 0x10

2853

#define IQM_AF_CMP_STATE_FILTERGAIN_GAIN1OVER16 0x18

2854

2855

#define IQM_AF_CMP_STATE_KEEPCOEFF__B 5

2856

#define IQM_AF_CMP_STATE_KEEPCOEFF__W 1

2857

#define IQM_AF_CMP_STATE_KEEPCOEFF__M 0x20

2858

#define IQM_AF_CMP_STATE_KEEPCOEFF__PRE 0x0

2859

2860

#define IQM_AF_CMP_STATE_SEG64__B 6

2861

#define IQM_AF_CMP_STATE_SEG64__W 1

2862

#define IQM_AF_CMP_STATE_SEG64__M 0x40

2863

#define IQM_AF_CMP_STATE_SEG64__PRE 0x0

2864

#define IQM_AF_CMP_STATE_SEG64_SEG32 0x0

2865

#define IQM_AF_CMP_STATE_SEG64_SEG64 0x40

2866

2867

2868

#define IQM_AF_CMP_DC_OUT__A 0x187003C

2869

#define IQM_AF_CMP_DC_OUT__W 12

2870

#define IQM_AF_CMP_DC_OUT__M 0xFFF

2871

#define IQM_AF_CMP_DC_OUT__PRE 0x0

2872

#define IQM_AF_CMP_DC_IN__A 0x187003D

2873

#define IQM_AF_CMP_DC_IN__W 13

2874

#define IQM_AF_CMP_DC_IN__M 0x1FFF

2875

#define IQM_AF_CMP_DC_IN__PRE 0x0

2876

2877

#define IQM_AF_CMP_DC_IN_DC__B 0

2878

#define IQM_AF_CMP_DC_IN_DC__W 12

2879

#define IQM_AF_CMP_DC_IN_DC__M 0xFFF

2880

#define IQM_AF_CMP_DC_IN_DC__PRE 0x0

2881

#define IQM_AF_CMP_DC_IN_DC_EN__B 12

2882

#define IQM_AF_CMP_DC_IN_DC_EN__W 1

2883

#define IQM_AF_CMP_DC_IN_DC_EN__M 0x1000

2884

#define IQM_AF_CMP_DC_IN_DC_EN__PRE 0x0

2885

#define IQM_AF_CMP_DC_IN_DC_EN_DISABLE 0x0

2886

#define IQM_AF_CMP_DC_IN_DC_EN_ENABLE 0x1000

2887

2888

2889

#define IQM_AF_CMP_AMP__A 0x187003E

2890

#define IQM_AF_CMP_AMP__W 10

2891

#define IQM_AF_CMP_AMP__M 0x3FF

2892

#define IQM_AF_CMP_AMP__PRE 0x0

2893

#define IQM_AF_CMP_DN_AVG__A 0x187003F

2894

#define IQM_AF_CMP_DN_AVG__W 8

2895

#define IQM_AF_CMP_DN_AVG__M 0xFF

2896

#define IQM_AF_CMP_DN_AVG__PRE 0x0

2897

2898

#define IQM_AF_CMP_DN_AVG_DN_AVG__B 0

2899

#define IQM_AF_CMP_DN_AVG_DN_AVG__W 8

2900

#define IQM_AF_CMP_DN_AVG_DN_AVG__M 0xFF

2901

#define IQM_AF_CMP_DN_AVG_DN_AVG__PRE 0x0

2902

2903

2904

#define IQM_AF_CMP_ACTIVE__A 0x1870040

2905

#define IQM_AF_CMP_ACTIVE__W 1

2906

#define IQM_AF_CMP_ACTIVE__M 0x1

2907

#define IQM_AF_CMP_ACTIVE__PRE 0x0

2908

#define IQM_AF_CMP_MEM0__A 0x1870080

2909

#define IQM_AF_CMP_MEM0__W 13

2910

#define IQM_AF_CMP_MEM0__M 0x1FFF

2911

#define IQM_AF_CMP_MEM0__PRE 0x0

2912

2913

#define IQM_AF_CMP_MEM0_COEF__B 0

2914

#define IQM_AF_CMP_MEM0_COEF__W 13

2915

#define IQM_AF_CMP_MEM0_COEF__M 0x1FFF

2916

#define IQM_AF_CMP_MEM0_COEF__PRE 0x0

2917

2918

#define IQM_AF_CMP_MEM1__A 0x1870081

2919

#define IQM_AF_CMP_MEM1__W 13

2920

#define IQM_AF_CMP_MEM1__M 0x1FFF

2921

#define IQM_AF_CMP_MEM1__PRE 0x0

2922

2923

#define IQM_AF_CMP_MEM1_COEF__B 0

2924

#define IQM_AF_CMP_MEM1_COEF__W 13

2925

#define IQM_AF_CMP_MEM1_COEF__M 0x1FFF

2926

#define IQM_AF_CMP_MEM1_COEF__PRE 0x0

2927

2928

#define IQM_AF_CMP_MEM2__A 0x1870082

2929

#define IQM_AF_CMP_MEM2__W 13

2930

#define IQM_AF_CMP_MEM2__M 0x1FFF

2931

#define IQM_AF_CMP_MEM2__PRE 0x0

2932

2933

#define IQM_AF_CMP_MEM2_COEF__B 0

2934

#define IQM_AF_CMP_MEM2_COEF__W 13

2935

#define IQM_AF_CMP_MEM2_COEF__M 0x1FFF

2936

#define IQM_AF_CMP_MEM2_COEF__PRE 0x0

2937

2938

#define IQM_AF_CMP_MEM3__A 0x1870083

2939

#define IQM_AF_CMP_MEM3__W 13

2940

#define IQM_AF_CMP_MEM3__M 0x1FFF

2941

#define IQM_AF_CMP_MEM3__PRE 0x0

2942

2943

#define IQM_AF_CMP_MEM3_COEF__B 0

2944

#define IQM_AF_CMP_MEM3_COEF__W 13

2945

#define IQM_AF_CMP_MEM3_COEF__M 0x1FFF

2946

#define IQM_AF_CMP_MEM3_COEF__PRE 0x0

2947

2948

#define IQM_AF_CMP_MEM4__A 0x1870084

2949

#define IQM_AF_CMP_MEM4__W 13

2950

#define IQM_AF_CMP_MEM4__M 0x1FFF

2951

#define IQM_AF_CMP_MEM4__PRE 0x0

2952

2953

#define IQM_AF_CMP_MEM4_COEF__B 0

2954

#define IQM_AF_CMP_MEM4_COEF__W 13

2955

#define IQM_AF_CMP_MEM4_COEF__M 0x1FFF

2956

#define IQM_AF_CMP_MEM4_COEF__PRE 0x0

2957

2958

#define IQM_AF_CMP_MEM5__A 0x1870085

2959

#define IQM_AF_CMP_MEM5__W 13

2960

#define IQM_AF_CMP_MEM5__M 0x1FFF

2961

#define IQM_AF_CMP_MEM5__PRE 0x0

2962

2963

#define IQM_AF_CMP_MEM5_COEF__B 0

2964

#define IQM_AF_CMP_MEM5_COEF__W 13

2965

#define IQM_AF_CMP_MEM5_COEF__M 0x1FFF

2966

#define IQM_AF_CMP_MEM5_COEF__PRE 0x0

2967

2968

#define IQM_AF_CMP_MEM6__A 0x1870086

2969

#define IQM_AF_CMP_MEM6__W 13

2970

#define IQM_AF_CMP_MEM6__M 0x1FFF

2971

#define IQM_AF_CMP_MEM6__PRE 0x0

2972

2973

#define IQM_AF_CMP_MEM6_COEF__B 0

2974

#define IQM_AF_CMP_MEM6_COEF__W 13

2975

#define IQM_AF_CMP_MEM6_COEF__M 0x1FFF

2976

#define IQM_AF_CMP_MEM6_COEF__PRE 0x0

2977

2978

#define IQM_AF_CMP_MEM7__A 0x1870087

2979

#define IQM_AF_CMP_MEM7__W 13

2980

#define IQM_AF_CMP_MEM7__M 0x1FFF

2981

#define IQM_AF_CMP_MEM7__PRE 0x0

2982

2983

#define IQM_AF_CMP_MEM7_COEF__B 0

2984

#define IQM_AF_CMP_MEM7_COEF__W 13

2985

#define IQM_AF_CMP_MEM7_COEF__M 0x1FFF

2986

#define IQM_AF_CMP_MEM7_COEF__PRE 0x0

2987

2988

#define IQM_AF_CMP_MEM8__A 0x1870088

2989

#define IQM_AF_CMP_MEM8__W 13

2990

#define IQM_AF_CMP_MEM8__M 0x1FFF

2991

#define IQM_AF_CMP_MEM8__PRE 0x0

2992

2993

#define IQM_AF_CMP_MEM8_COEF__B 0

2994

#define IQM_AF_CMP_MEM8_COEF__W 13

2995

#define IQM_AF_CMP_MEM8_COEF__M 0x1FFF

2996

#define IQM_AF_CMP_MEM8_COEF__PRE 0x0

2997

2998

#define IQM_AF_CMP_MEM9__A 0x1870089

2999

#define IQM_AF_CMP_MEM9__W 13

3000

#define IQM_AF_CMP_MEM9__M 0x1FFF

3001

#define IQM_AF_CMP_MEM9__PRE 0x0

3002

3003

#define IQM_AF_CMP_MEM9_COEF__B 0

3004

#define IQM_AF_CMP_MEM9_COEF__W 13

3005

#define IQM_AF_CMP_MEM9_COEF__M 0x1FFF

3006

#define IQM_AF_CMP_MEM9_COEF__PRE 0x0

3007

3008

#define IQM_AF_CMP_MEM10__A 0x187008A

3009

#define IQM_AF_CMP_MEM10__W 13

3010

#define IQM_AF_CMP_MEM10__M 0x1FFF

3011

#define IQM_AF_CMP_MEM10__PRE 0x0

3012

3013

#define IQM_AF_CMP_MEM10_COEF__B 0

3014

#define IQM_AF_CMP_MEM10_COEF__W 13

3015

#define IQM_AF_CMP_MEM10_COEF__M 0x1FFF

3016

#define IQM_AF_CMP_MEM10_COEF__PRE 0x0

3017

3018

#define IQM_AF_CMP_MEM11__A 0x187008B

3019

#define IQM_AF_CMP_MEM11__W 13

3020

#define IQM_AF_CMP_MEM11__M 0x1FFF

3021

#define IQM_AF_CMP_MEM11__PRE 0x0

3022

3023

#define IQM_AF_CMP_MEM11_COEF__B 0

3024

#define IQM_AF_CMP_MEM11_COEF__W 13

3025

#define IQM_AF_CMP_MEM11_COEF__M 0x1FFF

3026

#define IQM_AF_CMP_MEM11_COEF__PRE 0x0

3027

3028

#define IQM_AF_CMP_MEM12__A 0x187008C

3029

#define IQM_AF_CMP_MEM12__W 13

3030

#define IQM_AF_CMP_MEM12__M 0x1FFF

3031

#define IQM_AF_CMP_MEM12__PRE 0x0

3032

3033

#define IQM_AF_CMP_MEM12_COEF__B 0

3034

#define IQM_AF_CMP_MEM12_COEF__W 13

3035

#define IQM_AF_CMP_MEM12_COEF__M 0x1FFF

3036

#define IQM_AF_CMP_MEM12_COEF__PRE 0x0

3037

3038

#define IQM_AF_CMP_MEM13__A 0x187008D

3039

#define IQM_AF_CMP_MEM13__W 13

3040

#define IQM_AF_CMP_MEM13__M 0x1FFF

3041

#define IQM_AF_CMP_MEM13__PRE 0x0

3042

3043

#define IQM_AF_CMP_MEM13_COEF__B 0

3044

#define IQM_AF_CMP_MEM13_COEF__W 13

3045

#define IQM_AF_CMP_MEM13_COEF__M 0x1FFF

3046

#define IQM_AF_CMP_MEM13_COEF__PRE 0x0

3047

3048

#define IQM_AF_CMP_MEM14__A 0x187008E

3049

#define IQM_AF_CMP_MEM14__W 13

3050

#define IQM_AF_CMP_MEM14__M 0x1FFF

3051

#define IQM_AF_CMP_MEM14__PRE 0x0

3052

3053

#define IQM_AF_CMP_MEM14_COEF__B 0

3054

#define IQM_AF_CMP_MEM14_COEF__W 13

3055

#define IQM_AF_CMP_MEM14_COEF__M 0x1FFF

3056

#define IQM_AF_CMP_MEM14_COEF__PRE 0x0

3057

3058

#define IQM_AF_CMP_MEM15__A 0x187008F

3059

#define IQM_AF_CMP_MEM15__W 13

3060

#define IQM_AF_CMP_MEM15__M 0x1FFF

3061

#define IQM_AF_CMP_MEM15__PRE 0x0

3062

3063

#define IQM_AF_CMP_MEM15_COEF__B 0

3064

#define IQM_AF_CMP_MEM15_COEF__W 13

3065

#define IQM_AF_CMP_MEM15_COEF__M 0x1FFF

3066

#define IQM_AF_CMP_MEM15_COEF__PRE 0x0

3067

3068

#define IQM_AF_CMP_MEM16__A 0x1870090

3069

#define IQM_AF_CMP_MEM16__W 13

3070

#define IQM_AF_CMP_MEM16__M 0x1FFF

3071

#define IQM_AF_CMP_MEM16__PRE 0x0

3072

3073

#define IQM_AF_CMP_MEM16_COEF__B 0

3074

#define IQM_AF_CMP_MEM16_COEF__W 13

3075

#define IQM_AF_CMP_MEM16_COEF__M 0x1FFF

3076

#define IQM_AF_CMP_MEM16_COEF__PRE 0x0

3077

3078

#define IQM_AF_CMP_MEM17__A 0x1870091

3079

#define IQM_AF_CMP_MEM17__W 13

3080

#define IQM_AF_CMP_MEM17__M 0x1FFF

3081

#define IQM_AF_CMP_MEM17__PRE 0x0

3082

3083

#define IQM_AF_CMP_MEM17_COEF__B 0

3084

#define IQM_AF_CMP_MEM17_COEF__W 13

3085

#define IQM_AF_CMP_MEM17_COEF__M 0x1FFF

3086

#define IQM_AF_CMP_MEM17_COEF__PRE 0x0

3087

3088

#define IQM_AF_CMP_MEM18__A 0x1870092

3089

#define IQM_AF_CMP_MEM18__W 13

3090

#define IQM_AF_CMP_MEM18__M 0x1FFF

3091

#define IQM_AF_CMP_MEM18__PRE 0x0

3092

3093

#define IQM_AF_CMP_MEM18_COEF__B 0

3094

#define IQM_AF_CMP_MEM18_COEF__W 13

3095

#define IQM_AF_CMP_MEM18_COEF__M 0x1FFF

3096

#define IQM_AF_CMP_MEM18_COEF__PRE 0x0

3097

3098

#define IQM_AF_CMP_MEM19__A 0x1870093

3099

#define IQM_AF_CMP_MEM19__W 13

3100

#define IQM_AF_CMP_MEM19__M 0x1FFF

3101

#define IQM_AF_CMP_MEM19__PRE 0x0

3102

3103

#define IQM_AF_CMP_MEM19_COEF__B 0

3104

#define IQM_AF_CMP_MEM19_COEF__W 13

3105

#define IQM_AF_CMP_MEM19_COEF__M 0x1FFF

3106

#define IQM_AF_CMP_MEM19_COEF__PRE 0x0

3107

3108

#define IQM_AF_CMP_MEM20__A 0x1870094

3109

#define IQM_AF_CMP_MEM20__W 13

3110

#define IQM_AF_CMP_MEM20__M 0x1FFF

3111

#define IQM_AF_CMP_MEM20__PRE 0x0

3112

3113

#define IQM_AF_CMP_MEM20_COEF__B 0

3114

#define IQM_AF_CMP_MEM20_COEF__W 13

3115

#define IQM_AF_CMP_MEM20_COEF__M 0x1FFF

3116

#define IQM_AF_CMP_MEM20_COEF__PRE 0x0

3117

3118

#define IQM_AF_CMP_MEM21__A 0x1870095

3119

#define IQM_AF_CMP_MEM21__W 13

3120

#define IQM_AF_CMP_MEM21__M 0x1FFF

3121

#define IQM_AF_CMP_MEM21__PRE 0x0

3122

3123

#define IQM_AF_CMP_MEM21_COEF__B 0

3124

#define IQM_AF_CMP_MEM21_COEF__W 13

3125

#define IQM_AF_CMP_MEM21_COEF__M 0x1FFF

3126

#define IQM_AF_CMP_MEM21_COEF__PRE 0x0

3127

3128

#define IQM_AF_CMP_MEM22__A 0x1870096

3129

#define IQM_AF_CMP_MEM22__W 13

3130

#define IQM_AF_CMP_MEM22__M 0x1FFF

3131

#define IQM_AF_CMP_MEM22__PRE 0x0

3132

3133

#define IQM_AF_CMP_MEM22_COEF__B 0

3134

#define IQM_AF_CMP_MEM22_COEF__W 13

3135

#define IQM_AF_CMP_MEM22_COEF__M 0x1FFF

3136

#define IQM_AF_CMP_MEM22_COEF__PRE 0x0

3137

3138

#define IQM_AF_CMP_MEM23__A 0x1870097

3139

#define IQM_AF_CMP_MEM23__W 13

3140

#define IQM_AF_CMP_MEM23__M 0x1FFF

3141

#define IQM_AF_CMP_MEM23__PRE 0x0

3142

3143

#define IQM_AF_CMP_MEM23_COEF__B 0

3144

#define IQM_AF_CMP_MEM23_COEF__W 13

3145

#define IQM_AF_CMP_MEM23_COEF__M 0x1FFF

3146

#define IQM_AF_CMP_MEM23_COEF__PRE 0x0

3147

3148

#define IQM_AF_CMP_MEM24__A 0x1870098

3149

#define IQM_AF_CMP_MEM24__W 13

3150

#define IQM_AF_CMP_MEM24__M 0x1FFF

3151

#define IQM_AF_CMP_MEM24__PRE 0x0

3152

3153

#define IQM_AF_CMP_MEM24_COEF__B 0

3154

#define IQM_AF_CMP_MEM24_COEF__W 13

3155

#define IQM_AF_CMP_MEM24_COEF__M 0x1FFF

3156

#define IQM_AF_CMP_MEM24_COEF__PRE 0x0

3157

3158

#define IQM_AF_CMP_MEM25__A 0x1870099

3159

#define IQM_AF_CMP_MEM25__W 13

3160

#define IQM_AF_CMP_MEM25__M 0x1FFF

3161

#define IQM_AF_CMP_MEM25__PRE 0x0

3162

3163

#define IQM_AF_CMP_MEM25_COEF__B 0

3164

#define IQM_AF_CMP_MEM25_COEF__W 13

3165

#define IQM_AF_CMP_MEM25_COEF__M 0x1FFF

3166

#define IQM_AF_CMP_MEM25_COEF__PRE 0x0

3167

3168

#define IQM_AF_CMP_MEM26__A 0x187009A

3169

#define IQM_AF_CMP_MEM26__W 13

3170

#define IQM_AF_CMP_MEM26__M 0x1FFF

3171

#define IQM_AF_CMP_MEM26__PRE 0x0

3172

3173

#define IQM_AF_CMP_MEM26_COEF__B 0

3174

#define IQM_AF_CMP_MEM26_COEF__W 13

3175

#define IQM_AF_CMP_MEM26_COEF__M 0x1FFF

3176

#define IQM_AF_CMP_MEM26_COEF__PRE 0x0

3177

3178

#define IQM_AF_CMP_MEM27__A 0x187009B

3179

#define IQM_AF_CMP_MEM27__W 13

3180

#define IQM_AF_CMP_MEM27__M 0x1FFF

3181

#define IQM_AF_CMP_MEM27__PRE 0x0

3182

3183

#define IQM_AF_CMP_MEM27_COEF__B 0

3184

#define IQM_AF_CMP_MEM27_COEF__W 13

3185

#define IQM_AF_CMP_MEM27_COEF__M 0x1FFF

3186

#define IQM_AF_CMP_MEM27_COEF__PRE 0x0

3187

3188

#define IQM_AF_CMP_MEM28__A 0x187009C

3189

#define IQM_AF_CMP_MEM28__W 13

3190

#define IQM_AF_CMP_MEM28__M 0x1FFF

3191

#define IQM_AF_CMP_MEM28__PRE 0x0

3192

3193

#define IQM_AF_CMP_MEM28_COEF__B 0

3194

#define IQM_AF_CMP_MEM28_COEF__W 13

3195

#define IQM_AF_CMP_MEM28_COEF__M 0x1FFF

3196

#define IQM_AF_CMP_MEM28_COEF__PRE 0x0

3197

3198

#define IQM_AF_CMP_MEM29__A 0x187009D

3199

#define IQM_AF_CMP_MEM29__W 13

3200

#define IQM_AF_CMP_MEM29__M 0x1FFF

3201

#define IQM_AF_CMP_MEM29__PRE 0x0

3202

3203

#define IQM_AF_CMP_MEM29_COEF__B 0

3204

#define IQM_AF_CMP_MEM29_COEF__W 13

3205

#define IQM_AF_CMP_MEM29_COEF__M 0x1FFF

3206

#define IQM_AF_CMP_MEM29_COEF__PRE 0x0

3207

3208

#define IQM_AF_CMP_MEM30__A 0x187009E

3209

#define IQM_AF_CMP_MEM30__W 13

3210

#define IQM_AF_CMP_MEM30__M 0x1FFF

3211

#define IQM_AF_CMP_MEM30__PRE 0x0

3212

3213

#define IQM_AF_CMP_MEM30_COEF__B 0

3214

#define IQM_AF_CMP_MEM30_COEF__W 13

3215

#define IQM_AF_CMP_MEM30_COEF__M 0x1FFF

3216

#define IQM_AF_CMP_MEM30_COEF__PRE 0x0

3217

3218

#define IQM_AF_CMP_MEM31__A 0x187009F

3219

#define IQM_AF_CMP_MEM31__W 13

3220

#define IQM_AF_CMP_MEM31__M 0x1FFF

3221

#define IQM_AF_CMP_MEM31__PRE 0x0

3222

3223

#define IQM_AF_CMP_MEM31_COEF__B 0

3224

#define IQM_AF_CMP_MEM31_COEF__W 13

3225

#define IQM_AF_CMP_MEM31_COEF__M 0x1FFF

3226

#define IQM_AF_CMP_MEM31_COEF__PRE 0x0

3227

3228

#define IQM_AF_CMP_MEM32__A 0x18700A0

3229

#define IQM_AF_CMP_MEM32__W 13

3230

#define IQM_AF_CMP_MEM32__M 0x1FFF

3231

#define IQM_AF_CMP_MEM32__PRE 0x0

3232

3233

#define IQM_AF_CMP_MEM32_COEF__B 0

3234

#define IQM_AF_CMP_MEM32_COEF__W 13

3235

#define IQM_AF_CMP_MEM32_COEF__M 0x1FFF

3236

#define IQM_AF_CMP_MEM32_COEF__PRE 0x0

3237

3238

#define IQM_AF_CMP_MEM33__A 0x18700A1

3239

#define IQM_AF_CMP_MEM33__W 13

3240

#define IQM_AF_CMP_MEM33__M 0x1FFF

3241

#define IQM_AF_CMP_MEM33__PRE 0x0

3242

3243

#define IQM_AF_CMP_MEM33_COEF__B 0

3244

#define IQM_AF_CMP_MEM33_COEF__W 13

3245

#define IQM_AF_CMP_MEM33_COEF__M 0x1FFF

3246

#define IQM_AF_CMP_MEM33_COEF__PRE 0x0

3247

3248

#define IQM_AF_CMP_MEM34__A 0x18700A2

3249

#define IQM_AF_CMP_MEM34__W 13

3250

#define IQM_AF_CMP_MEM34__M 0x1FFF

3251

#define IQM_AF_CMP_MEM34__PRE 0x0

3252

3253

#define IQM_AF_CMP_MEM34_COEF__B 0

3254

#define IQM_AF_CMP_MEM34_COEF__W 13

3255

#define IQM_AF_CMP_MEM34_COEF__M 0x1FFF

3256

#define IQM_AF_CMP_MEM34_COEF__PRE 0x0

3257

3258

#define IQM_AF_CMP_MEM35__A 0x18700A3

3259

#define IQM_AF_CMP_MEM35__W 13

3260

#define IQM_AF_CMP_MEM35__M 0x1FFF

3261

#define IQM_AF_CMP_MEM35__PRE 0x0

3262

3263

#define IQM_AF_CMP_MEM35_COEF__B 0

3264

#define IQM_AF_CMP_MEM35_COEF__W 13

3265

#define IQM_AF_CMP_MEM35_COEF__M 0x1FFF

3266

#define IQM_AF_CMP_MEM35_COEF__PRE 0x0

3267

3268

#define IQM_AF_CMP_MEM36__A 0x18700A4

3269

#define IQM_AF_CMP_MEM36__W 13

3270

#define IQM_AF_CMP_MEM36__M 0x1FFF

3271

#define IQM_AF_CMP_MEM36__PRE 0x0

3272

3273

#define IQM_AF_CMP_MEM36_COEF__B 0

3274

#define IQM_AF_CMP_MEM36_COEF__W 13

3275

#define IQM_AF_CMP_MEM36_COEF__M 0x1FFF

3276

#define IQM_AF_CMP_MEM36_COEF__PRE 0x0

3277

3278

#define IQM_AF_CMP_MEM37__A 0x18700A5

3279

#define IQM_AF_CMP_MEM37__W 13

3280

#define IQM_AF_CMP_MEM37__M 0x1FFF

3281

#define IQM_AF_CMP_MEM37__PRE 0x0

3282

3283

#define IQM_AF_CMP_MEM37_COEF__B 0

3284

#define IQM_AF_CMP_MEM37_COEF__W 13

3285

#define IQM_AF_CMP_MEM37_COEF__M 0x1FFF

3286

#define IQM_AF_CMP_MEM37_COEF__PRE 0x0

3287

3288

#define IQM_AF_CMP_MEM38__A 0x18700A6

3289

#define IQM_AF_CMP_MEM38__W 13

3290

#define IQM_AF_CMP_MEM38__M 0x1FFF

3291

#define IQM_AF_CMP_MEM38__PRE 0x0

3292

3293

#define IQM_AF_CMP_MEM38_COEF__B 0

3294

#define IQM_AF_CMP_MEM38_COEF__W 13

3295

#define IQM_AF_CMP_MEM38_COEF__M 0x1FFF

3296

#define IQM_AF_CMP_MEM38_COEF__PRE 0x0

3297

3298

#define IQM_AF_CMP_MEM39__A 0x18700A7

3299

#define IQM_AF_CMP_MEM39__W 13

3300

#define IQM_AF_CMP_MEM39__M 0x1FFF

3301

#define IQM_AF_CMP_MEM39__PRE 0x0

3302

3303

#define IQM_AF_CMP_MEM39_COEF__B 0

3304

#define IQM_AF_CMP_MEM39_COEF__W 13

3305

#define IQM_AF_CMP_MEM39_COEF__M 0x1FFF

3306

#define IQM_AF_CMP_MEM39_COEF__PRE 0x0

3307

3308

#define IQM_AF_CMP_MEM40__A 0x18700A8

3309

#define IQM_AF_CMP_MEM40__W 13

3310

#define IQM_AF_CMP_MEM40__M 0x1FFF

3311

#define IQM_AF_CMP_MEM40__PRE 0x0

3312

3313

#define IQM_AF_CMP_MEM40_COEF__B 0

3314

#define IQM_AF_CMP_MEM40_COEF__W 13

3315

#define IQM_AF_CMP_MEM40_COEF__M 0x1FFF

3316

#define IQM_AF_CMP_MEM40_COEF__PRE 0x0

3317

3318

#define IQM_AF_CMP_MEM41__A 0x18700A9

3319

#define IQM_AF_CMP_MEM41__W 13

3320

#define IQM_AF_CMP_MEM41__M 0x1FFF

3321

#define IQM_AF_CMP_MEM41__PRE 0x0

3322

3323

#define IQM_AF_CMP_MEM41_COEF__B 0

3324

#define IQM_AF_CMP_MEM41_COEF__W 13

3325

#define IQM_AF_CMP_MEM41_COEF__M 0x1FFF

3326

#define IQM_AF_CMP_MEM41_COEF__PRE 0x0

3327

3328

#define IQM_AF_CMP_MEM42__A 0x18700AA

3329

#define IQM_AF_CMP_MEM42__W 13

3330

#define IQM_AF_CMP_MEM42__M 0x1FFF

3331

#define IQM_AF_CMP_MEM42__PRE 0x0

3332

3333

#define IQM_AF_CMP_MEM42_COEF__B 0

3334

#define IQM_AF_CMP_MEM42_COEF__W 13

3335

#define IQM_AF_CMP_MEM42_COEF__M 0x1FFF

3336

#define IQM_AF_CMP_MEM42_COEF__PRE 0x0

3337

3338

#define IQM_AF_CMP_MEM43__A 0x18700AB

3339

#define IQM_AF_CMP_MEM43__W 13

3340

#define IQM_AF_CMP_MEM43__M 0x1FFF

3341

#define IQM_AF_CMP_MEM43__PRE 0x0

3342

3343

#define IQM_AF_CMP_MEM43_COEF__B 0

3344

#define IQM_AF_CMP_MEM43_COEF__W 13

3345

#define IQM_AF_CMP_MEM43_COEF__M 0x1FFF

3346

#define IQM_AF_CMP_MEM43_COEF__PRE 0x0

3347

3348

#define IQM_AF_CMP_MEM44__A 0x18700AC

3349

#define IQM_AF_CMP_MEM44__W 13

3350

#define IQM_AF_CMP_MEM44__M 0x1FFF

3351

#define IQM_AF_CMP_MEM44__PRE 0x0

3352

3353

#define IQM_AF_CMP_MEM44_COEF__B 0

3354

#define IQM_AF_CMP_MEM44_COEF__W 13

3355

#define IQM_AF_CMP_MEM44_COEF__M 0x1FFF

3356

#define IQM_AF_CMP_MEM44_COEF__PRE 0x0

3357

3358

#define IQM_AF_CMP_MEM45__A 0x18700AD

3359

#define IQM_AF_CMP_MEM45__W 13

3360

#define IQM_AF_CMP_MEM45__M 0x1FFF

3361

#define IQM_AF_CMP_MEM45__PRE 0x0

3362

3363

#define IQM_AF_CMP_MEM45_COEF__B 0

3364

#define IQM_AF_CMP_MEM45_COEF__W 13

3365

#define IQM_AF_CMP_MEM45_COEF__M 0x1FFF

3366

#define IQM_AF_CMP_MEM45_COEF__PRE 0x0

3367

3368

#define IQM_AF_CMP_MEM46__A 0x18700AE

3369

#define IQM_AF_CMP_MEM46__W 13

3370

#define IQM_AF_CMP_MEM46__M 0x1FFF

3371

#define IQM_AF_CMP_MEM46__PRE 0x0

3372

3373

#define IQM_AF_CMP_MEM46_COEF__B 0

3374

#define IQM_AF_CMP_MEM46_COEF__W 13

3375

#define IQM_AF_CMP_MEM46_COEF__M 0x1FFF

3376

#define IQM_AF_CMP_MEM46_COEF__PRE 0x0

3377

3378

#define IQM_AF_CMP_MEM47__A 0x18700AF

3379

#define IQM_AF_CMP_MEM47__W 13

3380

#define IQM_AF_CMP_MEM47__M 0x1FFF

3381

#define IQM_AF_CMP_MEM47__PRE 0x0

3382

3383

#define IQM_AF_CMP_MEM47_COEF__B 0

3384

#define IQM_AF_CMP_MEM47_COEF__W 13

3385

#define IQM_AF_CMP_MEM47_COEF__M 0x1FFF

3386

#define IQM_AF_CMP_MEM47_COEF__PRE 0x0

3387

3388

#define IQM_AF_CMP_MEM48__A 0x18700B0

3389

#define IQM_AF_CMP_MEM48__W 13

3390

#define IQM_AF_CMP_MEM48__M 0x1FFF

3391

#define IQM_AF_CMP_MEM48__PRE 0x0

3392

3393

#define IQM_AF_CMP_MEM48_COEF__B 0

3394

#define IQM_AF_CMP_MEM48_COEF__W 13

3395

#define IQM_AF_CMP_MEM48_COEF__M 0x1FFF

3396

#define IQM_AF_CMP_MEM48_COEF__PRE 0x0

3397

3398

#define IQM_AF_CMP_MEM49__A 0x18700B1

3399

#define IQM_AF_CMP_MEM49__W 13

3400

#define IQM_AF_CMP_MEM49__M 0x1FFF

3401

#define IQM_AF_CMP_MEM49__PRE 0x0

3402

3403

#define IQM_AF_CMP_MEM49_COEF__B 0

3404

#define IQM_AF_CMP_MEM49_COEF__W 13

3405

#define IQM_AF_CMP_MEM49_COEF__M 0x1FFF

3406

#define IQM_AF_CMP_MEM49_COEF__PRE 0x0

3407

3408

#define IQM_AF_CMP_MEM50__A 0x18700B2

3409

#define IQM_AF_CMP_MEM50__W 13

3410

#define IQM_AF_CMP_MEM50__M 0x1FFF

3411

#define IQM_AF_CMP_MEM50__PRE 0x0

3412

3413

#define IQM_AF_CMP_MEM50_COEF__B 0

3414

#define IQM_AF_CMP_MEM50_COEF__W 13

3415

#define IQM_AF_CMP_MEM50_COEF__M 0x1FFF

3416

#define IQM_AF_CMP_MEM50_COEF__PRE 0x0

3417

3418

#define IQM_AF_CMP_MEM51__A 0x18700B3

3419

#define IQM_AF_CMP_MEM51__W 13

3420

#define IQM_AF_CMP_MEM51__M 0x1FFF

3421

#define IQM_AF_CMP_MEM51__PRE 0x0

3422

3423

#define IQM_AF_CMP_MEM51_COEF__B 0

3424

#define IQM_AF_CMP_MEM51_COEF__W 13

3425

#define IQM_AF_CMP_MEM51_COEF__M 0x1FFF

3426

#define IQM_AF_CMP_MEM51_COEF__PRE 0x0

3427

3428

#define IQM_AF_CMP_MEM52__A 0x18700B4

3429

#define IQM_AF_CMP_MEM52__W 13

3430

#define IQM_AF_CMP_MEM52__M 0x1FFF

3431

#define IQM_AF_CMP_MEM52__PRE 0x0

3432

3433

#define IQM_AF_CMP_MEM52_COEF__B 0

3434

#define IQM_AF_CMP_MEM52_COEF__W 13

3435

#define IQM_AF_CMP_MEM52_COEF__M 0x1FFF

3436

#define IQM_AF_CMP_MEM52_COEF__PRE 0x0

3437

3438

#define IQM_AF_CMP_MEM53__A 0x18700B5

3439

#define IQM_AF_CMP_MEM53__W 13

3440

#define IQM_AF_CMP_MEM53__M 0x1FFF

3441

#define IQM_AF_CMP_MEM53__PRE 0x0

3442

3443

#define IQM_AF_CMP_MEM53_COEF__B 0

3444

#define IQM_AF_CMP_MEM53_COEF__W 13

3445

#define IQM_AF_CMP_MEM53_COEF__M 0x1FFF

3446

#define IQM_AF_CMP_MEM53_COEF__PRE 0x0

3447

3448

#define IQM_AF_CMP_MEM54__A 0x18700B6

3449

#define IQM_AF_CMP_MEM54__W 13

3450

#define IQM_AF_CMP_MEM54__M 0x1FFF

3451

#define IQM_AF_CMP_MEM54__PRE 0x0

3452

3453

#define IQM_AF_CMP_MEM54_COEF__B 0

3454

#define IQM_AF_CMP_MEM54_COEF__W 13

3455

#define IQM_AF_CMP_MEM54_COEF__M 0x1FFF

3456

#define IQM_AF_CMP_MEM54_COEF__PRE 0x0

3457

3458

#define IQM_AF_CMP_MEM55__A 0x18700B7

3459

#define IQM_AF_CMP_MEM55__W 13

3460

#define IQM_AF_CMP_MEM55__M 0x1FFF

3461

#define IQM_AF_CMP_MEM55__PRE 0x0

3462

3463

#define IQM_AF_CMP_MEM55_COEF__B 0

3464

#define IQM_AF_CMP_MEM55_COEF__W 13

3465

#define IQM_AF_CMP_MEM55_COEF__M 0x1FFF

3466

#define IQM_AF_CMP_MEM55_COEF__PRE 0x0

3467

3468

#define IQM_AF_CMP_MEM56__A 0x18700B8

3469

#define IQM_AF_CMP_MEM56__W 13

3470

#define IQM_AF_CMP_MEM56__M 0x1FFF

3471

#define IQM_AF_CMP_MEM56__PRE 0x0

3472

3473

#define IQM_AF_CMP_MEM56_COEF__B 0

3474

#define IQM_AF_CMP_MEM56_COEF__W 13

3475

#define IQM_AF_CMP_MEM56_COEF__M 0x1FFF

3476

#define IQM_AF_CMP_MEM56_COEF__PRE 0x0

3477

3478

#define IQM_AF_CMP_MEM57__A 0x18700B9

3479

#define IQM_AF_CMP_MEM57__W 13

3480

#define IQM_AF_CMP_MEM57__M 0x1FFF

3481

#define IQM_AF_CMP_MEM57__PRE 0x0

3482

3483

#define IQM_AF_CMP_MEM57_COEF__B 0

3484

#define IQM_AF_CMP_MEM57_COEF__W 13

3485

#define IQM_AF_CMP_MEM57_COEF__M 0x1FFF

3486

#define IQM_AF_CMP_MEM57_COEF__PRE 0x0

3487

3488

#define IQM_AF_CMP_MEM58__A 0x18700BA

3489

#define IQM_AF_CMP_MEM58__W 13

3490

#define IQM_AF_CMP_MEM58__M 0x1FFF

3491

#define IQM_AF_CMP_MEM58__PRE 0x0

3492

3493

#define IQM_AF_CMP_MEM58_COEF__B 0

3494

#define IQM_AF_CMP_MEM58_COEF__W 13

3495

#define IQM_AF_CMP_MEM58_COEF__M 0x1FFF

3496

#define IQM_AF_CMP_MEM58_COEF__PRE 0x0

3497

3498

#define IQM_AF_CMP_MEM59__A 0x18700BB

3499

#define IQM_AF_CMP_MEM59__W 13

3500

#define IQM_AF_CMP_MEM59__M 0x1FFF

3501

#define IQM_AF_CMP_MEM59__PRE 0x0

3502

3503

#define IQM_AF_CMP_MEM59_COEF__B 0

3504

#define IQM_AF_CMP_MEM59_COEF__W 13

3505

#define IQM_AF_CMP_MEM59_COEF__M 0x1FFF

3506

#define IQM_AF_CMP_MEM59_COEF__PRE 0x0

3507

3508

#define IQM_AF_CMP_MEM60__A 0x18700BC

3509

#define IQM_AF_CMP_MEM60__W 13

3510

#define IQM_AF_CMP_MEM60__M 0x1FFF

3511

#define IQM_AF_CMP_MEM60__PRE 0x0

3512

3513

#define IQM_AF_CMP_MEM60_COEF__B 0

3514

#define IQM_AF_CMP_MEM60_COEF__W 13

3515

#define IQM_AF_CMP_MEM60_COEF__M 0x1FFF

3516

#define IQM_AF_CMP_MEM60_COEF__PRE 0x0

3517

3518

#define IQM_AF_CMP_MEM61__A 0x18700BD

3519

#define IQM_AF_CMP_MEM61__W 13

3520

#define IQM_AF_CMP_MEM61__M 0x1FFF

3521

#define IQM_AF_CMP_MEM61__PRE 0x0

3522

3523

#define IQM_AF_CMP_MEM61_COEF__B 0

3524

#define IQM_AF_CMP_MEM61_COEF__W 13

3525

#define IQM_AF_CMP_MEM61_COEF__M 0x1FFF

3526

#define IQM_AF_CMP_MEM61_COEF__PRE 0x0

3527

3528

#define IQM_AF_CMP_MEM62__A 0x18700BE

3529

#define IQM_AF_CMP_MEM62__W 13

3530

#define IQM_AF_CMP_MEM62__M 0x1FFF

3531

#define IQM_AF_CMP_MEM62__PRE 0x0

3532

3533

#define IQM_AF_CMP_MEM62_COEF__B 0

3534

#define IQM_AF_CMP_MEM62_COEF__W 13

3535

#define IQM_AF_CMP_MEM62_COEF__M 0x1FFF

3536

#define IQM_AF_CMP_MEM62_COEF__PRE 0x0

3537

3538

#define IQM_AF_CMP_MEM63__A 0x18700BF

3539

#define IQM_AF_CMP_MEM63__W 13

3540

#define IQM_AF_CMP_MEM63__M 0x1FFF

3541

#define IQM_AF_CMP_MEM63__PRE 0x0

3542

3543

#define IQM_AF_CMP_MEM63_COEF__B 0

3544

#define IQM_AF_CMP_MEM63_COEF__W 13

3545

#define IQM_AF_CMP_MEM63_COEF__M 0x1FFF

3546

#define IQM_AF_CMP_MEM63_COEF__PRE 0x0

#define IQM_RT_RAM__A 0x1880000

3551

3552

#define IQM_RT_RAM_DLY__B 0

3553

#define IQM_RT_RAM_DLY__W 13

3554

#define IQM_RT_RAM_DLY__M 0x1FFF

3555

#define IQM_RT_RAM_DLY__PRE 0x0

#define OFDM_CE_COMM_EXEC__A 0x2C00000

3562

#define OFDM_CE_COMM_EXEC__W 3

3563

#define OFDM_CE_COMM_EXEC__M 0x7

3564

#define OFDM_CE_COMM_EXEC__PRE 0x0

3565

#define OFDM_CE_COMM_EXEC_STOP 0x0

3566

#define OFDM_CE_COMM_EXEC_ACTIVE 0x1

3567

#define OFDM_CE_COMM_EXEC_HOLD 0x2

3568

#define OFDM_CE_COMM_EXEC_STEP 0x3

3569

#define OFDM_CE_COMM_EXEC_BYPASS_STOP 0x4

3570

#define OFDM_CE_COMM_EXEC_BYPASS_HOLD 0x6

3571

3572

#define OFDM_CE_COMM_STATE__A 0x2C00001

3573

#define OFDM_CE_COMM_STATE__W 16

3574

#define OFDM_CE_COMM_STATE__M 0xFFFF

3575

#define OFDM_CE_COMM_STATE__PRE 0x0

3576

#define OFDM_CE_COMM_MB__A 0x2C00002

3577

#define OFDM_CE_COMM_MB__W 16

3578

#define OFDM_CE_COMM_MB__M 0xFFFF

3579

#define OFDM_CE_COMM_MB__PRE 0x0

3580

#define OFDM_CE_COMM_INT_REQ__A 0x2C00004

3581

#define OFDM_CE_COMM_INT_REQ__W 16

3582

#define OFDM_CE_COMM_INT_REQ__M 0xFFFF

3583

#define OFDM_CE_COMM_INT_REQ__PRE 0x0

3584

#define OFDM_CE_COMM_INT_REQ_TOP_REQ__B 2

3585

#define OFDM_CE_COMM_INT_REQ_TOP_REQ__W 1

3586

#define OFDM_CE_COMM_INT_REQ_TOP_REQ__M 0x4

3587

#define OFDM_CE_COMM_INT_REQ_TOP_REQ__PRE 0x0

3588

3589

#define OFDM_CE_COMM_INT_STA__A 0x2C00005

3590

#define OFDM_CE_COMM_INT_STA__W 16

3591

#define OFDM_CE_COMM_INT_STA__M 0xFFFF

3592

#define OFDM_CE_COMM_INT_STA__PRE 0x0

3593

#define OFDM_CE_COMM_INT_MSK__A 0x2C00006

3594

#define OFDM_CE_COMM_INT_MSK__W 16

3595

#define OFDM_CE_COMM_INT_MSK__M 0xFFFF

3596

#define OFDM_CE_COMM_INT_MSK__PRE 0x0

3597

#define OFDM_CE_COMM_INT_STM__A 0x2C00007

3598

#define OFDM_CE_COMM_INT_STM__W 16

3599

#define OFDM_CE_COMM_INT_STM__M 0xFFFF

3600

#define OFDM_CE_COMM_INT_STM__PRE 0x0

3601

#define OFDM_CE_COMM_INT_STM_INT_MSK__B 0

3602

#define OFDM_CE_COMM_INT_STM_INT_MSK__W 16

3603

#define OFDM_CE_COMM_INT_STM_INT_MSK__M 0xFFFF

3604

#define OFDM_CE_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_CE_TOP_COMM_EXEC__A 0x2C10000

3609

#define OFDM_CE_TOP_COMM_EXEC__W 3

3610

#define OFDM_CE_TOP_COMM_EXEC__M 0x7

3611

#define OFDM_CE_TOP_COMM_EXEC__PRE 0x0

3612

#define OFDM_CE_TOP_COMM_EXEC_STOP 0x0

3613

#define OFDM_CE_TOP_COMM_EXEC_ACTIVE 0x1

3614

#define OFDM_CE_TOP_COMM_EXEC_HOLD 0x2

3615

#define OFDM_CE_TOP_COMM_EXEC_STEP 0x3

3616

3617

#define OFDM_CE_TOP_COMM_MB__A 0x2C10002

3618

#define OFDM_CE_TOP_COMM_MB__W 4

3619

#define OFDM_CE_TOP_COMM_MB__M 0xF

3620

#define OFDM_CE_TOP_COMM_MB__PRE 0x0

3621

#define OFDM_CE_TOP_COMM_MB_CTL__B 0

3622

#define OFDM_CE_TOP_COMM_MB_CTL__W 1

3623

#define OFDM_CE_TOP_COMM_MB_CTL__M 0x1

3624

#define OFDM_CE_TOP_COMM_MB_CTL__PRE 0x0

3625

#define OFDM_CE_TOP_COMM_MB_CTL_OFF 0x0

3626

#define OFDM_CE_TOP_COMM_MB_CTL_ON 0x1

3627

#define OFDM_CE_TOP_COMM_MB_OBS__B 1

3628

#define OFDM_CE_TOP_COMM_MB_OBS__W 1

3629

#define OFDM_CE_TOP_COMM_MB_OBS__M 0x2

3630

#define OFDM_CE_TOP_COMM_MB_OBS__PRE 0x0

3631

#define OFDM_CE_TOP_COMM_MB_OBS_OFF 0x0

3632

#define OFDM_CE_TOP_COMM_MB_OBS_ON 0x2

3633

#define OFDM_CE_TOP_COMM_MB_OBS_SEL__B 2

3634

#define OFDM_CE_TOP_COMM_MB_OBS_SEL__W 2

3635

#define OFDM_CE_TOP_COMM_MB_OBS_SEL__M 0xC

3636

#define OFDM_CE_TOP_COMM_MB_OBS_SEL__PRE 0x0

3637

#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FI 0x0

3638

#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TP 0x4

3639

#define OFDM_CE_TOP_COMM_MB_OBS_SEL_TI 0x8

3640

#define OFDM_CE_TOP_COMM_MB_OBS_SEL_FR 0xC

3641

3642

#define OFDM_CE_TOP_COMM_INT_REQ__A 0x2C10004

3643

#define OFDM_CE_TOP_COMM_INT_REQ__W 1

3644

#define OFDM_CE_TOP_COMM_INT_REQ__M 0x1

3645

#define OFDM_CE_TOP_COMM_INT_REQ__PRE 0x0

3646

#define OFDM_CE_TOP_COMM_INT_STA__A 0x2C10005

3647

#define OFDM_CE_TOP_COMM_INT_STA__W 3

3648

#define OFDM_CE_TOP_COMM_INT_STA__M 0x7

3649

#define OFDM_CE_TOP_COMM_INT_STA__PRE 0x0

3650

#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__B 0

3651

#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__W 1

3652

#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__M 0x1

3653

#define OFDM_CE_TOP_COMM_INT_STA_CE_PE__PRE 0x0

3654

#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__B 1

3655

#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__W 1

3656

#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__M 0x2

3657

#define OFDM_CE_TOP_COMM_INT_STA_CE_IR__PRE 0x0

3658

#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__B 2

3659

#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__W 1

3660

#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__M 0x4

3661

#define OFDM_CE_TOP_COMM_INT_STA_CE_FI__PRE 0x0

3662

3663

#define OFDM_CE_TOP_COMM_INT_MSK__A 0x2C10006

3664

#define OFDM_CE_TOP_COMM_INT_MSK__W 3

3665

#define OFDM_CE_TOP_COMM_INT_MSK__M 0x7

3666

#define OFDM_CE_TOP_COMM_INT_MSK__PRE 0x0

3667

#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__B 0

3668

#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__W 1

3669

#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__M 0x1

3670

#define OFDM_CE_TOP_COMM_INT_MSK_CE_PE__PRE 0x0

3671

#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__B 1

3672

#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__W 1

3673

#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__M 0x2

3674

#define OFDM_CE_TOP_COMM_INT_MSK_CE_IR__PRE 0x0

3675

#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__B 2

3676

#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__W 1

3677

#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__M 0x4

3678

#define OFDM_CE_TOP_COMM_INT_MSK_CE_FI__PRE 0x0

3679

3680

#define OFDM_CE_TOP_COMM_INT_STM__A 0x2C10007

3681

#define OFDM_CE_TOP_COMM_INT_STM__W 3

3682

#define OFDM_CE_TOP_COMM_INT_STM__M 0x7

3683

#define OFDM_CE_TOP_COMM_INT_STM__PRE 0x0

3684

#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__B 0

3685

#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__W 1

3686

#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__M 0x1

3687

#define OFDM_CE_TOP_COMM_INT_STM_CE_PE__PRE 0x0

3688

#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__B 1

3689

#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__W 1

3690

#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__M 0x2

3691

#define OFDM_CE_TOP_COMM_INT_STM_CE_IR__PRE 0x0

3692

#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__B 2

3693

#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__W 1

3694

#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__M 0x4

3695

#define OFDM_CE_TOP_COMM_INT_STM_CE_FI__PRE 0x0

3696

3697

3698

#define OFDM_CE_TOP_MODE_2K__A 0x2C10010

3699

#define OFDM_CE_TOP_MODE_2K__W 1

3700

#define OFDM_CE_TOP_MODE_2K__M 0x1

3701

#define OFDM_CE_TOP_MODE_2K__PRE 0x0

3702

3703

#define OFDM_CE_TOP_TAPSET__A 0x2C10011

3704

#define OFDM_CE_TOP_TAPSET__W 4

3705

#define OFDM_CE_TOP_TAPSET__M 0xF

3706

#define OFDM_CE_TOP_TAPSET__PRE 0x1

3707

#define OFDM_CE_TOP_AVG_POW__A 0x2C10012

3708

#define OFDM_CE_TOP_AVG_POW__W 8

3709

#define OFDM_CE_TOP_AVG_POW__M 0xFF

3710

#define OFDM_CE_TOP_AVG_POW__PRE 0x65

3711

#define OFDM_CE_TOP_MAX_POW__A 0x2C10013

3712

#define OFDM_CE_TOP_MAX_POW__W 8

3713

#define OFDM_CE_TOP_MAX_POW__M 0xFF

3714

#define OFDM_CE_TOP_MAX_POW__PRE 0x80

3715

#define OFDM_CE_TOP_ATT__A 0x2C10014

3716

#define OFDM_CE_TOP_ATT__W 8

3717

#define OFDM_CE_TOP_ATT__M 0xFF

3718

#define OFDM_CE_TOP_ATT__PRE 0x70

3719

#define OFDM_CE_TOP_NRED__A 0x2C10015

3720

#define OFDM_CE_TOP_NRED__W 6

3721

#define OFDM_CE_TOP_NRED__M 0x3F

3722

#define OFDM_CE_TOP_NRED__PRE 0x9

3723

3724

#define OFDM_CE_TOP_PU_SIGN__A 0x2C10020

3725

#define OFDM_CE_TOP_PU_SIGN__W 1

3726

#define OFDM_CE_TOP_PU_SIGN__M 0x1

3727

#define OFDM_CE_TOP_PU_SIGN__PRE 0x0

3728

3729

#define OFDM_CE_TOP_PU_MIX__A 0x2C10021

3730

#define OFDM_CE_TOP_PU_MIX__W 1

3731

#define OFDM_CE_TOP_PU_MIX__M 0x1

3732

#define OFDM_CE_TOP_PU_MIX__PRE 0x0

3733

#define OFDM_CE_TOP_PB_PILOT_REQ__A 0x2C10030

3734

#define OFDM_CE_TOP_PB_PILOT_REQ__W 15

3735

#define OFDM_CE_TOP_PB_PILOT_REQ__M 0x7FFF

3736

#define OFDM_CE_TOP_PB_PILOT_REQ__PRE 0x0

3737

#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__B 12

3738

#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__W 3

3739

#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000

3740

#define OFDM_CE_TOP_PB_PILOT_REQ_BUFFER_INDEX__PRE 0x0

3741

#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__B 0

3742

#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__W 12

3743

#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__M 0xFFF

3744

#define OFDM_CE_TOP_PB_PILOT_REQ_PILOT_ADR__PRE 0x0

3745

3746

3747

#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__A 0x2C10031

3748

#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__W 1

3749

#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__M 0x1

3750

#define OFDM_CE_TOP_PB_PILOT_REQ_VALID__PRE 0x0

3751

3752

#define OFDM_CE_TOP_PB_FREEZE__A 0x2C10032

3753

#define OFDM_CE_TOP_PB_FREEZE__W 1

3754

#define OFDM_CE_TOP_PB_FREEZE__M 0x1

3755

#define OFDM_CE_TOP_PB_FREEZE__PRE 0x0

3756

3757

#define OFDM_CE_TOP_PB_PILOT_EXP__A 0x2C10038

3758

#define OFDM_CE_TOP_PB_PILOT_EXP__W 4

3759

#define OFDM_CE_TOP_PB_PILOT_EXP__M 0xF

3760

#define OFDM_CE_TOP_PB_PILOT_EXP__PRE 0x0

3761

3762

#define OFDM_CE_TOP_PB_PILOT_REAL__A 0x2C10039

3763

#define OFDM_CE_TOP_PB_PILOT_REAL__W 10

3764

#define OFDM_CE_TOP_PB_PILOT_REAL__M 0x3FF

3765

#define OFDM_CE_TOP_PB_PILOT_REAL__PRE 0x0

3766

3767

#define OFDM_CE_TOP_PB_PILOT_IMAG__A 0x2C1003A

3768

#define OFDM_CE_TOP_PB_PILOT_IMAG__W 10

3769

#define OFDM_CE_TOP_PB_PILOT_IMAG__M 0x3FF

3770

#define OFDM_CE_TOP_PB_PILOT_IMAG__PRE 0x0

3771

3772

#define OFDM_CE_TOP_PB_SMBNR__A 0x2C1003B

3773

#define OFDM_CE_TOP_PB_SMBNR__W 5

3774

#define OFDM_CE_TOP_PB_SMBNR__M 0x1F

3775

#define OFDM_CE_TOP_PB_SMBNR__PRE 0x0

3776

3777

#define OFDM_CE_TOP_NE_PILOT_REQ__A 0x2C10040

3778

#define OFDM_CE_TOP_NE_PILOT_REQ__W 12

3779

#define OFDM_CE_TOP_NE_PILOT_REQ__M 0xFFF

3780

#define OFDM_CE_TOP_NE_PILOT_REQ__PRE 0x0

3781

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__A 0x2C10041

3782

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__W 2

3783

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__M 0x3

3784

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID__PRE 0x0

3785

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__B 1

3786

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__W 1

3787

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2

3788

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_WRITE_VALID__PRE 0x0

3789

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__B 0

3790

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__W 1

3791

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__M 0x1

3792

#define OFDM_CE_TOP_NE_PILOT_REQ_VALID_READ_VALID__PRE 0x0

3793

3794

3795

#define OFDM_CE_TOP_NE_PILOT_DATA__A 0x2C10042

3796

#define OFDM_CE_TOP_NE_PILOT_DATA__W 10

3797

#define OFDM_CE_TOP_NE_PILOT_DATA__M 0x3FF

3798

#define OFDM_CE_TOP_NE_PILOT_DATA__PRE 0x0

3799

#define OFDM_CE_TOP_NE_ERR_SELECT__A 0x2C10043

3800

#define OFDM_CE_TOP_NE_ERR_SELECT__W 5

3801

#define OFDM_CE_TOP_NE_ERR_SELECT__M 0x1F

3802

#define OFDM_CE_TOP_NE_ERR_SELECT__PRE 0x7

3803

3804

#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__B 4

3805

#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__W 1

3806

#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__M 0x10

3807

#define OFDM_CE_TOP_NE_ERR_SELECT_MAX_UPD__PRE 0x0

3808

3809

#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__B 3

3810

#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__W 1

3811

#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__M 0x8

3812

#define OFDM_CE_TOP_NE_ERR_SELECT_MED_MATCH__PRE 0x0

3813

3814

#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__B 2

3815

#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__W 1

3816

#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__M 0x4

3817

#define OFDM_CE_TOP_NE_ERR_SELECT_RESET_RAM__PRE 0x4

3818

3819

#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__B 1

3820

#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__W 1

3821

#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__M 0x2

3822

#define OFDM_CE_TOP_NE_ERR_SELECT_FD_ENABLE__PRE 0x2

3823

3824

#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__B 0

3825

#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__W 1

3826

#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__M 0x1

3827

#define OFDM_CE_TOP_NE_ERR_SELECT_TD_ENABLE__PRE 0x1

3828

3829

3830

#define OFDM_CE_TOP_NE_TD_CAL__A 0x2C10044

3831

#define OFDM_CE_TOP_NE_TD_CAL__W 9

3832

#define OFDM_CE_TOP_NE_TD_CAL__M 0x1FF

3833

#define OFDM_CE_TOP_NE_TD_CAL__PRE 0x1E8

3834

3835

#define OFDM_CE_TOP_NE_FD_CAL__A 0x2C10045

3836

#define OFDM_CE_TOP_NE_FD_CAL__W 9

3837

#define OFDM_CE_TOP_NE_FD_CAL__M 0x1FF

3838

#define OFDM_CE_TOP_NE_FD_CAL__PRE 0x1D9

3839

3840

#define OFDM_CE_TOP_NE_MIXAVG__A 0x2C10046

3841

#define OFDM_CE_TOP_NE_MIXAVG__W 3

3842

#define OFDM_CE_TOP_NE_MIXAVG__M 0x7

3843

#define OFDM_CE_TOP_NE_MIXAVG__PRE 0x6

3844

3845

#define OFDM_CE_TOP_NE_NUPD_OFS__A 0x2C10047

3846

#define OFDM_CE_TOP_NE_NUPD_OFS__W 4

3847

#define OFDM_CE_TOP_NE_NUPD_OFS__M 0xF

3848

#define OFDM_CE_TOP_NE_NUPD_OFS__PRE 0x4

3849

#define OFDM_CE_TOP_NE_TD_POW__A 0x2C10048

3850

#define OFDM_CE_TOP_NE_TD_POW__W 15

3851

#define OFDM_CE_TOP_NE_TD_POW__M 0x7FFF

3852

#define OFDM_CE_TOP_NE_TD_POW__PRE 0x0

3853

3854

#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__B 10

3855

#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__W 5

3856

#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__M 0x7C00

3857

#define OFDM_CE_TOP_NE_TD_POW_EXPONENT__PRE 0x0

3858

3859

#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__B 0

3860

#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__W 10

3861

#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__M 0x3FF

3862

#define OFDM_CE_TOP_NE_TD_POW_MANTISSA__PRE 0x0

3863

3864

#define OFDM_CE_TOP_NE_FD_POW__A 0x2C10049

3865

#define OFDM_CE_TOP_NE_FD_POW__W 15

3866

#define OFDM_CE_TOP_NE_FD_POW__M 0x7FFF

3867

#define OFDM_CE_TOP_NE_FD_POW__PRE 0x0

3868

3869

#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__B 10

3870

#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__W 5

3871

#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__M 0x7C00

3872

#define OFDM_CE_TOP_NE_FD_POW_EXPONENT__PRE 0x0

3873

3874

#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__B 0

3875

#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__W 10

3876

#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__M 0x3FF

3877

#define OFDM_CE_TOP_NE_FD_POW_MANTISSA__PRE 0x0

3878

3879

3880

#define OFDM_CE_TOP_NE_NEXP_AVG__A 0x2C1004A

3881

#define OFDM_CE_TOP_NE_NEXP_AVG__W 8

3882

#define OFDM_CE_TOP_NE_NEXP_AVG__M 0xFF

3883

#define OFDM_CE_TOP_NE_NEXP_AVG__PRE 0x0

3884

3885

#define OFDM_CE_TOP_NE_OFFSET__A 0x2C1004B

3886

#define OFDM_CE_TOP_NE_OFFSET__W 9

3887

#define OFDM_CE_TOP_NE_OFFSET__M 0x1FF

3888

#define OFDM_CE_TOP_NE_OFFSET__PRE 0x0

3889

3890

#define OFDM_CE_TOP_NE_NUPD_TRH__A 0x2C1004C

3891

#define OFDM_CE_TOP_NE_NUPD_TRH__W 5

3892

#define OFDM_CE_TOP_NE_NUPD_TRH__M 0x1F

3893

#define OFDM_CE_TOP_NE_NUPD_TRH__PRE 0x14

3894

3895

#define OFDM_CE_TOP_PE_NEXP_OFFS__A 0x2C10050

3896

#define OFDM_CE_TOP_PE_NEXP_OFFS__W 8

3897

#define OFDM_CE_TOP_PE_NEXP_OFFS__M 0xFF

3898

#define OFDM_CE_TOP_PE_NEXP_OFFS__PRE 0x0

3899

3900

#define OFDM_CE_TOP_PE_TIMESHIFT__A 0x2C10051

3901

#define OFDM_CE_TOP_PE_TIMESHIFT__W 14

3902

#define OFDM_CE_TOP_PE_TIMESHIFT__M 0x3FFF

3903

#define OFDM_CE_TOP_PE_TIMESHIFT__PRE 0x0

3904

3905

#define OFDM_CE_TOP_PE_DIF_REAL_L__A 0x2C10052

3906

#define OFDM_CE_TOP_PE_DIF_REAL_L__W 16

3907

#define OFDM_CE_TOP_PE_DIF_REAL_L__M 0xFFFF

3908

#define OFDM_CE_TOP_PE_DIF_REAL_L__PRE 0x0

3909

3910

#define OFDM_CE_TOP_PE_DIF_IMAG_L__A 0x2C10053

3911

#define OFDM_CE_TOP_PE_DIF_IMAG_L__W 16

3912

#define OFDM_CE_TOP_PE_DIF_IMAG_L__M 0xFFFF

3913

#define OFDM_CE_TOP_PE_DIF_IMAG_L__PRE 0x0

3914

3915

#define OFDM_CE_TOP_PE_DIF_REAL_R__A 0x2C10054

3916

#define OFDM_CE_TOP_PE_DIF_REAL_R__W 16

3917

#define OFDM_CE_TOP_PE_DIF_REAL_R__M 0xFFFF

3918

#define OFDM_CE_TOP_PE_DIF_REAL_R__PRE 0x0

3919

3920

#define OFDM_CE_TOP_PE_DIF_IMAG_R__A 0x2C10055

3921

#define OFDM_CE_TOP_PE_DIF_IMAG_R__W 16

3922

#define OFDM_CE_TOP_PE_DIF_IMAG_R__M 0xFFFF

3923

#define OFDM_CE_TOP_PE_DIF_IMAG_R__PRE 0x0

3924

3925

#define OFDM_CE_TOP_PE_ABS_REAL_L__A 0x2C10056

3926

#define OFDM_CE_TOP_PE_ABS_REAL_L__W 16

3927

#define OFDM_CE_TOP_PE_ABS_REAL_L__M 0xFFFF

3928

#define OFDM_CE_TOP_PE_ABS_REAL_L__PRE 0x0

3929

3930

#define OFDM_CE_TOP_PE_ABS_IMAG_L__A 0x2C10057

3931

#define OFDM_CE_TOP_PE_ABS_IMAG_L__W 16

3932

#define OFDM_CE_TOP_PE_ABS_IMAG_L__M 0xFFFF

3933

#define OFDM_CE_TOP_PE_ABS_IMAG_L__PRE 0x0

3934

3935

#define OFDM_CE_TOP_PE_ABS_REAL_R__A 0x2C10058

3936

#define OFDM_CE_TOP_PE_ABS_REAL_R__W 16

3937

#define OFDM_CE_TOP_PE_ABS_REAL_R__M 0xFFFF

3938

#define OFDM_CE_TOP_PE_ABS_REAL_R__PRE 0x0

3939

3940

#define OFDM_CE_TOP_PE_ABS_IMAG_R__A 0x2C10059

3941

#define OFDM_CE_TOP_PE_ABS_IMAG_R__W 16

3942

#define OFDM_CE_TOP_PE_ABS_IMAG_R__M 0xFFFF

3943

#define OFDM_CE_TOP_PE_ABS_IMAG_R__PRE 0x0

3944

3945

#define OFDM_CE_TOP_PE_ABS_EXP_L__A 0x2C1005A

3946

#define OFDM_CE_TOP_PE_ABS_EXP_L__W 5

3947

#define OFDM_CE_TOP_PE_ABS_EXP_L__M 0x1F

3948

#define OFDM_CE_TOP_PE_ABS_EXP_L__PRE 0x0

3949

3950

#define OFDM_CE_TOP_PE_ABS_EXP_R__A 0x2C1005B

3951

#define OFDM_CE_TOP_PE_ABS_EXP_R__W 5

3952

#define OFDM_CE_TOP_PE_ABS_EXP_R__M 0x1F

3953

#define OFDM_CE_TOP_PE_ABS_EXP_R__PRE 0x0

3954

3955

#define OFDM_CE_TOP_TP_UPDATE_MODE__A 0x2C10060

3956

#define OFDM_CE_TOP_TP_UPDATE_MODE__W 1

3957

#define OFDM_CE_TOP_TP_UPDATE_MODE__M 0x1

3958

#define OFDM_CE_TOP_TP_UPDATE_MODE__PRE 0x0

3959

3960

#define OFDM_CE_TOP_TP_LMS_TAP_ON__A 0x2C10061

3961

#define OFDM_CE_TOP_TP_LMS_TAP_ON__W 1

3962

#define OFDM_CE_TOP_TP_LMS_TAP_ON__M 0x1

3963

#define OFDM_CE_TOP_TP_LMS_TAP_ON__PRE 0x0

3964

3965

#define OFDM_CE_TOP_TP_A0_TAP_NEW__A 0x2C10064

3966

#define OFDM_CE_TOP_TP_A0_TAP_NEW__W 10

3967

#define OFDM_CE_TOP_TP_A0_TAP_NEW__M 0x3FF

3968

#define OFDM_CE_TOP_TP_A0_TAP_NEW__PRE 0x100

3969

3970

#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__A 0x2C10065

3971

#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__W 1

3972

#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__M 0x1

3973

#define OFDM_CE_TOP_TP_A0_TAP_NEW_VALID__PRE 0x0

3974

3975

#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__A 0x2C10066

3976

#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__W 5

3977

#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__M 0x1F

3978

#define OFDM_CE_TOP_TP_A0_MU_LMS_STEP__PRE 0xE

3979

3980

#define OFDM_CE_TOP_TP_A0_TAP_CURR__A 0x2C10067

3981

#define OFDM_CE_TOP_TP_A0_TAP_CURR__W 10

3982

#define OFDM_CE_TOP_TP_A0_TAP_CURR__M 0x3FF

3983

#define OFDM_CE_TOP_TP_A0_TAP_CURR__PRE 0x0

3984

3985

#define OFDM_CE_TOP_TP_A1_TAP_NEW__A 0x2C10068

3986

#define OFDM_CE_TOP_TP_A1_TAP_NEW__W 10

3987

#define OFDM_CE_TOP_TP_A1_TAP_NEW__M 0x3FF

3988

#define OFDM_CE_TOP_TP_A1_TAP_NEW__PRE 0x0

3989

3990

#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__A 0x2C10069

3991

#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__W 1

3992

#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__M 0x1

3993

#define OFDM_CE_TOP_TP_A1_TAP_NEW_VALID__PRE 0x0

3994

3995

#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__A 0x2C1006A

3996

#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__W 5

3997

#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__M 0x1F

3998

#define OFDM_CE_TOP_TP_A1_MU_LMS_STEP__PRE 0xA

3999

4000

#define OFDM_CE_TOP_TP_A1_TAP_CURR__A 0x2C1006B

4001

#define OFDM_CE_TOP_TP_A1_TAP_CURR__W 10

4002

#define OFDM_CE_TOP_TP_A1_TAP_CURR__M 0x3FF

4003

#define OFDM_CE_TOP_TP_A1_TAP_CURR__PRE 0x0

4004

#define OFDM_CE_TOP_TP_DOPP_ENERGY__A 0x2C1006C

4005

#define OFDM_CE_TOP_TP_DOPP_ENERGY__W 15

4006

#define OFDM_CE_TOP_TP_DOPP_ENERGY__M 0x7FFF

4007

#define OFDM_CE_TOP_TP_DOPP_ENERGY__PRE 0x0

4008

4009

#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__B 10

4010

#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__W 5

4011

#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__M 0x7C00

4012

#define OFDM_CE_TOP_TP_DOPP_ENERGY_EXPONENT__PRE 0x0

4013

4014

#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__B 0

4015

#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__W 10

4016

#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__M 0x3FF

4017

#define OFDM_CE_TOP_TP_DOPP_ENERGY_MANTISSA__PRE 0x0

4018

4019

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__A 0x2C1006D

4020

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__W 15

4021

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__M 0x7FFF

4022

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY__PRE 0x0

4023

4024

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10

4025

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5

4026

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00

4027

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_EXPONENT__PRE 0x0

4028

4029

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0

4030

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10

4031

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF

4032

#define OFDM_CE_TOP_TP_DOPP_DIFF_ENERGY_MANTISSA__PRE 0x0

4033

4034

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__A 0x2C1006E

4035

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__W 15

4036

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__M 0x7FFF

4037

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY__PRE 0x0

4038

4039

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__B 10

4040

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__W 5

4041

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00

4042

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_EXPONENT__PRE 0x0

4043

4044

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__B 0

4045

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__W 10

4046

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF

4047

#define OFDM_CE_TOP_TP_A0_TAP_ENERGY_MANTISSA__PRE 0x0

4048

4049

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__A 0x2C1006F

4050

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__W 15

4051

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__M 0x7FFF

4052

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY__PRE 0x0

4053

4054

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__B 10

4055

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__W 5

4056

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00

4057

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_EXPONENT__PRE 0x0

4058

4059

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__B 0

4060

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__W 10

4061

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF

4062

#define OFDM_CE_TOP_TP_A1_TAP_ENERGY_MANTISSA__PRE 0x0

4063

4064

4065

#define OFDM_CE_TOP_TI_SYM_CNT__A 0x2C10072

4066

#define OFDM_CE_TOP_TI_SYM_CNT__W 6

4067

#define OFDM_CE_TOP_TI_SYM_CNT__M 0x3F

4068

#define OFDM_CE_TOP_TI_SYM_CNT__PRE 0x20

4069

4070

#define OFDM_CE_TOP_TI_PHN_ENABLE__A 0x2C10073

4071

#define OFDM_CE_TOP_TI_PHN_ENABLE__W 1

4072

#define OFDM_CE_TOP_TI_PHN_ENABLE__M 0x1

4073

#define OFDM_CE_TOP_TI_PHN_ENABLE__PRE 0x1

4074

4075

#define OFDM_CE_TOP_TI_SHIFT__A 0x2C10074

4076

#define OFDM_CE_TOP_TI_SHIFT__W 2

4077

#define OFDM_CE_TOP_TI_SHIFT__M 0x3

4078

#define OFDM_CE_TOP_TI_SHIFT__PRE 0x0

4079

4080

#define OFDM_CE_TOP_TI_SLOW__A 0x2C10075

4081

#define OFDM_CE_TOP_TI_SLOW__W 1

4082

#define OFDM_CE_TOP_TI_SLOW__M 0x1

4083

#define OFDM_CE_TOP_TI_SLOW__PRE 0x1

4084

4085

#define OFDM_CE_TOP_TI_MGAIN__A 0x2C10076

4086

#define OFDM_CE_TOP_TI_MGAIN__W 8

4087

#define OFDM_CE_TOP_TI_MGAIN__M 0xFF

4088

#define OFDM_CE_TOP_TI_MGAIN__PRE 0x0

4089

4090

#define OFDM_CE_TOP_TI_ACCU1__A 0x2C10077

4091

#define OFDM_CE_TOP_TI_ACCU1__W 8

4092

#define OFDM_CE_TOP_TI_ACCU1__M 0xFF

4093

#define OFDM_CE_TOP_TI_ACCU1__PRE 0x0

4094

4095

#define OFDM_CE_TOP_NI_PER_LEFT__A 0x2C100B0

4096

#define OFDM_CE_TOP_NI_PER_LEFT__W 5

4097

#define OFDM_CE_TOP_NI_PER_LEFT__M 0x1F

4098

#define OFDM_CE_TOP_NI_PER_LEFT__PRE 0xE

4099

4100

#define OFDM_CE_TOP_NI_PER_RIGHT__A 0x2C100B1

4101

#define OFDM_CE_TOP_NI_PER_RIGHT__W 5

4102

#define OFDM_CE_TOP_NI_PER_RIGHT__M 0x1F

4103

#define OFDM_CE_TOP_NI_PER_RIGHT__PRE 0x7

4104

4105

#define OFDM_CE_TOP_NI_POS_LR__A 0x2C100B2

4106

#define OFDM_CE_TOP_NI_POS_LR__W 9

4107

#define OFDM_CE_TOP_NI_POS_LR__M 0x1FF

4108

#define OFDM_CE_TOP_NI_POS_LR__PRE 0xA0

4109

4110

#define OFDM_CE_TOP_FI_SHT_INCR__A 0x2C10090

4111

#define OFDM_CE_TOP_FI_SHT_INCR__W 9

4112

#define OFDM_CE_TOP_FI_SHT_INCR__M 0x1FF

4113

#define OFDM_CE_TOP_FI_SHT_INCR__PRE 0x1E

4114

4115

#define OFDM_CE_TOP_FI_EXP_NORM__A 0x2C10091

4116

#define OFDM_CE_TOP_FI_EXP_NORM__W 4

4117

#define OFDM_CE_TOP_FI_EXP_NORM__M 0xF

4118

#define OFDM_CE_TOP_FI_EXP_NORM__PRE 0xC

4119

4120

#define OFDM_CE_TOP_FI_SUPR_VAL__A 0x2C10092

4121

#define OFDM_CE_TOP_FI_SUPR_VAL__W 1

4122

#define OFDM_CE_TOP_FI_SUPR_VAL__M 0x1

4123

#define OFDM_CE_TOP_FI_SUPR_VAL__PRE 0x0

4124

4125

#define OFDM_CE_TOP_IR_INPUTSEL__A 0x2C100A0

4126

#define OFDM_CE_TOP_IR_INPUTSEL__W 1

4127

#define OFDM_CE_TOP_IR_INPUTSEL__M 0x1

4128

#define OFDM_CE_TOP_IR_INPUTSEL__PRE 0x0

4129

4130

#define OFDM_CE_TOP_IR_STARTPOS__A 0x2C100A1

4131

#define OFDM_CE_TOP_IR_STARTPOS__W 8

4132

#define OFDM_CE_TOP_IR_STARTPOS__M 0xFF

4133

#define OFDM_CE_TOP_IR_STARTPOS__PRE 0x0

4134

4135

#define OFDM_CE_TOP_IR_NEXP_THRES__A 0x2C100A2

4136

#define OFDM_CE_TOP_IR_NEXP_THRES__W 8

4137

#define OFDM_CE_TOP_IR_NEXP_THRES__M 0xFF

4138

#define OFDM_CE_TOP_IR_NEXP_THRES__PRE 0xFF

4139

4140

#define OFDM_CE_TOP_IR_LENGTH__A 0x2C100A3

4141

#define OFDM_CE_TOP_IR_LENGTH__W 4

4142

#define OFDM_CE_TOP_IR_LENGTH__M 0xF

4143

#define OFDM_CE_TOP_IR_LENGTH__PRE 0x9

4144

4145

#define OFDM_CE_TOP_IR_FREQ__A 0x2C100A4

4146

#define OFDM_CE_TOP_IR_FREQ__W 11

4147

#define OFDM_CE_TOP_IR_FREQ__M 0x7FF

4148

#define OFDM_CE_TOP_IR_FREQ__PRE 0x0

4149

4150

#define OFDM_CE_TOP_IR_FREQINC__A 0x2C100A5

4151

#define OFDM_CE_TOP_IR_FREQINC__W 11

4152

#define OFDM_CE_TOP_IR_FREQINC__M 0x7FF

4153

#define OFDM_CE_TOP_IR_FREQINC__PRE 0x4

4154

4155

#define OFDM_CE_TOP_IR_KAISINC__A 0x2C100A6

4156

#define OFDM_CE_TOP_IR_KAISINC__W 15

4157

#define OFDM_CE_TOP_IR_KAISINC__M 0x7FFF

4158

#define OFDM_CE_TOP_IR_KAISINC__PRE 0x100

4159

4160

#define OFDM_CE_TOP_IR_CTL__A 0x2C100A7

4161

#define OFDM_CE_TOP_IR_CTL__W 3

4162

#define OFDM_CE_TOP_IR_CTL__M 0x7

4163

#define OFDM_CE_TOP_IR_CTL__PRE 0x0

4164

4165

#define OFDM_CE_TOP_IR_REAL__A 0x2C100A8

4166

#define OFDM_CE_TOP_IR_REAL__W 16

4167

#define OFDM_CE_TOP_IR_REAL__M 0xFFFF

4168

#define OFDM_CE_TOP_IR_REAL__PRE 0x0

4169

4170

#define OFDM_CE_TOP_IR_IMAG__A 0x2C100A9

4171

#define OFDM_CE_TOP_IR_IMAG__W 16

4172

#define OFDM_CE_TOP_IR_IMAG__M 0xFFFF

4173

#define OFDM_CE_TOP_IR_IMAG__PRE 0x0

4174

4175

#define OFDM_CE_TOP_IR_INDEX__A 0x2C100AA

4176

#define OFDM_CE_TOP_IR_INDEX__W 12

4177

#define OFDM_CE_TOP_IR_INDEX__M 0xFFF

4178

#define OFDM_CE_TOP_IR_INDEX__PRE 0x0

#define OFDM_CE_FR_COMM_EXEC__A 0x2C20000

4183

#define OFDM_CE_FR_COMM_EXEC__W 3

4184

#define OFDM_CE_FR_COMM_EXEC__M 0x7

4185

#define OFDM_CE_FR_COMM_EXEC__PRE 0x0

4186

#define OFDM_CE_FR_COMM_EXEC_STOP 0x0

4187

#define OFDM_CE_FR_COMM_EXEC_ACTIVE 0x1

4188

#define OFDM_CE_FR_COMM_EXEC_HOLD 0x2

4189

#define OFDM_CE_FR_COMM_EXEC_STEP 0x3

4190

4191

4192

#define OFDM_CE_FR_TREAL00__A 0x2C20010

4193

#define OFDM_CE_FR_TREAL00__W 11

4194

#define OFDM_CE_FR_TREAL00__M 0x7FF

4195

#define OFDM_CE_FR_TREAL00__PRE 0x52

4196

4197

#define OFDM_CE_FR_TIMAG00__A 0x2C20011

4198

#define OFDM_CE_FR_TIMAG00__W 11

4199

#define OFDM_CE_FR_TIMAG00__M 0x7FF

4200

#define OFDM_CE_FR_TIMAG00__PRE 0x0

4201

4202

#define OFDM_CE_FR_TREAL01__A 0x2C20012

4203

#define OFDM_CE_FR_TREAL01__W 11

4204

#define OFDM_CE_FR_TREAL01__M 0x7FF

4205

#define OFDM_CE_FR_TREAL01__PRE 0x52

4206

4207

#define OFDM_CE_FR_TIMAG01__A 0x2C20013

4208

#define OFDM_CE_FR_TIMAG01__W 11

4209

#define OFDM_CE_FR_TIMAG01__M 0x7FF

4210

#define OFDM_CE_FR_TIMAG01__PRE 0x0

4211

4212

#define OFDM_CE_FR_TREAL02__A 0x2C20014

4213

#define OFDM_CE_FR_TREAL02__W 11

4214

#define OFDM_CE_FR_TREAL02__M 0x7FF

4215

#define OFDM_CE_FR_TREAL02__PRE 0x52

4216

4217

#define OFDM_CE_FR_TIMAG02__A 0x2C20015

4218

#define OFDM_CE_FR_TIMAG02__W 11

4219

#define OFDM_CE_FR_TIMAG02__M 0x7FF

4220

#define OFDM_CE_FR_TIMAG02__PRE 0x0

4221

4222

#define OFDM_CE_FR_TREAL03__A 0x2C20016

4223

#define OFDM_CE_FR_TREAL03__W 11

4224

#define OFDM_CE_FR_TREAL03__M 0x7FF

4225

#define OFDM_CE_FR_TREAL03__PRE 0x52

4226

4227

#define OFDM_CE_FR_TIMAG03__A 0x2C20017

4228

#define OFDM_CE_FR_TIMAG03__W 11

4229

#define OFDM_CE_FR_TIMAG03__M 0x7FF

4230

#define OFDM_CE_FR_TIMAG03__PRE 0x0

4231

4232

#define OFDM_CE_FR_TREAL04__A 0x2C20018

4233

#define OFDM_CE_FR_TREAL04__W 11

4234

#define OFDM_CE_FR_TREAL04__M 0x7FF

4235

#define OFDM_CE_FR_TREAL04__PRE 0x52

4236

4237

#define OFDM_CE_FR_TIMAG04__A 0x2C20019

4238

#define OFDM_CE_FR_TIMAG04__W 11

4239

#define OFDM_CE_FR_TIMAG04__M 0x7FF

4240

#define OFDM_CE_FR_TIMAG04__PRE 0x0

4241

4242

#define OFDM_CE_FR_TREAL05__A 0x2C2001A

4243

#define OFDM_CE_FR_TREAL05__W 11

4244

#define OFDM_CE_FR_TREAL05__M 0x7FF

4245

#define OFDM_CE_FR_TREAL05__PRE 0x52

4246

4247

#define OFDM_CE_FR_TIMAG05__A 0x2C2001B

4248

#define OFDM_CE_FR_TIMAG05__W 11

4249

#define OFDM_CE_FR_TIMAG05__M 0x7FF

4250

#define OFDM_CE_FR_TIMAG05__PRE 0x0

4251

4252

#define OFDM_CE_FR_TREAL06__A 0x2C2001C

4253

#define OFDM_CE_FR_TREAL06__W 11

4254

#define OFDM_CE_FR_TREAL06__M 0x7FF

4255

#define OFDM_CE_FR_TREAL06__PRE 0x52

4256

4257

#define OFDM_CE_FR_TIMAG06__A 0x2C2001D

4258

#define OFDM_CE_FR_TIMAG06__W 11

4259

#define OFDM_CE_FR_TIMAG06__M 0x7FF

4260

#define OFDM_CE_FR_TIMAG06__PRE 0x0

4261

4262

#define OFDM_CE_FR_TREAL07__A 0x2C2001E

4263

#define OFDM_CE_FR_TREAL07__W 11

4264

#define OFDM_CE_FR_TREAL07__M 0x7FF

4265

#define OFDM_CE_FR_TREAL07__PRE 0x52

4266

4267

#define OFDM_CE_FR_TIMAG07__A 0x2C2001F

4268

#define OFDM_CE_FR_TIMAG07__W 11

4269

#define OFDM_CE_FR_TIMAG07__M 0x7FF

4270

#define OFDM_CE_FR_TIMAG07__PRE 0x0

4271

4272

#define OFDM_CE_FR_TREAL08__A 0x2C20020

4273

#define OFDM_CE_FR_TREAL08__W 11

4274

#define OFDM_CE_FR_TREAL08__M 0x7FF

4275

#define OFDM_CE_FR_TREAL08__PRE 0x52

4276

4277

#define OFDM_CE_FR_TIMAG08__A 0x2C20021

4278

#define OFDM_CE_FR_TIMAG08__W 11

4279

#define OFDM_CE_FR_TIMAG08__M 0x7FF

4280

#define OFDM_CE_FR_TIMAG08__PRE 0x0

4281

4282

#define OFDM_CE_FR_TREAL09__A 0x2C20022

4283

#define OFDM_CE_FR_TREAL09__W 11

4284

#define OFDM_CE_FR_TREAL09__M 0x7FF

4285

#define OFDM_CE_FR_TREAL09__PRE 0x52

4286

4287

#define OFDM_CE_FR_TIMAG09__A 0x2C20023

4288

#define OFDM_CE_FR_TIMAG09__W 11

4289

#define OFDM_CE_FR_TIMAG09__M 0x7FF

4290

#define OFDM_CE_FR_TIMAG09__PRE 0x0

4291

4292

#define OFDM_CE_FR_TREAL10__A 0x2C20024

4293

#define OFDM_CE_FR_TREAL10__W 11

4294

#define OFDM_CE_FR_TREAL10__M 0x7FF

4295

#define OFDM_CE_FR_TREAL10__PRE 0x52

4296

4297

#define OFDM_CE_FR_TIMAG10__A 0x2C20025

4298

#define OFDM_CE_FR_TIMAG10__W 11

4299

#define OFDM_CE_FR_TIMAG10__M 0x7FF

4300

#define OFDM_CE_FR_TIMAG10__PRE 0x0

4301

4302

#define OFDM_CE_FR_TREAL11__A 0x2C20026

4303

#define OFDM_CE_FR_TREAL11__W 11

4304

#define OFDM_CE_FR_TREAL11__M 0x7FF

4305

#define OFDM_CE_FR_TREAL11__PRE 0x52

4306

4307

#define OFDM_CE_FR_TIMAG11__A 0x2C20027

4308

#define OFDM_CE_FR_TIMAG11__W 11

4309

#define OFDM_CE_FR_TIMAG11__M 0x7FF

4310

#define OFDM_CE_FR_TIMAG11__PRE 0x0

4311

4312

#define OFDM_CE_FR_MID_TAP__A 0x2C20028

4313

#define OFDM_CE_FR_MID_TAP__W 11

4314

#define OFDM_CE_FR_MID_TAP__M 0x7FF

4315

#define OFDM_CE_FR_MID_TAP__PRE 0x51

4316

4317

#define OFDM_CE_FR_SQS_G00__A 0x2C20029

4318

#define OFDM_CE_FR_SQS_G00__W 8

4319

#define OFDM_CE_FR_SQS_G00__M 0xFF

4320

#define OFDM_CE_FR_SQS_G00__PRE 0xB

4321

4322

#define OFDM_CE_FR_SQS_G01__A 0x2C2002A

4323

#define OFDM_CE_FR_SQS_G01__W 8

4324

#define OFDM_CE_FR_SQS_G01__M 0xFF

4325

#define OFDM_CE_FR_SQS_G01__PRE 0xB

4326

4327

#define OFDM_CE_FR_SQS_G02__A 0x2C2002B

4328

#define OFDM_CE_FR_SQS_G02__W 8

4329

#define OFDM_CE_FR_SQS_G02__M 0xFF

4330

#define OFDM_CE_FR_SQS_G02__PRE 0xB

4331

4332

#define OFDM_CE_FR_SQS_G03__A 0x2C2002C

4333

#define OFDM_CE_FR_SQS_G03__W 8

4334

#define OFDM_CE_FR_SQS_G03__M 0xFF

4335

#define OFDM_CE_FR_SQS_G03__PRE 0xB

4336

4337

#define OFDM_CE_FR_SQS_G04__A 0x2C2002D

4338

#define OFDM_CE_FR_SQS_G04__W 8

4339

#define OFDM_CE_FR_SQS_G04__M 0xFF

4340

#define OFDM_CE_FR_SQS_G04__PRE 0xB

4341

4342

#define OFDM_CE_FR_SQS_G05__A 0x2C2002E

4343

#define OFDM_CE_FR_SQS_G05__W 8

4344

#define OFDM_CE_FR_SQS_G05__M 0xFF

4345

#define OFDM_CE_FR_SQS_G05__PRE 0xB

4346

4347

#define OFDM_CE_FR_SQS_G06__A 0x2C2002F

4348

#define OFDM_CE_FR_SQS_G06__W 8

4349

#define OFDM_CE_FR_SQS_G06__M 0xFF

4350

#define OFDM_CE_FR_SQS_G06__PRE 0xB

4351

4352

#define OFDM_CE_FR_SQS_G07__A 0x2C20030

4353

#define OFDM_CE_FR_SQS_G07__W 8

4354

#define OFDM_CE_FR_SQS_G07__M 0xFF

4355

#define OFDM_CE_FR_SQS_G07__PRE 0xB

4356

4357

#define OFDM_CE_FR_SQS_G08__A 0x2C20031

4358

#define OFDM_CE_FR_SQS_G08__W 8

4359

#define OFDM_CE_FR_SQS_G08__M 0xFF

4360

#define OFDM_CE_FR_SQS_G08__PRE 0xB

4361

4362

#define OFDM_CE_FR_SQS_G09__A 0x2C20032

4363

#define OFDM_CE_FR_SQS_G09__W 8

4364

#define OFDM_CE_FR_SQS_G09__M 0xFF

4365

#define OFDM_CE_FR_SQS_G09__PRE 0xB

4366

4367

#define OFDM_CE_FR_SQS_G10__A 0x2C20033

4368

#define OFDM_CE_FR_SQS_G10__W 8

4369

#define OFDM_CE_FR_SQS_G10__M 0xFF

4370

#define OFDM_CE_FR_SQS_G10__PRE 0xB

4371

4372

#define OFDM_CE_FR_SQS_G11__A 0x2C20034

4373

#define OFDM_CE_FR_SQS_G11__W 8

4374

#define OFDM_CE_FR_SQS_G11__M 0xFF

4375

#define OFDM_CE_FR_SQS_G11__PRE 0xB

4376

4377

#define OFDM_CE_FR_SQS_G12__A 0x2C20035

4378

#define OFDM_CE_FR_SQS_G12__W 8

4379

#define OFDM_CE_FR_SQS_G12__M 0xFF

4380

#define OFDM_CE_FR_SQS_G12__PRE 0x5

4381

4382

#define OFDM_CE_FR_RIO_G00__A 0x2C20036

4383

#define OFDM_CE_FR_RIO_G00__W 9

4384

#define OFDM_CE_FR_RIO_G00__M 0x1FF

4385

#define OFDM_CE_FR_RIO_G00__PRE 0x1FF

4386

4387

#define OFDM_CE_FR_RIO_G01__A 0x2C20037

4388

#define OFDM_CE_FR_RIO_G01__W 9

4389

#define OFDM_CE_FR_RIO_G01__M 0x1FF

4390

#define OFDM_CE_FR_RIO_G01__PRE 0x190

4391

4392

#define OFDM_CE_FR_RIO_G02__A 0x2C20038

4393

#define OFDM_CE_FR_RIO_G02__W 9

4394

#define OFDM_CE_FR_RIO_G02__M 0x1FF

4395

#define OFDM_CE_FR_RIO_G02__PRE 0x10B

4396

4397

#define OFDM_CE_FR_RIO_G03__A 0x2C20039

4398

#define OFDM_CE_FR_RIO_G03__W 9

4399

#define OFDM_CE_FR_RIO_G03__M 0x1FF

4400

#define OFDM_CE_FR_RIO_G03__PRE 0xC8

4401

4402

#define OFDM_CE_FR_RIO_G04__A 0x2C2003A

4403

#define OFDM_CE_FR_RIO_G04__W 9

4404

#define OFDM_CE_FR_RIO_G04__M 0x1FF

4405

#define OFDM_CE_FR_RIO_G04__PRE 0xA0

4406

4407

#define OFDM_CE_FR_RIO_G05__A 0x2C2003B

4408

#define OFDM_CE_FR_RIO_G05__W 9

4409

#define OFDM_CE_FR_RIO_G05__M 0x1FF

4410

#define OFDM_CE_FR_RIO_G05__PRE 0x85

4411

4412

#define OFDM_CE_FR_RIO_G06__A 0x2C2003C

4413

#define OFDM_CE_FR_RIO_G06__W 9

4414

#define OFDM_CE_FR_RIO_G06__M 0x1FF

4415

#define OFDM_CE_FR_RIO_G06__PRE 0x72

4416

4417

#define OFDM_CE_FR_RIO_G07__A 0x2C2003D

4418

#define OFDM_CE_FR_RIO_G07__W 9

4419

#define OFDM_CE_FR_RIO_G07__M 0x1FF

4420

#define OFDM_CE_FR_RIO_G07__PRE 0x64

4421

4422

#define OFDM_CE_FR_RIO_G08__A 0x2C2003E

4423

#define OFDM_CE_FR_RIO_G08__W 9

4424

#define OFDM_CE_FR_RIO_G08__M 0x1FF

4425

#define OFDM_CE_FR_RIO_G08__PRE 0x59

4426

4427

#define OFDM_CE_FR_RIO_G09__A 0x2C2003F

4428

#define OFDM_CE_FR_RIO_G09__W 9

4429

#define OFDM_CE_FR_RIO_G09__M 0x1FF

4430

#define OFDM_CE_FR_RIO_G09__PRE 0x50

4431

4432

#define OFDM_CE_FR_RIO_G10__A 0x2C20040

4433

#define OFDM_CE_FR_RIO_G10__W 9

4434

#define OFDM_CE_FR_RIO_G10__M 0x1FF

4435

#define OFDM_CE_FR_RIO_G10__PRE 0x49

4436

#define OFDM_CE_FR_MODE__A 0x2C20041

4437

#define OFDM_CE_FR_MODE__W 9

4438

#define OFDM_CE_FR_MODE__M 0x1FF

4439

#define OFDM_CE_FR_MODE__PRE 0xDE

4440

4441

#define OFDM_CE_FR_MODE_UPDATE_ENABLE__B 0

4442

#define OFDM_CE_FR_MODE_UPDATE_ENABLE__W 1

4443

#define OFDM_CE_FR_MODE_UPDATE_ENABLE__M 0x1

4444

#define OFDM_CE_FR_MODE_UPDATE_ENABLE__PRE 0x0

4445

4446

#define OFDM_CE_FR_MODE_ERROR_SHIFT__B 1

4447

#define OFDM_CE_FR_MODE_ERROR_SHIFT__W 1

4448

#define OFDM_CE_FR_MODE_ERROR_SHIFT__M 0x2

4449

#define OFDM_CE_FR_MODE_ERROR_SHIFT__PRE 0x2

4450

4451

#define OFDM_CE_FR_MODE_NEXP_UPDATE__B 2

4452

#define OFDM_CE_FR_MODE_NEXP_UPDATE__W 1

4453

#define OFDM_CE_FR_MODE_NEXP_UPDATE__M 0x4

4454

#define OFDM_CE_FR_MODE_NEXP_UPDATE__PRE 0x4

4455

4456

#define OFDM_CE_FR_MODE_MANUAL_SHIFT__B 3

4457

#define OFDM_CE_FR_MODE_MANUAL_SHIFT__W 1

4458

#define OFDM_CE_FR_MODE_MANUAL_SHIFT__M 0x8

4459

#define OFDM_CE_FR_MODE_MANUAL_SHIFT__PRE 0x8

4460

4461

#define OFDM_CE_FR_MODE_SQUASH_MODE__B 4

4462

#define OFDM_CE_FR_MODE_SQUASH_MODE__W 1

4463

#define OFDM_CE_FR_MODE_SQUASH_MODE__M 0x10

4464

#define OFDM_CE_FR_MODE_SQUASH_MODE__PRE 0x10

4465

4466

#define OFDM_CE_FR_MODE_UPDATE_MODE__B 5

4467

#define OFDM_CE_FR_MODE_UPDATE_MODE__W 1

4468

#define OFDM_CE_FR_MODE_UPDATE_MODE__M 0x20

4469

#define OFDM_CE_FR_MODE_UPDATE_MODE__PRE 0x0

4470

4471

#define OFDM_CE_FR_MODE_MID_MODE__B 6

4472

#define OFDM_CE_FR_MODE_MID_MODE__W 1

4473

#define OFDM_CE_FR_MODE_MID_MODE__M 0x40

4474

#define OFDM_CE_FR_MODE_MID_MODE__PRE 0x40

4475

4476

#define OFDM_CE_FR_MODE_NOISE_MODE__B 7

4477

#define OFDM_CE_FR_MODE_NOISE_MODE__W 1

4478

#define OFDM_CE_FR_MODE_NOISE_MODE__M 0x80

4479

#define OFDM_CE_FR_MODE_NOISE_MODE__PRE 0x80

4480

4481

#define OFDM_CE_FR_MODE_NOTCH_MODE__B 8

4482

#define OFDM_CE_FR_MODE_NOTCH_MODE__W 1

4483

#define OFDM_CE_FR_MODE_NOTCH_MODE__M 0x100

4484

#define OFDM_CE_FR_MODE_NOTCH_MODE__PRE 0x0

4485

4486

4487

#define OFDM_CE_FR_SQS_TRH__A 0x2C20042

4488

#define OFDM_CE_FR_SQS_TRH__W 8

4489

#define OFDM_CE_FR_SQS_TRH__M 0xFF

4490

#define OFDM_CE_FR_SQS_TRH__PRE 0x80

4491

4492

#define OFDM_CE_FR_RIO_GAIN__A 0x2C20043

4493

#define OFDM_CE_FR_RIO_GAIN__W 3

4494

#define OFDM_CE_FR_RIO_GAIN__M 0x7

4495

#define OFDM_CE_FR_RIO_GAIN__PRE 0x7

4496

#define OFDM_CE_FR_BYPASS__A 0x2C20044

4497

#define OFDM_CE_FR_BYPASS__W 10

4498

#define OFDM_CE_FR_BYPASS__M 0x3FF

4499

#define OFDM_CE_FR_BYPASS__PRE 0x13B

4500

4501

#define OFDM_CE_FR_BYPASS_RUN_IN__B 0

4502

#define OFDM_CE_FR_BYPASS_RUN_IN__W 4

4503

#define OFDM_CE_FR_BYPASS_RUN_IN__M 0xF

4504

#define OFDM_CE_FR_BYPASS_RUN_IN__PRE 0xB

4505

4506

#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__B 4

4507

#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__W 5

4508

#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__M 0x1F0

4509

#define OFDM_CE_FR_BYPASS_RUN_SEMI_IN__PRE 0x130

4510

4511

#define OFDM_CE_FR_BYPASS_TOTAL__B 9

4512

#define OFDM_CE_FR_BYPASS_TOTAL__W 1

4513

#define OFDM_CE_FR_BYPASS_TOTAL__M 0x200

4514

#define OFDM_CE_FR_BYPASS_TOTAL__PRE 0x0

4515

4516

4517

#define OFDM_CE_FR_PM_SET__A 0x2C20045

4518

#define OFDM_CE_FR_PM_SET__W 4

4519

#define OFDM_CE_FR_PM_SET__M 0xF

4520

#define OFDM_CE_FR_PM_SET__PRE 0xD

4521

4522

#define OFDM_CE_FR_ERR_SH__A 0x2C20046

4523

#define OFDM_CE_FR_ERR_SH__W 4

4524

#define OFDM_CE_FR_ERR_SH__M 0xF

4525

#define OFDM_CE_FR_ERR_SH__PRE 0x4

4526

4527

#define OFDM_CE_FR_MAN_SH__A 0x2C20047

4528

#define OFDM_CE_FR_MAN_SH__W 4

4529

#define OFDM_CE_FR_MAN_SH__M 0xF

4530

#define OFDM_CE_FR_MAN_SH__PRE 0x7

4531

4532

#define OFDM_CE_FR_TAP_SH__A 0x2C20048

4533

#define OFDM_CE_FR_TAP_SH__W 3

4534

#define OFDM_CE_FR_TAP_SH__M 0x7

4535

#define OFDM_CE_FR_TAP_SH__PRE 0x3

4536

4537

#define OFDM_CE_FR_CLIP__A 0x2C20049

4538

#define OFDM_CE_FR_CLIP__W 9

4539

#define OFDM_CE_FR_CLIP__M 0x1FF

4540

#define OFDM_CE_FR_CLIP__PRE 0x49

4541

4542

#define OFDM_CE_FR_LEAK_UPD__A 0x2C2004A

4543

#define OFDM_CE_FR_LEAK_UPD__W 3

4544

#define OFDM_CE_FR_LEAK_UPD__M 0x7

4545

#define OFDM_CE_FR_LEAK_UPD__PRE 0x0

4546

4547

#define OFDM_CE_FR_LEAK_SH__A 0x2C2004B

4548

#define OFDM_CE_FR_LEAK_SH__W 3

4549

#define OFDM_CE_FR_LEAK_SH__M 0x7

4550

#define OFDM_CE_FR_LEAK_SH__PRE 0x1

#define OFDM_CE_NE_RAM__A 0x2C30000

#define OFDM_CE_PB_RAM__A 0x2C40000

#define OFDM_CP_COMM_EXEC__A 0x2800000

4565

#define OFDM_CP_COMM_EXEC__W 3

4566

#define OFDM_CP_COMM_EXEC__M 0x7

4567

#define OFDM_CP_COMM_EXEC__PRE 0x0

4568

#define OFDM_CP_COMM_EXEC_STOP 0x0

4569

#define OFDM_CP_COMM_EXEC_ACTIVE 0x1

4570

#define OFDM_CP_COMM_EXEC_HOLD 0x2

4571

#define OFDM_CP_COMM_EXEC_STEP 0x3

4572

#define OFDM_CP_COMM_EXEC_BYPASS_STOP 0x4

4573

#define OFDM_CP_COMM_EXEC_BYPASS_HOLD 0x6

4574

4575

#define OFDM_CP_COMM_STATE__A 0x2800001

4576

#define OFDM_CP_COMM_STATE__W 16

4577

#define OFDM_CP_COMM_STATE__M 0xFFFF

4578

#define OFDM_CP_COMM_STATE__PRE 0x0

4579

#define OFDM_CP_COMM_MB__A 0x2800002

4580

#define OFDM_CP_COMM_MB__W 16

4581

#define OFDM_CP_COMM_MB__M 0xFFFF

4582

#define OFDM_CP_COMM_MB__PRE 0x0

4583

#define OFDM_CP_COMM_INT_REQ__A 0x2800004

4584

#define OFDM_CP_COMM_INT_REQ__W 16

4585

#define OFDM_CP_COMM_INT_REQ__M 0xFFFF

4586

#define OFDM_CP_COMM_INT_REQ__PRE 0x0

4587

#define OFDM_CP_COMM_INT_REQ_TOP_REQ__B 1

4588

#define OFDM_CP_COMM_INT_REQ_TOP_REQ__W 1

4589

#define OFDM_CP_COMM_INT_REQ_TOP_REQ__M 0x2

4590

#define OFDM_CP_COMM_INT_REQ_TOP_REQ__PRE 0x0

4591

4592

#define OFDM_CP_COMM_INT_STA__A 0x2800005

4593

#define OFDM_CP_COMM_INT_STA__W 16

4594

#define OFDM_CP_COMM_INT_STA__M 0xFFFF

4595

#define OFDM_CP_COMM_INT_STA__PRE 0x0

4596

#define OFDM_CP_COMM_INT_MSK__A 0x2800006

4597

#define OFDM_CP_COMM_INT_MSK__W 16

4598

#define OFDM_CP_COMM_INT_MSK__M 0xFFFF

4599

#define OFDM_CP_COMM_INT_MSK__PRE 0x0

4600

#define OFDM_CP_COMM_INT_STM__A 0x2800007

4601

#define OFDM_CP_COMM_INT_STM__W 16

4602

#define OFDM_CP_COMM_INT_STM__M 0xFFFF

4603

#define OFDM_CP_COMM_INT_STM__PRE 0x0

4604

#define OFDM_CP_COMM_INT_STM_INT_MSK__B 0

4605

#define OFDM_CP_COMM_INT_STM_INT_MSK__W 16

4606

#define OFDM_CP_COMM_INT_STM_INT_MSK__M 0xFFFF

4607

#define OFDM_CP_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_CP_TOP_COMM_EXEC__A 0x2810000

4612

#define OFDM_CP_TOP_COMM_EXEC__W 3

4613

#define OFDM_CP_TOP_COMM_EXEC__M 0x7

4614

#define OFDM_CP_TOP_COMM_EXEC__PRE 0x0

4615

#define OFDM_CP_TOP_COMM_EXEC_STOP 0x0

4616

#define OFDM_CP_TOP_COMM_EXEC_ACTIVE 0x1

4617

#define OFDM_CP_TOP_COMM_EXEC_HOLD 0x2

4618

#define OFDM_CP_TOP_COMM_EXEC_STEP 0x3

4619

4620

#define OFDM_CP_TOP_COMM_MB__A 0x2810002

4621

#define OFDM_CP_TOP_COMM_MB__W 3

4622

#define OFDM_CP_TOP_COMM_MB__M 0x7

4623

#define OFDM_CP_TOP_COMM_MB__PRE 0x0

4624

#define OFDM_CP_TOP_COMM_MB_CTL__B 0

4625

#define OFDM_CP_TOP_COMM_MB_CTL__W 1

4626

#define OFDM_CP_TOP_COMM_MB_CTL__M 0x1

4627

#define OFDM_CP_TOP_COMM_MB_CTL__PRE 0x0

4628

#define OFDM_CP_TOP_COMM_MB_CTL_OFF 0x0

4629

#define OFDM_CP_TOP_COMM_MB_CTL_ON 0x1

4630

#define OFDM_CP_TOP_COMM_MB_OBS__B 1

4631

#define OFDM_CP_TOP_COMM_MB_OBS__W 1

4632

#define OFDM_CP_TOP_COMM_MB_OBS__M 0x2

4633

#define OFDM_CP_TOP_COMM_MB_OBS__PRE 0x0

4634

#define OFDM_CP_TOP_COMM_MB_OBS_OFF 0x0

4635

#define OFDM_CP_TOP_COMM_MB_OBS_ON 0x2

4636

#define OFDM_CP_TOP_COMM_MB_OBS_MUX__B 2

4637

#define OFDM_CP_TOP_COMM_MB_OBS_MUX__W 1

4638

#define OFDM_CP_TOP_COMM_MB_OBS_MUX__M 0x4

4639

#define OFDM_CP_TOP_COMM_MB_OBS_MUX__PRE 0x0

4640

#define OFDM_CP_TOP_COMM_MB_OBS_MUX_CE 0x0

4641

#define OFDM_CP_TOP_COMM_MB_OBS_MUX_DL 0x4

4642

4643

#define OFDM_CP_TOP_COMM_INT_REQ__A 0x2810004

4644

#define OFDM_CP_TOP_COMM_INT_REQ__W 1

4645

#define OFDM_CP_TOP_COMM_INT_REQ__M 0x1

4646

#define OFDM_CP_TOP_COMM_INT_REQ__PRE 0x0

4647

#define OFDM_CP_TOP_COMM_INT_STA__A 0x2810005

4648

#define OFDM_CP_TOP_COMM_INT_STA__W 1

4649

#define OFDM_CP_TOP_COMM_INT_STA__M 0x1

4650

#define OFDM_CP_TOP_COMM_INT_STA__PRE 0x0

4651

#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__B 0

4652

#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__W 1

4653

#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__M 0x1

4654

#define OFDM_CP_TOP_COMM_INT_STA_NEW_MEAS__PRE 0x0

4655

4656

#define OFDM_CP_TOP_COMM_INT_MSK__A 0x2810006

4657

#define OFDM_CP_TOP_COMM_INT_MSK__W 1

4658

#define OFDM_CP_TOP_COMM_INT_MSK__M 0x1

4659

#define OFDM_CP_TOP_COMM_INT_MSK__PRE 0x0

4660

#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__B 0

4661

#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__W 1

4662

#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__M 0x1

4663

#define OFDM_CP_TOP_COMM_INT_MSK_NEW_MEAS__PRE 0x0

4664

4665

#define OFDM_CP_TOP_COMM_INT_STM__A 0x2810007

4666

#define OFDM_CP_TOP_COMM_INT_STM__W 1

4667

#define OFDM_CP_TOP_COMM_INT_STM__M 0x1

4668

#define OFDM_CP_TOP_COMM_INT_STM__PRE 0x0

4669

#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__B 0

4670

#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__W 1

4671

#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__M 0x1

4672

#define OFDM_CP_TOP_COMM_INT_STM_NEW_MEAS__PRE 0x0

4673

4674

4675

#define OFDM_CP_TOP_MODE_2K__A 0x2810010

4676

#define OFDM_CP_TOP_MODE_2K__W 1

4677

#define OFDM_CP_TOP_MODE_2K__M 0x1

4678

#define OFDM_CP_TOP_MODE_2K__PRE 0x0

4679

4680

#define OFDM_CP_TOP_INTERVAL__A 0x2810011

4681

#define OFDM_CP_TOP_INTERVAL__W 4

4682

#define OFDM_CP_TOP_INTERVAL__M 0xF

4683

#define OFDM_CP_TOP_INTERVAL__PRE 0x5

4684

#define OFDM_CP_TOP_DETECT_ENA__A 0x2810012

4685

#define OFDM_CP_TOP_DETECT_ENA__W 2

4686

#define OFDM_CP_TOP_DETECT_ENA__M 0x3

4687

#define OFDM_CP_TOP_DETECT_ENA__PRE 0x0

4688

4689

#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__B 0

4690

#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__W 1

4691

#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__M 0x1

4692

#define OFDM_CP_TOP_DETECT_ENA_SCATTERED__PRE 0x0

4693

4694

#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__B 1

4695

#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__W 1

4696

#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__M 0x2

4697

#define OFDM_CP_TOP_DETECT_ENA_CONTINUOUS__PRE 0x0

4698

4699

#define OFDM_CP_TOP_FIX__A 0x2810013

4700

#define OFDM_CP_TOP_FIX__W 4

4701

#define OFDM_CP_TOP_FIX__M 0xF

4702

#define OFDM_CP_TOP_FIX__PRE 0xF

4703

4704

#define OFDM_CP_TOP_FIX_RT_SPD_MIX__B 0

4705

#define OFDM_CP_TOP_FIX_RT_SPD_MIX__W 1

4706

#define OFDM_CP_TOP_FIX_RT_SPD_MIX__M 0x1

4707

#define OFDM_CP_TOP_FIX_RT_SPD_MIX__PRE 0x1

4708

#define OFDM_CP_TOP_FIX_RT_SPD_MIX_DISABLE 0x0

4709

#define OFDM_CP_TOP_FIX_RT_SPD_MIX_ENABLE 0x1

4710

4711

#define OFDM_CP_TOP_FIX_RT_SPD_ADD__B 1

4712

#define OFDM_CP_TOP_FIX_RT_SPD_ADD__W 1

4713

#define OFDM_CP_TOP_FIX_RT_SPD_ADD__M 0x2

4714

#define OFDM_CP_TOP_FIX_RT_SPD_ADD__PRE 0x2

4715

#define OFDM_CP_TOP_FIX_RT_SPD_ADD_DISABLE 0x0

4716

#define OFDM_CP_TOP_FIX_RT_SPD_ADD_ENABLE 0x2

4717

4718

#define OFDM_CP_TOP_FIX_RT_SPD_CLP__B 2

4719

#define OFDM_CP_TOP_FIX_RT_SPD_CLP__W 1

4720

#define OFDM_CP_TOP_FIX_RT_SPD_CLP__M 0x4

4721

#define OFDM_CP_TOP_FIX_RT_SPD_CLP__PRE 0x4

4722

#define OFDM_CP_TOP_FIX_RT_SPD_CLP_DISABLE 0x0

4723

#define OFDM_CP_TOP_FIX_RT_SPD_CLP_ENABLE 0x4

4724

4725

#define OFDM_CP_TOP_FIX_RT_SPD_SSH__B 3

4726

#define OFDM_CP_TOP_FIX_RT_SPD_SSH__W 1

4727

#define OFDM_CP_TOP_FIX_RT_SPD_SSH__M 0x8

4728

#define OFDM_CP_TOP_FIX_RT_SPD_SSH__PRE 0x8

4729

#define OFDM_CP_TOP_FIX_RT_SPD_SSH_DISABLE 0x0

4730

#define OFDM_CP_TOP_FIX_RT_SPD_SSH_ENABLE 0x8

4731

4732

#define OFDM_CP_TOP_BR_SMB_NR__A 0x2810021

4733

#define OFDM_CP_TOP_BR_SMB_NR__W 4

4734

#define OFDM_CP_TOP_BR_SMB_NR__M 0xF

4735

#define OFDM_CP_TOP_BR_SMB_NR__PRE 0x0

4736

4737

#define OFDM_CP_TOP_BR_SMB_NR_SMB__B 0

4738

#define OFDM_CP_TOP_BR_SMB_NR_SMB__W 2

4739

#define OFDM_CP_TOP_BR_SMB_NR_SMB__M 0x3

4740

#define OFDM_CP_TOP_BR_SMB_NR_SMB__PRE 0x0

4741

4742

#define OFDM_CP_TOP_BR_SMB_NR_VAL__B 2

4743

#define OFDM_CP_TOP_BR_SMB_NR_VAL__W 1

4744

#define OFDM_CP_TOP_BR_SMB_NR_VAL__M 0x4

4745

#define OFDM_CP_TOP_BR_SMB_NR_VAL__PRE 0x0

4746

4747

#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__B 3

4748

#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__W 1

4749

#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__M 0x8

4750

#define OFDM_CP_TOP_BR_SMB_NR_OFFSET__PRE 0x0

4751

4752

4753

#define OFDM_CP_TOP_BR_CP_SMB_NR__A 0x2810022

4754

#define OFDM_CP_TOP_BR_CP_SMB_NR__W 2

4755

#define OFDM_CP_TOP_BR_CP_SMB_NR__M 0x3

4756

#define OFDM_CP_TOP_BR_CP_SMB_NR__PRE 0x0

4757

4758

#define OFDM_CP_TOP_BR_SPL_OFFSET__A 0x2810023

4759

#define OFDM_CP_TOP_BR_SPL_OFFSET__W 4

4760

#define OFDM_CP_TOP_BR_SPL_OFFSET__M 0xF

4761

#define OFDM_CP_TOP_BR_SPL_OFFSET__PRE 0x8

4762

4763

#define OFDM_CP_TOP_BR_STR_DEL__A 0x2810024

4764

#define OFDM_CP_TOP_BR_STR_DEL__W 10

4765

#define OFDM_CP_TOP_BR_STR_DEL__M 0x3FF

4766

#define OFDM_CP_TOP_BR_STR_DEL__PRE 0xA

4767

4768

#define OFDM_CP_TOP_BR_EXP_ADJ__A 0x2810025

4769

#define OFDM_CP_TOP_BR_EXP_ADJ__W 5

4770

#define OFDM_CP_TOP_BR_EXP_ADJ__M 0x1F

4771

#define OFDM_CP_TOP_BR_EXP_ADJ__PRE 0x10

4772

4773

#define OFDM_CP_TOP_RT_ANG_INC0__A 0x2810030

4774

#define OFDM_CP_TOP_RT_ANG_INC0__W 16

4775

#define OFDM_CP_TOP_RT_ANG_INC0__M 0xFFFF

4776

#define OFDM_CP_TOP_RT_ANG_INC0__PRE 0x0

4777

4778

#define OFDM_CP_TOP_RT_ANG_INC1__A 0x2810031

4779

#define OFDM_CP_TOP_RT_ANG_INC1__W 8

4780

#define OFDM_CP_TOP_RT_ANG_INC1__M 0xFF

4781

#define OFDM_CP_TOP_RT_ANG_INC1__PRE 0x0

4782

4783

#define OFDM_CP_TOP_RT_SPD_EXP_MARG__A 0x2810032

4784

#define OFDM_CP_TOP_RT_SPD_EXP_MARG__W 5

4785

#define OFDM_CP_TOP_RT_SPD_EXP_MARG__M 0x1F

4786

#define OFDM_CP_TOP_RT_SPD_EXP_MARG__PRE 0x5

4787

4788

#define OFDM_CP_TOP_RT_DETECT_TRH__A 0x2810033

4789

#define OFDM_CP_TOP_RT_DETECT_TRH__W 2

4790

#define OFDM_CP_TOP_RT_DETECT_TRH__M 0x3

4791

#define OFDM_CP_TOP_RT_DETECT_TRH__PRE 0x3

4792

4793

#define OFDM_CP_TOP_RT_SPD_RELIABLE__A 0x2810034

4794

#define OFDM_CP_TOP_RT_SPD_RELIABLE__W 3

4795

#define OFDM_CP_TOP_RT_SPD_RELIABLE__M 0x7

4796

#define OFDM_CP_TOP_RT_SPD_RELIABLE__PRE 0x0

4797

4798

#define OFDM_CP_TOP_RT_SPD_DIRECTION__A 0x2810035

4799

#define OFDM_CP_TOP_RT_SPD_DIRECTION__W 1

4800

#define OFDM_CP_TOP_RT_SPD_DIRECTION__M 0x1

4801

#define OFDM_CP_TOP_RT_SPD_DIRECTION__PRE 0x0

4802

4803

#define OFDM_CP_TOP_RT_SPD_MOD__A 0x2810036

4804

#define OFDM_CP_TOP_RT_SPD_MOD__W 2

4805

#define OFDM_CP_TOP_RT_SPD_MOD__M 0x3

4806

#define OFDM_CP_TOP_RT_SPD_MOD__PRE 0x0

4807

4808

#define OFDM_CP_TOP_RT_SPD_SMB__A 0x2810037

4809

#define OFDM_CP_TOP_RT_SPD_SMB__W 2

4810

#define OFDM_CP_TOP_RT_SPD_SMB__M 0x3

4811

#define OFDM_CP_TOP_RT_SPD_SMB__PRE 0x0

4812

#define OFDM_CP_TOP_RT_CPD_MODE__A 0x2810038

4813

#define OFDM_CP_TOP_RT_CPD_MODE__W 3

4814

#define OFDM_CP_TOP_RT_CPD_MODE__M 0x7

4815

#define OFDM_CP_TOP_RT_CPD_MODE__PRE 0x0

4816

4817

#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__B 0

4818

#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__W 2

4819

#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__M 0x3

4820

#define OFDM_CP_TOP_RT_CPD_MODE_MOD3__PRE 0x0

4821

4822

#define OFDM_CP_TOP_RT_CPD_MODE_ADD__B 2

4823

#define OFDM_CP_TOP_RT_CPD_MODE_ADD__W 1

4824

#define OFDM_CP_TOP_RT_CPD_MODE_ADD__M 0x4

4825

#define OFDM_CP_TOP_RT_CPD_MODE_ADD__PRE 0x0

4826

4827

4828

#define OFDM_CP_TOP_RT_CPD_RELIABLE__A 0x2810039

4829

#define OFDM_CP_TOP_RT_CPD_RELIABLE__W 3

4830

#define OFDM_CP_TOP_RT_CPD_RELIABLE__M 0x7

4831

#define OFDM_CP_TOP_RT_CPD_RELIABLE__PRE 0x0

4832

4833

#define OFDM_CP_TOP_RT_CPD_BIN__A 0x281003A

4834

#define OFDM_CP_TOP_RT_CPD_BIN__W 5

4835

#define OFDM_CP_TOP_RT_CPD_BIN__M 0x1F

4836

#define OFDM_CP_TOP_RT_CPD_BIN__PRE 0x0

4837

4838

#define OFDM_CP_TOP_RT_CPD_MAX__A 0x281003B

4839

#define OFDM_CP_TOP_RT_CPD_MAX__W 4

4840

#define OFDM_CP_TOP_RT_CPD_MAX__M 0xF

4841

#define OFDM_CP_TOP_RT_CPD_MAX__PRE 0x0

4842

#define OFDM_CP_TOP_RT_SUPR_VAL__A 0x281003C

4843

#define OFDM_CP_TOP_RT_SUPR_VAL__W 2

4844

#define OFDM_CP_TOP_RT_SUPR_VAL__M 0x3

4845

#define OFDM_CP_TOP_RT_SUPR_VAL__PRE 0x0

4846

4847

#define OFDM_CP_TOP_RT_SUPR_VAL_CE__B 0

4848

#define OFDM_CP_TOP_RT_SUPR_VAL_CE__W 1

4849

#define OFDM_CP_TOP_RT_SUPR_VAL_CE__M 0x1

4850

#define OFDM_CP_TOP_RT_SUPR_VAL_CE__PRE 0x0

4851

4852

#define OFDM_CP_TOP_RT_SUPR_VAL_DL__B 1

4853

#define OFDM_CP_TOP_RT_SUPR_VAL_DL__W 1

4854

#define OFDM_CP_TOP_RT_SUPR_VAL_DL__M 0x2

4855

#define OFDM_CP_TOP_RT_SUPR_VAL_DL__PRE 0x0

4856

4857

4858

#define OFDM_CP_TOP_RT_EXP_AVE__A 0x281003D

4859

#define OFDM_CP_TOP_RT_EXP_AVE__W 5

4860

#define OFDM_CP_TOP_RT_EXP_AVE__M 0x1F

4861

#define OFDM_CP_TOP_RT_EXP_AVE__PRE 0x0

4862

4863

#define OFDM_CP_TOP_RT_CPD_EXP_MARG__A 0x281003E

4864

#define OFDM_CP_TOP_RT_CPD_EXP_MARG__W 5

4865

#define OFDM_CP_TOP_RT_CPD_EXP_MARG__M 0x1F

4866

#define OFDM_CP_TOP_RT_CPD_EXP_MARG__PRE 0x3

4867

4868

#define OFDM_CP_TOP_AC_NEXP_OFFS__A 0x2810040

4869

#define OFDM_CP_TOP_AC_NEXP_OFFS__W 8

4870

#define OFDM_CP_TOP_AC_NEXP_OFFS__M 0xFF

4871

#define OFDM_CP_TOP_AC_NEXP_OFFS__PRE 0x0

4872

4873

#define OFDM_CP_TOP_AC_AVER_POW__A 0x2810041

4874

#define OFDM_CP_TOP_AC_AVER_POW__W 8

4875

#define OFDM_CP_TOP_AC_AVER_POW__M 0xFF

4876

#define OFDM_CP_TOP_AC_AVER_POW__PRE 0x5F

4877

4878

#define OFDM_CP_TOP_AC_MAX_POW__A 0x2810042

4879

#define OFDM_CP_TOP_AC_MAX_POW__W 8

4880

#define OFDM_CP_TOP_AC_MAX_POW__M 0xFF

4881

#define OFDM_CP_TOP_AC_MAX_POW__PRE 0x7A

4882

4883

#define OFDM_CP_TOP_AC_WEIGHT_MAN__A 0x2810043

4884

#define OFDM_CP_TOP_AC_WEIGHT_MAN__W 6

4885

#define OFDM_CP_TOP_AC_WEIGHT_MAN__M 0x3F

4886

#define OFDM_CP_TOP_AC_WEIGHT_MAN__PRE 0x31

4887

4888

#define OFDM_CP_TOP_AC_WEIGHT_EXP__A 0x2810044

4889

#define OFDM_CP_TOP_AC_WEIGHT_EXP__W 5

4890

#define OFDM_CP_TOP_AC_WEIGHT_EXP__M 0x1F

4891

#define OFDM_CP_TOP_AC_WEIGHT_EXP__PRE 0x10

4892

4893

#define OFDM_CP_TOP_AC_GAIN_MAN__A 0x2810045

4894

#define OFDM_CP_TOP_AC_GAIN_MAN__W 16

4895

#define OFDM_CP_TOP_AC_GAIN_MAN__M 0xFFFF

4896

#define OFDM_CP_TOP_AC_GAIN_MAN__PRE 0x0

4897

4898

#define OFDM_CP_TOP_AC_GAIN_EXP__A 0x2810046

4899

#define OFDM_CP_TOP_AC_GAIN_EXP__W 5

4900

#define OFDM_CP_TOP_AC_GAIN_EXP__M 0x1F

4901

#define OFDM_CP_TOP_AC_GAIN_EXP__PRE 0x0

4902

4903

#define OFDM_CP_TOP_AC_AMP_MODE__A 0x2810047

4904

#define OFDM_CP_TOP_AC_AMP_MODE__W 2

4905

#define OFDM_CP_TOP_AC_AMP_MODE__M 0x3

4906

#define OFDM_CP_TOP_AC_AMP_MODE__PRE 0x2

4907

#define OFDM_CP_TOP_AC_AMP_MODE_NEW 0x0

4908

#define OFDM_CP_TOP_AC_AMP_MODE_OLD 0x1

4909

#define OFDM_CP_TOP_AC_AMP_MODE_FIXED 0x2

4910

4911

#define OFDM_CP_TOP_AC_AMP_FIX__A 0x2810048

4912

#define OFDM_CP_TOP_AC_AMP_FIX__W 14

4913

#define OFDM_CP_TOP_AC_AMP_FIX__M 0x3FFF

4914

#define OFDM_CP_TOP_AC_AMP_FIX__PRE 0x0

4915

4916

#define OFDM_CP_TOP_AC_AMP_FIX_MAN__B 0

4917

#define OFDM_CP_TOP_AC_AMP_FIX_MAN__W 10

4918

#define OFDM_CP_TOP_AC_AMP_FIX_MAN__M 0x3FF

4919

#define OFDM_CP_TOP_AC_AMP_FIX_MAN__PRE 0x0

4920

4921

#define OFDM_CP_TOP_AC_AMP_FIX_EXP__B 10

4922

#define OFDM_CP_TOP_AC_AMP_FIX_EXP__W 4

4923

#define OFDM_CP_TOP_AC_AMP_FIX_EXP__M 0x3C00

4924

#define OFDM_CP_TOP_AC_AMP_FIX_EXP__PRE 0x0

4925

4926

#define OFDM_CP_TOP_AC_AMP_READ__A 0x2810049

4927

#define OFDM_CP_TOP_AC_AMP_READ__W 14

4928

#define OFDM_CP_TOP_AC_AMP_READ__M 0x3FFF

4929

#define OFDM_CP_TOP_AC_AMP_READ__PRE 0x0

4930

4931

#define OFDM_CP_TOP_AC_AMP_READ_MAN__B 0

4932

#define OFDM_CP_TOP_AC_AMP_READ_MAN__W 10

4933

#define OFDM_CP_TOP_AC_AMP_READ_MAN__M 0x3FF

4934

#define OFDM_CP_TOP_AC_AMP_READ_MAN__PRE 0x0

4935

4936

#define OFDM_CP_TOP_AC_AMP_READ_EXP__B 10

4937

#define OFDM_CP_TOP_AC_AMP_READ_EXP__W 4

4938

#define OFDM_CP_TOP_AC_AMP_READ_EXP__M 0x3C00

4939

#define OFDM_CP_TOP_AC_AMP_READ_EXP__PRE 0x0

4940

4941

4942

#define OFDM_CP_TOP_AC_ANG_MODE__A 0x281004A

4943

#define OFDM_CP_TOP_AC_ANG_MODE__W 2

4944

#define OFDM_CP_TOP_AC_ANG_MODE__M 0x3

4945

#define OFDM_CP_TOP_AC_ANG_MODE__PRE 0x3

4946

#define OFDM_CP_TOP_AC_ANG_MODE_NEW 0x0

4947

#define OFDM_CP_TOP_AC_ANG_MODE_OLD 0x1

4948

#define OFDM_CP_TOP_AC_ANG_MODE_NO_INT 0x2

4949

#define OFDM_CP_TOP_AC_ANG_MODE_OFFSET 0x3

4950

4951

4952

#define OFDM_CP_TOP_AC_ANG_OFFS__A 0x281004B

4953

#define OFDM_CP_TOP_AC_ANG_OFFS__W 16

4954

#define OFDM_CP_TOP_AC_ANG_OFFS__M 0xFFFF

4955

#define OFDM_CP_TOP_AC_ANG_OFFS__PRE 0x0

4956

4957

#define OFDM_CP_TOP_AC_ANG_READ__A 0x281004C

4958

#define OFDM_CP_TOP_AC_ANG_READ__W 16

4959

#define OFDM_CP_TOP_AC_ANG_READ__M 0xFFFF

4960

#define OFDM_CP_TOP_AC_ANG_READ__PRE 0x0

4961

4962

#define OFDM_CP_TOP_AC_ACCU_REAL0__A 0x2810060

4963

#define OFDM_CP_TOP_AC_ACCU_REAL0__W 8

4964

#define OFDM_CP_TOP_AC_ACCU_REAL0__M 0xFF

4965

#define OFDM_CP_TOP_AC_ACCU_REAL0__PRE 0x0

4966

4967

#define OFDM_CP_TOP_AC_ACCU_IMAG0__A 0x2810061

4968

#define OFDM_CP_TOP_AC_ACCU_IMAG0__W 8

4969

#define OFDM_CP_TOP_AC_ACCU_IMAG0__M 0xFF

4970

#define OFDM_CP_TOP_AC_ACCU_IMAG0__PRE 0x0

4971

4972

#define OFDM_CP_TOP_AC_ACCU_REAL1__A 0x2810062

4973

#define OFDM_CP_TOP_AC_ACCU_REAL1__W 8

4974

#define OFDM_CP_TOP_AC_ACCU_REAL1__M 0xFF

4975

#define OFDM_CP_TOP_AC_ACCU_REAL1__PRE 0x0

4976

4977

#define OFDM_CP_TOP_AC_ACCU_IMAG1__A 0x2810063

4978

#define OFDM_CP_TOP_AC_ACCU_IMAG1__W 8

4979

#define OFDM_CP_TOP_AC_ACCU_IMAG1__M 0xFF

4980

#define OFDM_CP_TOP_AC_ACCU_IMAG1__PRE 0x0

4981

4982

#define OFDM_CP_TOP_DL_MB_WR_ADDR__A 0x2810050

4983

#define OFDM_CP_TOP_DL_MB_WR_ADDR__W 15

4984

#define OFDM_CP_TOP_DL_MB_WR_ADDR__M 0x7FFF

4985

#define OFDM_CP_TOP_DL_MB_WR_ADDR__PRE 0x0

4986

#define OFDM_CP_TOP_DL_MB_WR_CTR__A 0x2810051

4987

#define OFDM_CP_TOP_DL_MB_WR_CTR__W 5

4988

#define OFDM_CP_TOP_DL_MB_WR_CTR__M 0x1F

4989

#define OFDM_CP_TOP_DL_MB_WR_CTR__PRE 0x0

4990

4991

#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__B 2

4992

#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__W 3

4993

#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__M 0x1C

4994

#define OFDM_CP_TOP_DL_MB_WR_CTR_WORD__PRE 0x0

4995

4996

#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__B 1

4997

#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__W 1

4998

#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__M 0x2

4999

#define OFDM_CP_TOP_DL_MB_WR_CTR_OBS__PRE 0x0

5000

5001

#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__B 0

5002

#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__W 1

5003

#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__M 0x1

5004

#define OFDM_CP_TOP_DL_MB_WR_CTR_CTR__PRE 0x0

5005

5006

5007

#define OFDM_CP_TOP_DL_MB_RD_ADDR__A 0x2810052

5008

#define OFDM_CP_TOP_DL_MB_RD_ADDR__W 15

5009

#define OFDM_CP_TOP_DL_MB_RD_ADDR__M 0x7FFF

5010

#define OFDM_CP_TOP_DL_MB_RD_ADDR__PRE 0x0

5011

#define OFDM_CP_TOP_DL_MB_RD_CTR__A 0x2810053

5012

#define OFDM_CP_TOP_DL_MB_RD_CTR__W 11

5013

#define OFDM_CP_TOP_DL_MB_RD_CTR__M 0x7FF

5014

#define OFDM_CP_TOP_DL_MB_RD_CTR__PRE 0x0

5015

5016

#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__B 10

5017

#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__W 1

5018

#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__M 0x400

5019

#define OFDM_CP_TOP_DL_MB_RD_CTR_TEST__PRE 0x0

5020

5021

#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__B 8

5022

#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__W 2

5023

#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__M 0x300

5024

#define OFDM_CP_TOP_DL_MB_RD_CTR_OFFSET__PRE 0x0

5025

5026

#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__B 5

5027

#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__W 3

5028

#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__M 0xE0

5029

#define OFDM_CP_TOP_DL_MB_RD_CTR_VALID__PRE 0x0

5030

5031

#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__B 2

5032

#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__W 3

5033

#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__M 0x1C

5034

#define OFDM_CP_TOP_DL_MB_RD_CTR_WORD__PRE 0x0

5035

5036

#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__B 1

5037

#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__W 1

5038

#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__M 0x2

5039

#define OFDM_CP_TOP_DL_MB_RD_CTR_OBS__PRE 0x0

5040

5041

#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__B 0

5042

#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__W 1

5043

#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__M 0x1

5044

#define OFDM_CP_TOP_DL_MB_RD_CTR_CTR__PRE 0x0

#define OFDM_CP_BR_BUF_CPL_RAM__A 0x2820000

#define OFDM_CP_BR_BUF_DAT_RAM__A 0x2830000

#define OFDM_CP_DL_0_RAM__A 0x2840000

#define OFDM_CP_DL_1_RAM__A 0x2850000

#define OFDM_CP_DL_2_RAM__A 0x2860000

#define OFDM_EC_COMM_EXEC__A 0x3400000

5071

#define OFDM_EC_COMM_EXEC__W 3

5072

#define OFDM_EC_COMM_EXEC__M 0x7

5073

#define OFDM_EC_COMM_EXEC__PRE 0x0

5074

#define OFDM_EC_COMM_EXEC_STOP 0x0

5075

#define OFDM_EC_COMM_EXEC_ACTIVE 0x1

5076

#define OFDM_EC_COMM_EXEC_HOLD 0x2

5077

#define OFDM_EC_COMM_EXEC_STEP 0x3

5078

#define OFDM_EC_COMM_EXEC_BYPASS_STOP 0x4

5079

#define OFDM_EC_COMM_EXEC_BYPASS_HOLD 0x6

5080

5081

#define OFDM_EC_COMM_STATE__A 0x3400001

5082

#define OFDM_EC_COMM_STATE__W 16

5083

#define OFDM_EC_COMM_STATE__M 0xFFFF

5084

#define OFDM_EC_COMM_STATE__PRE 0x0

5085

#define OFDM_EC_COMM_MB__A 0x3400002

5086

#define OFDM_EC_COMM_MB__W 16

5087

#define OFDM_EC_COMM_MB__M 0xFFFF

5088

#define OFDM_EC_COMM_MB__PRE 0x0

5089

#define OFDM_EC_COMM_INT_REQ__A 0x3400004

5090

#define OFDM_EC_COMM_INT_REQ__W 16

5091

#define OFDM_EC_COMM_INT_REQ__M 0xFFFF

5092

#define OFDM_EC_COMM_INT_REQ__PRE 0x0

5093

#define OFDM_EC_COMM_INT_REQ_VD_REQ__B 4

5094

#define OFDM_EC_COMM_INT_REQ_VD_REQ__W 1

5095

#define OFDM_EC_COMM_INT_REQ_VD_REQ__M 0x10

5096

#define OFDM_EC_COMM_INT_REQ_VD_REQ__PRE 0x0

5097

#define OFDM_EC_COMM_INT_REQ_SY_REQ__B 5

5098

#define OFDM_EC_COMM_INT_REQ_SY_REQ__W 1

5099

#define OFDM_EC_COMM_INT_REQ_SY_REQ__M 0x20

5100

#define OFDM_EC_COMM_INT_REQ_SY_REQ__PRE 0x0

5101

5102

#define OFDM_EC_COMM_INT_STA__A 0x3400005

5103

#define OFDM_EC_COMM_INT_STA__W 16

5104

#define OFDM_EC_COMM_INT_STA__M 0xFFFF

5105

#define OFDM_EC_COMM_INT_STA__PRE 0x0

5106

#define OFDM_EC_COMM_INT_MSK__A 0x3400006

5107

#define OFDM_EC_COMM_INT_MSK__W 16

5108

#define OFDM_EC_COMM_INT_MSK__M 0xFFFF

5109

#define OFDM_EC_COMM_INT_MSK__PRE 0x0

5110

#define OFDM_EC_COMM_INT_STM__A 0x3400007

5111

#define OFDM_EC_COMM_INT_STM__W 16

5112

#define OFDM_EC_COMM_INT_STM__M 0xFFFF

5113

#define OFDM_EC_COMM_INT_STM__PRE 0x0

5114

#define OFDM_EC_COMM_INT_STM_INT_MSK__B 0

5115

#define OFDM_EC_COMM_INT_STM_INT_MSK__W 16

5116

#define OFDM_EC_COMM_INT_STM_INT_MSK__M 0xFFFF

5117

#define OFDM_EC_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_EC_SB_COMM_EXEC__A 0x3410000

5122

#define OFDM_EC_SB_COMM_EXEC__W 3

5123

#define OFDM_EC_SB_COMM_EXEC__M 0x7

5124

#define OFDM_EC_SB_COMM_EXEC__PRE 0x0

5125

#define OFDM_EC_SB_COMM_EXEC_STOP 0x0

5126

#define OFDM_EC_SB_COMM_EXEC_ACTIVE 0x1

5127

#define OFDM_EC_SB_COMM_EXEC_HOLD 0x2

5128

#define OFDM_EC_SB_COMM_EXEC_STEP 0x3

5129

5130

#define OFDM_EC_SB_COMM_STATE__A 0x3410001

5131

#define OFDM_EC_SB_COMM_STATE__W 4

5132

#define OFDM_EC_SB_COMM_STATE__M 0xF

5133

#define OFDM_EC_SB_COMM_STATE__PRE 0x0

5134

#define OFDM_EC_SB_COMM_MB__A 0x3410002

5135

#define OFDM_EC_SB_COMM_MB__W 2

5136

#define OFDM_EC_SB_COMM_MB__M 0x3

5137

#define OFDM_EC_SB_COMM_MB__PRE 0x0

5138

#define OFDM_EC_SB_COMM_MB_CTL__B 0

5139

#define OFDM_EC_SB_COMM_MB_CTL__W 1

5140

#define OFDM_EC_SB_COMM_MB_CTL__M 0x1

5141

#define OFDM_EC_SB_COMM_MB_CTL__PRE 0x0

5142

#define OFDM_EC_SB_COMM_MB_CTL_OFF 0x0

5143

#define OFDM_EC_SB_COMM_MB_CTL_ON 0x1

5144

#define OFDM_EC_SB_COMM_MB_OBS__B 1

5145

#define OFDM_EC_SB_COMM_MB_OBS__W 1

5146

#define OFDM_EC_SB_COMM_MB_OBS__M 0x2

5147

#define OFDM_EC_SB_COMM_MB_OBS__PRE 0x0

5148

#define OFDM_EC_SB_COMM_MB_OBS_OFF 0x0

5149

#define OFDM_EC_SB_COMM_MB_OBS_ON 0x2

5150

5151

5152

#define OFDM_EC_SB_TR_MODE__A 0x3410010

5153

#define OFDM_EC_SB_TR_MODE__W 1

5154

#define OFDM_EC_SB_TR_MODE__M 0x1

5155

#define OFDM_EC_SB_TR_MODE__PRE 0x0

5156

#define OFDM_EC_SB_TR_MODE_8K 0x0

5157

#define OFDM_EC_SB_TR_MODE_2K 0x1

5158

5159

5160

#define OFDM_EC_SB_CONST__A 0x3410011

5161

#define OFDM_EC_SB_CONST__W 2

5162

#define OFDM_EC_SB_CONST__M 0x3

5163

#define OFDM_EC_SB_CONST__PRE 0x2

5164

#define OFDM_EC_SB_CONST_QPSK 0x0

5165

#define OFDM_EC_SB_CONST_16QAM 0x1

5166

#define OFDM_EC_SB_CONST_64QAM 0x2

5167

5168

5169

#define OFDM_EC_SB_ALPHA__A 0x3410012

5170

#define OFDM_EC_SB_ALPHA__W 3

5171

#define OFDM_EC_SB_ALPHA__M 0x7

5172

#define OFDM_EC_SB_ALPHA__PRE 0x0

5173

#define OFDM_EC_SB_ALPHA_NH 0x0

5174

#define OFDM_EC_SB_ALPHA_H1 0x1

5175

#define OFDM_EC_SB_ALPHA_H2 0x2

5176

#define OFDM_EC_SB_ALPHA_H4 0x3

5177

5178

5179

#define OFDM_EC_SB_PRIOR__A 0x3410013

5180

#define OFDM_EC_SB_PRIOR__W 1

5181

#define OFDM_EC_SB_PRIOR__M 0x1

5182

#define OFDM_EC_SB_PRIOR__PRE 0x0

5183

#define OFDM_EC_SB_PRIOR_HI 0x0

5184

#define OFDM_EC_SB_PRIOR_LO 0x1

5185

5186

5187

#define OFDM_EC_SB_CSI_HI__A 0x3410014

5188

#define OFDM_EC_SB_CSI_HI__W 5

5189

#define OFDM_EC_SB_CSI_HI__M 0x1F

5190

#define OFDM_EC_SB_CSI_HI__PRE 0x18

5191

#define OFDM_EC_SB_CSI_HI_MAX 0x1F

5192

#define OFDM_EC_SB_CSI_HI_MIN 0x0

5193

#define OFDM_EC_SB_CSI_HI_TAG 0x0

5194

5195

5196

#define OFDM_EC_SB_CSI_LO__A 0x3410015

5197

#define OFDM_EC_SB_CSI_LO__W 5

5198

#define OFDM_EC_SB_CSI_LO__M 0x1F

5199

#define OFDM_EC_SB_CSI_LO__PRE 0xC

5200

#define OFDM_EC_SB_CSI_LO_MAX 0x1F

5201

#define OFDM_EC_SB_CSI_LO_MIN 0x0

5202

#define OFDM_EC_SB_CSI_LO_TAG 0x0

5203

5204

5205

#define OFDM_EC_SB_SMB_TGL__A 0x3410016

5206

#define OFDM_EC_SB_SMB_TGL__W 1

5207

#define OFDM_EC_SB_SMB_TGL__M 0x1

5208

#define OFDM_EC_SB_SMB_TGL__PRE 0x1

5209

#define OFDM_EC_SB_SMB_TGL_OFF 0x0

5210

#define OFDM_EC_SB_SMB_TGL_ON 0x1

5211

5212

5213

#define OFDM_EC_SB_SNR_HI__A 0x3410017

5214

#define OFDM_EC_SB_SNR_HI__W 7

5215

#define OFDM_EC_SB_SNR_HI__M 0x7F

5216

#define OFDM_EC_SB_SNR_HI__PRE 0x7F

5217

#define OFDM_EC_SB_SNR_HI_MAX 0x7F

5218

#define OFDM_EC_SB_SNR_HI_MIN 0x0

5219

#define OFDM_EC_SB_SNR_HI_TAG 0x0

5220

5221

5222

#define OFDM_EC_SB_SNR_MID__A 0x3410018

5223

#define OFDM_EC_SB_SNR_MID__W 7

5224

#define OFDM_EC_SB_SNR_MID__M 0x7F

5225

#define OFDM_EC_SB_SNR_MID__PRE 0x7F

5226

#define OFDM_EC_SB_SNR_MID_MAX 0x7F

5227

#define OFDM_EC_SB_SNR_MID_MIN 0x0

5228

#define OFDM_EC_SB_SNR_MID_TAG 0x0

5229

5230

5231

#define OFDM_EC_SB_SNR_LO__A 0x3410019

5232

#define OFDM_EC_SB_SNR_LO__W 7

5233

#define OFDM_EC_SB_SNR_LO__M 0x7F

5234

#define OFDM_EC_SB_SNR_LO__PRE 0x7F

5235

#define OFDM_EC_SB_SNR_LO_MAX 0x7F

5236

#define OFDM_EC_SB_SNR_LO_MIN 0x0

5237

#define OFDM_EC_SB_SNR_LO_TAG 0x0

5238

5239

5240

#define OFDM_EC_SB_SCALE_MSB__A 0x341001A

5241

#define OFDM_EC_SB_SCALE_MSB__W 6

5242

#define OFDM_EC_SB_SCALE_MSB__M 0x3F

5243

#define OFDM_EC_SB_SCALE_MSB__PRE 0x30

5244

#define OFDM_EC_SB_SCALE_MSB_MAX 0x3F

5245

5246

5247

#define OFDM_EC_SB_SCALE_BIT2__A 0x341001B

5248

#define OFDM_EC_SB_SCALE_BIT2__W 6

5249

#define OFDM_EC_SB_SCALE_BIT2__M 0x3F

5250

#define OFDM_EC_SB_SCALE_BIT2__PRE 0xC

5251

#define OFDM_EC_SB_SCALE_BIT2_MAX 0x3F

5252

5253

5254

#define OFDM_EC_SB_SCALE_LSB__A 0x341001C

5255

#define OFDM_EC_SB_SCALE_LSB__W 6

5256

#define OFDM_EC_SB_SCALE_LSB__M 0x3F

5257

#define OFDM_EC_SB_SCALE_LSB__PRE 0x3

5258

#define OFDM_EC_SB_SCALE_LSB_MAX 0x3F

5259

5260

5261

#define OFDM_EC_SB_CSI_OFS0__A 0x341001D

5262

#define OFDM_EC_SB_CSI_OFS0__W 4

5263

#define OFDM_EC_SB_CSI_OFS0__M 0xF

5264

#define OFDM_EC_SB_CSI_OFS0__PRE 0x1

5265

5266

#define OFDM_EC_SB_CSI_OFS1__A 0x341001E

5267

#define OFDM_EC_SB_CSI_OFS1__W 4

5268

#define OFDM_EC_SB_CSI_OFS1__M 0xF

5269

#define OFDM_EC_SB_CSI_OFS1__PRE 0x1

5270

5271

#define OFDM_EC_SB_CSI_OFS2__A 0x341001F

5272

#define OFDM_EC_SB_CSI_OFS2__W 4

5273

#define OFDM_EC_SB_CSI_OFS2__M 0xF

5274

#define OFDM_EC_SB_CSI_OFS2__PRE 0x1

5275

5276

#define OFDM_EC_SB_MAX0__A 0x3410020

5277

#define OFDM_EC_SB_MAX0__W 6

5278

#define OFDM_EC_SB_MAX0__M 0x3F

5279

#define OFDM_EC_SB_MAX0__PRE 0x3F

5280

5281

#define OFDM_EC_SB_MAX1__A 0x3410021

5282

#define OFDM_EC_SB_MAX1__W 6

5283

#define OFDM_EC_SB_MAX1__M 0x3F

5284

#define OFDM_EC_SB_MAX1__PRE 0x3F

5285

#define OFDM_EC_SB_MAX1_INIT 0x3F

5286

5287

5288

#define OFDM_EC_SB_MAX2__A 0x3410022

5289

#define OFDM_EC_SB_MAX2__W 6

5290

#define OFDM_EC_SB_MAX2__M 0x3F

5291

#define OFDM_EC_SB_MAX2__PRE 0x3F

5292

5293

#define OFDM_EC_SB_CSI_DIS__A 0x3410023

5294

#define OFDM_EC_SB_CSI_DIS__W 1

5295

#define OFDM_EC_SB_CSI_DIS__M 0x1

5296

#define OFDM_EC_SB_CSI_DIS__PRE 0x0

#define OFDM_EC_VD_COMM_EXEC__A 0x3420000

5301

#define OFDM_EC_VD_COMM_EXEC__W 3

5302

#define OFDM_EC_VD_COMM_EXEC__M 0x7

5303

#define OFDM_EC_VD_COMM_EXEC__PRE 0x0

5304

#define OFDM_EC_VD_COMM_EXEC_STOP 0x0

5305

#define OFDM_EC_VD_COMM_EXEC_ACTIVE 0x1

5306

#define OFDM_EC_VD_COMM_EXEC_HOLD 0x2

5307

#define OFDM_EC_VD_COMM_EXEC_STEP 0x3

5308

5309

#define OFDM_EC_VD_COMM_STATE__A 0x3420001

5310

#define OFDM_EC_VD_COMM_STATE__W 4

5311

#define OFDM_EC_VD_COMM_STATE__M 0xF

5312

#define OFDM_EC_VD_COMM_STATE__PRE 0x0

5313

#define OFDM_EC_VD_COMM_MB__A 0x3420002

5314

#define OFDM_EC_VD_COMM_MB__W 2

5315

#define OFDM_EC_VD_COMM_MB__M 0x3

5316

#define OFDM_EC_VD_COMM_MB__PRE 0x0

5317

#define OFDM_EC_VD_COMM_MB_CTL__B 0

5318

#define OFDM_EC_VD_COMM_MB_CTL__W 1

5319

#define OFDM_EC_VD_COMM_MB_CTL__M 0x1

5320

#define OFDM_EC_VD_COMM_MB_CTL__PRE 0x0

5321

#define OFDM_EC_VD_COMM_MB_CTL_OFF 0x0

5322

#define OFDM_EC_VD_COMM_MB_CTL_ON 0x1

5323

#define OFDM_EC_VD_COMM_MB_OBS__B 1

5324

#define OFDM_EC_VD_COMM_MB_OBS__W 1

5325

#define OFDM_EC_VD_COMM_MB_OBS__M 0x2

5326

#define OFDM_EC_VD_COMM_MB_OBS__PRE 0x0

5327

#define OFDM_EC_VD_COMM_MB_OBS_OFF 0x0

5328

#define OFDM_EC_VD_COMM_MB_OBS_ON 0x2

5329

5330

#define OFDM_EC_VD_COMM_INT_REQ__A 0x3420003

5331

#define OFDM_EC_VD_COMM_INT_REQ__W 1

5332

#define OFDM_EC_VD_COMM_INT_REQ__M 0x1

5333

#define OFDM_EC_VD_COMM_INT_REQ__PRE 0x0

5334

#define OFDM_EC_VD_COMM_INT_STA__A 0x3420005

5335

#define OFDM_EC_VD_COMM_INT_STA__W 1

5336

#define OFDM_EC_VD_COMM_INT_STA__M 0x1

5337

#define OFDM_EC_VD_COMM_INT_STA__PRE 0x0

5338

#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__B 0

5339

#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__W 1

5340

#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__M 0x1

5341

#define OFDM_EC_VD_COMM_INT_STA_BER_RDY__PRE 0x0

5342

5343

#define OFDM_EC_VD_COMM_INT_MSK__A 0x3420006

5344

#define OFDM_EC_VD_COMM_INT_MSK__W 1

5345

#define OFDM_EC_VD_COMM_INT_MSK__M 0x1

5346

#define OFDM_EC_VD_COMM_INT_MSK__PRE 0x0

5347

#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__B 0

5348

#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__W 1

5349

#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__M 0x1

5350

#define OFDM_EC_VD_COMM_INT_MSK_BER_RDY__PRE 0x0

5351

5352

#define OFDM_EC_VD_COMM_INT_STM__A 0x3420007

5353

#define OFDM_EC_VD_COMM_INT_STM__W 1

5354

#define OFDM_EC_VD_COMM_INT_STM__M 0x1

5355

#define OFDM_EC_VD_COMM_INT_STM__PRE 0x0

5356

#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__B 0

5357

#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__W 1

5358

#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__M 0x1

5359

#define OFDM_EC_VD_COMM_INT_STM_BER_RDY__PRE 0x0

5360

5361

5362

#define OFDM_EC_VD_FORCE__A 0x3420010

5363

#define OFDM_EC_VD_FORCE__W 2

5364

#define OFDM_EC_VD_FORCE__M 0x3

5365

#define OFDM_EC_VD_FORCE__PRE 0x2

5366

#define OFDM_EC_VD_FORCE_FREE 0x0

5367

#define OFDM_EC_VD_FORCE_PROP 0x1

5368

#define OFDM_EC_VD_FORCE_FORCED 0x2

5369

#define OFDM_EC_VD_FORCE_FIXED 0x3

5370

5371

5372

#define OFDM_EC_VD_SET_CODERATE__A 0x3420011

5373

#define OFDM_EC_VD_SET_CODERATE__W 3

5374

#define OFDM_EC_VD_SET_CODERATE__M 0x7

5375

#define OFDM_EC_VD_SET_CODERATE__PRE 0x1

5376

#define OFDM_EC_VD_SET_CODERATE_C1_2 0x0

5377

#define OFDM_EC_VD_SET_CODERATE_C2_3 0x1

5378

#define OFDM_EC_VD_SET_CODERATE_C3_4 0x2

5379

#define OFDM_EC_VD_SET_CODERATE_C5_6 0x3

5380

#define OFDM_EC_VD_SET_CODERATE_C7_8 0x4

5381

5382

5383

#define OFDM_EC_VD_REQ_SMB_CNT__A 0x3420012

5384

#define OFDM_EC_VD_REQ_SMB_CNT__W 16

5385

#define OFDM_EC_VD_REQ_SMB_CNT__M 0xFFFF

5386

#define OFDM_EC_VD_REQ_SMB_CNT__PRE 0x1

5387

5388

#define OFDM_EC_VD_REQ_BIT_CNT__A 0x3420013

5389

#define OFDM_EC_VD_REQ_BIT_CNT__W 16

5390

#define OFDM_EC_VD_REQ_BIT_CNT__M 0xFFFF

5391

#define OFDM_EC_VD_REQ_BIT_CNT__PRE 0xFFF

5392

5393

#define OFDM_EC_VD_RLK_ENA__A 0x3420014

5394

#define OFDM_EC_VD_RLK_ENA__W 1

5395

#define OFDM_EC_VD_RLK_ENA__M 0x1

5396

#define OFDM_EC_VD_RLK_ENA__PRE 0x1

5397

#define OFDM_EC_VD_RLK_ENA_OFF 0x0

5398

#define OFDM_EC_VD_RLK_ENA_ON 0x1

5399

5400

5401

#define OFDM_EC_VD_VAL__A 0x3420015

5402

#define OFDM_EC_VD_VAL__W 2

5403

#define OFDM_EC_VD_VAL__M 0x3

5404

#define OFDM_EC_VD_VAL__PRE 0x0

5405

#define OFDM_EC_VD_VAL_CODE 0x1

5406

#define OFDM_EC_VD_VAL_CNT 0x2

5407

5408

5409

#define OFDM_EC_VD_GET_CODERATE__A 0x3420016

5410

#define OFDM_EC_VD_GET_CODERATE__W 3

5411

#define OFDM_EC_VD_GET_CODERATE__M 0x7

5412

#define OFDM_EC_VD_GET_CODERATE__PRE 0x0

5413

#define OFDM_EC_VD_GET_CODERATE_C1_2 0x0

5414

#define OFDM_EC_VD_GET_CODERATE_C2_3 0x1

5415

#define OFDM_EC_VD_GET_CODERATE_C3_4 0x2

5416

#define OFDM_EC_VD_GET_CODERATE_C5_6 0x3

5417

#define OFDM_EC_VD_GET_CODERATE_C7_8 0x4

5418

5419

5420

#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017

5421

#define OFDM_EC_VD_ERR_BIT_CNT__W 16

5422

#define OFDM_EC_VD_ERR_BIT_CNT__M 0xFFFF

5423

#define OFDM_EC_VD_ERR_BIT_CNT__PRE 0xFFFF

5424

5425

#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018

5426

#define OFDM_EC_VD_IN_BIT_CNT__W 16

5427

#define OFDM_EC_VD_IN_BIT_CNT__M 0xFFFF

5428

#define OFDM_EC_VD_IN_BIT_CNT__PRE 0x0

5429

5430

#define OFDM_EC_VD_STS__A 0x3420019

5431

#define OFDM_EC_VD_STS__W 1

5432

#define OFDM_EC_VD_STS__M 0x1

5433

#define OFDM_EC_VD_STS__PRE 0x0

5434

#define OFDM_EC_VD_STS_NO_LOCK 0x0

5435

#define OFDM_EC_VD_STS_IN_LOCK 0x1

5436

5437

5438

#define OFDM_EC_VD_RLK_CNT__A 0x342001A

5439

#define OFDM_EC_VD_RLK_CNT__W 16

5440

#define OFDM_EC_VD_RLK_CNT__M 0xFFFF

5441

#define OFDM_EC_VD_RLK_CNT__PRE 0x0

#define OFDM_EC_SY_COMM_EXEC__A 0x3430000

5446

#define OFDM_EC_SY_COMM_EXEC__W 2

5447

#define OFDM_EC_SY_COMM_EXEC__M 0x3

5448

#define OFDM_EC_SY_COMM_EXEC__PRE 0x0

5449

#define OFDM_EC_SY_COMM_EXEC_STOP 0x0

5450

#define OFDM_EC_SY_COMM_EXEC_ACTIVE 0x1

5451

#define OFDM_EC_SY_COMM_EXEC_HOLD 0x2

5452

#define OFDM_EC_SY_COMM_EXEC_STEP 0x3

5453

5454

#define OFDM_EC_SY_COMM_MB__A 0x3430002

5455

#define OFDM_EC_SY_COMM_MB__W 2

5456

#define OFDM_EC_SY_COMM_MB__M 0x3

5457

#define OFDM_EC_SY_COMM_MB__PRE 0x0

5458

#define OFDM_EC_SY_COMM_MB_CTL__B 0

5459

#define OFDM_EC_SY_COMM_MB_CTL__W 1

5460

#define OFDM_EC_SY_COMM_MB_CTL__M 0x1

5461

#define OFDM_EC_SY_COMM_MB_CTL__PRE 0x0

5462

#define OFDM_EC_SY_COMM_MB_CTL_OFF 0x0

5463

#define OFDM_EC_SY_COMM_MB_CTL_ON 0x1

5464

#define OFDM_EC_SY_COMM_MB_OBS__B 1

5465

#define OFDM_EC_SY_COMM_MB_OBS__W 1

5466

#define OFDM_EC_SY_COMM_MB_OBS__M 0x2

5467

#define OFDM_EC_SY_COMM_MB_OBS__PRE 0x0

5468

#define OFDM_EC_SY_COMM_MB_OBS_OFF 0x0

5469

#define OFDM_EC_SY_COMM_MB_OBS_ON 0x2

5470

5471

#define OFDM_EC_SY_COMM_INT_REQ__A 0x3430003

5472

#define OFDM_EC_SY_COMM_INT_REQ__W 1

5473

#define OFDM_EC_SY_COMM_INT_REQ__M 0x1

5474

#define OFDM_EC_SY_COMM_INT_REQ__PRE 0x0

5475

#define OFDM_EC_SY_COMM_INT_STA__A 0x3430005

5476

#define OFDM_EC_SY_COMM_INT_STA__W 3

5477

#define OFDM_EC_SY_COMM_INT_STA__M 0x7

5478

#define OFDM_EC_SY_COMM_INT_STA__PRE 0x0

5479

5480

#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__B 0

5481

#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__W 1

5482

#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__M 0x1

5483

#define OFDM_EC_SY_COMM_INT_STA_LOCK_INT__PRE 0x0

5484

5485

#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__B 1

5486

#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__W 1

5487

#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__M 0x2

5488

#define OFDM_EC_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0

5489

5490

#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__B 2

5491

#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__W 1

5492

#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4

5493

#define OFDM_EC_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0

5494

5495

#define OFDM_EC_SY_COMM_INT_MSK__A 0x3430006

5496

#define OFDM_EC_SY_COMM_INT_MSK__W 3

5497

#define OFDM_EC_SY_COMM_INT_MSK__M 0x7

5498

#define OFDM_EC_SY_COMM_INT_MSK__PRE 0x0

5499

#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__B 0

5500

#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__W 1

5501

#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__M 0x1

5502

#define OFDM_EC_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0

5503

#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__B 1

5504

#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__W 1

5505

#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2

5506

#define OFDM_EC_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0

5507

#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2

5508

#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1

5509

#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4

5510

#define OFDM_EC_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0

5511

5512

#define OFDM_EC_SY_COMM_INT_STM__A 0x3430007

5513

#define OFDM_EC_SY_COMM_INT_STM__W 3

5514

#define OFDM_EC_SY_COMM_INT_STM__M 0x7

5515

#define OFDM_EC_SY_COMM_INT_STM__PRE 0x0

5516

#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__B 0

5517

#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__W 1

5518

#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__M 0x1

5519

#define OFDM_EC_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0

5520

#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__B 1

5521

#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__W 1

5522

#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2

5523

#define OFDM_EC_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0

5524

#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__B 2

5525

#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__W 1

5526

#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4

5527

#define OFDM_EC_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0

5528

5529

#define OFDM_EC_SY_STATUS__A 0x3430010

5530

#define OFDM_EC_SY_STATUS__W 2

5531

#define OFDM_EC_SY_STATUS__M 0x3

5532

#define OFDM_EC_SY_STATUS__PRE 0x0

5533

#define OFDM_EC_SY_STATUS_SYNC_STATE__B 0

5534

#define OFDM_EC_SY_STATUS_SYNC_STATE__W 2

5535

#define OFDM_EC_SY_STATUS_SYNC_STATE__M 0x3

5536

#define OFDM_EC_SY_STATUS_SYNC_STATE__PRE 0x0

5537

#define OFDM_EC_SY_STATUS_SYNC_STATE_HUNTING 0x0

5538

#define OFDM_EC_SY_STATUS_SYNC_STATE_TRYING 0x1

5539

#define OFDM_EC_SY_STATUS_SYNC_STATE_IN_SYNC 0x2

5540

5541

5542

#define OFDM_EC_SY_TIMEOUT__A 0x3430011

5543

#define OFDM_EC_SY_TIMEOUT__W 16

5544

#define OFDM_EC_SY_TIMEOUT__M 0xFFFF

5545

#define OFDM_EC_SY_TIMEOUT__PRE 0x3A98

5546

5547

#define OFDM_EC_SY_SYNC_LWM__A 0x3430012

5548

#define OFDM_EC_SY_SYNC_LWM__W 4

5549

#define OFDM_EC_SY_SYNC_LWM__M 0xF

5550

#define OFDM_EC_SY_SYNC_LWM__PRE 0x2

5551

5552

#define OFDM_EC_SY_SYNC_AWM__A 0x3430013

5553

#define OFDM_EC_SY_SYNC_AWM__W 4

5554

#define OFDM_EC_SY_SYNC_AWM__M 0xF

5555

#define OFDM_EC_SY_SYNC_AWM__PRE 0x3

5556

5557

#define OFDM_EC_SY_SYNC_HWM__A 0x3430014

5558

#define OFDM_EC_SY_SYNC_HWM__W 4

5559

#define OFDM_EC_SY_SYNC_HWM__M 0xF

5560

#define OFDM_EC_SY_SYNC_HWM__PRE 0x5

5561

5562

#define OFDM_EC_SY_UNLOCK__A 0x3430015

5563

#define OFDM_EC_SY_UNLOCK__W 1

5564

#define OFDM_EC_SY_UNLOCK__M 0x1

5565

#define OFDM_EC_SY_UNLOCK__PRE 0x0

#define OFDM_EC_SB_BD0_RAM__A 0x3440000

#define OFDM_EC_SB_BD1_RAM__A 0x3450000

#define OFDM_EC_SB_SD_RAM__A 0x3460000

#define OFDM_EC_VD_RE_RAM__A 0x3470000

#define OFDM_EC_VD_TB0_RAM__A 0x3480000

#define OFDM_EC_VD_TB1_RAM__A 0x3490000

#define OFDM_EC_VD_TB2_RAM__A 0x34A0000

#define OFDM_EC_VD_TB3_RAM__A 0x34B0000

#define OFDM_EQ_COMM_EXEC__A 0x3000000

5604

#define OFDM_EQ_COMM_EXEC__W 3

5605

#define OFDM_EQ_COMM_EXEC__M 0x7

5606

#define OFDM_EQ_COMM_EXEC__PRE 0x0

5607

#define OFDM_EQ_COMM_EXEC_STOP 0x0

5608

#define OFDM_EQ_COMM_EXEC_ACTIVE 0x1

5609

#define OFDM_EQ_COMM_EXEC_HOLD 0x2

5610

#define OFDM_EQ_COMM_EXEC_STEP 0x3

5611

#define OFDM_EQ_COMM_EXEC_BYPASS_STOP 0x4

5612

#define OFDM_EQ_COMM_EXEC_BYPASS_HOLD 0x6

5613

5614

#define OFDM_EQ_COMM_STATE__A 0x3000001

5615

#define OFDM_EQ_COMM_STATE__W 16

5616

#define OFDM_EQ_COMM_STATE__M 0xFFFF

5617

#define OFDM_EQ_COMM_STATE__PRE 0x0

5618

#define OFDM_EQ_COMM_MB__A 0x3000002

5619

#define OFDM_EQ_COMM_MB__W 16

5620

#define OFDM_EQ_COMM_MB__M 0xFFFF

5621

#define OFDM_EQ_COMM_MB__PRE 0x0

5622

#define OFDM_EQ_COMM_INT_REQ__A 0x3000004

5623

#define OFDM_EQ_COMM_INT_REQ__W 16

5624

#define OFDM_EQ_COMM_INT_REQ__M 0xFFFF

5625

#define OFDM_EQ_COMM_INT_REQ__PRE 0x0

5626

#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__B 3

5627

#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__W 1

5628

#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__M 0x8

5629

#define OFDM_EQ_COMM_INT_REQ_TOP_REQ__PRE 0x0

5630

5631

#define OFDM_EQ_COMM_INT_STA__A 0x3000005

5632

#define OFDM_EQ_COMM_INT_STA__W 16

5633

#define OFDM_EQ_COMM_INT_STA__M 0xFFFF

5634

#define OFDM_EQ_COMM_INT_STA__PRE 0x0

5635

#define OFDM_EQ_COMM_INT_MSK__A 0x3000006

5636

#define OFDM_EQ_COMM_INT_MSK__W 16

5637

#define OFDM_EQ_COMM_INT_MSK__M 0xFFFF

5638

#define OFDM_EQ_COMM_INT_MSK__PRE 0x0

5639

#define OFDM_EQ_COMM_INT_STM__A 0x3000007

5640

#define OFDM_EQ_COMM_INT_STM__W 16

5641

#define OFDM_EQ_COMM_INT_STM__M 0xFFFF

5642

#define OFDM_EQ_COMM_INT_STM__PRE 0x0

5643

#define OFDM_EQ_COMM_INT_STM_INT_MSK__B 0

5644

#define OFDM_EQ_COMM_INT_STM_INT_MSK__W 16

5645

#define OFDM_EQ_COMM_INT_STM_INT_MSK__M 0xFFFF

5646

#define OFDM_EQ_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_EQ_TOP_COMM_EXEC__A 0x3010000

5651

#define OFDM_EQ_TOP_COMM_EXEC__W 3

5652

#define OFDM_EQ_TOP_COMM_EXEC__M 0x7

5653

#define OFDM_EQ_TOP_COMM_EXEC__PRE 0x0

5654

#define OFDM_EQ_TOP_COMM_EXEC_STOP 0x0

5655

#define OFDM_EQ_TOP_COMM_EXEC_ACTIVE 0x1

5656

#define OFDM_EQ_TOP_COMM_EXEC_HOLD 0x2

5657

#define OFDM_EQ_TOP_COMM_EXEC_STEP 0x3

5658

5659

#define OFDM_EQ_TOP_COMM_STATE__A 0x3010001

5660

#define OFDM_EQ_TOP_COMM_STATE__W 4

5661

#define OFDM_EQ_TOP_COMM_STATE__M 0xF

5662

#define OFDM_EQ_TOP_COMM_STATE__PRE 0x0

5663

#define OFDM_EQ_TOP_COMM_MB__A 0x3010002

5664

#define OFDM_EQ_TOP_COMM_MB__W 6

5665

#define OFDM_EQ_TOP_COMM_MB__M 0x3F

5666

#define OFDM_EQ_TOP_COMM_MB__PRE 0x0

5667

#define OFDM_EQ_TOP_COMM_MB_CTL__B 0

5668

#define OFDM_EQ_TOP_COMM_MB_CTL__W 1

5669

#define OFDM_EQ_TOP_COMM_MB_CTL__M 0x1

5670

#define OFDM_EQ_TOP_COMM_MB_CTL__PRE 0x0

5671

#define OFDM_EQ_TOP_COMM_MB_CTL_OFF 0x0

5672

#define OFDM_EQ_TOP_COMM_MB_CTL_ON 0x1

5673

#define OFDM_EQ_TOP_COMM_MB_OBS__B 1

5674

#define OFDM_EQ_TOP_COMM_MB_OBS__W 1

5675

#define OFDM_EQ_TOP_COMM_MB_OBS__M 0x2

5676

#define OFDM_EQ_TOP_COMM_MB_OBS__PRE 0x0

5677

#define OFDM_EQ_TOP_COMM_MB_OBS_OFF 0x0

5678

#define OFDM_EQ_TOP_COMM_MB_OBS_ON 0x2

5679

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__B 2

5680

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__W 2

5681

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__M 0xC

5682

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX__PRE 0x0

5683

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_OT 0x0

5684

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_RC 0x4

5685

#define OFDM_EQ_TOP_COMM_MB_CTL_MUX_EQ_IS 0x8

5686

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__B 4

5687

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__W 2

5688

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__M 0x30

5689

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX__PRE 0x0

5690

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_OT 0x0

5691

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_RC 0x10

5692

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_IS 0x20

5693

#define OFDM_EQ_TOP_COMM_MB_OBS_MUX_EQ_SN 0x30

5694

5695

#define OFDM_EQ_TOP_COMM_INT_REQ__A 0x3010004

5696

#define OFDM_EQ_TOP_COMM_INT_REQ__W 1

5697

#define OFDM_EQ_TOP_COMM_INT_REQ__M 0x1

5698

#define OFDM_EQ_TOP_COMM_INT_REQ__PRE 0x0

5699

#define OFDM_EQ_TOP_COMM_INT_STA__A 0x3010005

5700

#define OFDM_EQ_TOP_COMM_INT_STA__W 2

5701

#define OFDM_EQ_TOP_COMM_INT_STA__M 0x3

5702

#define OFDM_EQ_TOP_COMM_INT_STA__PRE 0x0

5703

#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__B 0

5704

#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__W 1

5705

#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__M 0x1

5706

#define OFDM_EQ_TOP_COMM_INT_STA_TPS_RDY__PRE 0x0

5707

#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__B 1

5708

#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__W 1

5709

#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__M 0x2

5710

#define OFDM_EQ_TOP_COMM_INT_STA_ERR_RDY__PRE 0x0

5711

5712

#define OFDM_EQ_TOP_COMM_INT_MSK__A 0x3010006

5713

#define OFDM_EQ_TOP_COMM_INT_MSK__W 2

5714

#define OFDM_EQ_TOP_COMM_INT_MSK__M 0x3

5715

#define OFDM_EQ_TOP_COMM_INT_MSK__PRE 0x0

5716

#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__B 0

5717

#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__W 1

5718

#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__M 0x1

5719

#define OFDM_EQ_TOP_COMM_INT_MSK_TPS_RDY__PRE 0x0

5720

#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__B 1

5721

#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__W 1

5722

#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__M 0x2

5723

#define OFDM_EQ_TOP_COMM_INT_MSK_MER_RDY__PRE 0x0

5724

5725

#define OFDM_EQ_TOP_COMM_INT_STM__A 0x3010007

5726

#define OFDM_EQ_TOP_COMM_INT_STM__W 2

5727

#define OFDM_EQ_TOP_COMM_INT_STM__M 0x3

5728

#define OFDM_EQ_TOP_COMM_INT_STM__PRE 0x0

5729

#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__B 0

5730

#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__W 1

5731

#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__M 0x1

5732

#define OFDM_EQ_TOP_COMM_INT_STM_TPS_RDY__PRE 0x0

5733

#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__B 1

5734

#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__W 1

5735

#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__M 0x2

5736

#define OFDM_EQ_TOP_COMM_INT_STM_MER_RDY__PRE 0x0

5737

5738

#define OFDM_EQ_TOP_IS_MODE__A 0x3010014

5739

#define OFDM_EQ_TOP_IS_MODE__W 4

5740

#define OFDM_EQ_TOP_IS_MODE__M 0xF

5741

#define OFDM_EQ_TOP_IS_MODE__PRE 0x0

5742

5743

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__B 0

5744

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__W 1

5745

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__M 0x1

5746

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL__PRE 0x0

5747

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_MAX 0x0

5748

#define OFDM_EQ_TOP_IS_MODE_LIM_EXP_SEL_LIM_EXP_SEL_EXP_SEL_ZER 0x1

5749

5750

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__B 1

5751

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__W 1

5752

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__M 0x2

5753

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL__PRE 0x0

5754

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_ONE 0x0

5755

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_SEL_LIM_CLP_SEL_CLP_SEL_TWO 0x2

5756

5757

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__B 2

5758

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__W 1

5759

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__M 0x4

5760

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS__PRE 0x0

5761

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_ENABLE 0x0

5762

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_REA_DIS_DISABLE 0x4

5763

5764

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__B 3

5765

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__W 1

5766

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__M 0x8

5767

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS__PRE 0x0

5768

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_ENABLE 0x0

5769

#define OFDM_EQ_TOP_IS_MODE_LIM_CLP_IMA_DIS_DISABLE 0x8

5770

5771

5772

#define OFDM_EQ_TOP_IS_GAIN_MAN__A 0x3010015

5773

#define OFDM_EQ_TOP_IS_GAIN_MAN__W 10

5774

#define OFDM_EQ_TOP_IS_GAIN_MAN__M 0x3FF

5775

#define OFDM_EQ_TOP_IS_GAIN_MAN__PRE 0x114

5776

5777

#define OFDM_EQ_TOP_IS_GAIN_EXP__A 0x3010016

5778

#define OFDM_EQ_TOP_IS_GAIN_EXP__W 5

5779

#define OFDM_EQ_TOP_IS_GAIN_EXP__M 0x1F

5780

#define OFDM_EQ_TOP_IS_GAIN_EXP__PRE 0x5

5781

5782

#define OFDM_EQ_TOP_IS_CLIP_EXP__A 0x3010017

5783

#define OFDM_EQ_TOP_IS_CLIP_EXP__W 5

5784

#define OFDM_EQ_TOP_IS_CLIP_EXP__M 0x1F

5785

#define OFDM_EQ_TOP_IS_CLIP_EXP__PRE 0x10

5786

#define OFDM_EQ_TOP_DV_MODE__A 0x301001E

5787

#define OFDM_EQ_TOP_DV_MODE__W 4

5788

#define OFDM_EQ_TOP_DV_MODE__M 0xF

5789

#define OFDM_EQ_TOP_DV_MODE__PRE 0xF

5790

5791

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__B 0

5792

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__W 1

5793

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__M 0x1

5794

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR__PRE 0x1

5795

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_DIS 0x0

5796

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVR_ENA 0x1

5797

5798

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__B 1

5799

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__W 1

5800

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__M 0x2

5801

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI__PRE 0x2

5802

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_DIS 0x0

5803

#define OFDM_EQ_TOP_DV_MODE_CLP_CNT_EVI_ENA 0x2

5804

5805

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__B 2

5806

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__W 1

5807

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__M 0x4

5808

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA__PRE 0x4

5809

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_DIS 0x0

5810

#define OFDM_EQ_TOP_DV_MODE_CLP_REA_ENA_ENA 0x4

5811

5812

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__B 3

5813

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__W 1

5814

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__M 0x8

5815

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA__PRE 0x8

5816

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_DIS 0x0

5817

#define OFDM_EQ_TOP_DV_MODE_CLP_IMA_ENA_ENA 0x8

5818

5819

5820

#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__A 0x301001F

5821

#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__W 16

5822

#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__M 0xFFFF

5823

#define OFDM_EQ_TOP_DV_POS_CLIP_DAT__PRE 0x0

5824

#define OFDM_EQ_TOP_SN_MODE__A 0x3010028

5825

#define OFDM_EQ_TOP_SN_MODE__W 8

5826

#define OFDM_EQ_TOP_SN_MODE__M 0xFF

5827

#define OFDM_EQ_TOP_SN_MODE__PRE 0x18

5828

5829

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__B 0

5830

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__W 1

5831

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__M 0x1

5832

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA__PRE 0x0

5833

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_DISABLE 0x0

5834

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_DAT_ENA_ENABLE 0x1

5835

5836

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__B 1

5837

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__W 1

5838

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__M 0x2

5839

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA__PRE 0x0

5840

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_DISABLE 0x0

5841

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_DAT_ENA_ENABLE 0x2

5842

5843

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__B 2

5844

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__W 1

5845

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__M 0x4

5846

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA__PRE 0x0

5847

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_DISABLE 0x0

5848

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_DAT_ENA_ENABLE 0x4

5849

5850

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__B 3

5851

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__W 1

5852

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__M 0x8

5853

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA__PRE 0x8

5854

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_DISABLE 0x0

5855

#define OFDM_EQ_TOP_SN_MODE_EQ_IS_SNR_ENA_ENABLE 0x8

5856

5857

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__B 4

5858

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__W 1

5859

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__M 0x10

5860

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA__PRE 0x10

5861

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_DISABLE 0x0

5862

#define OFDM_EQ_TOP_SN_MODE_EQ_DV_SNR_ENA_ENABLE 0x10

5863

5864

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__B 5

5865

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__W 1

5866

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__M 0x20

5867

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA__PRE 0x0

5868

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_DISABLE 0x0

5869

#define OFDM_EQ_TOP_SN_MODE_EQ_SN_SNR_ENA_ENABLE 0x20

5870

5871

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__B 6

5872

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__W 1

5873

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__M 0x40

5874

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC__PRE 0x0

5875

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_DYNAMIC 0x0

5876

#define OFDM_EQ_TOP_SN_MODE_CPOW_STATIC_STATIC 0x40

5877

5878

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__B 7

5879

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__W 1

5880

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__M 0x80

5881

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC__PRE 0x0

5882

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_DYNAMIC 0x0

5883

#define OFDM_EQ_TOP_SN_MODE_NPOW_STATIC_STATIC 0x80

5884

5885

5886

#define OFDM_EQ_TOP_SN_PFIX__A 0x3010029

5887

#define OFDM_EQ_TOP_SN_PFIX__W 8

5888

#define OFDM_EQ_TOP_SN_PFIX__M 0xFF

5889

#define OFDM_EQ_TOP_SN_PFIX__PRE 0x0

5890

5891

#define OFDM_EQ_TOP_SN_CEGAIN__A 0x301002A

5892

#define OFDM_EQ_TOP_SN_CEGAIN__W 8

5893

#define OFDM_EQ_TOP_SN_CEGAIN__M 0xFF

5894

#define OFDM_EQ_TOP_SN_CEGAIN__PRE 0x30

5895

5896

#define OFDM_EQ_TOP_SN_OFFSET__A 0x301002B

5897

#define OFDM_EQ_TOP_SN_OFFSET__W 6

5898

#define OFDM_EQ_TOP_SN_OFFSET__M 0x3F

5899

#define OFDM_EQ_TOP_SN_OFFSET__PRE 0x39

5900

5901

#define OFDM_EQ_TOP_SN_NULLIFY__A 0x301002C

5902

#define OFDM_EQ_TOP_SN_NULLIFY__W 6

5903

#define OFDM_EQ_TOP_SN_NULLIFY__M 0x3F

5904

#define OFDM_EQ_TOP_SN_NULLIFY__PRE 0x0

5905

#define OFDM_EQ_TOP_SN_SQUASH__A 0x301002D

5906

#define OFDM_EQ_TOP_SN_SQUASH__W 10

5907

#define OFDM_EQ_TOP_SN_SQUASH__M 0x3FF

5908

#define OFDM_EQ_TOP_SN_SQUASH__PRE 0x7

5909

5910

#define OFDM_EQ_TOP_SN_SQUASH_MAN__B 0

5911

#define OFDM_EQ_TOP_SN_SQUASH_MAN__W 6

5912

#define OFDM_EQ_TOP_SN_SQUASH_MAN__M 0x3F

5913

#define OFDM_EQ_TOP_SN_SQUASH_MAN__PRE 0x7

5914

5915

#define OFDM_EQ_TOP_SN_SQUASH_EXP__B 6

5916

#define OFDM_EQ_TOP_SN_SQUASH_EXP__W 4

5917

#define OFDM_EQ_TOP_SN_SQUASH_EXP__M 0x3C0

5918

#define OFDM_EQ_TOP_SN_SQUASH_EXP__PRE 0x0

5919

5920

#define OFDM_EQ_TOP_RC_SEL_CAR__A 0x3010032

5921

#define OFDM_EQ_TOP_RC_SEL_CAR__W 8

5922

#define OFDM_EQ_TOP_RC_SEL_CAR__M 0xFF

5923

#define OFDM_EQ_TOP_RC_SEL_CAR__PRE 0x2

5924

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__B 0

5925

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__W 1

5926

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__M 0x1

5927

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV__PRE 0x0

5928

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_OFF 0x0

5929

#define OFDM_EQ_TOP_RC_SEL_CAR_DIV_ON 0x1

5930

5931

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__B 1

5932

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__W 2

5933

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__M 0x6

5934

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS__PRE 0x2

5935

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_A_CC 0x0

5936

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_B_CE 0x2

5937

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_C_DRI 0x4

5938

#define OFDM_EQ_TOP_RC_SEL_CAR_PASS_D_CC 0x6

5939

5940

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__B 3

5941

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__W 2

5942

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__M 0x18

5943

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL__PRE 0x0

5944

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_A_CC 0x0

5945

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_B_CE 0x8

5946

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_C_DRI 0x10

5947

#define OFDM_EQ_TOP_RC_SEL_CAR_LOCAL_D_CC 0x18

5948

5949

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__B 5

5950

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__W 2

5951

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__M 0x60

5952

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS__PRE 0x0

5953

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_A_CC 0x0

5954

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_B_CE 0x20

5955

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_C_DRI 0x40

5956

#define OFDM_EQ_TOP_RC_SEL_CAR_MEAS_D_CC 0x60

5957

5958

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__B 7

5959

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__W 1

5960

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__M 0x80

5961

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE__PRE 0x0

5962

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_2K 0x0

5963

#define OFDM_EQ_TOP_RC_SEL_CAR_FFTMODE_8K 0x80

5964

5965

#define OFDM_EQ_TOP_RC_STS__A 0x3010033

5966

#define OFDM_EQ_TOP_RC_STS__W 16

5967

#define OFDM_EQ_TOP_RC_STS__M 0xFFFF

5968

#define OFDM_EQ_TOP_RC_STS__PRE 0x0

5969

5970

#define OFDM_EQ_TOP_RC_STS_DIFF__B 0

5971

#define OFDM_EQ_TOP_RC_STS_DIFF__W 11

5972

#define OFDM_EQ_TOP_RC_STS_DIFF__M 0x7FF

5973

#define OFDM_EQ_TOP_RC_STS_DIFF__PRE 0x0

5974

5975

#define OFDM_EQ_TOP_RC_STS_FIRST__B 11

5976

#define OFDM_EQ_TOP_RC_STS_FIRST__W 1

5977

#define OFDM_EQ_TOP_RC_STS_FIRST__M 0x800

5978

#define OFDM_EQ_TOP_RC_STS_FIRST__PRE 0x0

5979

#define OFDM_EQ_TOP_RC_STS_FIRST_A_CE 0x0

5980

#define OFDM_EQ_TOP_RC_STS_FIRST_B_DRI 0x800

5981

5982

#define OFDM_EQ_TOP_RC_STS_SELEC__B 12

5983

#define OFDM_EQ_TOP_RC_STS_SELEC__W 1

5984

#define OFDM_EQ_TOP_RC_STS_SELEC__M 0x1000

5985

#define OFDM_EQ_TOP_RC_STS_SELEC__PRE 0x0

5986

#define OFDM_EQ_TOP_RC_STS_SELEC_A_CE 0x0

5987

#define OFDM_EQ_TOP_RC_STS_SELEC_B_DRI 0x1000

5988

5989

#define OFDM_EQ_TOP_RC_STS_OVERFLOW__B 13

5990

#define OFDM_EQ_TOP_RC_STS_OVERFLOW__W 1

5991

#define OFDM_EQ_TOP_RC_STS_OVERFLOW__M 0x2000

5992

#define OFDM_EQ_TOP_RC_STS_OVERFLOW__PRE 0x0

5993

#define OFDM_EQ_TOP_RC_STS_OVERFLOW_NO 0x0

5994

#define OFDM_EQ_TOP_RC_STS_OVERFLOW_YES 0x2000

5995

5996

#define OFDM_EQ_TOP_RC_STS_LOC_PRS__B 14

5997

#define OFDM_EQ_TOP_RC_STS_LOC_PRS__W 1

5998

#define OFDM_EQ_TOP_RC_STS_LOC_PRS__M 0x4000

5999

#define OFDM_EQ_TOP_RC_STS_LOC_PRS__PRE 0x0

6000

#define OFDM_EQ_TOP_RC_STS_LOC_PRS_NO 0x0

6001

#define OFDM_EQ_TOP_RC_STS_LOC_PRS_YES 0x4000

6002

6003

#define OFDM_EQ_TOP_RC_STS_DRI_PRS__B 15

6004

#define OFDM_EQ_TOP_RC_STS_DRI_PRS__W 1

6005

#define OFDM_EQ_TOP_RC_STS_DRI_PRS__M 0x8000

6006

#define OFDM_EQ_TOP_RC_STS_DRI_PRS__PRE 0x0

6007

#define OFDM_EQ_TOP_RC_STS_DRI_PRS_NO 0x0

6008

#define OFDM_EQ_TOP_RC_STS_DRI_PRS_YES 0x8000

6009

6010

6011

#define OFDM_EQ_TOP_OT_CONST__A 0x3010046

6012

#define OFDM_EQ_TOP_OT_CONST__W 2

6013

#define OFDM_EQ_TOP_OT_CONST__M 0x3

6014

#define OFDM_EQ_TOP_OT_CONST__PRE 0x2

6015

6016

#define OFDM_EQ_TOP_OT_ALPHA__A 0x3010047

6017

#define OFDM_EQ_TOP_OT_ALPHA__W 2

6018

#define OFDM_EQ_TOP_OT_ALPHA__M 0x3

6019

#define OFDM_EQ_TOP_OT_ALPHA__PRE 0x0

6020

6021

#define OFDM_EQ_TOP_OT_QNT_THRES0__A 0x3010048

6022

#define OFDM_EQ_TOP_OT_QNT_THRES0__W 5

6023

#define OFDM_EQ_TOP_OT_QNT_THRES0__M 0x1F

6024

#define OFDM_EQ_TOP_OT_QNT_THRES0__PRE 0x1E

6025

6026

#define OFDM_EQ_TOP_OT_QNT_THRES1__A 0x3010049

6027

#define OFDM_EQ_TOP_OT_QNT_THRES1__W 5

6028

#define OFDM_EQ_TOP_OT_QNT_THRES1__M 0x1F

6029

#define OFDM_EQ_TOP_OT_QNT_THRES1__PRE 0x1F

6030

6031

#define OFDM_EQ_TOP_OT_CSI_STEP__A 0x301004A

6032

#define OFDM_EQ_TOP_OT_CSI_STEP__W 4

6033

#define OFDM_EQ_TOP_OT_CSI_STEP__M 0xF

6034

#define OFDM_EQ_TOP_OT_CSI_STEP__PRE 0x5

6035

6036

#define OFDM_EQ_TOP_OT_CSI_OFFSET__A 0x301004B

6037

#define OFDM_EQ_TOP_OT_CSI_OFFSET__W 8

6038

#define OFDM_EQ_TOP_OT_CSI_OFFSET__M 0xFF

6039

#define OFDM_EQ_TOP_OT_CSI_OFFSET__PRE 0x5

6040

6041

#define OFDM_EQ_TOP_OT_CSI_GAIN__A 0x301004C

6042

#define OFDM_EQ_TOP_OT_CSI_GAIN__W 8

6043

#define OFDM_EQ_TOP_OT_CSI_GAIN__M 0xFF

6044

#define OFDM_EQ_TOP_OT_CSI_GAIN__PRE 0x2B

6045

6046

#define OFDM_EQ_TOP_OT_CSI_MEAN__A 0x301004D

6047

#define OFDM_EQ_TOP_OT_CSI_MEAN__W 7

6048

#define OFDM_EQ_TOP_OT_CSI_MEAN__M 0x7F

6049

#define OFDM_EQ_TOP_OT_CSI_MEAN__PRE 0x0

6050

6051

#define OFDM_EQ_TOP_OT_CSI_VARIANCE__A 0x301004E

6052

#define OFDM_EQ_TOP_OT_CSI_VARIANCE__W 7

6053

#define OFDM_EQ_TOP_OT_CSI_VARIANCE__M 0x7F

6054

#define OFDM_EQ_TOP_OT_CSI_VARIANCE__PRE 0x0

6055

6056

#define OFDM_EQ_TOP_TD_TPS_INIT__A 0x3010050

6057

#define OFDM_EQ_TOP_TD_TPS_INIT__W 1

6058

#define OFDM_EQ_TOP_TD_TPS_INIT__M 0x1

6059

#define OFDM_EQ_TOP_TD_TPS_INIT__PRE 0x0

6060

#define OFDM_EQ_TOP_TD_TPS_INIT_POS 0x0

6061

#define OFDM_EQ_TOP_TD_TPS_INIT_NEG 0x1

6062

6063

6064

#define OFDM_EQ_TOP_TD_TPS_SYNC__A 0x3010051

6065

#define OFDM_EQ_TOP_TD_TPS_SYNC__W 16

6066

#define OFDM_EQ_TOP_TD_TPS_SYNC__M 0xFFFF

6067

#define OFDM_EQ_TOP_TD_TPS_SYNC__PRE 0x0

6068

#define OFDM_EQ_TOP_TD_TPS_SYNC_ODD 0x35EE

6069

#define OFDM_EQ_TOP_TD_TPS_SYNC_EVEN 0xCA11

6070

6071

6072

#define OFDM_EQ_TOP_TD_TPS_LEN__A 0x3010052

6073

#define OFDM_EQ_TOP_TD_TPS_LEN__W 6

6074

#define OFDM_EQ_TOP_TD_TPS_LEN__M 0x3F

6075

#define OFDM_EQ_TOP_TD_TPS_LEN__PRE 0x0

6076

#define OFDM_EQ_TOP_TD_TPS_LEN_DEF 0x17

6077

#define OFDM_EQ_TOP_TD_TPS_LEN_ID_SUP 0x1F

6078

6079

6080

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__A 0x3010053

6081

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__W 2

6082

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__M 0x3

6083

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB__PRE 0x0

6084

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_1 0x0

6085

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_2 0x1

6086

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_3 0x2

6087

#define OFDM_EQ_TOP_TD_TPS_FRM_NMB_4 0x3

6088

6089

6090

#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054

6091

#define OFDM_EQ_TOP_TD_TPS_CONST__W 2

6092

#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3

6093

#define OFDM_EQ_TOP_TD_TPS_CONST__PRE 0x0

6094

#define OFDM_EQ_TOP_TD_TPS_CONST_QPSK 0x0

6095

#define OFDM_EQ_TOP_TD_TPS_CONST_16QAM 0x1

6096

#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2

6097

6098

6099

#define OFDM_EQ_TOP_TD_TPS_HINFO__A 0x3010055

6100

#define OFDM_EQ_TOP_TD_TPS_HINFO__W 3

6101

#define OFDM_EQ_TOP_TD_TPS_HINFO__M 0x7

6102

#define OFDM_EQ_TOP_TD_TPS_HINFO__PRE 0x0

6103

#define OFDM_EQ_TOP_TD_TPS_HINFO_NH 0x0

6104

#define OFDM_EQ_TOP_TD_TPS_HINFO_H1 0x1

6105

#define OFDM_EQ_TOP_TD_TPS_HINFO_H2 0x2

6106

#define OFDM_EQ_TOP_TD_TPS_HINFO_H4 0x3

6107

6108

6109

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056

6110

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__W 3

6111

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7

6112

#define OFDM_EQ_TOP_TD_TPS_CODE_HP__PRE 0x0

6113

#define OFDM_EQ_TOP_TD_TPS_CODE_HP_1_2 0x0

6114

#define OFDM_EQ_TOP_TD_TPS_CODE_HP_2_3 0x1

6115

#define OFDM_EQ_TOP_TD_TPS_CODE_HP_3_4 0x2

6116

#define OFDM_EQ_TOP_TD_TPS_CODE_HP_5_6 0x3

6117

#define OFDM_EQ_TOP_TD_TPS_CODE_HP_7_8 0x4

6118

6119

6120

#define OFDM_EQ_TOP_TD_TPS_CODE_LP__A 0x3010057

6121

#define OFDM_EQ_TOP_TD_TPS_CODE_LP__W 3

6122

#define OFDM_EQ_TOP_TD_TPS_CODE_LP__M 0x7

6123

#define OFDM_EQ_TOP_TD_TPS_CODE_LP__PRE 0x0

6124

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_1_2 0x0

6125

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_2_3 0x1

6126

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_3_4 0x2

6127

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_5_6 0x3

6128

#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4

6129

6130

6131

#define OFDM_EQ_TOP_TD_TPS_GUARD__A 0x3010058

6132

#define OFDM_EQ_TOP_TD_TPS_GUARD__W 2

6133

#define OFDM_EQ_TOP_TD_TPS_GUARD__M 0x3

6134

#define OFDM_EQ_TOP_TD_TPS_GUARD__PRE 0x0

6135

#define OFDM_EQ_TOP_TD_TPS_GUARD_32 0x0

6136

#define OFDM_EQ_TOP_TD_TPS_GUARD_16 0x1

6137

#define OFDM_EQ_TOP_TD_TPS_GUARD_08 0x2

6138

#define OFDM_EQ_TOP_TD_TPS_GUARD_04 0x3

6139

6140

6141

#define OFDM_EQ_TOP_TD_TPS_TR_MODE__A 0x3010059

6142

#define OFDM_EQ_TOP_TD_TPS_TR_MODE__W 2

6143

#define OFDM_EQ_TOP_TD_TPS_TR_MODE__M 0x3

6144

#define OFDM_EQ_TOP_TD_TPS_TR_MODE__PRE 0x0

6145

#define OFDM_EQ_TOP_TD_TPS_TR_MODE_2K 0x0

6146

#define OFDM_EQ_TOP_TD_TPS_TR_MODE_8K 0x1

6147

6148

6149

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__A 0x301005A

6150

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__W 8

6151

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__M 0xFF

6152

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_HI__PRE 0x0

6153

6154

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__A 0x301005B

6155

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__W 8

6156

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__M 0xFF

6157

#define OFDM_EQ_TOP_TD_TPS_CELL_ID_LO__PRE 0x0

6158

6159

#define OFDM_EQ_TOP_TD_TPS_RSV__A 0x301005C

6160

#define OFDM_EQ_TOP_TD_TPS_RSV__W 6

6161

#define OFDM_EQ_TOP_TD_TPS_RSV__M 0x3F

6162

#define OFDM_EQ_TOP_TD_TPS_RSV__PRE 0x0

6163

6164

#define OFDM_EQ_TOP_TD_TPS_BCH__A 0x301005D

6165

#define OFDM_EQ_TOP_TD_TPS_BCH__W 14

6166

#define OFDM_EQ_TOP_TD_TPS_BCH__M 0x3FFF

6167

#define OFDM_EQ_TOP_TD_TPS_BCH__PRE 0x0

6168

6169

#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E

6170

#define OFDM_EQ_TOP_TD_SQR_ERR_I__W 16

6171

#define OFDM_EQ_TOP_TD_SQR_ERR_I__M 0xFFFF

6172

#define OFDM_EQ_TOP_TD_SQR_ERR_I__PRE 0x0

6173

6174

#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F

6175

#define OFDM_EQ_TOP_TD_SQR_ERR_Q__W 16

6176

#define OFDM_EQ_TOP_TD_SQR_ERR_Q__M 0xFFFF

6177

#define OFDM_EQ_TOP_TD_SQR_ERR_Q__PRE 0x0

6178

6179

#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060

6180

#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__W 4

6181

#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__M 0xF

6182

#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__PRE 0x0

6183

6184

#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061

6185

#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__W 16

6186

#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__M 0xFFFF

6187

#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__PRE 0x200

6188

6189

#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062

6190

#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__W 10

6191

#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__M 0x3FF

6192

#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__PRE 0x19F

#define OFDM_FE_COMM_EXEC__A 0x2000000

6199

#define OFDM_FE_COMM_EXEC__W 3

6200

#define OFDM_FE_COMM_EXEC__M 0x7

6201

#define OFDM_FE_COMM_EXEC__PRE 0x0

6202

#define OFDM_FE_COMM_EXEC_STOP 0x0

6203

#define OFDM_FE_COMM_EXEC_ACTIVE 0x1

6204

#define OFDM_FE_COMM_EXEC_HOLD 0x2

6205

#define OFDM_FE_COMM_EXEC_STEP 0x3

6206

6207

#define OFDM_FE_COMM_STATE__A 0x2000001

6208

#define OFDM_FE_COMM_STATE__W 16

6209

#define OFDM_FE_COMM_STATE__M 0xFFFF

6210

#define OFDM_FE_COMM_STATE__PRE 0x0

6211

#define OFDM_FE_COMM_MB__A 0x2000002

6212

#define OFDM_FE_COMM_MB__W 16

6213

#define OFDM_FE_COMM_MB__M 0xFFFF

6214

#define OFDM_FE_COMM_MB__PRE 0x0

6215

#define OFDM_FE_COMM_INT_REQ__A 0x2000004

6216

#define OFDM_FE_COMM_INT_REQ__W 16

6217

#define OFDM_FE_COMM_INT_REQ__M 0xFFFF

6218

#define OFDM_FE_COMM_INT_REQ__PRE 0x0

6219

#define OFDM_FE_COMM_INT_REQ_CU_REQ__B 0

6220

#define OFDM_FE_COMM_INT_REQ_CU_REQ__W 1

6221

#define OFDM_FE_COMM_INT_REQ_CU_REQ__M 0x1

6222

#define OFDM_FE_COMM_INT_REQ_CU_REQ__PRE 0x0

6223

6224

#define OFDM_FE_COMM_INT_STA__A 0x2000005

6225

#define OFDM_FE_COMM_INT_STA__W 16

6226

#define OFDM_FE_COMM_INT_STA__M 0xFFFF

6227

#define OFDM_FE_COMM_INT_STA__PRE 0x0

6228

#define OFDM_FE_COMM_INT_MSK__A 0x2000006

6229

#define OFDM_FE_COMM_INT_MSK__W 16

6230

#define OFDM_FE_COMM_INT_MSK__M 0xFFFF

6231

#define OFDM_FE_COMM_INT_MSK__PRE 0x0

6232

#define OFDM_FE_COMM_INT_STM__A 0x2000007

6233

#define OFDM_FE_COMM_INT_STM__W 16

6234

#define OFDM_FE_COMM_INT_STM__M 0xFFFF

6235

#define OFDM_FE_COMM_INT_STM__PRE 0x0

6236

#define OFDM_FE_COMM_INT_STM_INT_MSK__B 0

6237

#define OFDM_FE_COMM_INT_STM_INT_MSK__W 16

6238

#define OFDM_FE_COMM_INT_STM_INT_MSK__M 0xFFFF

6239

#define OFDM_FE_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_FE_CU_COMM_EXEC__A 0x2010000

6244

#define OFDM_FE_CU_COMM_EXEC__W 3

6245

#define OFDM_FE_CU_COMM_EXEC__M 0x7

6246

#define OFDM_FE_CU_COMM_EXEC__PRE 0x0

6247

#define OFDM_FE_CU_COMM_EXEC_STOP 0x0

6248

#define OFDM_FE_CU_COMM_EXEC_ACTIVE 0x1

6249

#define OFDM_FE_CU_COMM_EXEC_HOLD 0x2

6250

#define OFDM_FE_CU_COMM_EXEC_STEP 0x3

6251

6252

#define OFDM_FE_CU_COMM_STATE__A 0x2010001

6253

#define OFDM_FE_CU_COMM_STATE__W 4

6254

#define OFDM_FE_CU_COMM_STATE__M 0xF

6255

#define OFDM_FE_CU_COMM_STATE__PRE 0x0

6256

#define OFDM_FE_CU_COMM_MB__A 0x2010002

6257

#define OFDM_FE_CU_COMM_MB__W 2

6258

#define OFDM_FE_CU_COMM_MB__M 0x3

6259

#define OFDM_FE_CU_COMM_MB__PRE 0x0

6260

#define OFDM_FE_CU_COMM_MB_CTL__B 0

6261

#define OFDM_FE_CU_COMM_MB_CTL__W 1

6262

#define OFDM_FE_CU_COMM_MB_CTL__M 0x1

6263

#define OFDM_FE_CU_COMM_MB_CTL__PRE 0x0

6264

#define OFDM_FE_CU_COMM_MB_CTL_OFF 0x0

6265

#define OFDM_FE_CU_COMM_MB_CTL_ON 0x1

6266

#define OFDM_FE_CU_COMM_MB_OBS__B 1

6267

#define OFDM_FE_CU_COMM_MB_OBS__W 1

6268

#define OFDM_FE_CU_COMM_MB_OBS__M 0x2

6269

#define OFDM_FE_CU_COMM_MB_OBS__PRE 0x0

6270

#define OFDM_FE_CU_COMM_MB_OBS_OFF 0x0

6271

#define OFDM_FE_CU_COMM_MB_OBS_ON 0x2

6272

6273

#define OFDM_FE_CU_COMM_INT_REQ__A 0x2010004

6274

#define OFDM_FE_CU_COMM_INT_REQ__W 1

6275

#define OFDM_FE_CU_COMM_INT_REQ__M 0x1

6276

#define OFDM_FE_CU_COMM_INT_REQ__PRE 0x0

6277

#define OFDM_FE_CU_COMM_INT_STA__A 0x2010005

6278

#define OFDM_FE_CU_COMM_INT_STA__W 4

6279

#define OFDM_FE_CU_COMM_INT_STA__M 0xF

6280

#define OFDM_FE_CU_COMM_INT_STA__PRE 0x0

6281

#define OFDM_FE_CU_COMM_INT_STA_FE_START__B 0

6282

#define OFDM_FE_CU_COMM_INT_STA_FE_START__W 1

6283

#define OFDM_FE_CU_COMM_INT_STA_FE_START__M 0x1

6284

#define OFDM_FE_CU_COMM_INT_STA_FE_START__PRE 0x0

6285

#define OFDM_FE_CU_COMM_INT_STA_FT_START__B 1

6286

#define OFDM_FE_CU_COMM_INT_STA_FT_START__W 1

6287

#define OFDM_FE_CU_COMM_INT_STA_FT_START__M 0x2

6288

#define OFDM_FE_CU_COMM_INT_STA_FT_START__PRE 0x0

6289

#define OFDM_FE_CU_COMM_INT_STA_SB_START__B 2

6290

#define OFDM_FE_CU_COMM_INT_STA_SB_START__W 1

6291

#define OFDM_FE_CU_COMM_INT_STA_SB_START__M 0x4

6292

#define OFDM_FE_CU_COMM_INT_STA_SB_START__PRE 0x0

6293

#define OFDM_FE_CU_COMM_INT_STA_NF_READY__B 3

6294

#define OFDM_FE_CU_COMM_INT_STA_NF_READY__W 1

6295

#define OFDM_FE_CU_COMM_INT_STA_NF_READY__M 0x8

6296

#define OFDM_FE_CU_COMM_INT_STA_NF_READY__PRE 0x0

6297

6298

#define OFDM_FE_CU_COMM_INT_MSK__A 0x2010006

6299

#define OFDM_FE_CU_COMM_INT_MSK__W 4

6300

#define OFDM_FE_CU_COMM_INT_MSK__M 0xF

6301

#define OFDM_FE_CU_COMM_INT_MSK__PRE 0x0

6302

#define OFDM_FE_CU_COMM_INT_MSK_FE_START__B 0

6303

#define OFDM_FE_CU_COMM_INT_MSK_FE_START__W 1

6304

#define OFDM_FE_CU_COMM_INT_MSK_FE_START__M 0x1

6305

#define OFDM_FE_CU_COMM_INT_MSK_FE_START__PRE 0x0

6306

#define OFDM_FE_CU_COMM_INT_MSK_FT_START__B 1

6307

#define OFDM_FE_CU_COMM_INT_MSK_FT_START__W 1

6308

#define OFDM_FE_CU_COMM_INT_MSK_FT_START__M 0x2

6309

#define OFDM_FE_CU_COMM_INT_MSK_FT_START__PRE 0x0

6310

#define OFDM_FE_CU_COMM_INT_MSK_SB_START__B 2

6311

#define OFDM_FE_CU_COMM_INT_MSK_SB_START__W 1

6312

#define OFDM_FE_CU_COMM_INT_MSK_SB_START__M 0x4

6313

#define OFDM_FE_CU_COMM_INT_MSK_SB_START__PRE 0x0

6314

#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__B 3

6315

#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__W 1

6316

#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__M 0x8

6317

#define OFDM_FE_CU_COMM_INT_MSK_NF_READY__PRE 0x0

6318

6319

#define OFDM_FE_CU_COMM_INT_STM__A 0x2010007

6320

#define OFDM_FE_CU_COMM_INT_STM__W 4

6321

#define OFDM_FE_CU_COMM_INT_STM__M 0xF

6322

#define OFDM_FE_CU_COMM_INT_STM__PRE 0x0

6323

#define OFDM_FE_CU_COMM_INT_STM_FE_START__B 0

6324

#define OFDM_FE_CU_COMM_INT_STM_FE_START__W 1

6325

#define OFDM_FE_CU_COMM_INT_STM_FE_START__M 0x1

6326

#define OFDM_FE_CU_COMM_INT_STM_FE_START__PRE 0x0

6327

#define OFDM_FE_CU_COMM_INT_STM_FT_START__B 1

6328

#define OFDM_FE_CU_COMM_INT_STM_FT_START__W 1

6329

#define OFDM_FE_CU_COMM_INT_STM_FT_START__M 0x2

6330

#define OFDM_FE_CU_COMM_INT_STM_FT_START__PRE 0x0

6331

#define OFDM_FE_CU_COMM_INT_STM_SB_START__B 2

6332

#define OFDM_FE_CU_COMM_INT_STM_SB_START__W 1

6333

#define OFDM_FE_CU_COMM_INT_STM_SB_START__M 0x4

6334

#define OFDM_FE_CU_COMM_INT_STM_SB_START__PRE 0x0

6335

#define OFDM_FE_CU_COMM_INT_STM_NF_READY__B 3

6336

#define OFDM_FE_CU_COMM_INT_STM_NF_READY__W 1

6337

#define OFDM_FE_CU_COMM_INT_STM_NF_READY__M 0x8

6338

#define OFDM_FE_CU_COMM_INT_STM_NF_READY__PRE 0x0

6339

6340

#define OFDM_FE_CU_MODE__A 0x2010010

6341

#define OFDM_FE_CU_MODE__W 8

6342

#define OFDM_FE_CU_MODE__M 0xFF

6343

#define OFDM_FE_CU_MODE__PRE 0x20

6344

6345

#define OFDM_FE_CU_MODE_FFT__B 0

6346

#define OFDM_FE_CU_MODE_FFT__W 1

6347

#define OFDM_FE_CU_MODE_FFT__M 0x1

6348

#define OFDM_FE_CU_MODE_FFT__PRE 0x0

6349

#define OFDM_FE_CU_MODE_FFT_M8K 0x0

6350

#define OFDM_FE_CU_MODE_FFT_M2K 0x1

6351

6352

#define OFDM_FE_CU_MODE_COR__B 1

6353

#define OFDM_FE_CU_MODE_COR__W 1

6354

#define OFDM_FE_CU_MODE_COR__M 0x2

6355

#define OFDM_FE_CU_MODE_COR__PRE 0x0

6356

#define OFDM_FE_CU_MODE_COR_OFF 0x0

6357

#define OFDM_FE_CU_MODE_COR_ON 0x2

6358

6359

#define OFDM_FE_CU_MODE_IFD__B 2

6360

#define OFDM_FE_CU_MODE_IFD__W 1

6361

#define OFDM_FE_CU_MODE_IFD__M 0x4

6362

#define OFDM_FE_CU_MODE_IFD__PRE 0x0

6363

#define OFDM_FE_CU_MODE_IFD_ENABLE 0x0

6364

#define OFDM_FE_CU_MODE_IFD_DISABLE 0x4

6365

6366

#define OFDM_FE_CU_MODE_SEL__B 3

6367

#define OFDM_FE_CU_MODE_SEL__W 1

6368

#define OFDM_FE_CU_MODE_SEL__M 0x8

6369

#define OFDM_FE_CU_MODE_SEL__PRE 0x0

6370

#define OFDM_FE_CU_MODE_SEL_COR 0x0

6371

#define OFDM_FE_CU_MODE_SEL_COR_NFC 0x8

6372

6373

#define OFDM_FE_CU_MODE_FES__B 4

6374

#define OFDM_FE_CU_MODE_FES__W 1

6375

#define OFDM_FE_CU_MODE_FES__M 0x10

6376

#define OFDM_FE_CU_MODE_FES__PRE 0x0

6377

#define OFDM_FE_CU_MODE_FES_SEL_RST 0x0

6378

#define OFDM_FE_CU_MODE_FES_SEL_UPD 0x10

6379

#define OFDM_FE_CU_MODE_AVG__B 5

6380

#define OFDM_FE_CU_MODE_AVG__W 1

6381

#define OFDM_FE_CU_MODE_AVG__M 0x20

6382

#define OFDM_FE_CU_MODE_AVG__PRE 0x20

6383

#define OFDM_FE_CU_MODE_AVG_OFF 0x0

6384

#define OFDM_FE_CU_MODE_AVG_ON 0x20

6385

#define OFDM_FE_CU_MODE_SHF_ENA__B 6

6386

#define OFDM_FE_CU_MODE_SHF_ENA__W 1

6387

#define OFDM_FE_CU_MODE_SHF_ENA__M 0x40

6388

#define OFDM_FE_CU_MODE_SHF_ENA__PRE 0x0

6389

#define OFDM_FE_CU_MODE_SHF_ENA_OFF 0x0

6390

#define OFDM_FE_CU_MODE_SHF_ENA_ON 0x40

6391

#define OFDM_FE_CU_MODE_SHF_DIR__B 7

6392

#define OFDM_FE_CU_MODE_SHF_DIR__W 1

6393

#define OFDM_FE_CU_MODE_SHF_DIR__M 0x80

6394

#define OFDM_FE_CU_MODE_SHF_DIR__PRE 0x0

6395

#define OFDM_FE_CU_MODE_SHF_DIR_POS 0x0

6396

#define OFDM_FE_CU_MODE_SHF_DIR_NEG 0x80

6397

6398

6399

#define OFDM_FE_CU_FRM_CNT_RST__A 0x2010011

6400

#define OFDM_FE_CU_FRM_CNT_RST__W 15

6401

#define OFDM_FE_CU_FRM_CNT_RST__M 0x7FFF

6402

#define OFDM_FE_CU_FRM_CNT_RST__PRE 0x20FF

6403

6404

#define OFDM_FE_CU_FRM_CNT_STR__A 0x2010012

6405

#define OFDM_FE_CU_FRM_CNT_STR__W 15

6406

#define OFDM_FE_CU_FRM_CNT_STR__M 0x7FFF

6407

#define OFDM_FE_CU_FRM_CNT_STR__PRE 0x1E

6408

6409

#define OFDM_FE_CU_FRM_SMP_CNT__A 0x2010013

6410

#define OFDM_FE_CU_FRM_SMP_CNT__W 15

6411

#define OFDM_FE_CU_FRM_SMP_CNT__M 0x7FFF

6412

#define OFDM_FE_CU_FRM_SMP_CNT__PRE 0x0

6413

6414

#define OFDM_FE_CU_FRM_SMB_CNT__A 0x2010014

6415

#define OFDM_FE_CU_FRM_SMB_CNT__W 16

6416

#define OFDM_FE_CU_FRM_SMB_CNT__M 0xFFFF

6417

#define OFDM_FE_CU_FRM_SMB_CNT__PRE 0x0

6418

6419

#define OFDM_FE_CU_CMP_MAX_DAT__A 0x2010015

6420

#define OFDM_FE_CU_CMP_MAX_DAT__W 12

6421

#define OFDM_FE_CU_CMP_MAX_DAT__M 0xFFF

6422

#define OFDM_FE_CU_CMP_MAX_DAT__PRE 0x0

6423

6424

#define OFDM_FE_CU_CMP_MAX_ADR__A 0x2010016

6425

#define OFDM_FE_CU_CMP_MAX_ADR__W 10

6426

#define OFDM_FE_CU_CMP_MAX_ADR__M 0x3FF

6427

#define OFDM_FE_CU_CMP_MAX_ADR__PRE 0x0

6428

6429

#define OFDM_FE_CU_CMP_MAX_RE__A 0x2010017

6430

#define OFDM_FE_CU_CMP_MAX_RE__W 12

6431

#define OFDM_FE_CU_CMP_MAX_RE__M 0xFFF

6432

#define OFDM_FE_CU_CMP_MAX_RE__PRE 0x0

6433

6434

#define OFDM_FE_CU_CMP_MAX_IM__A 0x2010018

6435

#define OFDM_FE_CU_CMP_MAX_IM__W 12

6436

#define OFDM_FE_CU_CMP_MAX_IM__M 0xFFF

6437

#define OFDM_FE_CU_CMP_MAX_IM__PRE 0x0

6438

6439

#define OFDM_FE_CU_BUF_NFC_DEL__A 0x201001F

6440

#define OFDM_FE_CU_BUF_NFC_DEL__W 14

6441

#define OFDM_FE_CU_BUF_NFC_DEL__M 0x3FFF

6442

#define OFDM_FE_CU_BUF_NFC_DEL__PRE 0x0

6443

6444

#define OFDM_FE_CU_CTR_NFC_ICR__A 0x2010020

6445

#define OFDM_FE_CU_CTR_NFC_ICR__W 5

6446

#define OFDM_FE_CU_CTR_NFC_ICR__M 0x1F

6447

#define OFDM_FE_CU_CTR_NFC_ICR__PRE 0x1

6448

6449

#define OFDM_FE_CU_CTR_NFC_OCR__A 0x2010021

6450

#define OFDM_FE_CU_CTR_NFC_OCR__W 15

6451

#define OFDM_FE_CU_CTR_NFC_OCR__M 0x7FFF

6452

#define OFDM_FE_CU_CTR_NFC_OCR__PRE 0x61A8

6453

6454

#define OFDM_FE_CU_CTR_NFC_CNT__A 0x2010022

6455

#define OFDM_FE_CU_CTR_NFC_CNT__W 15

6456

#define OFDM_FE_CU_CTR_NFC_CNT__M 0x7FFF

6457

#define OFDM_FE_CU_CTR_NFC_CNT__PRE 0x0

6458

6459

#define OFDM_FE_CU_CTR_NFC_STS__A 0x2010023

6460

#define OFDM_FE_CU_CTR_NFC_STS__W 3

6461

#define OFDM_FE_CU_CTR_NFC_STS__M 0x7

6462

#define OFDM_FE_CU_CTR_NFC_STS__PRE 0x0

6463

#define OFDM_FE_CU_CTR_NFC_STS_RUN 0x0

6464

#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_IMA 0x1

6465

#define OFDM_FE_CU_CTR_NFC_STS_ACC_MAX_REA 0x2

6466

#define OFDM_FE_CU_CTR_NFC_STS_CNT_MAX 0x4

6467

6468

6469

#define OFDM_FE_CU_DIV_NFC_REA__A 0x2010024

6470

#define OFDM_FE_CU_DIV_NFC_REA__W 14

6471

#define OFDM_FE_CU_DIV_NFC_REA__M 0x3FFF

6472

#define OFDM_FE_CU_DIV_NFC_REA__PRE 0x0

6473

6474

#define OFDM_FE_CU_DIV_NFC_IMA__A 0x2010025

6475

#define OFDM_FE_CU_DIV_NFC_IMA__W 14

6476

#define OFDM_FE_CU_DIV_NFC_IMA__M 0x3FFF

6477

#define OFDM_FE_CU_DIV_NFC_IMA__PRE 0x0

6478

6479

#define OFDM_FE_CU_FRM_CNT_UPD__A 0x2010026

6480

#define OFDM_FE_CU_FRM_CNT_UPD__W 15

6481

#define OFDM_FE_CU_FRM_CNT_UPD__M 0x7FFF

6482

#define OFDM_FE_CU_FRM_CNT_UPD__PRE 0x20FF

6483

6484

#define OFDM_FE_CU_DIV_NFC_CLP__A 0x2010027

6485

#define OFDM_FE_CU_DIV_NFC_CLP__W 2

6486

#define OFDM_FE_CU_DIV_NFC_CLP__M 0x3

6487

#define OFDM_FE_CU_DIV_NFC_CLP__PRE 0x0

6488

#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S11 0x0

6489

#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S12 0x1

6490

#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S13 0x2

6491

#define OFDM_FE_CU_DIV_NFC_CLP_CLIP_S14 0x3

6492

6493

6494

#define OFDM_FE_CU_CMP_MAX_32__A 0x2010028

6495

#define OFDM_FE_CU_CMP_MAX_32__W 12

6496

#define OFDM_FE_CU_CMP_MAX_32__M 0xFFF

6497

#define OFDM_FE_CU_CMP_MAX_32__PRE 0x0

6498

6499

#define OFDM_FE_CU_CMP_MAX_16__A 0x2010029

6500

#define OFDM_FE_CU_CMP_MAX_16__W 12

6501

#define OFDM_FE_CU_CMP_MAX_16__M 0xFFF

6502

#define OFDM_FE_CU_CMP_MAX_16__PRE 0x0

6503

6504

#define OFDM_FE_CU_CMP_MAX_8__A 0x201002A

6505

#define OFDM_FE_CU_CMP_MAX_8__W 12

6506

#define OFDM_FE_CU_CMP_MAX_8__M 0xFFF

6507

#define OFDM_FE_CU_CMP_MAX_8__PRE 0x0

6508

6509

#define OFDM_FE_CU_CMP_MAX_4__A 0x201002B

6510

#define OFDM_FE_CU_CMP_MAX_4__W 12

6511

#define OFDM_FE_CU_CMP_MAX_4__M 0xFFF

6512

#define OFDM_FE_CU_CMP_MAX_4__PRE 0x0

6513

6514

#define OFDM_FE_CU_CMP_SUM_32_RE__A 0x201002C

6515

#define OFDM_FE_CU_CMP_SUM_32_RE__W 14

6516

#define OFDM_FE_CU_CMP_SUM_32_RE__M 0x3FFF

6517

#define OFDM_FE_CU_CMP_SUM_32_RE__PRE 0x0

6518

6519

#define OFDM_FE_CU_CMP_SUM_32_IM__A 0x201002D

6520

#define OFDM_FE_CU_CMP_SUM_32_IM__W 14

6521

#define OFDM_FE_CU_CMP_SUM_32_IM__M 0x3FFF

6522

#define OFDM_FE_CU_CMP_SUM_32_IM__PRE 0x0

6523

6524

#define OFDM_FE_CU_CMP_SUM_16_RE__A 0x201002E

6525

#define OFDM_FE_CU_CMP_SUM_16_RE__W 14

6526

#define OFDM_FE_CU_CMP_SUM_16_RE__M 0x3FFF

6527

#define OFDM_FE_CU_CMP_SUM_16_RE__PRE 0x0

6528

6529

#define OFDM_FE_CU_CMP_SUM_16_IM__A 0x201002F

6530

#define OFDM_FE_CU_CMP_SUM_16_IM__W 14

6531

#define OFDM_FE_CU_CMP_SUM_16_IM__M 0x3FFF

6532

#define OFDM_FE_CU_CMP_SUM_16_IM__PRE 0x0

6533

6534

#define OFDM_FE_CU_CMP_SUM_8_RE__A 0x2010030

6535

#define OFDM_FE_CU_CMP_SUM_8_RE__W 14

6536

#define OFDM_FE_CU_CMP_SUM_8_RE__M 0x3FFF

6537

#define OFDM_FE_CU_CMP_SUM_8_RE__PRE 0x0

6538

6539

#define OFDM_FE_CU_CMP_SUM_8_IM__A 0x2010031

6540

#define OFDM_FE_CU_CMP_SUM_8_IM__W 14

6541

#define OFDM_FE_CU_CMP_SUM_8_IM__M 0x3FFF

6542

#define OFDM_FE_CU_CMP_SUM_8_IM__PRE 0x0

6543

6544

#define OFDM_FE_CU_CMP_SUM_4_RE__A 0x2010032

6545

#define OFDM_FE_CU_CMP_SUM_4_RE__W 14

6546

#define OFDM_FE_CU_CMP_SUM_4_RE__M 0x3FFF

6547

#define OFDM_FE_CU_CMP_SUM_4_RE__PRE 0x0

6548

6549

#define OFDM_FE_CU_CMP_SUM_4_IM__A 0x2010033

6550

#define OFDM_FE_CU_CMP_SUM_4_IM__W 14

6551

#define OFDM_FE_CU_CMP_SUM_4_IM__M 0x3FFF

6552

#define OFDM_FE_CU_CMP_SUM_4_IM__PRE 0x0

#define OFDM_FE_CU_BUF_RAM__A 0x2020000

#define OFDM_FE_CU_CMP_RAM__A 0x2030000

#define OFDM_FT_COMM_EXEC__A 0x2400000

6567

#define OFDM_FT_COMM_EXEC__W 3

6568

#define OFDM_FT_COMM_EXEC__M 0x7

6569

#define OFDM_FT_COMM_EXEC__PRE 0x0

6570

#define OFDM_FT_COMM_EXEC_STOP 0x0

6571

#define OFDM_FT_COMM_EXEC_ACTIVE 0x1

6572

#define OFDM_FT_COMM_EXEC_HOLD 0x2

6573

#define OFDM_FT_COMM_EXEC_STEP 0x3

6574

#define OFDM_FT_COMM_EXEC_BYPASS_STOP 0x4

6575

#define OFDM_FT_COMM_EXEC_BYPASS_HOLD 0x6

6576

6577

#define OFDM_FT_COMM_STATE__A 0x2400001

6578

#define OFDM_FT_COMM_STATE__W 16

6579

#define OFDM_FT_COMM_STATE__M 0xFFFF

6580

#define OFDM_FT_COMM_STATE__PRE 0x0

6581

#define OFDM_FT_COMM_MB__A 0x2400002

6582

#define OFDM_FT_COMM_MB__W 16

6583

#define OFDM_FT_COMM_MB__M 0xFFFF

6584

#define OFDM_FT_COMM_MB__PRE 0x0

#define OFDM_FT_TOP_COMM_EXEC__A 0x2410000

6589

#define OFDM_FT_TOP_COMM_EXEC__W 3

6590

#define OFDM_FT_TOP_COMM_EXEC__M 0x7

6591

#define OFDM_FT_TOP_COMM_EXEC__PRE 0x0

6592

#define OFDM_FT_TOP_COMM_EXEC_STOP 0x0

6593

#define OFDM_FT_TOP_COMM_EXEC_ACTIVE 0x1

6594

#define OFDM_FT_TOP_COMM_EXEC_HOLD 0x2

6595

#define OFDM_FT_TOP_COMM_EXEC_STEP 0x3

6596

6597

#define OFDM_FT_TOP_COMM_MB__A 0x2410002

6598

#define OFDM_FT_TOP_COMM_MB__W 2

6599

#define OFDM_FT_TOP_COMM_MB__M 0x3

6600

#define OFDM_FT_TOP_COMM_MB__PRE 0x0

6601

#define OFDM_FT_TOP_COMM_MB_CTL__B 0

6602

#define OFDM_FT_TOP_COMM_MB_CTL__W 1

6603

#define OFDM_FT_TOP_COMM_MB_CTL__M 0x1

6604

#define OFDM_FT_TOP_COMM_MB_CTL__PRE 0x0

6605

#define OFDM_FT_TOP_COMM_MB_CTL_OFF 0x0

6606

#define OFDM_FT_TOP_COMM_MB_CTL_ON 0x1

6607

#define OFDM_FT_TOP_COMM_MB_OBS__B 1

6608

#define OFDM_FT_TOP_COMM_MB_OBS__W 1

6609

#define OFDM_FT_TOP_COMM_MB_OBS__M 0x2

6610

#define OFDM_FT_TOP_COMM_MB_OBS__PRE 0x0

6611

#define OFDM_FT_TOP_COMM_MB_OBS_OFF 0x0

6612

#define OFDM_FT_TOP_COMM_MB_OBS_ON 0x2

6613

6614

6615

#define OFDM_FT_TOP_MODE_2K__A 0x2410010

6616

#define OFDM_FT_TOP_MODE_2K__W 1

6617

#define OFDM_FT_TOP_MODE_2K__M 0x1

6618

#define OFDM_FT_TOP_MODE_2K__PRE 0x0

6619

#define OFDM_FT_TOP_MODE_2K_MODE_8K 0x0

6620

#define OFDM_FT_TOP_MODE_2K_MODE_2K 0x1

6621

6622

6623

#define OFDM_FT_TOP_NORM_OFF__A 0x2410016

6624

#define OFDM_FT_TOP_NORM_OFF__W 4

6625

#define OFDM_FT_TOP_NORM_OFF__M 0xF

6626

#define OFDM_FT_TOP_NORM_OFF__PRE 0x2

#define OFDM_FT_0TO2_0_RAM__A 0x2420000

#define OFDM_FT_0TO2_1_RAM__A 0x2430000

#define OFDM_FT_0TO2_2_RAM__A 0x2440000

#define OFDM_FT_3TO7_0_RAM__A 0x2450000

#define OFDM_FT_3TO7_1_RAM__A 0x2460000

#define OFDM_LC_COMM_EXEC__A 0x3800000

6653

#define OFDM_LC_COMM_EXEC__W 3

6654

#define OFDM_LC_COMM_EXEC__M 0x7

6655

#define OFDM_LC_COMM_EXEC__PRE 0x0

6656

#define OFDM_LC_COMM_EXEC_STOP 0x0

6657

#define OFDM_LC_COMM_EXEC_ACTIVE 0x1

6658

#define OFDM_LC_COMM_EXEC_HOLD 0x2

6659

#define OFDM_LC_COMM_EXEC_STEP 0x3

6660

#define OFDM_LC_COMM_EXEC_BYPASS_STOP 0x4

6661

#define OFDM_LC_COMM_EXEC_BYPASS_HOLD 0x6

6662

6663

#define OFDM_LC_COMM_STATE__A 0x3800001

6664

#define OFDM_LC_COMM_STATE__W 16

6665

#define OFDM_LC_COMM_STATE__M 0xFFFF

6666

#define OFDM_LC_COMM_STATE__PRE 0x0

6667

#define OFDM_LC_COMM_MB__A 0x3800002

6668

#define OFDM_LC_COMM_MB__W 16

6669

#define OFDM_LC_COMM_MB__M 0xFFFF

6670

#define OFDM_LC_COMM_MB__PRE 0x0

6671

#define OFDM_LC_COMM_INT_REQ__A 0x3800004

6672

#define OFDM_LC_COMM_INT_REQ__W 16

6673

#define OFDM_LC_COMM_INT_REQ__M 0xFFFF

6674

#define OFDM_LC_COMM_INT_REQ__PRE 0x0

6675

#define OFDM_LC_COMM_INT_REQ_CT_REQ__B 6

6676

#define OFDM_LC_COMM_INT_REQ_CT_REQ__W 1

6677

#define OFDM_LC_COMM_INT_REQ_CT_REQ__M 0x40

6678

#define OFDM_LC_COMM_INT_REQ_CT_REQ__PRE 0x0

6679

6680

#define OFDM_LC_COMM_INT_STA__A 0x3800005

6681

#define OFDM_LC_COMM_INT_STA__W 16

6682

#define OFDM_LC_COMM_INT_STA__M 0xFFFF

6683

#define OFDM_LC_COMM_INT_STA__PRE 0x0

6684

#define OFDM_LC_COMM_INT_MSK__A 0x3800006

6685

#define OFDM_LC_COMM_INT_MSK__W 16

6686

#define OFDM_LC_COMM_INT_MSK__M 0xFFFF

6687

#define OFDM_LC_COMM_INT_MSK__PRE 0x0

6688

#define OFDM_LC_COMM_INT_STM__A 0x3800007

6689

#define OFDM_LC_COMM_INT_STM__W 16

6690

#define OFDM_LC_COMM_INT_STM__M 0xFFFF

6691

#define OFDM_LC_COMM_INT_STM__PRE 0x0

6692

#define OFDM_LC_COMM_INT_STM_INT_MSK__B 0

6693

#define OFDM_LC_COMM_INT_STM_INT_MSK__W 16

6694

#define OFDM_LC_COMM_INT_STM_INT_MSK__M 0xFFFF

6695

#define OFDM_LC_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_LC_CT_COMM_EXEC__A 0x3810000

6700

#define OFDM_LC_CT_COMM_EXEC__W 3

6701

#define OFDM_LC_CT_COMM_EXEC__M 0x7

6702

#define OFDM_LC_CT_COMM_EXEC__PRE 0x0

6703

#define OFDM_LC_CT_COMM_EXEC_STOP 0x0

6704

#define OFDM_LC_CT_COMM_EXEC_ACTIVE 0x1

6705

#define OFDM_LC_CT_COMM_EXEC_HOLD 0x2

6706

#define OFDM_LC_CT_COMM_EXEC_STEP 0x3

6707

6708

6709

#define OFDM_LC_CT_COMM_STATE__A 0x3810001

6710

#define OFDM_LC_CT_COMM_STATE__W 10

6711

#define OFDM_LC_CT_COMM_STATE__M 0x3FF

6712

#define OFDM_LC_CT_COMM_STATE__PRE 0x0

6713

#define OFDM_LC_CT_COMM_INT_REQ__A 0x3810004

6714

#define OFDM_LC_CT_COMM_INT_REQ__W 1

6715

#define OFDM_LC_CT_COMM_INT_REQ__M 0x1

6716

#define OFDM_LC_CT_COMM_INT_REQ__PRE 0x0

6717

#define OFDM_LC_CT_COMM_INT_STA__A 0x3810005

6718

#define OFDM_LC_CT_COMM_INT_STA__W 1

6719

#define OFDM_LC_CT_COMM_INT_STA__M 0x1

6720

#define OFDM_LC_CT_COMM_INT_STA__PRE 0x0

6721

#define OFDM_LC_CT_COMM_INT_STA_REQUEST__B 0

6722

#define OFDM_LC_CT_COMM_INT_STA_REQUEST__W 1

6723

#define OFDM_LC_CT_COMM_INT_STA_REQUEST__M 0x1

6724

#define OFDM_LC_CT_COMM_INT_STA_REQUEST__PRE 0x0

6725

6726

#define OFDM_LC_CT_COMM_INT_MSK__A 0x3810006

6727

#define OFDM_LC_CT_COMM_INT_MSK__W 1

6728

#define OFDM_LC_CT_COMM_INT_MSK__M 0x1

6729

#define OFDM_LC_CT_COMM_INT_MSK__PRE 0x0

6730

#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__B 0

6731

#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__W 1

6732

#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__M 0x1

6733

#define OFDM_LC_CT_COMM_INT_MSK_REQUEST__PRE 0x0

6734

6735

#define OFDM_LC_CT_COMM_INT_STM__A 0x3810007

6736

#define OFDM_LC_CT_COMM_INT_STM__W 1

6737

#define OFDM_LC_CT_COMM_INT_STM__M 0x1

6738

#define OFDM_LC_CT_COMM_INT_STM__PRE 0x0

6739

#define OFDM_LC_CT_COMM_INT_STM_REQUEST__B 0

6740

#define OFDM_LC_CT_COMM_INT_STM_REQUEST__W 1

6741

#define OFDM_LC_CT_COMM_INT_STM_REQUEST__M 0x1

6742

#define OFDM_LC_CT_COMM_INT_STM_REQUEST__PRE 0x0

6743

6744

6745

#define OFDM_LC_CT_CTL_STK_0__A 0x3810010

6746

#define OFDM_LC_CT_CTL_STK_0__W 10

6747

#define OFDM_LC_CT_CTL_STK_0__M 0x3FF

6748

#define OFDM_LC_CT_CTL_STK_0__PRE 0x0

6749

6750

#define OFDM_LC_CT_CTL_STK_1__A 0x3810011

6751

#define OFDM_LC_CT_CTL_STK_1__W 10

6752

#define OFDM_LC_CT_CTL_STK_1__M 0x3FF

6753

#define OFDM_LC_CT_CTL_STK_1__PRE 0x0

6754

6755

#define OFDM_LC_CT_CTL_STK_2__A 0x3810012

6756

#define OFDM_LC_CT_CTL_STK_2__W 10

6757

#define OFDM_LC_CT_CTL_STK_2__M 0x3FF

6758

#define OFDM_LC_CT_CTL_STK_2__PRE 0x0

6759

6760

#define OFDM_LC_CT_CTL_STK_3__A 0x3810013

6761

#define OFDM_LC_CT_CTL_STK_3__W 10

6762

#define OFDM_LC_CT_CTL_STK_3__M 0x3FF

6763

#define OFDM_LC_CT_CTL_STK_3__PRE 0x0

6764

6765

#define OFDM_LC_CT_CTL_BPT_IDX__A 0x381001F

6766

#define OFDM_LC_CT_CTL_BPT_IDX__W 1

6767

#define OFDM_LC_CT_CTL_BPT_IDX__M 0x1

6768

#define OFDM_LC_CT_CTL_BPT_IDX__PRE 0x0

6769

6770

#define OFDM_LC_CT_CTL_BPT__A 0x3810020

6771

#define OFDM_LC_CT_CTL_BPT__W 10

6772

#define OFDM_LC_CT_CTL_BPT__M 0x3FF

6773

#define OFDM_LC_CT_CTL_BPT__PRE 0x0

#define OFDM_LC_RA_RAM__A 0x3820000

#define OFDM_LC_IF_RAM_TRP_BPT0_0__A 0x3830000

6783

#define OFDM_LC_IF_RAM_TRP_BPT0_0__W 12

6784

#define OFDM_LC_IF_RAM_TRP_BPT0_0__M 0xFFF

6785

#define OFDM_LC_IF_RAM_TRP_BPT0_0__PRE 0x0

6786

6787

#define OFDM_LC_IF_RAM_TRP_BPT0_1__A 0x3830001

6788

#define OFDM_LC_IF_RAM_TRP_BPT0_1__W 12

6789

#define OFDM_LC_IF_RAM_TRP_BPT0_1__M 0xFFF

6790

#define OFDM_LC_IF_RAM_TRP_BPT0_1__PRE 0x0

6791

6792

#define OFDM_LC_IF_RAM_TRP_STKU_0__A 0x3830002

6793

#define OFDM_LC_IF_RAM_TRP_STKU_0__W 12

6794

#define OFDM_LC_IF_RAM_TRP_STKU_0__M 0xFFF

6795

#define OFDM_LC_IF_RAM_TRP_STKU_0__PRE 0x0

6796

6797

#define OFDM_LC_IF_RAM_TRP_STKU_1__A 0x3830004

6798

#define OFDM_LC_IF_RAM_TRP_STKU_1__W 12

6799

#define OFDM_LC_IF_RAM_TRP_STKU_1__M 0xFFF

6800

#define OFDM_LC_IF_RAM_TRP_STKU_1__PRE 0x0

6801

6802

#define OFDM_LC_IF_RAM_TRP_WARM_0__A 0x3830006

6803

#define OFDM_LC_IF_RAM_TRP_WARM_0__W 12

6804

#define OFDM_LC_IF_RAM_TRP_WARM_0__M 0xFFF

6805

#define OFDM_LC_IF_RAM_TRP_WARM_0__PRE 0x0

6806

6807

#define OFDM_LC_IF_RAM_TRP_WARM_1__A 0x3830007

6808

#define OFDM_LC_IF_RAM_TRP_WARM_1__W 12

6809

#define OFDM_LC_IF_RAM_TRP_WARM_1__M 0xFFF

6810

#define OFDM_LC_IF_RAM_TRP_WARM_1__PRE 0x0

#define OFDM_LC_RA_RAM_PROC_DELAY_IF__A 0x3820006

6819

#define OFDM_LC_RA_RAM_PROC_DELAY_IF__W 16

6820

#define OFDM_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF

6821

#define OFDM_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6

6822

#define OFDM_LC_RA_RAM_PROC_DELAY_FS__A 0x3820007

6823

#define OFDM_LC_RA_RAM_PROC_DELAY_FS__W 16

6824

#define OFDM_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF

6825

#define OFDM_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3

6826

#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__A 0x3820008

6827

#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__W 16

6828

#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF

6829

#define OFDM_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8

6830

#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__A 0x3820009

6831

#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__W 16

6832

#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF

6833

#define OFDM_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46

6834

#define OFDM_LC_RA_RAM_LOCK_COUNT__A 0x382000A

6835

#define OFDM_LC_RA_RAM_LOCK_COUNT__W 16

6836

#define OFDM_LC_RA_RAM_LOCK_COUNT__M 0xFFFF

6837

#define OFDM_LC_RA_RAM_LOCK_COUNT__PRE 0x0

6838

#define OFDM_LC_RA_RAM_CPRTOFS_NOM__A 0x382000B

6839

#define OFDM_LC_RA_RAM_CPRTOFS_NOM__W 16

6840

#define OFDM_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF

6841

#define OFDM_LC_RA_RAM_CPRTOFS_NOM__PRE 0x0

6842

#define OFDM_LC_RA_RAM_IFINCR_NOM_L__A 0x382000C

6843

#define OFDM_LC_RA_RAM_IFINCR_NOM_L__W 16

6844

#define OFDM_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF

6845

#define OFDM_LC_RA_RAM_IFINCR_NOM_L__PRE 0x0

6846

#define OFDM_LC_RA_RAM_IFINCR_NOM_H__A 0x382000D

6847

#define OFDM_LC_RA_RAM_IFINCR_NOM_H__W 16

6848

#define OFDM_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF

6849

#define OFDM_LC_RA_RAM_IFINCR_NOM_H__PRE 0x0

6850

#define OFDM_LC_RA_RAM_FSINCR_NOM_L__A 0x382000E

6851

#define OFDM_LC_RA_RAM_FSINCR_NOM_L__W 16

6852

#define OFDM_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF

6853

#define OFDM_LC_RA_RAM_FSINCR_NOM_L__PRE 0x0

6854

#define OFDM_LC_RA_RAM_FSINCR_NOM_H__A 0x382000F

6855

#define OFDM_LC_RA_RAM_FSINCR_NOM_H__W 16

6856

#define OFDM_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF

6857

#define OFDM_LC_RA_RAM_FSINCR_NOM_H__PRE 0x0

6858

#define OFDM_LC_RA_RAM_MODE_2K__A 0x3820010

6859

#define OFDM_LC_RA_RAM_MODE_2K__W 16

6860

#define OFDM_LC_RA_RAM_MODE_2K__M 0xFFFF

6861

#define OFDM_LC_RA_RAM_MODE_2K__PRE 0x0

6862

#define OFDM_LC_RA_RAM_MODE_GUARD__A 0x3820011

6863

#define OFDM_LC_RA_RAM_MODE_GUARD__W 16

6864

#define OFDM_LC_RA_RAM_MODE_GUARD__M 0xFFFF

6865

#define OFDM_LC_RA_RAM_MODE_GUARD__PRE 0x0

6866

#define OFDM_LC_RA_RAM_MODE_GUARD_32 0x0

6867

#define OFDM_LC_RA_RAM_MODE_GUARD_16 0x1

6868

#define OFDM_LC_RA_RAM_MODE_GUARD_8 0x2

6869

#define OFDM_LC_RA_RAM_MODE_GUARD_4 0x3

6870

6871

#define OFDM_LC_RA_RAM_MODE_ADJUST__A 0x3820012

6872

#define OFDM_LC_RA_RAM_MODE_ADJUST__W 16

6873

#define OFDM_LC_RA_RAM_MODE_ADJUST__M 0xFFFF

6874

#define OFDM_LC_RA_RAM_MODE_ADJUST__PRE 0x0

6875

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0

6876

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1

6877

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1

6878

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_CRMM__PRE 0x0

6879

#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1

6880

#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1

6881

#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2

6882

#define OFDM_LC_RA_RAM_MODE_ADJUST_CE_CRMM__PRE 0x0

6883

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__B 2

6884

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__W 1

6885

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4

6886

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM__PRE 0x0

6887

#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__B 3

6888

#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__W 1

6889

#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8

6890

#define OFDM_LC_RA_RAM_MODE_ADJUST_PHASE__PRE 0x0

6891

#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__B 4

6892

#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__W 1

6893

#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10

6894

#define OFDM_LC_RA_RAM_MODE_ADJUST_DELAY__PRE 0x0

6895

#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5

6896

#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1

6897

#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20

6898

#define OFDM_LC_RA_RAM_MODE_ADJUST_OPENLOOP__PRE 0x0

6899

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6

6900

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1

6901

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40

6902

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_CP__PRE 0x0

6903

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7

6904

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1

6905

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80

6906

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_FS__PRE 0x0

6907

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8

6908

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1

6909

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100

6910

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_IF__PRE 0x0

6911

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9

6912

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1

6913

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200

6914

#define OFDM_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__PRE 0x0

6915

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10

6916

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1

6917

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400

6918

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__PRE 0x0

6919

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11

6920

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1

6921

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800

6922

#define OFDM_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__PRE 0x0

6923

#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__B 12

6924

#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__W 1

6925

#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__M 0x1000

6926

#define OFDM_LC_RA_RAM_MODE_ADJUST_CRMM_NO_FILT__PRE 0x0

6927

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__B 13

6928

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__W 1

6929

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__M 0x2000

6930

#define OFDM_LC_RA_RAM_MODE_ADJUST_SRMM_NO_FILT__PRE 0x0

6931

6932

#define OFDM_LC_RA_RAM_RC_STS__A 0x3820014

6933

#define OFDM_LC_RA_RAM_RC_STS__W 16

6934

#define OFDM_LC_RA_RAM_RC_STS__M 0xFFFF

6935

#define OFDM_LC_RA_RAM_RC_STS__PRE 0x0

6936

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x3820018

6937

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16

6938

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF

6939

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__PRE 0x0

6940

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x3820019

6941

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16

6942

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF

6943

#define OFDM_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__PRE 0x0

6944

#define OFDM_LC_RA_RAM_FILTER_SYM_SET__A 0x382001A

6945

#define OFDM_LC_RA_RAM_FILTER_SYM_SET__W 16

6946

#define OFDM_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF

6947

#define OFDM_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8

6948

#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__A 0x382001B

6949

#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__W 16

6950

#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF

6951

#define OFDM_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0

6952

#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__A 0x382001C

6953

#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__W 16

6954

#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF

6955

#define OFDM_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8

6956

#define OFDM_LC_RA_RAM_MAX_ABS_EXP__A 0x382001D

6957

#define OFDM_LC_RA_RAM_MAX_ABS_EXP__W 16

6958

#define OFDM_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF

6959

#define OFDM_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10

6960

#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x382001F

6961

#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__W 16

6962

#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF

6963

#define OFDM_LC_RA_RAM_ACTUAL_CP_CRMM__PRE 0x0

6964

#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x3820020

6965

#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__W 16

6966

#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF

6967

#define OFDM_LC_RA_RAM_ACTUAL_CE_CRMM__PRE 0x0

6968

#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x3820021

6969

#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__W 16

6970

#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF

6971

#define OFDM_LC_RA_RAM_ACTUAL_CE_SRMM__PRE 0x0

6972

#define OFDM_LC_RA_RAM_ACTUAL_PHASE__A 0x3820022

6973

#define OFDM_LC_RA_RAM_ACTUAL_PHASE__W 16

6974

#define OFDM_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF

6975

#define OFDM_LC_RA_RAM_ACTUAL_PHASE__PRE 0x0

6976

#define OFDM_LC_RA_RAM_ACTUAL_DELAY__A 0x3820023

6977

#define OFDM_LC_RA_RAM_ACTUAL_DELAY__W 16

6978

#define OFDM_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF

6979

#define OFDM_LC_RA_RAM_ACTUAL_DELAY__PRE 0x0

6980

#define OFDM_LC_RA_RAM_ADJUST_CRMM__A 0x3820024

6981

#define OFDM_LC_RA_RAM_ADJUST_CRMM__W 16

6982

#define OFDM_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF

6983

#define OFDM_LC_RA_RAM_ADJUST_CRMM__PRE 0x0

6984

#define OFDM_LC_RA_RAM_ADJUST_SRMM__A 0x3820025

6985

#define OFDM_LC_RA_RAM_ADJUST_SRMM__W 16

6986

#define OFDM_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF

6987

#define OFDM_LC_RA_RAM_ADJUST_SRMM__PRE 0x0

6988

#define OFDM_LC_RA_RAM_ADJUST_PHASE__A 0x3820026

6989

#define OFDM_LC_RA_RAM_ADJUST_PHASE__W 16

6990

#define OFDM_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF

6991

#define OFDM_LC_RA_RAM_ADJUST_PHASE__PRE 0x0

6992

#define OFDM_LC_RA_RAM_ADJUST_DELAY__A 0x3820027

6993

#define OFDM_LC_RA_RAM_ADJUST_DELAY__W 16

6994

#define OFDM_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF

6995

#define OFDM_LC_RA_RAM_ADJUST_DELAY__PRE 0x0

6996

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x3820028

6997

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__W 16

6998

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF

6999

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_0__PRE 0x0

7000

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x3820029

7001

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__W 16

7002

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF

7003

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_1__PRE 0x0

7004

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x382002A

7005

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16

7006

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF

7007

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_CON__PRE 0x0

7008

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x382002B

7009

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16

7010

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF

7011

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_DIF__PRE 0x0

7012

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x382002C

7013

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16

7014

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF

7015

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RES__PRE 0x0

7016

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x382002D

7017

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16

7018

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF

7019

#define OFDM_LC_RA_RAM_PIPE_CP_PHASE_RZ__PRE 0x0

7020

#define OFDM_LC_RA_RAM_FILTER_BACKUP__A 0x382002E

7021

#define OFDM_LC_RA_RAM_FILTER_BACKUP__W 16

7022

#define OFDM_LC_RA_RAM_FILTER_BACKUP__M 0xFFFF

7023

#define OFDM_LC_RA_RAM_FILTER_BACKUP__PRE 0x4

7024

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x3820030

7025

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__W 16

7026

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF

7027

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_0__PRE 0x0

7028

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x3820031

7029

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__W 16

7030

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF

7031

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_1__PRE 0x0

7032

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x3820032

7033

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16

7034

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF

7035

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_CON__PRE 0x0

7036

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x3820033

7037

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16

7038

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF

7039

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_DIF__PRE 0x0

7040

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x3820034

7041

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16

7042

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF

7043

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RES__PRE 0x0

7044

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x3820035

7045

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16

7046

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF

7047

#define OFDM_LC_RA_RAM_PIPE_CP_CRMM_RZ__PRE 0x0

7048

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x3820038

7049

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__W 16

7050

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF

7051

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_0__PRE 0x0

7052

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x3820039

7053

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__W 16

7054

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF

7055

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_1__PRE 0x0

7056

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x382003A

7057

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16

7058

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF

7059

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_CON__PRE 0x0

7060

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x382003B

7061

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16

7062

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF

7063

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_DIF__PRE 0x0

7064

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x382003C

7065

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16

7066

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF

7067

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RES__PRE 0x0

7068

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x382003D

7069

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16

7070

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF

7071

#define OFDM_LC_RA_RAM_PIPE_CP_SRMM_RZ__PRE 0x0

7072

#define OFDM_LC_RA_RAM_FILTER_CRMM_A__A 0x3820060

7073

#define OFDM_LC_RA_RAM_FILTER_CRMM_A__W 16

7074

#define OFDM_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF

7075

#define OFDM_LC_RA_RAM_FILTER_CRMM_A__PRE 0x7

7076

#define OFDM_LC_RA_RAM_FILTER_CRMM_B__A 0x3820061

7077

#define OFDM_LC_RA_RAM_FILTER_CRMM_B__W 16

7078

#define OFDM_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF

7079

#define OFDM_LC_RA_RAM_FILTER_CRMM_B__PRE 0x2

7080

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__A 0x3820062

7081

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__W 16

7082

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__M 0xFFFF

7083

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_0__PRE 0x0

7084

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__A 0x3820063

7085

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__W 16

7086

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__M 0xFFFF

7087

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z1_1__PRE 0x0

7088

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__A 0x3820064

7089

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__W 16

7090

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__M 0xFFFF

7091

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_0__PRE 0x0

7092

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__A 0x3820065

7093

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__W 16

7094

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__M 0xFFFF

7095

#define OFDM_LC_RA_RAM_FILTER_CRMM_Z2_1__PRE 0x0

7096

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__A 0x3820066

7097

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__W 16

7098

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__M 0xFFFF

7099

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_0__PRE 0x0

7100

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__A 0x3820067

7101

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__W 16

7102

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__M 0xFFFF

7103

#define OFDM_LC_RA_RAM_FILTER_CRMM_TMP_1__PRE 0x0

7104

#define OFDM_LC_RA_RAM_FILTER_SRMM_A__A 0x3820068

7105

#define OFDM_LC_RA_RAM_FILTER_SRMM_A__W 16

7106

#define OFDM_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF

7107

#define OFDM_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4

7108

#define OFDM_LC_RA_RAM_FILTER_SRMM_B__A 0x3820069

7109

#define OFDM_LC_RA_RAM_FILTER_SRMM_B__W 16

7110

#define OFDM_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF

7111

#define OFDM_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1

7112

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__A 0x382006A

7113

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__W 16

7114

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__M 0xFFFF

7115

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_0__PRE 0x0

7116

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__A 0x382006B

7117

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__W 16

7118

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__M 0xFFFF

7119

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z1_1__PRE 0x0

7120

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__A 0x382006C

7121

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__W 16

7122

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__M 0xFFFF

7123

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_0__PRE 0x0

7124

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__A 0x382006D

7125

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__W 16

7126

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__M 0xFFFF

7127

#define OFDM_LC_RA_RAM_FILTER_SRMM_Z2_1__PRE 0x0

7128

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__A 0x382006E

7129

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__W 16

7130

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__M 0xFFFF

7131

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_0__PRE 0x0

7132

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__A 0x382006F

7133

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__W 16

7134

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__M 0xFFFF

7135

#define OFDM_LC_RA_RAM_FILTER_SRMM_TMP_1__PRE 0x0

7136

#define OFDM_LC_RA_RAM_FILTER_PHASE_A__A 0x3820070

7137

#define OFDM_LC_RA_RAM_FILTER_PHASE_A__W 16

7138

#define OFDM_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF

7139

#define OFDM_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4

7140

#define OFDM_LC_RA_RAM_FILTER_PHASE_B__A 0x3820071

7141

#define OFDM_LC_RA_RAM_FILTER_PHASE_B__W 16

7142

#define OFDM_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF

7143

#define OFDM_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1

7144

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__A 0x3820072

7145

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__W 16

7146

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__M 0xFFFF

7147

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_0__PRE 0x0

7148

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__A 0x3820073

7149

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__W 16

7150

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__M 0xFFFF

7151

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z1_1__PRE 0x0

7152

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__A 0x3820074

7153

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__W 16

7154

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__M 0xFFFF

7155

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_0__PRE 0x0

7156

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__A 0x3820075

7157

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__W 16

7158

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__M 0xFFFF

7159

#define OFDM_LC_RA_RAM_FILTER_PHASE_Z2_1__PRE 0x0

7160

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__A 0x3820076

7161

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__W 16

7162

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__M 0xFFFF

7163

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_0__PRE 0x0

7164

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__A 0x3820077

7165

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__W 16

7166

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__M 0xFFFF

7167

#define OFDM_LC_RA_RAM_FILTER_PHASE_TMP_1__PRE 0x0

7168

#define OFDM_LC_RA_RAM_FILTER_DELAY_A__A 0x3820078

7169

#define OFDM_LC_RA_RAM_FILTER_DELAY_A__W 16

7170

#define OFDM_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF

7171

#define OFDM_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4

7172

#define OFDM_LC_RA_RAM_FILTER_DELAY_B__A 0x3820079

7173

#define OFDM_LC_RA_RAM_FILTER_DELAY_B__W 16

7174

#define OFDM_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF

7175

#define OFDM_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1

7176

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__A 0x382007A

7177

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__W 16

7178

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__M 0xFFFF

7179

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_0__PRE 0x0

7180

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__A 0x382007B

7181

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__W 16

7182

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__M 0xFFFF

7183

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z1_1__PRE 0x0

7184

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__A 0x382007C

7185

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__W 16

7186

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__M 0xFFFF

7187

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_0__PRE 0x0

7188

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__A 0x382007D

7189

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__W 16

7190

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__M 0xFFFF

7191

#define OFDM_LC_RA_RAM_FILTER_DELAY_Z2_1__PRE 0x0

7192

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__A 0x382007E

7193

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__W 16

7194

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__M 0xFFFF

7195

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_0__PRE 0x0

7196

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__A 0x382007F

7197

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__W 16

7198

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__M 0xFFFF

7199

#define OFDM_LC_RA_RAM_FILTER_DELAY_TMP_1__PRE 0x0

#define OFDM_SC_COMM_EXEC__A 0x3C00000

7206

#define OFDM_SC_COMM_EXEC__W 3

7207

#define OFDM_SC_COMM_EXEC__M 0x7

7208

#define OFDM_SC_COMM_EXEC__PRE 0x0

7209

#define OFDM_SC_COMM_EXEC_STOP 0x0

7210

#define OFDM_SC_COMM_EXEC_ACTIVE 0x1

7211

#define OFDM_SC_COMM_EXEC_HOLD 0x2

7212

#define OFDM_SC_COMM_EXEC_STEP 0x3

7213

#define OFDM_SC_COMM_EXEC_BYPASS_STOP 0x4

7214

#define OFDM_SC_COMM_EXEC_BYPASS_HOLD 0x6

7215

7216

#define OFDM_SC_COMM_STATE__A 0x3C00001

7217

#define OFDM_SC_COMM_STATE__W 16

7218

#define OFDM_SC_COMM_STATE__M 0xFFFF

7219

#define OFDM_SC_COMM_STATE__PRE 0x0

7220

#define OFDM_SC_COMM_MB__A 0x3C00002

7221

#define OFDM_SC_COMM_MB__W 16

7222

#define OFDM_SC_COMM_MB__M 0xFFFF

7223

#define OFDM_SC_COMM_MB__PRE 0x0

7224

#define OFDM_SC_COMM_INT_REQ__A 0x3C00004

7225

#define OFDM_SC_COMM_INT_REQ__W 16

7226

#define OFDM_SC_COMM_INT_REQ__M 0xFFFF

7227

#define OFDM_SC_COMM_INT_REQ__PRE 0x0

7228

#define OFDM_SC_COMM_INT_REQ_CT_REQ__B 7

7229

#define OFDM_SC_COMM_INT_REQ_CT_REQ__W 1

7230

#define OFDM_SC_COMM_INT_REQ_CT_REQ__M 0x80

7231

#define OFDM_SC_COMM_INT_REQ_CT_REQ__PRE 0x0

7232

7233

#define OFDM_SC_COMM_INT_STA__A 0x3C00005

7234

#define OFDM_SC_COMM_INT_STA__W 16

7235

#define OFDM_SC_COMM_INT_STA__M 0xFFFF

7236

#define OFDM_SC_COMM_INT_STA__PRE 0x0

7237

#define OFDM_SC_COMM_INT_MSK__A 0x3C00006

7238

#define OFDM_SC_COMM_INT_MSK__W 16

7239

#define OFDM_SC_COMM_INT_MSK__M 0xFFFF

7240

#define OFDM_SC_COMM_INT_MSK__PRE 0x0

7241

#define OFDM_SC_COMM_INT_STM__A 0x3C00007

7242

#define OFDM_SC_COMM_INT_STM__W 16

7243

#define OFDM_SC_COMM_INT_STM__M 0xFFFF

7244

#define OFDM_SC_COMM_INT_STM__PRE 0x0

7245

#define OFDM_SC_COMM_INT_STM_INT_MSK__B 0

7246

#define OFDM_SC_COMM_INT_STM_INT_MSK__W 16

7247

#define OFDM_SC_COMM_INT_STM_INT_MSK__M 0xFFFF

7248

#define OFDM_SC_COMM_INT_STM_INT_MSK__PRE 0x0

#define OFDM_SC_CT_COMM_EXEC__A 0x3C10000

7253

#define OFDM_SC_CT_COMM_EXEC__W 3

7254

#define OFDM_SC_CT_COMM_EXEC__M 0x7

7255

#define OFDM_SC_CT_COMM_EXEC__PRE 0x0

7256

#define OFDM_SC_CT_COMM_EXEC_STOP 0x0

7257

#define OFDM_SC_CT_COMM_EXEC_ACTIVE 0x1

7258

#define OFDM_SC_CT_COMM_EXEC_HOLD 0x2

7259

#define OFDM_SC_CT_COMM_EXEC_STEP 0x3

7260

7261

7262

#define OFDM_SC_CT_COMM_STATE__A 0x3C10001

7263

#define OFDM_SC_CT_COMM_STATE__W 10

7264

#define OFDM_SC_CT_COMM_STATE__M 0x3FF

7265

#define OFDM_SC_CT_COMM_STATE__PRE 0x0

7266

#define OFDM_SC_CT_COMM_INT_REQ__A 0x3C10004

7267

#define OFDM_SC_CT_COMM_INT_REQ__W 1

7268

#define OFDM_SC_CT_COMM_INT_REQ__M 0x1

7269

#define OFDM_SC_CT_COMM_INT_REQ__PRE 0x0

7270

#define OFDM_SC_CT_COMM_INT_STA__A 0x3C10005

7271

#define OFDM_SC_CT_COMM_INT_STA__W 1

7272

#define OFDM_SC_CT_COMM_INT_STA__M 0x1

7273

#define OFDM_SC_CT_COMM_INT_STA__PRE 0x0

7274

#define OFDM_SC_CT_COMM_INT_STA_REQUEST__B 0

7275

#define OFDM_SC_CT_COMM_INT_STA_REQUEST__W 1

7276

#define OFDM_SC_CT_COMM_INT_STA_REQUEST__M 0x1

7277

#define OFDM_SC_CT_COMM_INT_STA_REQUEST__PRE 0x0

7278

7279

#define OFDM_SC_CT_COMM_INT_MSK__A 0x3C10006

7280

#define OFDM_SC_CT_COMM_INT_MSK__W 1

7281

#define OFDM_SC_CT_COMM_INT_MSK__M 0x1

7282

#define OFDM_SC_CT_COMM_INT_MSK__PRE 0x0

7283

#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__B 0

7284

#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__W 1

7285

#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__M 0x1

7286

#define OFDM_SC_CT_COMM_INT_MSK_REQUEST__PRE 0x0

7287

7288

#define OFDM_SC_CT_COMM_INT_STM__A 0x3C10007

7289

#define OFDM_SC_CT_COMM_INT_STM__W 1

7290

#define OFDM_SC_CT_COMM_INT_STM__M 0x1

7291

#define OFDM_SC_CT_COMM_INT_STM__PRE 0x0

7292

#define OFDM_SC_CT_COMM_INT_STM_REQUEST__B 0

7293

#define OFDM_SC_CT_COMM_INT_STM_REQUEST__W 1

7294

#define OFDM_SC_CT_COMM_INT_STM_REQUEST__M 0x1

7295

#define OFDM_SC_CT_COMM_INT_STM_REQUEST__PRE 0x0

7296

7297

7298

#define OFDM_SC_CT_CTL_STK_0__A 0x3C10010

7299

#define OFDM_SC_CT_CTL_STK_0__W 10

7300

#define OFDM_SC_CT_CTL_STK_0__M 0x3FF

7301

#define OFDM_SC_CT_CTL_STK_0__PRE 0x0

7302

7303

#define OFDM_SC_CT_CTL_STK_1__A 0x3C10011

7304

#define OFDM_SC_CT_CTL_STK_1__W 10

7305

#define OFDM_SC_CT_CTL_STK_1__M 0x3FF

7306

#define OFDM_SC_CT_CTL_STK_1__PRE 0x0

7307

7308

#define OFDM_SC_CT_CTL_STK_2__A 0x3C10012

7309

#define OFDM_SC_CT_CTL_STK_2__W 10

7310

#define OFDM_SC_CT_CTL_STK_2__M 0x3FF

7311

#define OFDM_SC_CT_CTL_STK_2__PRE 0x0

7312

7313

#define OFDM_SC_CT_CTL_STK_3__A 0x3C10013

7314

#define OFDM_SC_CT_CTL_STK_3__W 10

7315

#define OFDM_SC_CT_CTL_STK_3__M 0x3FF

7316

#define OFDM_SC_CT_CTL_STK_3__PRE 0x0

7317

7318

#define OFDM_SC_CT_CTL_BPT_IDX__A 0x3C1001F

7319

#define OFDM_SC_CT_CTL_BPT_IDX__W 1

7320

#define OFDM_SC_CT_CTL_BPT_IDX__M 0x1

7321

#define OFDM_SC_CT_CTL_BPT_IDX__PRE 0x0

7322

7323

#define OFDM_SC_CT_CTL_BPT__A 0x3C10020

7324

#define OFDM_SC_CT_CTL_BPT__W 13

7325

#define OFDM_SC_CT_CTL_BPT__M 0x1FFF

7326

#define OFDM_SC_CT_CTL_BPT__PRE 0x0

#define OFDM_SC_RA_RAM__A 0x3C20000

#define OFDM_SC_IF_RAM_TRP_RST_0__A 0x3C30000

7336

#define OFDM_SC_IF_RAM_TRP_RST_0__W 12

7337

#define OFDM_SC_IF_RAM_TRP_RST_0__M 0xFFF

7338

#define OFDM_SC_IF_RAM_TRP_RST_0__PRE 0x0

7339

7340

#define OFDM_SC_IF_RAM_TRP_RST_1__A 0x3C30001

7341

#define OFDM_SC_IF_RAM_TRP_RST_1__W 12

7342

#define OFDM_SC_IF_RAM_TRP_RST_1__M 0xFFF

7343

#define OFDM_SC_IF_RAM_TRP_RST_1__PRE 0x0

7344

7345

#define OFDM_SC_IF_RAM_TRP_BPT0_0__A 0x3C30002

7346

#define OFDM_SC_IF_RAM_TRP_BPT0_0__W 12

7347

#define OFDM_SC_IF_RAM_TRP_BPT0_0__M 0xFFF

7348

#define OFDM_SC_IF_RAM_TRP_BPT0_0__PRE 0x0

7349

7350

#define OFDM_SC_IF_RAM_TRP_BPT0_1__A 0x3C30004

7351

#define OFDM_SC_IF_RAM_TRP_BPT0_1__W 12

7352

#define OFDM_SC_IF_RAM_TRP_BPT0_1__M 0xFFF

7353

#define OFDM_SC_IF_RAM_TRP_BPT0_1__PRE 0x0

7354

7355

#define OFDM_SC_IF_RAM_TRP_STKU_0__A 0x3C30004

7356

#define OFDM_SC_IF_RAM_TRP_STKU_0__W 12

7357

#define OFDM_SC_IF_RAM_TRP_STKU_0__M 0xFFF

7358

#define OFDM_SC_IF_RAM_TRP_STKU_0__PRE 0x0

7359

7360

#define OFDM_SC_IF_RAM_TRP_STKU_1__A 0x3C30005

7361

#define OFDM_SC_IF_RAM_TRP_STKU_1__W 12

7362

#define OFDM_SC_IF_RAM_TRP_STKU_1__M 0xFFF

7363

#define OFDM_SC_IF_RAM_TRP_STKU_1__PRE 0x0

7364

7365

#define OFDM_SC_IF_RAM_VERSION_MA_MI__A 0x3C30FFE

7366

#define OFDM_SC_IF_RAM_VERSION_MA_MI__W 12

7367

#define OFDM_SC_IF_RAM_VERSION_MA_MI__M 0xFFF

7368

#define OFDM_SC_IF_RAM_VERSION_MA_MI__PRE 0x0

7369

7370

#define OFDM_SC_IF_RAM_VERSION_PATCH__A 0x3C30FFF

7371

#define OFDM_SC_IF_RAM_VERSION_PATCH__W 12

7372

#define OFDM_SC_IF_RAM_VERSION_PATCH__M 0xFFF

7373

#define OFDM_SC_IF_RAM_VERSION_PATCH__PRE 0x0

#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040

7382

#define OFDM_SC_RA_RAM_PARAM0__W 16

7383

#define OFDM_SC_RA_RAM_PARAM0__M 0xFFFF

7384

#define OFDM_SC_RA_RAM_PARAM0__PRE 0x0

7385

#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041

7386

#define OFDM_SC_RA_RAM_PARAM1__W 16

7387

#define OFDM_SC_RA_RAM_PARAM1__M 0xFFFF

7388

#define OFDM_SC_RA_RAM_PARAM1__PRE 0x0

7389

#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042

7390

#define OFDM_SC_RA_RAM_CMD_ADDR__W 16

7391

#define OFDM_SC_RA_RAM_CMD_ADDR__M 0xFFFF

7392

#define OFDM_SC_RA_RAM_CMD_ADDR__PRE 0x0

7393

#define OFDM_SC_RA_RAM_CMD__A 0x3C20043

7394

#define OFDM_SC_RA_RAM_CMD__W 16

7395

#define OFDM_SC_RA_RAM_CMD__M 0xFFFF

7396

#define OFDM_SC_RA_RAM_CMD__PRE 0x0

7397

#define OFDM_SC_RA_RAM_CMD_NULL 0x0

7398

#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1

7399

#define OFDM_SC_RA_RAM_CMD_PROC_TRIGGER 0x2

7400

#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3

7401

#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4

7402

#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5

7403

#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6

7404

#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7

7405

#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8

7406

#define OFDM_SC_RA_RAM_CMD_MAX 0x9

7407

#define OFDM_SC_RA_RAM_CMD_LOCK__C 0x4

7408

7409

#define OFDM_SC_RA_RAM_PROC_ACTIVATE__A 0x3C20044

7410

#define OFDM_SC_RA_RAM_PROC_ACTIVATE__W 16

7411

#define OFDM_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF

7412

#define OFDM_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF

7413

#define OFDM_SC_RA_RAM_PROC_TERMINATED__A 0x3C20045

7414

#define OFDM_SC_RA_RAM_PROC_TERMINATED__W 16

7415

#define OFDM_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF

7416

#define OFDM_SC_RA_RAM_PROC_TERMINATED__PRE 0x0

7417

#define OFDM_SC_RA_RAM_SW_EVENT__A 0x3C20046

7418

#define OFDM_SC_RA_RAM_SW_EVENT__W 14

7419

#define OFDM_SC_RA_RAM_SW_EVENT__M 0x3FFF

7420

#define OFDM_SC_RA_RAM_SW_EVENT__PRE 0x0

7421

#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0

7422

#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1

7423

#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1

7424

#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__PRE 0x0

7425

#define OFDM_SC_RA_RAM_SW_EVENT_RUN__B 1

7426

#define OFDM_SC_RA_RAM_SW_EVENT_RUN__W 1

7427

#define OFDM_SC_RA_RAM_SW_EVENT_RUN__M 0x2

7428

#define OFDM_SC_RA_RAM_SW_EVENT_RUN__PRE 0x0

7429

#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__B 2

7430

#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__W 1

7431

#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4

7432

#define OFDM_SC_RA_RAM_SW_EVENT_TERMINATE__PRE 0x0

7433

#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__B 3

7434

#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__W 1

7435

#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__M 0x8

7436

#define OFDM_SC_RA_RAM_SW_EVENT_FT_START__PRE 0x0

7437

#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__B 4

7438

#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__W 1

7439

#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__M 0x10

7440

#define OFDM_SC_RA_RAM_SW_EVENT_FI_START__PRE 0x0

7441

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5

7442

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1

7443

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20

7444

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_TPS__PRE 0x0

7445

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6

7446

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1

7447

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40

7448

#define OFDM_SC_RA_RAM_SW_EVENT_EQ_ERR__PRE 0x0

7449

#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__B 7

7450

#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__W 1

7451

#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80

7452

#define OFDM_SC_RA_RAM_SW_EVENT_CE_IR__PRE 0x0

7453

#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__B 8

7454

#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__W 1

7455

#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100

7456

#define OFDM_SC_RA_RAM_SW_EVENT_FE_FD__PRE 0x0

7457

#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__B 9

7458

#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__W 1

7459

#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200

7460

#define OFDM_SC_RA_RAM_SW_EVENT_FE_CF__PRE 0x0

7461

#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__B 12

7462

#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__W 1

7463

#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000

7464

#define OFDM_SC_RA_RAM_SW_EVENT_NF_READY__PRE 0x0

7465

7466

#define OFDM_SC_RA_RAM_LOCKTRACK__A 0x3C20047

7467

#define OFDM_SC_RA_RAM_LOCKTRACK__W 16

7468

#define OFDM_SC_RA_RAM_LOCKTRACK__M 0xFFFF

7469

#define OFDM_SC_RA_RAM_LOCKTRACK__PRE 0x0

7470

#define OFDM_SC_RA_RAM_LOCKTRACK_NULL 0x0

7471

#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1

7472

#define OFDM_SC_RA_RAM_LOCKTRACK_RESET 0x1

7473

#define OFDM_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2

7474

#define OFDM_SC_RA_RAM_LOCKTRACK_SRMM_FIX 0x3

7475

#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT 0x4

7476

#define OFDM_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x5

7477

#define OFDM_SC_RA_RAM_LOCKTRACK_LC 0x6

7478

#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK 0x7

7479

#define OFDM_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0x8

7480

#define OFDM_SC_RA_RAM_LOCKTRACK_MAX 0x9

7481

7482

#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048

7483

#define OFDM_SC_RA_RAM_OP_PARAM__W 13

7484

#define OFDM_SC_RA_RAM_OP_PARAM__M 0x1FFF

7485

#define OFDM_SC_RA_RAM_OP_PARAM__PRE 0x0

7486

#define OFDM_SC_RA_RAM_OP_PARAM_MODE__B 0

7487

#define OFDM_SC_RA_RAM_OP_PARAM_MODE__W 2

7488

#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3

7489

#define OFDM_SC_RA_RAM_OP_PARAM_MODE__PRE 0x0

7490

#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0

7491

#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1

7492

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__B 2

7493

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__W 2

7494

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__M 0xC

7495

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD__PRE 0x0

7496

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0

7497

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4

7498

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8

7499

#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC

7500

#define OFDM_SC_RA_RAM_OP_PARAM_CONST__B 4

7501

#define OFDM_SC_RA_RAM_OP_PARAM_CONST__W 2

7502

#define OFDM_SC_RA_RAM_OP_PARAM_CONST__M 0x30

7503

#define OFDM_SC_RA_RAM_OP_PARAM_CONST__PRE 0x0

7504

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0

7505

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10

7506

#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20

7507

#define OFDM_SC_RA_RAM_OP_PARAM_HIER__B 6

7508

#define OFDM_SC_RA_RAM_OP_PARAM_HIER__W 3

7509

#define OFDM_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0

7510

#define OFDM_SC_RA_RAM_OP_PARAM_HIER__PRE 0x0

7511

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0

7512

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40

7513

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80

7514

#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0

7515

#define OFDM_SC_RA_RAM_OP_PARAM_RATE__B 9

7516

#define OFDM_SC_RA_RAM_OP_PARAM_RATE__W 3

7517

#define OFDM_SC_RA_RAM_OP_PARAM_RATE__M 0xE00

7518

#define OFDM_SC_RA_RAM_OP_PARAM_RATE__PRE 0x0

7519

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0

7520

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200

7521

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400

7522

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600

7523

#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800

7524

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__B 12

7525

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__W 1

7526

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000

7527

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO__PRE 0x0

7528

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0

7529

#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000

7530

7531

#define OFDM_SC_RA_RAM_OP_AUTO__A 0x3C20049

7532

#define OFDM_SC_RA_RAM_OP_AUTO__W 6

7533

#define OFDM_SC_RA_RAM_OP_AUTO__M 0x3F

7534

#define OFDM_SC_RA_RAM_OP_AUTO__PRE 0x1F

7535

#define OFDM_SC_RA_RAM_OP_AUTO_MODE__B 0

7536

#define OFDM_SC_RA_RAM_OP_AUTO_MODE__W 1

7537

#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1

7538

#define OFDM_SC_RA_RAM_OP_AUTO_MODE__PRE 0x1

7539

#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__B 1

7540

#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__W 1

7541

#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2

7542

#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__PRE 0x2

7543

#define OFDM_SC_RA_RAM_OP_AUTO_CONST__B 2

7544

#define OFDM_SC_RA_RAM_OP_AUTO_CONST__W 1

7545

#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4

7546

#define OFDM_SC_RA_RAM_OP_AUTO_CONST__PRE 0x4

7547

#define OFDM_SC_RA_RAM_OP_AUTO_HIER__B 3

7548

#define OFDM_SC_RA_RAM_OP_AUTO_HIER__W 1

7549

#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8

7550

#define OFDM_SC_RA_RAM_OP_AUTO_HIER__PRE 0x8

7551

#define OFDM_SC_RA_RAM_OP_AUTO_RATE__B 4

7552

#define OFDM_SC_RA_RAM_OP_AUTO_RATE__W 1

7553

#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10

7554

#define OFDM_SC_RA_RAM_OP_AUTO_RATE__PRE 0x10

7555

#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__B 5

7556

#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__W 1

7557

#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__M 0x20

7558

#define OFDM_SC_RA_RAM_OP_AUTO_PRIO__PRE 0x0

7559

7560

#define OFDM_SC_RA_RAM_PILOT_STATUS__A 0x3C2004A

7561

#define OFDM_SC_RA_RAM_PILOT_STATUS__W 16

7562

#define OFDM_SC_RA_RAM_PILOT_STATUS__M 0xFFFF

7563

#define OFDM_SC_RA_RAM_PILOT_STATUS__PRE 0x0

7564

#define OFDM_SC_RA_RAM_PILOT_STATUS_OK 0x0

7565

#define OFDM_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1

7566

#define OFDM_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2

7567

#define OFDM_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3

7568

7569

#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B

7570

#define OFDM_SC_RA_RAM_LOCK__W 4

7571

#define OFDM_SC_RA_RAM_LOCK__M 0xF

7572

#define OFDM_SC_RA_RAM_LOCK__PRE 0x0

7573

#define OFDM_SC_RA_RAM_LOCK_DEMOD__B 0

7574

#define OFDM_SC_RA_RAM_LOCK_DEMOD__W 1

7575

#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1

7576

#define OFDM_SC_RA_RAM_LOCK_DEMOD__PRE 0x0

7577

#define OFDM_SC_RA_RAM_LOCK_FEC__B 1

7578

#define OFDM_SC_RA_RAM_LOCK_FEC__W 1

7579

#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2

7580

#define OFDM_SC_RA_RAM_LOCK_FEC__PRE 0x0

7581

#define OFDM_SC_RA_RAM_LOCK_MPEG__B 2

7582

#define OFDM_SC_RA_RAM_LOCK_MPEG__W 1

7583

#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4

7584

#define OFDM_SC_RA_RAM_LOCK_MPEG__PRE 0x0

7585

#define OFDM_SC_RA_RAM_LOCK_NODVBT__B 3

7586

#define OFDM_SC_RA_RAM_LOCK_NODVBT__W 1

7587

#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8

7588

#define OFDM_SC_RA_RAM_LOCK_NODVBT__PRE 0x0

7589

7590

#define OFDM_SC_RA_RAM_BE_OPT_ENA__A 0x3C2004C

7591

#define OFDM_SC_RA_RAM_BE_OPT_ENA__W 5

7592

#define OFDM_SC_RA_RAM_BE_OPT_ENA__M 0x1F

7593

#define OFDM_SC_RA_RAM_BE_OPT_ENA__PRE 0x1C

7594

#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__B 0

7595

#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__W 1

7596

#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__M 0x1

7597

#define OFDM_SC_RA_RAM_BE_OPT_ENA_PILOT_POW_OPT__PRE 0x0

7598

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__B 1

7599

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__W 1

7600

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__M 0x2

7601

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CP_OPT__PRE 0x0

7602

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__B 2

7603

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__W 1

7604

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__M 0x4

7605

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CSI_OPT__PRE 0x4

7606

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__B 3

7607

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__W 1

7608

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__M 0x8

7609

#define OFDM_SC_RA_RAM_BE_OPT_ENA_CAL_OPT__PRE 0x8

7610

#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__B 4

7611

#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__W 1

7612

#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__M 0x10

7613

#define OFDM_SC_RA_RAM_BE_OPT_ENA_FR_WATCH__PRE 0x10

7614

7615

#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D

7616

#define OFDM_SC_RA_RAM_BE_OPT_DELAY__W 16

7617

#define OFDM_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF

7618

#define OFDM_SC_RA_RAM_BE_OPT_DELAY__PRE 0x80

7619

#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E

7620

#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16

7621

#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF

7622

#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400

7623

#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F

7624

#define OFDM_SC_RA_RAM_ECHO_THRES__W 16

7625

#define OFDM_SC_RA_RAM_ECHO_THRES__M 0xFFFF

7626

#define OFDM_SC_RA_RAM_ECHO_THRES__PRE 0x6419

7627

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0

7628

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__W 8

7629

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF

7630

#define OFDM_SC_RA_RAM_ECHO_THRES_8K__PRE 0x19

7631

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8

7632

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__W 8

7633

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00

7634

#define OFDM_SC_RA_RAM_ECHO_THRES_2K__PRE 0x6400

7635

7636

#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050

7637

#define OFDM_SC_RA_RAM_CONFIG__W 16

7638

#define OFDM_SC_RA_RAM_CONFIG__M 0xFFFF

7639

#define OFDM_SC_RA_RAM_CONFIG__PRE 0x14

7640

#define OFDM_SC_RA_RAM_CONFIG_ID__B 0

7641

#define OFDM_SC_RA_RAM_CONFIG_ID__W 1

7642

#define OFDM_SC_RA_RAM_CONFIG_ID__M 0x1

7643

#define OFDM_SC_RA_RAM_CONFIG_ID__PRE 0x0

7644

#define OFDM_SC_RA_RAM_CONFIG_ID_ID_PRO 0x0

7645

#define OFDM_SC_RA_RAM_CONFIG_ID_ID_CONSUMER 0x1

7646

#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1

7647

#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1

7648

#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2

7649

#define OFDM_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__PRE 0x0

7650

#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__B 2

7651

#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__W 1

7652

#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4

7653

#define OFDM_SC_RA_RAM_CONFIG_FR_ENABLE__PRE 0x4

7654

#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__B 3

7655

#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__W 1

7656

#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__M 0x8

7657

#define OFDM_SC_RA_RAM_CONFIG_MIXMODE__PRE 0x0

7658

#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__B 4

7659

#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__W 1

7660

#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10

7661

#define OFDM_SC_RA_RAM_CONFIG_FREQSCAN__PRE 0x10

7662

#define OFDM_SC_RA_RAM_CONFIG_SLAVE__B 5

7663

#define OFDM_SC_RA_RAM_CONFIG_SLAVE__W 1

7664

#define OFDM_SC_RA_RAM_CONFIG_SLAVE__M 0x20

7665

#define OFDM_SC_RA_RAM_CONFIG_SLAVE__PRE 0x0

7666

#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__B 6

7667

#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__W 1

7668

#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40

7669

#define OFDM_SC_RA_RAM_CONFIG_FAR_OFF__PRE 0x0

7670

#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7

7671

#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1

7672

#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80

7673

#define OFDM_SC_RA_RAM_CONFIG_FEC_CHECK_ON__PRE 0x0

7674

#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8

7675

#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1

7676

#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100

7677

#define OFDM_SC_RA_RAM_CONFIG_ECHO_UPDATED__PRE 0x0

7678

#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9

7679

#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1

7680

#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200

7681

#define OFDM_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__PRE 0x0

7682

#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10

7683

#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1

7684

#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400

7685

#define OFDM_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__PRE 0x0

7686

#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__B 11

7687

#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__W 1

7688

#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800

7689

#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__PRE 0x0

7690

#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15

7691

#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1

7692

#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000

7693

#define OFDM_SC_RA_RAM_CONFIG_ADJUST_OFF__PRE 0x0

7694

7695

#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x3C20054

7696

#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16

7697

#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF

7698

#define OFDM_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0

7699

#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__A 0x3C20055

7700

#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__W 16

7701

#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF

7702

#define OFDM_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7

7703

#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__A 0x3C20056

7704

#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__W 16

7705

#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF

7706

#define OFDM_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3

7707

#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x3C20057

7708

#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__W 16

7709

#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF

7710

#define OFDM_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2

7711

#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__A 0x3C20058

7712

#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__W 16

7713

#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF

7714

#define OFDM_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2

7715

#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__A 0x3C20059

7716

#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__W 16

7717

#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF

7718

#define OFDM_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7

7719

#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__A 0x3C2005A

7720

#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__W 16

7721

#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF

7722

#define OFDM_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x1

7723

#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x3C2005B

7724

#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__W 16

7725

#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF

7726

#define OFDM_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2

7727

#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__A 0x3C2005C

7728

#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__W 16

7729

#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF

7730

#define OFDM_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x1

7731

#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__A 0x3C2005D

7732

#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__W 16

7733

#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF

7734

#define OFDM_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB

7735

#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__A 0x3C2005E

7736

#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__W 16

7737

#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF

7738

#define OFDM_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8

7739

#define OFDM_SC_RA_RAM_MOTION_OFFSET__A 0x3C2005F

7740

#define OFDM_SC_RA_RAM_MOTION_OFFSET__W 16

7741

#define OFDM_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF

7742

#define OFDM_SC_RA_RAM_MOTION_OFFSET__PRE 0x2

7743

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__A 0x3C20060

7744

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__W 16

7745

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__M 0xFFFF

7746

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE

7747

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__A 0x3C20061

7748

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__W 16

7749

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__M 0xFFFF

7750

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x330

7751

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__A 0x3C20062

7752

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__W 16

7753

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__M 0xFFFF

7754

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x0

7755

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__A 0x3C20063

7756

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__W 16

7757

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__M 0xFFFF

7758

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x4

7759

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__A 0x3C20064

7760

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__W 16

7761

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__M 0xFFFF

7762

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0

7763

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__A 0x3C20065

7764

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__W 16

7765

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__M 0xFFFF

7766

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x80

7767

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__A 0x3C20066

7768

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__W 16

7769

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__M 0xFFFF

7770

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0

7771

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__A 0x3C20067

7772

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__W 16

7773

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__M 0xFFFF

7774

#define OFDM_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0xFFFE

7775

#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__A 0x3C2006E

7776

#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__W 16

7777

#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__M 0xFFFF

7778

#define OFDM_SC_RA_RAM_PILOT_POW_WEIGHT__PRE 0x1

7779

#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__A 0x3C2006F

7780

#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__W 16

7781

#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__M 0xFFFF

7782

#define OFDM_SC_RA_RAM_PILOT_POW_TARGET__PRE 0x320

7783

#define OFDM_SC_RA_RAM_STATE_PROC_START_1__A 0x3C20070

7784

#define OFDM_SC_RA_RAM_STATE_PROC_START_1__W 16

7785

#define OFDM_SC_RA_RAM_STATE_PROC_START_1__M 0xFFFF

7786

#define OFDM_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80

7787

#define OFDM_SC_RA_RAM_STATE_PROC_START_2__A 0x3C20071

7788

#define OFDM_SC_RA_RAM_STATE_PROC_START_2__W 16

7789

#define OFDM_SC_RA_RAM_STATE_PROC_START_2__M 0xFFFF

7790

#define OFDM_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2

7791

#define OFDM_SC_RA_RAM_STATE_PROC_START_3__A 0x3C20072

7792

#define OFDM_SC_RA_RAM_STATE_PROC_START_3__W 16

7793

#define OFDM_SC_RA_RAM_STATE_PROC_START_3__M 0xFFFF

7794

#define OFDM_SC_RA_RAM_STATE_PROC_START_3__PRE 0x40

7795

#define OFDM_SC_RA_RAM_STATE_PROC_START_4__A 0x3C20073

7796

#define OFDM_SC_RA_RAM_STATE_PROC_START_4__W 16

7797

#define OFDM_SC_RA_RAM_STATE_PROC_START_4__M 0xFFFF

7798

#define OFDM_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4

7799

#define OFDM_SC_RA_RAM_STATE_PROC_START_5__A 0x3C20074

7800

#define OFDM_SC_RA_RAM_STATE_PROC_START_5__W 16

7801

#define OFDM_SC_RA_RAM_STATE_PROC_START_5__M 0xFFFF

7802

#define OFDM_SC_RA_RAM_STATE_PROC_START_5__PRE 0x4

7803

#define OFDM_SC_RA_RAM_STATE_PROC_START_6__A 0x3C20075

7804

#define OFDM_SC_RA_RAM_STATE_PROC_START_6__W 16

7805

#define OFDM_SC_RA_RAM_STATE_PROC_START_6__M 0xFFFF

7806

#define OFDM_SC_RA_RAM_STATE_PROC_START_6__PRE 0x780

7807

#define OFDM_SC_RA_RAM_STATE_PROC_START_7__A 0x3C20076

7808

#define OFDM_SC_RA_RAM_STATE_PROC_START_7__W 16

7809

#define OFDM_SC_RA_RAM_STATE_PROC_START_7__M 0xFFFF

7810

#define OFDM_SC_RA_RAM_STATE_PROC_START_7__PRE 0x230

7811

#define OFDM_SC_RA_RAM_STATE_PROC_START_8__A 0x3C20077

7812

#define OFDM_SC_RA_RAM_STATE_PROC_START_8__W 16

7813

#define OFDM_SC_RA_RAM_STATE_PROC_START_8__M 0xFFFF

7814

#define OFDM_SC_RA_RAM_STATE_PROC_START_8__PRE 0x0

7815

#define OFDM_SC_RA_RAM_FR_THRES_2K__A 0x3C2007C

7816

#define OFDM_SC_RA_RAM_FR_THRES_2K__W 16

7817

#define OFDM_SC_RA_RAM_FR_THRES_2K__M 0xFFFF

7818

#define OFDM_SC_RA_RAM_FR_THRES_2K__PRE 0xEA6

7819

#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D

7820

#define OFDM_SC_RA_RAM_FR_THRES_8K__W 16

7821

#define OFDM_SC_RA_RAM_FR_THRES_8K__M 0xFFFF

7822

#define OFDM_SC_RA_RAM_FR_THRES_8K__PRE 0x1A2C

7823

#define OFDM_SC_RA_RAM_STATUS__A 0x3C2007E

7824

#define OFDM_SC_RA_RAM_STATUS__W 16

7825

#define OFDM_SC_RA_RAM_STATUS__M 0xFFFF

7826

#define OFDM_SC_RA_RAM_STATUS__PRE 0x0

7827

#define OFDM_SC_RA_RAM_NF_BORDER_INIT__A 0x3C2007F

7828

#define OFDM_SC_RA_RAM_NF_BORDER_INIT__W 16

7829

#define OFDM_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF

7830

#define OFDM_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708

7831

#define OFDM_SC_RA_RAM_TIMER__A 0x3C20080

7832

#define OFDM_SC_RA_RAM_TIMER__W 16

7833

#define OFDM_SC_RA_RAM_TIMER__M 0xFFFF

7834

#define OFDM_SC_RA_RAM_TIMER__PRE 0x0

7835

#define OFDM_SC_RA_RAM_FI_OFFSET__A 0x3C20081

7836

#define OFDM_SC_RA_RAM_FI_OFFSET__W 16

7837

#define OFDM_SC_RA_RAM_FI_OFFSET__M 0xFFFF

7838

#define OFDM_SC_RA_RAM_FI_OFFSET__PRE 0x382

7839

#define OFDM_SC_RA_RAM_ECHO_GUARD__A 0x3C20082

7840

#define OFDM_SC_RA_RAM_ECHO_GUARD__W 16

7841

#define OFDM_SC_RA_RAM_ECHO_GUARD__M 0xFFFF

7842

#define OFDM_SC_RA_RAM_ECHO_GUARD__PRE 0x18

7843

#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__A 0x3C2008D

7844

#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__W 16

7845

#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__M 0xFFFF

7846

#define OFDM_SC_RA_RAM_FEC_LOCK_DELAY__PRE 0x640

7847

#define OFDM_SC_RA_RAM_IF_SAVE_0__A 0x3C2008E

7848

#define OFDM_SC_RA_RAM_IF_SAVE_0__W 16

7849

#define OFDM_SC_RA_RAM_IF_SAVE_0__M 0xFFFF

7850

#define OFDM_SC_RA_RAM_IF_SAVE_0__PRE 0x0

7851

#define OFDM_SC_RA_RAM_IF_SAVE_1__A 0x3C2008F

7852

#define OFDM_SC_RA_RAM_IF_SAVE_1__W 16

7853

#define OFDM_SC_RA_RAM_IF_SAVE_1__M 0xFFFF

7854

#define OFDM_SC_RA_RAM_IF_SAVE_1__PRE 0x0

7855

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x3C20098

7856

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16

7857

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF

7858

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258

7859

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x3C20099

7860

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16

7861

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF

7862

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258

7863

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x3C2009A

7864

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16

7865

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF

7866

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258

7867

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x3C2009B

7868

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16

7869

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF

7870

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258

7871

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x3C2009C

7872

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16

7873

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF

7874

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC

7875

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x3C2009D

7876

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16

7877

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF

7878

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC

7879

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x3C2009E

7880

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16

7881

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF

7882

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC

7883

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x3C2009F

7884

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16

7885

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF

7886

#define OFDM_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC

7887

#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__A 0x3C200B2

7888

#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__W 16

7889

#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__M 0xFFFF

7890

#define OFDM_SC_RA_RAM_TD_REQ_SMB_CNT__PRE 0xC8

7891

#define OFDM_SC_RA_RAM_MG_VALID_THRES__A 0x3C200B7

7892

#define OFDM_SC_RA_RAM_MG_VALID_THRES__W 16

7893

#define OFDM_SC_RA_RAM_MG_VALID_THRES__M 0xFFFF

7894

#define OFDM_SC_RA_RAM_MG_VALID_THRES__PRE 0x230

7895

#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__A 0x3C200B8

7896

#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__W 16

7897

#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__M 0xFFFF

7898

#define OFDM_SC_RA_RAM_MG_MAX_DAT_THRES__PRE 0x320

7899

#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__A 0x3C200B9

7900

#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__W 16

7901

#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__M 0xFFFF

7902

#define OFDM_SC_RA_RAM_MG_CORR_TIMEOUT_8K__PRE 0x32

7903

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__A 0x3C200BA

7904

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__W 16

7905

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__M 0xFFFF

7906

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL__PRE 0x443

7907

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__B 0

7908

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__W 5

7909

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__M 0x1F

7910

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N0__PRE 0x3

7911

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__B 5

7912

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__W 5

7913

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__M 0x3E0

7914

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N1__PRE 0x40

7915

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__B 10

7916

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__W 5

7917

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__M 0x7C00

7918

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_VAL_N2__PRE 0x400

7919

7920

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__A 0x3C200BB

7921

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__W 16

7922

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__M 0xFFFF

7923

#define OFDM_SC_RA_RAM_PILOT_CPD_EXP_MARG_COUNT__PRE 0x3

7924

#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__A 0x3C200BC

7925

#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__W 16

7926

#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__M 0xFFFF

7927

#define OFDM_SC_RA_RAM_PILOT_SPD_THRES__PRE 0x6

7928

#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__A 0x3C200BD

7929

#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__W 16

7930

#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__M 0xFFFF

7931

#define OFDM_SC_RA_RAM_PILOT_SPD_TIMEOUT__PRE 0x28

7932

#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__A 0x3C200BE

7933

#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__W 16

7934

#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__M 0xFFFF

7935

#define OFDM_SC_RA_RAM_PILOT_CPD_THRES__PRE 0x6

7936

#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__A 0x3C200BF

7937

#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__W 16

7938

#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__M 0xFFFF

7939

#define OFDM_SC_RA_RAM_PILOT_CPD_TIMEOUT__PRE 0x14

7940

#define OFDM_SC_RA_RAM_IR_FREQ__A 0x3C200D0

7941

#define OFDM_SC_RA_RAM_IR_FREQ__W 16

7942

#define OFDM_SC_RA_RAM_IR_FREQ__M 0xFFFF

7943

#define OFDM_SC_RA_RAM_IR_FREQ__PRE 0x0

7944

#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x3C200D1

7945

#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16

7946

#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF

7947

#define OFDM_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9

7948

#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x3C200D2

7949

#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16

7950

#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF

7951

#define OFDM_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4

7952

#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x3C200D3

7953

#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16

7954

#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF

7955

#define OFDM_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100

7956

#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x3C200D4

7957

#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16

7958

#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF

7959

#define OFDM_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x9

7960

#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x3C200D5

7961

#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16

7962

#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF

7963

#define OFDM_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x4

7964

#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x3C200D6

7965

#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16

7966

#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF

7967

#define OFDM_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x100

7968

#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x3C200D7

7969

#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16

7970

#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF

7971

#define OFDM_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9

7972

#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x3C200D8

7973

#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16

7974

#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF

7975

#define OFDM_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4

7976

#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x3C200D9

7977

#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16

7978

#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF

7979

#define OFDM_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100

7980

#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x3C200DA

7981

#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16

7982

#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF

7983

#define OFDM_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB

7984

#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x3C200DB

7985

#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16

7986

#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF

7987

#define OFDM_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1

7988

#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x3C200DC

7989

#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16

7990

#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF

7991

#define OFDM_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40

7992

#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x3C200DD

7993

#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__W 16

7994

#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF

7995

#define OFDM_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18

7996

#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__A 0x3C200DE

7997

#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__W 16

7998

#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF

7999

#define OFDM_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1

8000

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x3C200DF

8001

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__W 16

8002

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF

8003

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0x14C0

8004

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0

8005

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10

8006

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF

8007

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__PRE 0xC0

8008

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10

8009

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6

8010

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00

8011

#define OFDM_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__PRE 0x1400

8012

8013

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0

8014

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16

8015

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF

8016

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7

8017

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1

8018

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16

8019

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF

8020

#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1

8021

#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x3C200E2

8022

#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16

8023

#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF

8024

#define OFDM_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8

8025

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3

8026

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16

8027

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF

8028

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE

8029

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4

8030

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16

8031

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF

8032

#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7

8033

#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x3C200E5

8034

#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16

8035

#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF

8036

#define OFDM_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0

8037

#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__A 0x3C200E7

8038

#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__W 16

8039

#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__M 0xFFFF

8040

#define OFDM_SC_RA_RAM_FREQ_OFFSET_LIM__PRE 0x4E2

8041

#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x3C200E8

8042

#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16

8043

#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF

8044

#define OFDM_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2

8045

#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x3C200E9

8046

#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__W 16

8047

#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF

8048

#define OFDM_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C

8049

#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x3C200EA

8050

#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16

8051

#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF

8052

#define OFDM_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8

8053

#define OFDM_SC_RA_RAM_TPS_TIMEOUT__A 0x3C200EB

8054

#define OFDM_SC_RA_RAM_TPS_TIMEOUT__W 16

8055

#define OFDM_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF

8056

#define OFDM_SC_RA_RAM_TPS_TIMEOUT__PRE 0x0

8057

#define OFDM_SC_RA_RAM_BAND__A 0x3C200EC

8058

#define OFDM_SC_RA_RAM_BAND__W 16

8059

#define OFDM_SC_RA_RAM_BAND__M 0xFFFF

8060

#define OFDM_SC_RA_RAM_BAND__PRE 0x0

8061

#define OFDM_SC_RA_RAM_BAND_INTERVAL__B 0

8062

#define OFDM_SC_RA_RAM_BAND_INTERVAL__W 4

8063

#define OFDM_SC_RA_RAM_BAND_INTERVAL__M 0xF

8064

#define OFDM_SC_RA_RAM_BAND_INTERVAL__PRE 0x0

8065

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8

8066

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1

8067

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100

8068

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__PRE 0x0

8069

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9

8070

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1

8071

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200

8072

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__PRE 0x0

8073

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10

8074

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1

8075

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400

8076

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__PRE 0x0

8077

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11

8078

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1

8079

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800

8080

#define OFDM_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__PRE 0x0

8081

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12

8082

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1

8083

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000

8084

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__PRE 0x0

8085

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13

8086

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1

8087

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000

8088

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__PRE 0x0

8089

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14

8090

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1

8091

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000

8092

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__PRE 0x0

8093

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15

8094

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1

8095

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000

8096

#define OFDM_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__PRE 0x0

8097

8098

#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x3C200ED

8099

#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16

8100

#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF

8101

#define OFDM_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0

8102

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__A 0x3C200EE

8103

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__W 16

8104

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__M 0xFFFF

8105

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_2K__PRE 0x19

8106

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__A 0x3C200EF

8107

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__W 16

8108

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__M 0xFFFF

8109

#define OFDM_SC_RA_RAM_NE_ERR_SELECT_8K__PRE 0x1B

8110

#define OFDM_SC_RA_RAM_REG_0__A 0x3C200F0

8111

#define OFDM_SC_RA_RAM_REG_0__W 16

8112

#define OFDM_SC_RA_RAM_REG_0__M 0xFFFF

8113

#define OFDM_SC_RA_RAM_REG_0__PRE 0x0

8114

#define OFDM_SC_RA_RAM_REG_1__A 0x3C200F1

8115

#define OFDM_SC_RA_RAM_REG_1__W 16

8116

#define OFDM_SC_RA_RAM_REG_1__M 0xFFFF

8117

#define OFDM_SC_RA_RAM_REG_1__PRE 0x0

8118

#define OFDM_SC_RA_RAM_BREAK__A 0x3C200F2

8119

#define OFDM_SC_RA_RAM_BREAK__W 16

8120

#define OFDM_SC_RA_RAM_BREAK__M 0xFFFF

8121

#define OFDM_SC_RA_RAM_BREAK__PRE 0x0

8122

#define OFDM_SC_RA_RAM_BOOTCOUNT__A 0x3C200F3

8123

#define OFDM_SC_RA_RAM_BOOTCOUNT__W 16

8124

#define OFDM_SC_RA_RAM_BOOTCOUNT__M 0xFFFF

8125

#define OFDM_SC_RA_RAM_BOOTCOUNT__PRE 0x0

8126

#define OFDM_SC_RA_RAM_LC_ABS_2K__A 0x3C200F4

8127

#define OFDM_SC_RA_RAM_LC_ABS_2K__W 16

8128

#define OFDM_SC_RA_RAM_LC_ABS_2K__M 0xFFFF

8129

#define OFDM_SC_RA_RAM_LC_ABS_2K__PRE 0x1F

8130

#define OFDM_SC_RA_RAM_LC_ABS_8K__A 0x3C200F5

8131

#define OFDM_SC_RA_RAM_LC_ABS_8K__W 16

8132

#define OFDM_SC_RA_RAM_LC_ABS_8K__M 0xFFFF

8133

#define OFDM_SC_RA_RAM_LC_ABS_8K__PRE 0x1F

8134

#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__A 0x3C200F6

8135

#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__W 16

8136

#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__M 0xFFFF

8137

#define OFDM_SC_RA_RAM_NE_NOTCH_WIDTH__PRE 0x1

8138

#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x3C200F7

8139

#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16

8140

#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF

8141

#define OFDM_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14

8142

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8

8143

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__W 16

8144

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__M 0xFFFF

8145

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__PRE 0xB6F

8146

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__B 0

8147

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__W 16

8148

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__M 0xFFFF

8149

#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K_CRMM_FIX_FACT_8K__PRE 0xB6F

8150

8151

#define OFDM_SC_RA_RAM_LC_CP__A 0x3C200F9

8152

#define OFDM_SC_RA_RAM_LC_CP__W 16

8153

#define OFDM_SC_RA_RAM_LC_CP__M 0xFFFF

8154

#define OFDM_SC_RA_RAM_LC_CP__PRE 0x1

8155

#define OFDM_SC_RA_RAM_LC_DIFF__A 0x3C200FA

8156

#define OFDM_SC_RA_RAM_LC_DIFF__W 16

8157

#define OFDM_SC_RA_RAM_LC_DIFF__M 0xFFFF

8158

#define OFDM_SC_RA_RAM_LC_DIFF__PRE 0x7

8159

#define OFDM_SC_RA_RAM_ECHO_NF_THRES__A 0x3C200FB

8160

#define OFDM_SC_RA_RAM_ECHO_NF_THRES__W 16

8161

#define OFDM_SC_RA_RAM_ECHO_NF_THRES__M 0xFFFF

8162

#define OFDM_SC_RA_RAM_ECHO_NF_THRES__PRE 0x1B58

8163

#define OFDM_SC_RA_RAM_ECHO_NF_FEC__A 0x3C200FC

8164

#define OFDM_SC_RA_RAM_ECHO_NF_FEC__W 16

8165

#define OFDM_SC_RA_RAM_ECHO_NF_FEC__M 0xFFFF

8166

#define OFDM_SC_RA_RAM_ECHO_NF_FEC__PRE 0x0

8167

8168

#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__A 0x3C200FD

8169

#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__W 16

8170

#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__M 0xFFFF

8171

#define OFDM_SC_RA_RAM_ECHO_RANGE_OFS__PRE 0xFF38

8172

#define OFDM_SC_RA_RAM_RELOCK__A 0x3C200FE

8173

#define OFDM_SC_RA_RAM_RELOCK__W 16

8174

#define OFDM_SC_RA_RAM_RELOCK__M 0xFFFF

8175

#define OFDM_SC_RA_RAM_RELOCK__PRE 0x0

8176

#define OFDM_SC_RA_RAM_STACKUNDERFLOW__A 0x3C200FF

8177

#define OFDM_SC_RA_RAM_STACKUNDERFLOW__W 16

8178

#define OFDM_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF

8179

#define OFDM_SC_RA_RAM_STACKUNDERFLOW__PRE 0x0

8180

#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x3C20148

8181

#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__W 16

8182

#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF

8183

#define OFDM_SC_RA_RAM_NF_MAXECHOTOKEN__PRE 0x0

8184

#define OFDM_SC_RA_RAM_NF_PREPOST__A 0x3C20149

8185

#define OFDM_SC_RA_RAM_NF_PREPOST__W 16

8186

#define OFDM_SC_RA_RAM_NF_PREPOST__M 0xFFFF

8187

#define OFDM_SC_RA_RAM_NF_PREPOST__PRE 0x0

8188

#define OFDM_SC_RA_RAM_NF_PREBORDER__A 0x3C2014A

8189

#define OFDM_SC_RA_RAM_NF_PREBORDER__W 16

8190

#define OFDM_SC_RA_RAM_NF_PREBORDER__M 0xFFFF

8191

#define OFDM_SC_RA_RAM_NF_PREBORDER__PRE 0x0

8192

#define OFDM_SC_RA_RAM_NF_START__A 0x3C2014B

8193

#define OFDM_SC_RA_RAM_NF_START__W 16

8194

#define OFDM_SC_RA_RAM_NF_START__M 0xFFFF

8195

#define OFDM_SC_RA_RAM_NF_START__PRE 0x0

8196

#define OFDM_SC_RA_RAM_NF_MINISI_0__A 0x3C2014C

8197

#define OFDM_SC_RA_RAM_NF_MINISI_0__W 16

8198

#define OFDM_SC_RA_RAM_NF_MINISI_0__M 0xFFFF

8199

#define OFDM_SC_RA_RAM_NF_MINISI_0__PRE 0x0

8200

#define OFDM_SC_RA_RAM_NF_MINISI_1__A 0x3C2014D

8201

#define OFDM_SC_RA_RAM_NF_MINISI_1__W 16

8202

#define OFDM_SC_RA_RAM_NF_MINISI_1__M 0xFFFF

8203

#define OFDM_SC_RA_RAM_NF_MINISI_1__PRE 0x0

8204

#define OFDM_SC_RA_RAM_NF_NRECHOES__A 0x3C2014F

8205

#define OFDM_SC_RA_RAM_NF_NRECHOES__W 16

8206

#define OFDM_SC_RA_RAM_NF_NRECHOES__M 0xFFFF

8207

#define OFDM_SC_RA_RAM_NF_NRECHOES__PRE 0x0

8208

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__A 0x3C20150

8209

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__W 16

8210

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__M 0xFFFF

8211

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_0__PRE 0x0

8212

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__A 0x3C20151

8213

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__W 16

8214

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__M 0xFFFF

8215

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_1__PRE 0x0

8216

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__A 0x3C20152

8217

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__W 16

8218

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__M 0xFFFF

8219

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_2__PRE 0x0

8220

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__A 0x3C20153

8221

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__W 16

8222

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__M 0xFFFF

8223

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_3__PRE 0x0

8224

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__A 0x3C20154

8225

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__W 16

8226

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__M 0xFFFF

8227

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_4__PRE 0x0

8228

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__A 0x3C20155

8229

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__W 16

8230

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__M 0xFFFF

8231

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_5__PRE 0x0

8232

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__A 0x3C20156

8233

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__W 16

8234

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__M 0xFFFF

8235

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_6__PRE 0x0

8236

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__A 0x3C20157

8237

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__W 16

8238

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__M 0xFFFF

8239

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_7__PRE 0x0

8240

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__A 0x3C20158

8241

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__W 16

8242

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__M 0xFFFF

8243

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_8__PRE 0x0

8244

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__A 0x3C20159

8245

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__W 16

8246

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__M 0xFFFF

8247

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_9__PRE 0x0

8248

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__A 0x3C2015A

8249

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__W 16

8250

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__M 0xFFFF

8251

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_10__PRE 0x0

8252

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__A 0x3C2015B

8253

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__W 16

8254

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__M 0xFFFF

8255

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_11__PRE 0x0

8256

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__A 0x3C2015C

8257

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__W 16

8258

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__M 0xFFFF

8259

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_12__PRE 0x0

8260

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__A 0x3C2015D

8261

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__W 16

8262

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__M 0xFFFF

8263

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_13__PRE 0x0

8264

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__A 0x3C2015E

8265

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__W 16

8266

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__M 0xFFFF

8267

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_14__PRE 0x0

8268

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__A 0x3C2015F

8269

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__W 16

8270

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__M 0xFFFF

8271

#define OFDM_SC_RA_RAM_NF_ECHOTABLE_15__PRE 0x0

8272

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x3C201A0

8273

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16

8274

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF

8275

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100

8276

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x3C201A1

8277

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16

8278

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF

8279

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4

8280

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x3C201A2

8281

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16

8282

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF

8283

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2

8284

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x3C201A3

8285

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16

8286

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF

8287

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4

8288

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x3C201A4

8289

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16

8290

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF

8291

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D

8292

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x3C201A5

8293

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16

8294

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF

8295

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5

8296

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x3C201A6

8297

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16

8298

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF

8299

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D

8300

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x3C201A7

8301

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16

8302

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF

8303

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4

8304

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x3C201A8

8305

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16

8306

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF

8307

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133

8308

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x3C201A9

8309

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16

8310

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF

8311

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5

8312

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x3C201AA

8313

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16

8314

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF

8315

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114

8316

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x3C201AB

8317

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16

8318

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF

8319

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5

8320

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x3C201AC

8321

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16

8322

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF

8323

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A

8324

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x3C201AD

8325

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16

8326

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF

8327

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4

8328

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x3C201AE

8329

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16

8330

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF

8331

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB

8332

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x3C201AF

8333

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16

8334

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF

8335

#define OFDM_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4

8336

#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__A 0x3C201FE

8337

#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__W 16

8338

#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__M 0xFFFF

8339

#define OFDM_SC_RA_RAM_DRIVER_VERSION_0__PRE 0x0

8340

#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__A 0x3C201FF

8341

#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__W 16

8342

#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__M 0xFFFF

8343

#define OFDM_SC_RA_RAM_DRIVER_VERSION_1__PRE 0x0

#define QAM_COMM_EXEC__A 0x1400000

8350

#define QAM_COMM_EXEC__W 2

8351

#define QAM_COMM_EXEC__M 0x3

8352

#define QAM_COMM_EXEC__PRE 0x0

8353

#define QAM_COMM_EXEC_STOP 0x0

8354

#define QAM_COMM_EXEC_ACTIVE 0x1

8355

#define QAM_COMM_EXEC_HOLD 0x2

8356

8357

#define QAM_COMM_MB__A 0x1400002

8358

#define QAM_COMM_MB__W 16

8359

#define QAM_COMM_MB__M 0xFFFF

8360

#define QAM_COMM_MB__PRE 0x0

8361

#define QAM_COMM_INT_REQ__A 0x1400003

8362

#define QAM_COMM_INT_REQ__W 16

8363

#define QAM_COMM_INT_REQ__M 0xFFFF

8364

#define QAM_COMM_INT_REQ__PRE 0x0

8365

8366

#define QAM_COMM_INT_REQ_SL_REQ__B 0

8367

#define QAM_COMM_INT_REQ_SL_REQ__W 1

8368

#define QAM_COMM_INT_REQ_SL_REQ__M 0x1

8369

#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x0

8370

8371

#define QAM_COMM_INT_REQ_LC_REQ__B 1

8372

#define QAM_COMM_INT_REQ_LC_REQ__W 1

8373

#define QAM_COMM_INT_REQ_LC_REQ__M 0x2

8374

#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x0

8375

8376

#define QAM_COMM_INT_REQ_VD_REQ__B 2

8377

#define QAM_COMM_INT_REQ_VD_REQ__W 1

8378

#define QAM_COMM_INT_REQ_VD_REQ__M 0x4

8379

#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x0

8380

8381

#define QAM_COMM_INT_REQ_SY_REQ__B 3

8382

#define QAM_COMM_INT_REQ_SY_REQ__W 1

8383

#define QAM_COMM_INT_REQ_SY_REQ__M 0x8

8384

#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x0

8385

8386

#define QAM_COMM_INT_STA__A 0x1400005

8387

#define QAM_COMM_INT_STA__W 16

8388

#define QAM_COMM_INT_STA__M 0xFFFF

8389

#define QAM_COMM_INT_STA__PRE 0x0

8390

#define QAM_COMM_INT_MSK__A 0x1400006

8391

#define QAM_COMM_INT_MSK__W 16

8392

#define QAM_COMM_INT_MSK__M 0xFFFF

8393

#define QAM_COMM_INT_MSK__PRE 0x0

8394

#define QAM_COMM_INT_STM__A 0x1400007

8395

#define QAM_COMM_INT_STM__W 16

8396

#define QAM_COMM_INT_STM__M 0xFFFF

8397

#define QAM_COMM_INT_STM__PRE 0x0

#define QAM_TOP_COMM_EXEC__A 0x1410000

8402

#define QAM_TOP_COMM_EXEC__W 2

8403

#define QAM_TOP_COMM_EXEC__M 0x3

8404

#define QAM_TOP_COMM_EXEC__PRE 0x0

8405

#define QAM_TOP_COMM_EXEC_STOP 0x0

8406

#define QAM_TOP_COMM_EXEC_ACTIVE 0x1

8407

#define QAM_TOP_COMM_EXEC_HOLD 0x2

8408

8409

8410

#define QAM_TOP_ANNEX__A 0x1410010

8411

#define QAM_TOP_ANNEX__W 2

8412

#define QAM_TOP_ANNEX__M 0x3

8413

#define QAM_TOP_ANNEX__PRE 0x0

8414

#define QAM_TOP_ANNEX_A 0x0

8415

#define QAM_TOP_ANNEX_B 0x1

8416

#define QAM_TOP_ANNEX_C 0x2

8417

#define QAM_TOP_ANNEX_D 0x3

8418

8419

8420

#define QAM_TOP_CONSTELLATION__A 0x1410011

8421

#define QAM_TOP_CONSTELLATION__W 3

8422

#define QAM_TOP_CONSTELLATION__M 0x7

8423

#define QAM_TOP_CONSTELLATION__PRE 0x5

8424

#define QAM_TOP_CONSTELLATION_NONE 0x0

8425

#define QAM_TOP_CONSTELLATION_QPSK 0x1

8426

#define QAM_TOP_CONSTELLATION_QAM8 0x2

8427

#define QAM_TOP_CONSTELLATION_QAM16 0x3

8428

#define QAM_TOP_CONSTELLATION_QAM32 0x4

8429

#define QAM_TOP_CONSTELLATION_QAM64 0x5

8430

#define QAM_TOP_CONSTELLATION_QAM128 0x6

8431

#define QAM_TOP_CONSTELLATION_QAM256 0x7

#define QAM_FQ_COMM_EXEC__A 0x1420000

8436

#define QAM_FQ_COMM_EXEC__W 2

8437

#define QAM_FQ_COMM_EXEC__M 0x3

8438

#define QAM_FQ_COMM_EXEC__PRE 0x0

8439

#define QAM_FQ_COMM_EXEC_STOP 0x0

8440

#define QAM_FQ_COMM_EXEC_ACTIVE 0x1

8441

#define QAM_FQ_COMM_EXEC_HOLD 0x2

8442

8443

#define QAM_FQ_MODE__A 0x1420010

8444

#define QAM_FQ_MODE__W 3

8445

#define QAM_FQ_MODE__M 0x7

8446

#define QAM_FQ_MODE__PRE 0x0

8447

8448

#define QAM_FQ_MODE_TAPRESET__B 0

8449

#define QAM_FQ_MODE_TAPRESET__W 1

8450

#define QAM_FQ_MODE_TAPRESET__M 0x1

8451

#define QAM_FQ_MODE_TAPRESET__PRE 0x0

8452

#define QAM_FQ_MODE_TAPRESET_RST 0x1

8453

8454

#define QAM_FQ_MODE_TAPLMS__B 1

8455

#define QAM_FQ_MODE_TAPLMS__W 1

8456

#define QAM_FQ_MODE_TAPLMS__M 0x2

8457

#define QAM_FQ_MODE_TAPLMS__PRE 0x0

8458

#define QAM_FQ_MODE_TAPLMS_UPD 0x2

8459

8460

#define QAM_FQ_MODE_TAPDRAIN__B 2

8461

#define QAM_FQ_MODE_TAPDRAIN__W 1

8462

#define QAM_FQ_MODE_TAPDRAIN__M 0x4

8463

#define QAM_FQ_MODE_TAPDRAIN__PRE 0x0

8464

#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x4

8465

8466

8467

#define QAM_FQ_MU_FACTOR__A 0x1420011

8468

#define QAM_FQ_MU_FACTOR__W 3

8469

#define QAM_FQ_MU_FACTOR__M 0x7

8470

#define QAM_FQ_MU_FACTOR__PRE 0x0

8471

8472

#define QAM_FQ_LA_FACTOR__A 0x1420012

8473

#define QAM_FQ_LA_FACTOR__W 4

8474

#define QAM_FQ_LA_FACTOR__M 0xF

8475

#define QAM_FQ_LA_FACTOR__PRE 0xC

8476

#define QAM_FQ_CENTTAP_IDX__A 0x1420016

8477

#define QAM_FQ_CENTTAP_IDX__W 5

8478

#define QAM_FQ_CENTTAP_IDX__M 0x1F

8479

#define QAM_FQ_CENTTAP_IDX__PRE 0x13

8480

8481

#define QAM_FQ_CENTTAP_IDX_IDX__B 0

8482

#define QAM_FQ_CENTTAP_IDX_IDX__W 5

8483

#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F

8484

#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x13

8485

8486

#define QAM_FQ_CENTTAP_VALUE__A 0x1420017

8487

#define QAM_FQ_CENTTAP_VALUE__W 12

8488

#define QAM_FQ_CENTTAP_VALUE__M 0xFFF

8489

#define QAM_FQ_CENTTAP_VALUE__PRE 0x600

8490

8491

#define QAM_FQ_CENTTAP_VALUE_TAP__B 0

8492

#define QAM_FQ_CENTTAP_VALUE_TAP__W 12

8493

#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF

8494

#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x600

8495

8496

#define QAM_FQ_TAP_RE_EL0__A 0x1420020

8497

#define QAM_FQ_TAP_RE_EL0__W 12

8498

#define QAM_FQ_TAP_RE_EL0__M 0xFFF

8499

#define QAM_FQ_TAP_RE_EL0__PRE 0x2

8500

8501

#define QAM_FQ_TAP_RE_EL0_TAP__B 0

8502

#define QAM_FQ_TAP_RE_EL0_TAP__W 12

8503

#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF

8504

#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x2

8505

8506

#define QAM_FQ_TAP_IM_EL0__A 0x1420021

8507

#define QAM_FQ_TAP_IM_EL0__W 12

8508

#define QAM_FQ_TAP_IM_EL0__M 0xFFF

8509

#define QAM_FQ_TAP_IM_EL0__PRE 0x2

8510

8511

#define QAM_FQ_TAP_IM_EL0_TAP__B 0

8512

#define QAM_FQ_TAP_IM_EL0_TAP__W 12

8513

#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF

8514

#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x2

8515

8516

#define QAM_FQ_TAP_RE_EL1__A 0x1420022

8517

#define QAM_FQ_TAP_RE_EL1__W 12

8518

#define QAM_FQ_TAP_RE_EL1__M 0xFFF

8519

#define QAM_FQ_TAP_RE_EL1__PRE 0x2

8520

8521

#define QAM_FQ_TAP_RE_EL1_TAP__B 0

8522

#define QAM_FQ_TAP_RE_EL1_TAP__W 12

8523

#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF

8524

#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x2

8525

8526

#define QAM_FQ_TAP_IM_EL1__A 0x1420023

8527

#define QAM_FQ_TAP_IM_EL1__W 12

8528

#define QAM_FQ_TAP_IM_EL1__M 0xFFF

8529

#define QAM_FQ_TAP_IM_EL1__PRE 0x2

8530

8531

#define QAM_FQ_TAP_IM_EL1_TAP__B 0

8532

#define QAM_FQ_TAP_IM_EL1_TAP__W 12

8533

#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF

8534

#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x2

8535

8536

#define QAM_FQ_TAP_RE_EL2__A 0x1420024

8537

#define QAM_FQ_TAP_RE_EL2__W 12

8538

#define QAM_FQ_TAP_RE_EL2__M 0xFFF

8539

#define QAM_FQ_TAP_RE_EL2__PRE 0x2

8540

8541

#define QAM_FQ_TAP_RE_EL2_TAP__B 0

8542

#define QAM_FQ_TAP_RE_EL2_TAP__W 12

8543

#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF

8544

#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x2

8545

8546

#define QAM_FQ_TAP_IM_EL2__A 0x1420025

8547

#define QAM_FQ_TAP_IM_EL2__W 12

8548

#define QAM_FQ_TAP_IM_EL2__M 0xFFF

8549

#define QAM_FQ_TAP_IM_EL2__PRE 0x2

8550

8551

#define QAM_FQ_TAP_IM_EL2_TAP__B 0

8552

#define QAM_FQ_TAP_IM_EL2_TAP__W 12

8553

#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF

8554

#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x2

8555

8556

#define QAM_FQ_TAP_RE_EL3__A 0x1420026

8557

#define QAM_FQ_TAP_RE_EL3__W 12

8558

#define QAM_FQ_TAP_RE_EL3__M 0xFFF

8559

#define QAM_FQ_TAP_RE_EL3__PRE 0x2

8560

8561

#define QAM_FQ_TAP_RE_EL3_TAP__B 0

8562

#define QAM_FQ_TAP_RE_EL3_TAP__W 12

8563

#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF

8564

#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x2

8565

8566

#define QAM_FQ_TAP_IM_EL3__A 0x1420027

8567

#define QAM_FQ_TAP_IM_EL3__W 12

8568

#define QAM_FQ_TAP_IM_EL3__M 0xFFF

8569

#define QAM_FQ_TAP_IM_EL3__PRE 0x2

8570

8571

#define QAM_FQ_TAP_IM_EL3_TAP__B 0

8572

#define QAM_FQ_TAP_IM_EL3_TAP__W 12

8573

#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF

8574

#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x2

8575

8576

#define QAM_FQ_TAP_RE_EL4__A 0x1420028

8577

#define QAM_FQ_TAP_RE_EL4__W 12

8578

#define QAM_FQ_TAP_RE_EL4__M 0xFFF

8579

#define QAM_FQ_TAP_RE_EL4__PRE 0x2

8580

8581

#define QAM_FQ_TAP_RE_EL4_TAP__B 0

8582

#define QAM_FQ_TAP_RE_EL4_TAP__W 12

8583

#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF

8584

#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x2

8585

8586

#define QAM_FQ_TAP_IM_EL4__A 0x1420029

8587

#define QAM_FQ_TAP_IM_EL4__W 12

8588

#define QAM_FQ_TAP_IM_EL4__M 0xFFF

8589

#define QAM_FQ_TAP_IM_EL4__PRE 0x2

8590

8591

#define QAM_FQ_TAP_IM_EL4_TAP__B 0

8592

#define QAM_FQ_TAP_IM_EL4_TAP__W 12

8593

#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF

8594

#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x2

8595

8596

#define QAM_FQ_TAP_RE_EL5__A 0x142002A

8597

#define QAM_FQ_TAP_RE_EL5__W 12

8598

#define QAM_FQ_TAP_RE_EL5__M 0xFFF

8599

#define QAM_FQ_TAP_RE_EL5__PRE 0x2

8600

8601

#define QAM_FQ_TAP_RE_EL5_TAP__B 0

8602

#define QAM_FQ_TAP_RE_EL5_TAP__W 12

8603

#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF

8604

#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x2

8605

8606

#define QAM_FQ_TAP_IM_EL5__A 0x142002B

8607

#define QAM_FQ_TAP_IM_EL5__W 12

8608

#define QAM_FQ_TAP_IM_EL5__M 0xFFF

8609

#define QAM_FQ_TAP_IM_EL5__PRE 0x2

8610

8611

#define QAM_FQ_TAP_IM_EL5_TAP__B 0

8612

#define QAM_FQ_TAP_IM_EL5_TAP__W 12

8613

#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF

8614

#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x2

8615

8616

#define QAM_FQ_TAP_RE_EL6__A 0x142002C

8617

#define QAM_FQ_TAP_RE_EL6__W 12

8618

#define QAM_FQ_TAP_RE_EL6__M 0xFFF

8619

#define QAM_FQ_TAP_RE_EL6__PRE 0x2

8620

8621

#define QAM_FQ_TAP_RE_EL6_TAP__B 0

8622

#define QAM_FQ_TAP_RE_EL6_TAP__W 12

8623

#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF

8624

#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x2

8625

8626

#define QAM_FQ_TAP_IM_EL6__A 0x142002D

8627

#define QAM_FQ_TAP_IM_EL6__W 12

8628

#define QAM_FQ_TAP_IM_EL6__M 0xFFF

8629

#define QAM_FQ_TAP_IM_EL6__PRE 0x2

8630

8631

#define QAM_FQ_TAP_IM_EL6_TAP__B 0

8632

#define QAM_FQ_TAP_IM_EL6_TAP__W 12

8633

#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF

8634

#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x2

8635

8636

#define QAM_FQ_TAP_RE_EL7__A 0x142002E

8637

#define QAM_FQ_TAP_RE_EL7__W 12

8638

#define QAM_FQ_TAP_RE_EL7__M 0xFFF

8639

#define QAM_FQ_TAP_RE_EL7__PRE 0x2

8640

8641

#define QAM_FQ_TAP_RE_EL7_TAP__B 0

8642

#define QAM_FQ_TAP_RE_EL7_TAP__W 12

8643

#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF

8644

#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x2

8645

8646

#define QAM_FQ_TAP_IM_EL7__A 0x142002F

8647

#define QAM_FQ_TAP_IM_EL7__W 12

8648

#define QAM_FQ_TAP_IM_EL7__M 0xFFF

8649

#define QAM_FQ_TAP_IM_EL7__PRE 0x2

8650

8651

#define QAM_FQ_TAP_IM_EL7_TAP__B 0

8652

#define QAM_FQ_TAP_IM_EL7_TAP__W 12

8653

#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF

8654

#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x2

8655

8656

#define QAM_FQ_TAP_RE_EL8__A 0x1420030

8657

#define QAM_FQ_TAP_RE_EL8__W 12

8658

#define QAM_FQ_TAP_RE_EL8__M 0xFFF

8659

#define QAM_FQ_TAP_RE_EL8__PRE 0x2

8660

8661

#define QAM_FQ_TAP_RE_EL8_TAP__B 0

8662

#define QAM_FQ_TAP_RE_EL8_TAP__W 12

8663

#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF

8664

#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x2

8665

8666

#define QAM_FQ_TAP_IM_EL8__A 0x1420031

8667

#define QAM_FQ_TAP_IM_EL8__W 12

8668

#define QAM_FQ_TAP_IM_EL8__M 0xFFF

8669

#define QAM_FQ_TAP_IM_EL8__PRE 0x2

8670

8671

#define QAM_FQ_TAP_IM_EL8_TAP__B 0

8672

#define QAM_FQ_TAP_IM_EL8_TAP__W 12

8673

#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF

8674

#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x2

8675

8676

#define QAM_FQ_TAP_RE_EL9__A 0x1420032

8677

#define QAM_FQ_TAP_RE_EL9__W 12

8678

#define QAM_FQ_TAP_RE_EL9__M 0xFFF

8679

#define QAM_FQ_TAP_RE_EL9__PRE 0x2

8680

8681

#define QAM_FQ_TAP_RE_EL9_TAP__B 0

8682

#define QAM_FQ_TAP_RE_EL9_TAP__W 12

8683

#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF

8684

#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x2

8685

8686

#define QAM_FQ_TAP_IM_EL9__A 0x1420033

8687

#define QAM_FQ_TAP_IM_EL9__W 12

8688

#define QAM_FQ_TAP_IM_EL9__M 0xFFF

8689

#define QAM_FQ_TAP_IM_EL9__PRE 0x2

8690

8691

#define QAM_FQ_TAP_IM_EL9_TAP__B 0

8692

#define QAM_FQ_TAP_IM_EL9_TAP__W 12

8693

#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF

8694

#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x2

8695

8696

#define QAM_FQ_TAP_RE_EL10__A 0x1420034

8697

#define QAM_FQ_TAP_RE_EL10__W 12

8698

#define QAM_FQ_TAP_RE_EL10__M 0xFFF

8699

#define QAM_FQ_TAP_RE_EL10__PRE 0x2

8700

8701

#define QAM_FQ_TAP_RE_EL10_TAP__B 0

8702

#define QAM_FQ_TAP_RE_EL10_TAP__W 12

8703

#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF

8704

#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x2

8705

8706

#define QAM_FQ_TAP_IM_EL10__A 0x1420035

8707

#define QAM_FQ_TAP_IM_EL10__W 12

8708

#define QAM_FQ_TAP_IM_EL10__M 0xFFF

8709

#define QAM_FQ_TAP_IM_EL10__PRE 0x2

8710

8711

#define QAM_FQ_TAP_IM_EL10_TAP__B 0

8712

#define QAM_FQ_TAP_IM_EL10_TAP__W 12

8713

#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF

8714

#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x2

8715

8716

#define QAM_FQ_TAP_RE_EL11__A 0x1420036

8717

#define QAM_FQ_TAP_RE_EL11__W 12

8718

#define QAM_FQ_TAP_RE_EL11__M 0xFFF

8719

#define QAM_FQ_TAP_RE_EL11__PRE 0x2

8720

8721

#define QAM_FQ_TAP_RE_EL11_TAP__B 0

8722

#define QAM_FQ_TAP_RE_EL11_TAP__W 12

8723

#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF

8724

#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x2

8725

8726

#define QAM_FQ_TAP_IM_EL11__A 0x1420037

8727

#define QAM_FQ_TAP_IM_EL11__W 12

8728

#define QAM_FQ_TAP_IM_EL11__M 0xFFF

8729

#define QAM_FQ_TAP_IM_EL11__PRE 0x2

8730

8731

#define QAM_FQ_TAP_IM_EL11_TAP__B 0

8732

#define QAM_FQ_TAP_IM_EL11_TAP__W 12

8733

#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF

8734

#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x2

8735

8736

#define QAM_FQ_TAP_RE_EL12__A 0x1420038

8737

#define QAM_FQ_TAP_RE_EL12__W 12

8738

#define QAM_FQ_TAP_RE_EL12__M 0xFFF

8739

#define QAM_FQ_TAP_RE_EL12__PRE 0x2

8740

8741

#define QAM_FQ_TAP_RE_EL12_TAP__B 0

8742

#define QAM_FQ_TAP_RE_EL12_TAP__W 12

8743

#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF

8744

#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x2

8745

8746

#define QAM_FQ_TAP_IM_EL12__A 0x1420039

8747

#define QAM_FQ_TAP_IM_EL12__W 12

8748

#define QAM_FQ_TAP_IM_EL12__M 0xFFF

8749

#define QAM_FQ_TAP_IM_EL12__PRE 0x2

8750

8751

#define QAM_FQ_TAP_IM_EL12_TAP__B 0

8752

#define QAM_FQ_TAP_IM_EL12_TAP__W 12

8753

#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF

8754

#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x2

8755

8756

#define QAM_FQ_TAP_RE_EL13__A 0x142003A

8757

#define QAM_FQ_TAP_RE_EL13__W 12

8758

#define QAM_FQ_TAP_RE_EL13__M 0xFFF

8759

#define QAM_FQ_TAP_RE_EL13__PRE 0x2

8760

8761

#define QAM_FQ_TAP_RE_EL13_TAP__B 0

8762

#define QAM_FQ_TAP_RE_EL13_TAP__W 12

8763

#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF

8764

#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x2

8765

8766

#define QAM_FQ_TAP_IM_EL13__A 0x142003B

8767

#define QAM_FQ_TAP_IM_EL13__W 12

8768

#define QAM_FQ_TAP_IM_EL13__M 0xFFF

8769

#define QAM_FQ_TAP_IM_EL13__PRE 0x2

8770

8771

#define QAM_FQ_TAP_IM_EL13_TAP__B 0

8772

#define QAM_FQ_TAP_IM_EL13_TAP__W 12

8773

#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF

8774

#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x2

8775

8776

#define QAM_FQ_TAP_RE_EL14__A 0x142003C

8777

#define QAM_FQ_TAP_RE_EL14__W 12

8778

#define QAM_FQ_TAP_RE_EL14__M 0xFFF

8779

#define QAM_FQ_TAP_RE_EL14__PRE 0x2

8780

8781

#define QAM_FQ_TAP_RE_EL14_TAP__B 0

8782

#define QAM_FQ_TAP_RE_EL14_TAP__W 12

8783

#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF

8784

#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x2

8785

8786

#define QAM_FQ_TAP_IM_EL14__A 0x142003D

8787

#define QAM_FQ_TAP_IM_EL14__W 12

8788

#define QAM_FQ_TAP_IM_EL14__M 0xFFF

8789

#define QAM_FQ_TAP_IM_EL14__PRE 0x2

8790

8791

#define QAM_FQ_TAP_IM_EL14_TAP__B 0

8792

#define QAM_FQ_TAP_IM_EL14_TAP__W 12

8793

#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF

8794

#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x2

8795

8796

#define QAM_FQ_TAP_RE_EL15__A 0x142003E

8797

#define QAM_FQ_TAP_RE_EL15__W 12

8798

#define QAM_FQ_TAP_RE_EL15__M 0xFFF

8799

#define QAM_FQ_TAP_RE_EL15__PRE 0x2

8800

8801

#define QAM_FQ_TAP_RE_EL15_TAP__B 0

8802

#define QAM_FQ_TAP_RE_EL15_TAP__W 12

8803

#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF

8804

#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x2

8805

8806

#define QAM_FQ_TAP_IM_EL15__A 0x142003F

8807

#define QAM_FQ_TAP_IM_EL15__W 12

8808

#define QAM_FQ_TAP_IM_EL15__M 0xFFF

8809

#define QAM_FQ_TAP_IM_EL15__PRE 0x2

8810

8811

#define QAM_FQ_TAP_IM_EL15_TAP__B 0

8812

#define QAM_FQ_TAP_IM_EL15_TAP__W 12

8813

#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF

8814

#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x2

8815

8816

#define QAM_FQ_TAP_RE_EL16__A 0x1420040

8817

#define QAM_FQ_TAP_RE_EL16__W 12

8818

#define QAM_FQ_TAP_RE_EL16__M 0xFFF

8819

#define QAM_FQ_TAP_RE_EL16__PRE 0x2

8820

8821

#define QAM_FQ_TAP_RE_EL16_TAP__B 0

8822

#define QAM_FQ_TAP_RE_EL16_TAP__W 12

8823

#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF

8824

#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x2

8825

8826

#define QAM_FQ_TAP_IM_EL16__A 0x1420041

8827

#define QAM_FQ_TAP_IM_EL16__W 12

8828

#define QAM_FQ_TAP_IM_EL16__M 0xFFF

8829

#define QAM_FQ_TAP_IM_EL16__PRE 0x2

8830

8831

#define QAM_FQ_TAP_IM_EL16_TAP__B 0

8832

#define QAM_FQ_TAP_IM_EL16_TAP__W 12

8833

#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF

8834

#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x2

8835

8836

#define QAM_FQ_TAP_RE_EL17__A 0x1420042

8837

#define QAM_FQ_TAP_RE_EL17__W 12

8838

#define QAM_FQ_TAP_RE_EL17__M 0xFFF

8839

#define QAM_FQ_TAP_RE_EL17__PRE 0x2

8840

8841

#define QAM_FQ_TAP_RE_EL17_TAP__B 0

8842

#define QAM_FQ_TAP_RE_EL17_TAP__W 12

8843

#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF

8844

#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x2

8845

8846

#define QAM_FQ_TAP_IM_EL17__A 0x1420043

8847

#define QAM_FQ_TAP_IM_EL17__W 12

8848

#define QAM_FQ_TAP_IM_EL17__M 0xFFF

8849

#define QAM_FQ_TAP_IM_EL17__PRE 0x2

8850

8851

#define QAM_FQ_TAP_IM_EL17_TAP__B 0

8852

#define QAM_FQ_TAP_IM_EL17_TAP__W 12

8853

#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF

8854

#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x2

8855

8856

#define QAM_FQ_TAP_RE_EL18__A 0x1420044

8857

#define QAM_FQ_TAP_RE_EL18__W 12

8858

#define QAM_FQ_TAP_RE_EL18__M 0xFFF

8859

#define QAM_FQ_TAP_RE_EL18__PRE 0x2

8860

8861

#define QAM_FQ_TAP_RE_EL18_TAP__B 0

8862

#define QAM_FQ_TAP_RE_EL18_TAP__W 12

8863

#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF

8864

#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x2

8865

8866

#define QAM_FQ_TAP_IM_EL18__A 0x1420045

8867

#define QAM_FQ_TAP_IM_EL18__W 12

8868

#define QAM_FQ_TAP_IM_EL18__M 0xFFF

8869

#define QAM_FQ_TAP_IM_EL18__PRE 0x2

8870

8871

#define QAM_FQ_TAP_IM_EL18_TAP__B 0

8872

#define QAM_FQ_TAP_IM_EL18_TAP__W 12

8873

#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF

8874

#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x2

8875

8876

#define QAM_FQ_TAP_RE_EL19__A 0x1420046

8877

#define QAM_FQ_TAP_RE_EL19__W 12

8878

#define QAM_FQ_TAP_RE_EL19__M 0xFFF

8879

#define QAM_FQ_TAP_RE_EL19__PRE 0x600

8880

8881

#define QAM_FQ_TAP_RE_EL19_TAP__B 0

8882

#define QAM_FQ_TAP_RE_EL19_TAP__W 12

8883

#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF

8884

#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x600

8885

8886

#define QAM_FQ_TAP_IM_EL19__A 0x1420047

8887

#define QAM_FQ_TAP_IM_EL19__W 12

8888

#define QAM_FQ_TAP_IM_EL19__M 0xFFF

8889

#define QAM_FQ_TAP_IM_EL19__PRE 0x2

8890

8891

#define QAM_FQ_TAP_IM_EL19_TAP__B 0

8892

#define QAM_FQ_TAP_IM_EL19_TAP__W 12

8893

#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF

8894

#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x2

8895

8896

#define QAM_FQ_TAP_RE_EL20__A 0x1420048

8897

#define QAM_FQ_TAP_RE_EL20__W 12

8898

#define QAM_FQ_TAP_RE_EL20__M 0xFFF

8899

#define QAM_FQ_TAP_RE_EL20__PRE 0x2

8900

8901

#define QAM_FQ_TAP_RE_EL20_TAP__B 0

8902

#define QAM_FQ_TAP_RE_EL20_TAP__W 12

8903

#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF

8904

#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x2

8905

8906

#define QAM_FQ_TAP_IM_EL20__A 0x1420049

8907

#define QAM_FQ_TAP_IM_EL20__W 12

8908

#define QAM_FQ_TAP_IM_EL20__M 0xFFF

8909

#define QAM_FQ_TAP_IM_EL20__PRE 0x2

8910

8911

#define QAM_FQ_TAP_IM_EL20_TAP__B 0

8912

#define QAM_FQ_TAP_IM_EL20_TAP__W 12

8913

#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF

8914

#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x2

8915

8916

#define QAM_FQ_TAP_RE_EL21__A 0x142004A

8917

#define QAM_FQ_TAP_RE_EL21__W 12

8918

#define QAM_FQ_TAP_RE_EL21__M 0xFFF

8919

#define QAM_FQ_TAP_RE_EL21__PRE 0x2

8920

8921

#define QAM_FQ_TAP_RE_EL21_TAP__B 0

8922

#define QAM_FQ_TAP_RE_EL21_TAP__W 12

8923

#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF

8924

#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x2

8925

8926

#define QAM_FQ_TAP_IM_EL21__A 0x142004B

8927

#define QAM_FQ_TAP_IM_EL21__W 12

8928

#define QAM_FQ_TAP_IM_EL21__M 0xFFF

8929

#define QAM_FQ_TAP_IM_EL21__PRE 0x2

8930

8931

#define QAM_FQ_TAP_IM_EL21_TAP__B 0

8932

#define QAM_FQ_TAP_IM_EL21_TAP__W 12

8933

#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF

8934

#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x2

8935

8936

#define QAM_FQ_TAP_RE_EL22__A 0x142004C

8937

#define QAM_FQ_TAP_RE_EL22__W 12

8938

#define QAM_FQ_TAP_RE_EL22__M 0xFFF

8939

#define QAM_FQ_TAP_RE_EL22__PRE 0x2

8940

8941

#define QAM_FQ_TAP_RE_EL22_TAP__B 0

8942

#define QAM_FQ_TAP_RE_EL22_TAP__W 12

8943

#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF

8944

#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x2

8945

8946

#define QAM_FQ_TAP_IM_EL22__A 0x142004D

8947

#define QAM_FQ_TAP_IM_EL22__W 12

8948

#define QAM_FQ_TAP_IM_EL22__M 0xFFF

8949

#define QAM_FQ_TAP_IM_EL22__PRE 0x2

8950

8951

#define QAM_FQ_TAP_IM_EL22_TAP__B 0

8952

#define QAM_FQ_TAP_IM_EL22_TAP__W 12

8953

#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF

8954

#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x2

8955

8956

#define QAM_FQ_TAP_RE_EL23__A 0x142004E

8957

#define QAM_FQ_TAP_RE_EL23__W 12

8958

#define QAM_FQ_TAP_RE_EL23__M 0xFFF

8959

#define QAM_FQ_TAP_RE_EL23__PRE 0x2

8960

8961

#define QAM_FQ_TAP_RE_EL23_TAP__B 0

8962

#define QAM_FQ_TAP_RE_EL23_TAP__W 12

8963

#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF

8964

#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x2

8965

8966

#define QAM_FQ_TAP_IM_EL23__A 0x142004F

8967

#define QAM_FQ_TAP_IM_EL23__W 12

8968

#define QAM_FQ_TAP_IM_EL23__M 0xFFF

8969

#define QAM_FQ_TAP_IM_EL23__PRE 0x2

8970

8971

#define QAM_FQ_TAP_IM_EL23_TAP__B 0

8972

#define QAM_FQ_TAP_IM_EL23_TAP__W 12

8973

#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF

8974

#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x2

#define QAM_SL_COMM_EXEC__A 0x1430000

8979

#define QAM_SL_COMM_EXEC__W 2

8980

#define QAM_SL_COMM_EXEC__M 0x3

8981

#define QAM_SL_COMM_EXEC__PRE 0x0

8982

#define QAM_SL_COMM_EXEC_STOP 0x0

8983

#define QAM_SL_COMM_EXEC_ACTIVE 0x1

8984

#define QAM_SL_COMM_EXEC_HOLD 0x2

8985

8986

#define QAM_SL_COMM_MB__A 0x1430002

8987

#define QAM_SL_COMM_MB__W 4

8988

#define QAM_SL_COMM_MB__M 0xF

8989

#define QAM_SL_COMM_MB__PRE 0x0

8990

#define QAM_SL_COMM_MB_CTL__B 0

8991

#define QAM_SL_COMM_MB_CTL__W 1

8992

#define QAM_SL_COMM_MB_CTL__M 0x1

8993

#define QAM_SL_COMM_MB_CTL__PRE 0x0

8994

#define QAM_SL_COMM_MB_CTL_OFF 0x0

8995

#define QAM_SL_COMM_MB_CTL_ON 0x1

8996

#define QAM_SL_COMM_MB_OBS__B 1

8997

#define QAM_SL_COMM_MB_OBS__W 1

8998

#define QAM_SL_COMM_MB_OBS__M 0x2

8999

#define QAM_SL_COMM_MB_OBS__PRE 0x0

9000

#define QAM_SL_COMM_MB_OBS_OFF 0x0

9001

#define QAM_SL_COMM_MB_OBS_ON 0x2

9002

#define QAM_SL_COMM_MB_MUX_OBS__B 2

9003

#define QAM_SL_COMM_MB_MUX_OBS__W 2

9004

#define QAM_SL_COMM_MB_MUX_OBS__M 0xC

9005

#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x0

9006

#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x0

9007

#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x4

9008

#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x8

9009

#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC

9010

9011

#define QAM_SL_COMM_INT_REQ__A 0x1430003

9012

#define QAM_SL_COMM_INT_REQ__W 1

9013

#define QAM_SL_COMM_INT_REQ__M 0x1

9014

#define QAM_SL_COMM_INT_REQ__PRE 0x0

9015

#define QAM_SL_COMM_INT_STA__A 0x1430005

9016

#define QAM_SL_COMM_INT_STA__W 2

9017

#define QAM_SL_COMM_INT_STA__M 0x3

9018

#define QAM_SL_COMM_INT_STA__PRE 0x0

9019

9020

#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 0

9021

#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 1

9022

#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x1

9023

#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x0

9024

9025

#define QAM_SL_COMM_INT_STA_MER_INT__B 1

9026

#define QAM_SL_COMM_INT_STA_MER_INT__W 1

9027

#define QAM_SL_COMM_INT_STA_MER_INT__M 0x2

9028

#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x0

9029

9030

#define QAM_SL_COMM_INT_MSK__A 0x1430006

9031

#define QAM_SL_COMM_INT_MSK__W 2

9032

#define QAM_SL_COMM_INT_MSK__M 0x3

9033

#define QAM_SL_COMM_INT_MSK__PRE 0x0

9034

#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 0

9035

#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 1

9036

#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x1

9037

#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x0

9038

#define QAM_SL_COMM_INT_MSK_MER_MSK__B 1

9039

#define QAM_SL_COMM_INT_MSK_MER_MSK__W 1

9040

#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x2

9041

#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x0

9042

9043

#define QAM_SL_COMM_INT_STM__A 0x1430007

9044

#define QAM_SL_COMM_INT_STM__W 2

9045

#define QAM_SL_COMM_INT_STM__M 0x3

9046

#define QAM_SL_COMM_INT_STM__PRE 0x0

9047

#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 0

9048

#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 1

9049

#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x1

9050

#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x0

9051

#define QAM_SL_COMM_INT_STM_MER_STM__B 1

9052

#define QAM_SL_COMM_INT_STM_MER_STM__W 1

9053

#define QAM_SL_COMM_INT_STM_MER_STM__M 0x2

9054

#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x0

9055

9056

#define QAM_SL_MODE__A 0x1430010

9057

#define QAM_SL_MODE__W 11

9058

#define QAM_SL_MODE__M 0x7FF

9059

#define QAM_SL_MODE__PRE 0xA

9060

9061

#define QAM_SL_MODE_SLICER4LC__B 0

9062

#define QAM_SL_MODE_SLICER4LC__W 2

9063

#define QAM_SL_MODE_SLICER4LC__M 0x3

9064

#define QAM_SL_MODE_SLICER4LC__PRE 0x2

9065

#define QAM_SL_MODE_SLICER4LC_RECT 0x0

9066

#define QAM_SL_MODE_SLICER4LC_ONET 0x1

9067

#define QAM_SL_MODE_SLICER4LC_RAD 0x2

9068

9069

#define QAM_SL_MODE_SLICER4DQ__B 2

9070

#define QAM_SL_MODE_SLICER4DQ__W 2

9071

#define QAM_SL_MODE_SLICER4DQ__M 0xC

9072

#define QAM_SL_MODE_SLICER4DQ__PRE 0x8

9073

#define QAM_SL_MODE_SLICER4DQ_RECT 0x0

9074

#define QAM_SL_MODE_SLICER4DQ_ONET 0x4

9075

#define QAM_SL_MODE_SLICER4DQ_RAD 0x8

9076

9077

#define QAM_SL_MODE_SLICER4VD__B 4

9078

#define QAM_SL_MODE_SLICER4VD__W 2

9079

#define QAM_SL_MODE_SLICER4VD__M 0x30

9080

#define QAM_SL_MODE_SLICER4VD__PRE 0x0

9081

#define QAM_SL_MODE_SLICER4VD_RECT 0x0

9082

#define QAM_SL_MODE_SLICER4VD_ONET 0x10

9083

#define QAM_SL_MODE_SLICER4VD_RAD 0x20

9084

9085

#define QAM_SL_MODE_ROT_DIS__B 6

9086

#define QAM_SL_MODE_ROT_DIS__W 1

9087

#define QAM_SL_MODE_ROT_DIS__M 0x40

9088

#define QAM_SL_MODE_ROT_DIS__PRE 0x0

9089

#define QAM_SL_MODE_ROT_DIS_ROTATE 0x0

9090

#define QAM_SL_MODE_ROT_DIS_DISABLED 0x40

9091

9092

#define QAM_SL_MODE_DQROT_DIS__B 7

9093

#define QAM_SL_MODE_DQROT_DIS__W 1

9094

#define QAM_SL_MODE_DQROT_DIS__M 0x80

9095

#define QAM_SL_MODE_DQROT_DIS__PRE 0x0

9096

#define QAM_SL_MODE_DQROT_DIS_ROTATE 0x0

9097

#define QAM_SL_MODE_DQROT_DIS_DISABLED 0x80

9098

9099

#define QAM_SL_MODE_DFE_DIS__B 8

9100

#define QAM_SL_MODE_DFE_DIS__W 1

9101

#define QAM_SL_MODE_DFE_DIS__M 0x100

9102

#define QAM_SL_MODE_DFE_DIS__PRE 0x0

9103

#define QAM_SL_MODE_DFE_DIS_DQ 0x0

9104

#define QAM_SL_MODE_DFE_DIS_DISABLED 0x100

9105

9106

#define QAM_SL_MODE_RADIUS_MIX__B 9

9107

#define QAM_SL_MODE_RADIUS_MIX__W 1

9108

#define QAM_SL_MODE_RADIUS_MIX__M 0x200

9109

#define QAM_SL_MODE_RADIUS_MIX__PRE 0x0

9110

#define QAM_SL_MODE_RADIUS_MIX_OFF 0x0

9111

#define QAM_SL_MODE_RADIUS_MIX_RADMIX 0x200

9112

9113

#define QAM_SL_MODE_TILT_COMP__B 10

9114

#define QAM_SL_MODE_TILT_COMP__W 1

9115

#define QAM_SL_MODE_TILT_COMP__M 0x400

9116

#define QAM_SL_MODE_TILT_COMP__PRE 0x0

9117

#define QAM_SL_MODE_TILT_COMP_OFF 0x0

9118

#define QAM_SL_MODE_TILT_COMP_TILTCOMP 0x400

9119

9120

9121

#define QAM_SL_K_FACTOR__A 0x1430011

9122

#define QAM_SL_K_FACTOR__W 4

9123

#define QAM_SL_K_FACTOR__M 0xF

9124

#define QAM_SL_K_FACTOR__PRE 0xC

9125

#define QAM_SL_MEDIAN__A 0x1430012

9126

#define QAM_SL_MEDIAN__W 14

9127

#define QAM_SL_MEDIAN__M 0x3FFF

9128

#define QAM_SL_MEDIAN__PRE 0x2C86

9129

9130

#define QAM_SL_MEDIAN_LENGTH__B 0

9131

#define QAM_SL_MEDIAN_LENGTH__W 2

9132

#define QAM_SL_MEDIAN_LENGTH__M 0x3

9133

#define QAM_SL_MEDIAN_LENGTH__PRE 0x2

9134

#define QAM_SL_MEDIAN_LENGTH_MEDL1 0x0

9135

#define QAM_SL_MEDIAN_LENGTH_MEDL2 0x1

9136

#define QAM_SL_MEDIAN_LENGTH_MEDL4 0x2

9137

#define QAM_SL_MEDIAN_LENGTH_MEDL8 0x3

9138

9139

#define QAM_SL_MEDIAN_CORRECT__B 2

9140

#define QAM_SL_MEDIAN_CORRECT__W 4

9141

#define QAM_SL_MEDIAN_CORRECT__M 0x3C

9142

#define QAM_SL_MEDIAN_CORRECT__PRE 0x4

9143

9144

#define QAM_SL_MEDIAN_TOLERANCE__B 6

9145

#define QAM_SL_MEDIAN_TOLERANCE__W 7

9146

#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC0

9147

#define QAM_SL_MEDIAN_TOLERANCE__PRE 0xC80

9148

9149

#define QAM_SL_MEDIAN_FAST__B 13

9150

#define QAM_SL_MEDIAN_FAST__W 1

9151

#define QAM_SL_MEDIAN_FAST__M 0x2000

9152

#define QAM_SL_MEDIAN_FAST__PRE 0x2000

9153

#define QAM_SL_MEDIAN_FAST_AVER 0x0

9154

#define QAM_SL_MEDIAN_FAST_LAST 0x2000

9155

9156

9157

#define QAM_SL_ALPHA__A 0x1430013

9158

#define QAM_SL_ALPHA__W 3

9159

#define QAM_SL_ALPHA__M 0x7

9160

#define QAM_SL_ALPHA__PRE 0x0

9161

9162

#define QAM_SL_PHASELIMIT__A 0x1430014

9163

#define QAM_SL_PHASELIMIT__W 9

9164

#define QAM_SL_PHASELIMIT__M 0x1FF

9165

#define QAM_SL_PHASELIMIT__PRE 0x0

9166

#define QAM_SL_MTA_LENGTH__A 0x1430015

9167

#define QAM_SL_MTA_LENGTH__W 2

9168

#define QAM_SL_MTA_LENGTH__M 0x3

9169

#define QAM_SL_MTA_LENGTH__PRE 0x1

9170

9171

#define QAM_SL_MTA_LENGTH_LENGTH__B 0

9172

#define QAM_SL_MTA_LENGTH_LENGTH__W 2

9173

#define QAM_SL_MTA_LENGTH_LENGTH__M 0x3

9174

#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x1

9175

9176

#define QAM_SL_MEDIAN_ERROR__A 0x1430016

9177

#define QAM_SL_MEDIAN_ERROR__W 10

9178

#define QAM_SL_MEDIAN_ERROR__M 0x3FF

9179

#define QAM_SL_MEDIAN_ERROR__PRE 0x0

9180

9181

#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 0

9182

#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 10

9183

#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF

9184

#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x0

9185

9186

9187

#define QAM_SL_ERR_POWER__A 0x1430017

9188

#define QAM_SL_ERR_POWER__W 16

9189

#define QAM_SL_ERR_POWER__M 0xFFFF

9190

#define QAM_SL_ERR_POWER__PRE 0x0

9191

#define QAM_SL_QUAL_QAM_4_0__A 0x1430018

9192

#define QAM_SL_QUAL_QAM_4_0__W 3

9193

#define QAM_SL_QUAL_QAM_4_0__M 0x7

9194

#define QAM_SL_QUAL_QAM_4_0__PRE 0x5

9195

9196

#define QAM_SL_QUAL_QAM_4_0_Q0__B 0

9197

#define QAM_SL_QUAL_QAM_4_0_Q0__W 3

9198

#define QAM_SL_QUAL_QAM_4_0_Q0__M 0x7

9199

#define QAM_SL_QUAL_QAM_4_0_Q0__PRE 0x5

9200

9201

#define QAM_SL_QUAL_QAM_8_0__A 0x1430019

9202

#define QAM_SL_QUAL_QAM_8_0__W 6

9203

#define QAM_SL_QUAL_QAM_8_0__M 0x3F

9204

#define QAM_SL_QUAL_QAM_8_0__PRE 0xD

9205

9206

#define QAM_SL_QUAL_QAM_8_0_Q0__B 0

9207

#define QAM_SL_QUAL_QAM_8_0_Q0__W 3

9208

#define QAM_SL_QUAL_QAM_8_0_Q0__M 0x7

9209

#define QAM_SL_QUAL_QAM_8_0_Q0__PRE 0x5

9210

9211

#define QAM_SL_QUAL_QAM_8_0_Q1__B 3

9212

#define QAM_SL_QUAL_QAM_8_0_Q1__W 3

9213

#define QAM_SL_QUAL_QAM_8_0_Q1__M 0x38

9214

#define QAM_SL_QUAL_QAM_8_0_Q1__PRE 0x8

9215

9216

#define QAM_SL_QUAL_QAM_16_0__A 0x143001A

9217

#define QAM_SL_QUAL_QAM_16_0__W 3

9218

#define QAM_SL_QUAL_QAM_16_0__M 0x7

9219

#define QAM_SL_QUAL_QAM_16_0__PRE 0x1

9220

9221

#define QAM_SL_QUAL_QAM_16_0_Q0__B 0

9222

#define QAM_SL_QUAL_QAM_16_0_Q0__W 3

9223

#define QAM_SL_QUAL_QAM_16_0_Q0__M 0x7

9224

#define QAM_SL_QUAL_QAM_16_0_Q0__PRE 0x1

9225

9226

#define QAM_SL_QUAL_QAM_16_1__A 0x143001B

9227

#define QAM_SL_QUAL_QAM_16_1__W 6

9228

#define QAM_SL_QUAL_QAM_16_1__M 0x3F

9229

#define QAM_SL_QUAL_QAM_16_1__PRE 0x5

9230

9231

#define QAM_SL_QUAL_QAM_16_1_Q0__B 0

9232

#define QAM_SL_QUAL_QAM_16_1_Q0__W 3

9233

#define QAM_SL_QUAL_QAM_16_1_Q0__M 0x7

9234

#define QAM_SL_QUAL_QAM_16_1_Q0__PRE 0x5

9235

9236

#define QAM_SL_QUAL_QAM_16_1_Q1__B 3

9237

#define QAM_SL_QUAL_QAM_16_1_Q1__W 3

9238

#define QAM_SL_QUAL_QAM_16_1_Q1__M 0x38

9239

#define QAM_SL_QUAL_QAM_16_1_Q1__PRE 0x0

9240

9241

#define QAM_SL_QUAL_QAM_32_0__A 0x143001C

9242

#define QAM_SL_QUAL_QAM_32_0__W 3

9243

#define QAM_SL_QUAL_QAM_32_0__M 0x7

9244

#define QAM_SL_QUAL_QAM_32_0__PRE 0x4

9245

9246

#define QAM_SL_QUAL_QAM_32_0_Q0__B 0

9247

#define QAM_SL_QUAL_QAM_32_0_Q0__W 3

9248

#define QAM_SL_QUAL_QAM_32_0_Q0__M 0x7

9249

#define QAM_SL_QUAL_QAM_32_0_Q0__PRE 0x4

9250

9251

#define QAM_SL_QUAL_QAM_32_1__A 0x143001D

9252

#define QAM_SL_QUAL_QAM_32_1__W 6

9253

#define QAM_SL_QUAL_QAM_32_1__M 0x3F

9254

#define QAM_SL_QUAL_QAM_32_1__PRE 0x3

9255

9256

#define QAM_SL_QUAL_QAM_32_1_Q0__B 0

9257

#define QAM_SL_QUAL_QAM_32_1_Q0__W 3

9258

#define QAM_SL_QUAL_QAM_32_1_Q0__M 0x7

9259

#define QAM_SL_QUAL_QAM_32_1_Q0__PRE 0x3

9260

9261

#define QAM_SL_QUAL_QAM_32_1_Q1__B 3

9262

#define QAM_SL_QUAL_QAM_32_1_Q1__W 3

9263

#define QAM_SL_QUAL_QAM_32_1_Q1__M 0x38

9264

#define QAM_SL_QUAL_QAM_32_1_Q1__PRE 0x0

9265

9266

#define QAM_SL_QUAL_QAM_32_2__A 0x143001E

9267

#define QAM_SL_QUAL_QAM_32_2__W 9

9268

#define QAM_SL_QUAL_QAM_32_2__M 0x1FF

9269

#define QAM_SL_QUAL_QAM_32_2__PRE 0x0

9270

9271

#define QAM_SL_QUAL_QAM_32_2_Q0__B 0

9272

#define QAM_SL_QUAL_QAM_32_2_Q0__W 3

9273

#define QAM_SL_QUAL_QAM_32_2_Q0__M 0x7

9274

#define QAM_SL_QUAL_QAM_32_2_Q0__PRE 0x0

9275

9276

#define QAM_SL_QUAL_QAM_32_2_Q1__B 3

9277

#define QAM_SL_QUAL_QAM_32_2_Q1__W 3

9278

#define QAM_SL_QUAL_QAM_32_2_Q1__M 0x38

9279

#define QAM_SL_QUAL_QAM_32_2_Q1__PRE 0x0

9280

9281

#define QAM_SL_QUAL_QAM_32_2_Q2__B 6

9282

#define QAM_SL_QUAL_QAM_32_2_Q2__W 3

9283

#define QAM_SL_QUAL_QAM_32_2_Q2__M 0x1C0

9284

#define QAM_SL_QUAL_QAM_32_2_Q2__PRE 0x0

9285

9286

#define QAM_SL_QUAL_QAM_64_0__A 0x143001F

9287

#define QAM_SL_QUAL_QAM_64_0__W 3

9288

#define QAM_SL_QUAL_QAM_64_0__M 0x7

9289

#define QAM_SL_QUAL_QAM_64_0__PRE 0x1

9290

9291

#define QAM_SL_QUAL_QAM_64_0_Q0__B 0

9292

#define QAM_SL_QUAL_QAM_64_0_Q0__W 3

9293

#define QAM_SL_QUAL_QAM_64_0_Q0__M 0x7

9294

#define QAM_SL_QUAL_QAM_64_0_Q0__PRE 0x1

9295

9296

#define QAM_SL_QUAL_QAM_64_1__A 0x1430020

9297

#define QAM_SL_QUAL_QAM_64_1__W 6

9298

#define QAM_SL_QUAL_QAM_64_1__M 0x3F

9299

#define QAM_SL_QUAL_QAM_64_1__PRE 0x2

9300

9301

#define QAM_SL_QUAL_QAM_64_1_Q0__B 0

9302

#define QAM_SL_QUAL_QAM_64_1_Q0__W 3

9303

#define QAM_SL_QUAL_QAM_64_1_Q0__M 0x7

9304

#define QAM_SL_QUAL_QAM_64_1_Q0__PRE 0x2

9305

9306

#define QAM_SL_QUAL_QAM_64_1_Q1__B 3

9307

#define QAM_SL_QUAL_QAM_64_1_Q1__W 3

9308

#define QAM_SL_QUAL_QAM_64_1_Q1__M 0x38

9309

#define QAM_SL_QUAL_QAM_64_1_Q1__PRE 0x0

9310

9311

#define QAM_SL_QUAL_QAM_64_2__A 0x1430021

9312

#define QAM_SL_QUAL_QAM_64_2__W 9

9313

#define QAM_SL_QUAL_QAM_64_2__M 0x1FF

9314

#define QAM_SL_QUAL_QAM_64_2__PRE 0x9

9315

9316

#define QAM_SL_QUAL_QAM_64_2_Q0__B 0

9317

#define QAM_SL_QUAL_QAM_64_2_Q0__W 3

9318

#define QAM_SL_QUAL_QAM_64_2_Q0__M 0x7

9319

#define QAM_SL_QUAL_QAM_64_2_Q0__PRE 0x1

9320

9321

#define QAM_SL_QUAL_QAM_64_2_Q1__B 3

9322

#define QAM_SL_QUAL_QAM_64_2_Q1__W 3

9323

#define QAM_SL_QUAL_QAM_64_2_Q1__M 0x38

9324

#define QAM_SL_QUAL_QAM_64_2_Q1__PRE 0x8

9325

9326

#define QAM_SL_QUAL_QAM_64_2_Q2__B 6

9327

#define QAM_SL_QUAL_QAM_64_2_Q2__W 3

9328

#define QAM_SL_QUAL_QAM_64_2_Q2__M 0x1C0

9329

#define QAM_SL_QUAL_QAM_64_2_Q2__PRE 0x0

9330

9331

#define QAM_SL_QUAL_QAM_64_3__A 0x1430022

9332

#define QAM_SL_QUAL_QAM_64_3__W 12

9333

#define QAM_SL_QUAL_QAM_64_3__M 0xFFF

9334

#define QAM_SL_QUAL_QAM_64_3__PRE 0xD

9335

9336

#define QAM_SL_QUAL_QAM_64_3_Q0__B 0

9337

#define QAM_SL_QUAL_QAM_64_3_Q0__W 3

9338

#define QAM_SL_QUAL_QAM_64_3_Q0__M 0x7

9339

#define QAM_SL_QUAL_QAM_64_3_Q0__PRE 0x5

9340

9341

#define QAM_SL_QUAL_QAM_64_3_Q1__B 3

9342

#define QAM_SL_QUAL_QAM_64_3_Q1__W 3

9343

#define QAM_SL_QUAL_QAM_64_3_Q1__M 0x38

9344

#define QAM_SL_QUAL_QAM_64_3_Q1__PRE 0x8

9345

9346

#define QAM_SL_QUAL_QAM_64_3_Q2__B 6

9347

#define QAM_SL_QUAL_QAM_64_3_Q2__W 3

9348

#define QAM_SL_QUAL_QAM_64_3_Q2__M 0x1C0

9349

#define QAM_SL_QUAL_QAM_64_3_Q2__PRE 0x0

9350

9351

#define QAM_SL_QUAL_QAM_64_3_Q3__B 9

9352

#define QAM_SL_QUAL_QAM_64_3_Q3__W 3

9353

#define QAM_SL_QUAL_QAM_64_3_Q3__M 0xE00

9354

#define QAM_SL_QUAL_QAM_64_3_Q3__PRE 0x0

9355

9356

#define QAM_SL_QUAL_QAM_128_0__A 0x1430023

9357

#define QAM_SL_QUAL_QAM_128_0__W 3

9358

#define QAM_SL_QUAL_QAM_128_0__M 0x7

9359

#define QAM_SL_QUAL_QAM_128_0__PRE 0x4

9360

9361

#define QAM_SL_QUAL_QAM_128_0_Q0__B 0

9362

#define QAM_SL_QUAL_QAM_128_0_Q0__W 3

9363

#define QAM_SL_QUAL_QAM_128_0_Q0__M 0x7

9364

#define QAM_SL_QUAL_QAM_128_0_Q0__PRE 0x4

9365

9366

#define QAM_SL_QUAL_QAM_128_1__A 0x1430024

9367

#define QAM_SL_QUAL_QAM_128_1__W 6

9368

#define QAM_SL_QUAL_QAM_128_1__M 0x3F

9369

#define QAM_SL_QUAL_QAM_128_1__PRE 0x5

9370

9371

#define QAM_SL_QUAL_QAM_128_1_Q0__B 0

9372

#define QAM_SL_QUAL_QAM_128_1_Q0__W 3

9373

#define QAM_SL_QUAL_QAM_128_1_Q0__M 0x7

9374

#define QAM_SL_QUAL_QAM_128_1_Q0__PRE 0x5

9375

9376

#define QAM_SL_QUAL_QAM_128_1_Q1__B 3

9377

#define QAM_SL_QUAL_QAM_128_1_Q1__W 3

9378

#define QAM_SL_QUAL_QAM_128_1_Q1__M 0x38

9379

#define QAM_SL_QUAL_QAM_128_1_Q1__PRE 0x0

9380

9381

#define QAM_SL_QUAL_QAM_128_2__A 0x1430025

9382

#define QAM_SL_QUAL_QAM_128_2__W 9

9383

#define QAM_SL_QUAL_QAM_128_2__M 0x1FF

9384

#define QAM_SL_QUAL_QAM_128_2__PRE 0x1

9385

9386

#define QAM_SL_QUAL_QAM_128_2_Q0__B 0

9387

#define QAM_SL_QUAL_QAM_128_2_Q0__W 3

9388

#define QAM_SL_QUAL_QAM_128_2_Q0__M 0x7

9389

#define QAM_SL_QUAL_QAM_128_2_Q0__PRE 0x1

9390

9391

#define QAM_SL_QUAL_QAM_128_2_Q1__B 3

9392

#define QAM_SL_QUAL_QAM_128_2_Q1__W 3

9393

#define QAM_SL_QUAL_QAM_128_2_Q1__M 0x38

9394

#define QAM_SL_QUAL_QAM_128_2_Q1__PRE 0x0

9395

9396

#define QAM_SL_QUAL_QAM_128_2_Q2__B 6

9397

#define QAM_SL_QUAL_QAM_128_2_Q2__W 3

9398

#define QAM_SL_QUAL_QAM_128_2_Q2__M 0x1C0

9399

#define QAM_SL_QUAL_QAM_128_2_Q2__PRE 0x0

9400

9401

#define QAM_SL_QUAL_QAM_128_3__A 0x1430026

9402

#define QAM_SL_QUAL_QAM_128_3__W 12

9403

#define QAM_SL_QUAL_QAM_128_3__M 0xFFF

9404

#define QAM_SL_QUAL_QAM_128_3__PRE 0x1

9405

9406

#define QAM_SL_QUAL_QAM_128_3_Q0__B 0

9407

#define QAM_SL_QUAL_QAM_128_3_Q0__W 3

9408

#define QAM_SL_QUAL_QAM_128_3_Q0__M 0x7

9409

#define QAM_SL_QUAL_QAM_128_3_Q0__PRE 0x1

9410

9411

#define QAM_SL_QUAL_QAM_128_3_Q1__B 3

9412

#define QAM_SL_QUAL_QAM_128_3_Q1__W 3

9413

#define QAM_SL_QUAL_QAM_128_3_Q1__M 0x38

9414

#define QAM_SL_QUAL_QAM_128_3_Q1__PRE 0x0

9415

9416

#define QAM_SL_QUAL_QAM_128_3_Q2__B 6

9417

#define QAM_SL_QUAL_QAM_128_3_Q2__W 3

9418

#define QAM_SL_QUAL_QAM_128_3_Q2__M 0x1C0

9419

#define QAM_SL_QUAL_QAM_128_3_Q2__PRE 0x0

9420

9421

#define QAM_SL_QUAL_QAM_128_3_Q3__B 9

9422

#define QAM_SL_QUAL_QAM_128_3_Q3__W 3

9423

#define QAM_SL_QUAL_QAM_128_3_Q3__M 0xE00

9424

#define QAM_SL_QUAL_QAM_128_3_Q3__PRE 0x0

9425

9426

#define QAM_SL_QUAL_QAM_128_4__A 0x1430027

9427

#define QAM_SL_QUAL_QAM_128_4__W 15

9428

#define QAM_SL_QUAL_QAM_128_4__M 0x7FFF

9429

#define QAM_SL_QUAL_QAM_128_4__PRE 0x0

9430

9431

#define QAM_SL_QUAL_QAM_128_4_Q0__B 0

9432

#define QAM_SL_QUAL_QAM_128_4_Q0__W 3

9433

#define QAM_SL_QUAL_QAM_128_4_Q0__M 0x7

9434

#define QAM_SL_QUAL_QAM_128_4_Q0__PRE 0x0

9435

9436

#define QAM_SL_QUAL_QAM_128_4_Q1__B 3

9437

#define QAM_SL_QUAL_QAM_128_4_Q1__W 3

9438

#define QAM_SL_QUAL_QAM_128_4_Q1__M 0x38

9439

#define QAM_SL_QUAL_QAM_128_4_Q1__PRE 0x0

9440

9441

#define QAM_SL_QUAL_QAM_128_4_Q2__B 6

9442

#define QAM_SL_QUAL_QAM_128_4_Q2__W 3

9443

#define QAM_SL_QUAL_QAM_128_4_Q2__M 0x1C0

9444

#define QAM_SL_QUAL_QAM_128_4_Q2__PRE 0x0

9445

9446

#define QAM_SL_QUAL_QAM_128_4_Q3__B 9

9447

#define QAM_SL_QUAL_QAM_128_4_Q3__W 3

9448

#define QAM_SL_QUAL_QAM_128_4_Q3__M 0xE00

9449

#define QAM_SL_QUAL_QAM_128_4_Q3__PRE 0x0

9450

9451

#define QAM_SL_QUAL_QAM_128_4_Q4__B 12

9452

#define QAM_SL_QUAL_QAM_128_4_Q4__W 3

9453

#define QAM_SL_QUAL_QAM_128_4_Q4__M 0x7000

9454

#define QAM_SL_QUAL_QAM_128_4_Q4__PRE 0x0

9455

9456

#define QAM_SL_QUAL_QAM_128_5__A 0x1430028

9457

#define QAM_SL_QUAL_QAM_128_5__W 15

9458

#define QAM_SL_QUAL_QAM_128_5__M 0x7FFF

9459

#define QAM_SL_QUAL_QAM_128_5__PRE 0x90

9460

9461

#define QAM_SL_QUAL_QAM_128_5_Q0__B 0

9462

#define QAM_SL_QUAL_QAM_128_5_Q0__W 3

9463

#define QAM_SL_QUAL_QAM_128_5_Q0__M 0x7

9464

#define QAM_SL_QUAL_QAM_128_5_Q0__PRE 0x0

9465

9466

#define QAM_SL_QUAL_QAM_128_5_Q1__B 3

9467

#define QAM_SL_QUAL_QAM_128_5_Q1__W 3

9468

#define QAM_SL_QUAL_QAM_128_5_Q1__M 0x38

9469

#define QAM_SL_QUAL_QAM_128_5_Q1__PRE 0x10

9470

9471

#define QAM_SL_QUAL_QAM_128_5_Q2__B 6

9472

#define QAM_SL_QUAL_QAM_128_5_Q2__W 3

9473

#define QAM_SL_QUAL_QAM_128_5_Q2__M 0x1C0

9474

#define QAM_SL_QUAL_QAM_128_5_Q2__PRE 0x80

9475

9476

#define QAM_SL_QUAL_QAM_128_5_Q3__B 9

9477

#define QAM_SL_QUAL_QAM_128_5_Q3__W 3

9478

#define QAM_SL_QUAL_QAM_128_5_Q3__M 0xE00

9479

#define QAM_SL_QUAL_QAM_128_5_Q3__PRE 0x0

9480

9481

#define QAM_SL_QUAL_QAM_128_5_Q4__B 12

9482

#define QAM_SL_QUAL_QAM_128_5_Q4__W 3

9483

#define QAM_SL_QUAL_QAM_128_5_Q4__M 0x7000

9484

#define QAM_SL_QUAL_QAM_128_5_Q4__PRE 0x0

9485

9486

#define QAM_SL_QUAL_QAM_128_5H__A 0x1430029

9487

#define QAM_SL_QUAL_QAM_128_5H__W 3

9488

#define QAM_SL_QUAL_QAM_128_5H__M 0x7

9489

#define QAM_SL_QUAL_QAM_128_5H__PRE 0x0

9490

9491

#define QAM_SL_QUAL_QAM_128_5H_Q5__B 0

9492

#define QAM_SL_QUAL_QAM_128_5H_Q5__W 3

9493

#define QAM_SL_QUAL_QAM_128_5H_Q5__M 0x7

9494

#define QAM_SL_QUAL_QAM_128_5H_Q5__PRE 0x0

9495

9496

#define QAM_SL_QUAL_QAM_256_0__A 0x143002A

9497

#define QAM_SL_QUAL_QAM_256_0__W 3

9498

#define QAM_SL_QUAL_QAM_256_0__M 0x7

9499

#define QAM_SL_QUAL_QAM_256_0__PRE 0x3

9500

9501

#define QAM_SL_QUAL_QAM_256_0_Q0__B 0

9502

#define QAM_SL_QUAL_QAM_256_0_Q0__W 3

9503

#define QAM_SL_QUAL_QAM_256_0_Q0__M 0x7

9504

#define QAM_SL_QUAL_QAM_256_0_Q0__PRE 0x3

9505

9506

#define QAM_SL_QUAL_QAM_256_1__A 0x143002B

9507

#define QAM_SL_QUAL_QAM_256_1__W 6

9508

#define QAM_SL_QUAL_QAM_256_1__M 0x3F

9509

#define QAM_SL_QUAL_QAM_256_1__PRE 0x1

9510

9511

#define QAM_SL_QUAL_QAM_256_1_Q0__B 0

9512

#define QAM_SL_QUAL_QAM_256_1_Q0__W 3

9513

#define QAM_SL_QUAL_QAM_256_1_Q0__M 0x7

9514

#define QAM_SL_QUAL_QAM_256_1_Q0__PRE 0x1

9515

9516

#define QAM_SL_QUAL_QAM_256_1_Q1__B 3

9517

#define QAM_SL_QUAL_QAM_256_1_Q1__W 3

9518

#define QAM_SL_QUAL_QAM_256_1_Q1__M 0x38

9519

#define QAM_SL_QUAL_QAM_256_1_Q1__PRE 0x0

9520

9521

#define QAM_SL_QUAL_QAM_256_2__A 0x143002C

9522

#define QAM_SL_QUAL_QAM_256_2__W 9

9523

#define QAM_SL_QUAL_QAM_256_2__M 0x1FF

9524

#define QAM_SL_QUAL_QAM_256_2__PRE 0x9

9525

9526

#define QAM_SL_QUAL_QAM_256_2_Q0__B 0

9527

#define QAM_SL_QUAL_QAM_256_2_Q0__W 3

9528

#define QAM_SL_QUAL_QAM_256_2_Q0__M 0x7

9529

#define QAM_SL_QUAL_QAM_256_2_Q0__PRE 0x1

9530

9531

#define QAM_SL_QUAL_QAM_256_2_Q1__B 3

9532

#define QAM_SL_QUAL_QAM_256_2_Q1__W 3

9533

#define QAM_SL_QUAL_QAM_256_2_Q1__M 0x38

9534

#define QAM_SL_QUAL_QAM_256_2_Q1__PRE 0x8

9535

9536

#define QAM_SL_QUAL_QAM_256_2_Q2__B 6

9537

#define QAM_SL_QUAL_QAM_256_2_Q2__W 3

9538

#define QAM_SL_QUAL_QAM_256_2_Q2__M 0x1C0

9539

#define QAM_SL_QUAL_QAM_256_2_Q2__PRE 0x0

9540

9541

#define QAM_SL_QUAL_QAM_256_3__A 0x143002D

9542

#define QAM_SL_QUAL_QAM_256_3__W 12

9543

#define QAM_SL_QUAL_QAM_256_3__M 0xFFF

9544

#define QAM_SL_QUAL_QAM_256_3__PRE 0x13

9545

9546

#define QAM_SL_QUAL_QAM_256_3_Q0__B 0

9547

#define QAM_SL_QUAL_QAM_256_3_Q0__W 3

9548

#define QAM_SL_QUAL_QAM_256_3_Q0__M 0x7

9549

#define QAM_SL_QUAL_QAM_256_3_Q0__PRE 0x3

9550

9551

#define QAM_SL_QUAL_QAM_256_3_Q1__B 3

9552

#define QAM_SL_QUAL_QAM_256_3_Q1__W 3

9553

#define QAM_SL_QUAL_QAM_256_3_Q1__M 0x38

9554

#define QAM_SL_QUAL_QAM_256_3_Q1__PRE 0x10

9555

9556

#define QAM_SL_QUAL_QAM_256_3_Q2__B 6

9557

#define QAM_SL_QUAL_QAM_256_3_Q2__W 3

9558

#define QAM_SL_QUAL_QAM_256_3_Q2__M 0x1C0

9559

#define QAM_SL_QUAL_QAM_256_3_Q2__PRE 0x0

9560

9561

#define QAM_SL_QUAL_QAM_256_3_Q3__B 9

9562

#define QAM_SL_QUAL_QAM_256_3_Q3__W 3

9563

#define QAM_SL_QUAL_QAM_256_3_Q3__M 0xE00

9564

#define QAM_SL_QUAL_QAM_256_3_Q3__PRE 0x0

9565

9566

#define QAM_SL_QUAL_QAM_256_4__A 0x143002E

9567

#define QAM_SL_QUAL_QAM_256_4__W 15

9568

#define QAM_SL_QUAL_QAM_256_4__M 0x7FFF

9569

#define QAM_SL_QUAL_QAM_256_4__PRE 0x49

9570

9571

#define QAM_SL_QUAL_QAM_256_4_Q0__B 0

9572

#define QAM_SL_QUAL_QAM_256_4_Q0__W 3

9573

#define QAM_SL_QUAL_QAM_256_4_Q0__M 0x7

9574

#define QAM_SL_QUAL_QAM_256_4_Q0__PRE 0x1

9575

9576

#define QAM_SL_QUAL_QAM_256_4_Q1__B 3

9577

#define QAM_SL_QUAL_QAM_256_4_Q1__W 3

9578

#define QAM_SL_QUAL_QAM_256_4_Q1__M 0x38

9579

#define QAM_SL_QUAL_QAM_256_4_Q1__PRE 0x8

9580

9581

#define QAM_SL_QUAL_QAM_256_4_Q2__B 6

9582

#define QAM_SL_QUAL_QAM_256_4_Q2__W 3

9583

#define QAM_SL_QUAL_QAM_256_4_Q2__M 0x1C0

9584

#define QAM_SL_QUAL_QAM_256_4_Q2__PRE 0x40

9585

9586

#define QAM_SL_QUAL_QAM_256_4_Q3__B 9

9587

#define QAM_SL_QUAL_QAM_256_4_Q3__W 3

9588

#define QAM_SL_QUAL_QAM_256_4_Q3__M 0xE00

9589

#define QAM_SL_QUAL_QAM_256_4_Q3__PRE 0x0

9590

9591

#define QAM_SL_QUAL_QAM_256_4_Q4__B 12

9592

#define QAM_SL_QUAL_QAM_256_4_Q4__W 3

9593

#define QAM_SL_QUAL_QAM_256_4_Q4__M 0x7000

9594

#define QAM_SL_QUAL_QAM_256_4_Q4__PRE 0x0

9595

9596

#define QAM_SL_QUAL_QAM_256_5__A 0x143002F

9597

#define QAM_SL_QUAL_QAM_256_5__W 15

9598

#define QAM_SL_QUAL_QAM_256_5__M 0x7FFF

9599

#define QAM_SL_QUAL_QAM_256_5__PRE 0x59

9600

9601

#define QAM_SL_QUAL_QAM_256_5_Q0__B 0

9602

#define QAM_SL_QUAL_QAM_256_5_Q0__W 3

9603

#define QAM_SL_QUAL_QAM_256_5_Q0__M 0x7

9604

#define QAM_SL_QUAL_QAM_256_5_Q0__PRE 0x1

9605

9606

#define QAM_SL_QUAL_QAM_256_5_Q1__B 3

9607

#define QAM_SL_QUAL_QAM_256_5_Q1__W 3

9608

#define QAM_SL_QUAL_QAM_256_5_Q1__M 0x38

9609

#define QAM_SL_QUAL_QAM_256_5_Q1__PRE 0x18

9610

9611

#define QAM_SL_QUAL_QAM_256_5_Q2__B 6

9612

#define QAM_SL_QUAL_QAM_256_5_Q2__W 3

9613

#define QAM_SL_QUAL_QAM_256_5_Q2__M 0x1C0

9614

#define QAM_SL_QUAL_QAM_256_5_Q2__PRE 0x40

9615

9616

#define QAM_SL_QUAL_QAM_256_5_Q3__B 9

9617

#define QAM_SL_QUAL_QAM_256_5_Q3__W 3

9618

#define QAM_SL_QUAL_QAM_256_5_Q3__M 0xE00

9619

#define QAM_SL_QUAL_QAM_256_5_Q3__PRE 0x0

9620

9621

#define QAM_SL_QUAL_QAM_256_5_Q4__B 12

9622

#define QAM_SL_QUAL_QAM_256_5_Q4__W 3

9623

#define QAM_SL_QUAL_QAM_256_5_Q4__M 0x7000

9624

#define QAM_SL_QUAL_QAM_256_5_Q4__PRE 0x0

9625

9626

#define QAM_SL_QUAL_QAM_256_5H__A 0x1430030

9627

#define QAM_SL_QUAL_QAM_256_5H__W 3

9628

#define QAM_SL_QUAL_QAM_256_5H__M 0x7

9629

#define QAM_SL_QUAL_QAM_256_5H__PRE 0x0

9630

9631

#define QAM_SL_QUAL_QAM_256_5H_Q5__B 0

9632

#define QAM_SL_QUAL_QAM_256_5H_Q5__W 3

9633

#define QAM_SL_QUAL_QAM_256_5H_Q5__M 0x7

9634

#define QAM_SL_QUAL_QAM_256_5H_Q5__PRE 0x0

9635

9636

#define QAM_SL_QUAL_QAM_256_6__A 0x1430031

9637

#define QAM_SL_QUAL_QAM_256_6__W 15

9638

#define QAM_SL_QUAL_QAM_256_6__M 0x7FFF

9639

#define QAM_SL_QUAL_QAM_256_6__PRE 0x21A

9640

9641

#define QAM_SL_QUAL_QAM_256_6_Q0__B 0

9642

#define QAM_SL_QUAL_QAM_256_6_Q0__W 3

9643

#define QAM_SL_QUAL_QAM_256_6_Q0__M 0x7

9644

#define QAM_SL_QUAL_QAM_256_6_Q0__PRE 0x2

9645

9646

#define QAM_SL_QUAL_QAM_256_6_Q1__B 3

9647

#define QAM_SL_QUAL_QAM_256_6_Q1__W 3

9648

#define QAM_SL_QUAL_QAM_256_6_Q1__M 0x38

9649

#define QAM_SL_QUAL_QAM_256_6_Q1__PRE 0x18

9650

9651

#define QAM_SL_QUAL_QAM_256_6_Q2__B 6

9652

#define QAM_SL_QUAL_QAM_256_6_Q2__W 3

9653

#define QAM_SL_QUAL_QAM_256_6_Q2__M 0x1C0

9654

#define QAM_SL_QUAL_QAM_256_6_Q2__PRE 0x0

9655

9656

#define QAM_SL_QUAL_QAM_256_6_Q3__B 9

9657

#define QAM_SL_QUAL_QAM_256_6_Q3__W 3

9658

#define QAM_SL_QUAL_QAM_256_6_Q3__M 0xE00

9659

#define QAM_SL_QUAL_QAM_256_6_Q3__PRE 0x200

9660

9661

#define QAM_SL_QUAL_QAM_256_6_Q4__B 12

9662

#define QAM_SL_QUAL_QAM_256_6_Q4__W 3

9663

#define QAM_SL_QUAL_QAM_256_6_Q4__M 0x7000

9664

#define QAM_SL_QUAL_QAM_256_6_Q4__PRE 0x0

9665

9666

#define QAM_SL_QUAL_QAM_256_6H__A 0x1430032

9667

#define QAM_SL_QUAL_QAM_256_6H__W 6

9668

#define QAM_SL_QUAL_QAM_256_6H__M 0x3F

9669

#define QAM_SL_QUAL_QAM_256_6H__PRE 0x0

9670

9671

#define QAM_SL_QUAL_QAM_256_6H_Q5__B 0

9672

#define QAM_SL_QUAL_QAM_256_6H_Q5__W 3

9673

#define QAM_SL_QUAL_QAM_256_6H_Q5__M 0x7

9674

#define QAM_SL_QUAL_QAM_256_6H_Q5__PRE 0x0

9675

9676

#define QAM_SL_QUAL_QAM_256_6H_Q6__B 3

9677

#define QAM_SL_QUAL_QAM_256_6H_Q6__W 3

9678

#define QAM_SL_QUAL_QAM_256_6H_Q6__M 0x38

9679

#define QAM_SL_QUAL_QAM_256_6H_Q6__PRE 0x0

9680

9681

#define QAM_SL_QUAL_QAM_256_7__A 0x1430033

9682

#define QAM_SL_QUAL_QAM_256_7__W 15

9683

#define QAM_SL_QUAL_QAM_256_7__M 0x7FFF

9684

#define QAM_SL_QUAL_QAM_256_7__PRE 0x29D

9685

9686

#define QAM_SL_QUAL_QAM_256_7_Q0__B 0

9687

#define QAM_SL_QUAL_QAM_256_7_Q0__W 3

9688

#define QAM_SL_QUAL_QAM_256_7_Q0__M 0x7

9689

#define QAM_SL_QUAL_QAM_256_7_Q0__PRE 0x5

9690

9691

#define QAM_SL_QUAL_QAM_256_7_Q1__B 3

9692

#define QAM_SL_QUAL_QAM_256_7_Q1__W 3

9693

#define QAM_SL_QUAL_QAM_256_7_Q1__M 0x38

9694

#define QAM_SL_QUAL_QAM_256_7_Q1__PRE 0x18

9695

9696

#define QAM_SL_QUAL_QAM_256_7_Q2__B 6

9697

#define QAM_SL_QUAL_QAM_256_7_Q2__W 3

9698

#define QAM_SL_QUAL_QAM_256_7_Q2__M 0x1C0

9699

#define QAM_SL_QUAL_QAM_256_7_Q2__PRE 0x80

9700

9701

#define QAM_SL_QUAL_QAM_256_7_Q3__B 9

9702

#define QAM_SL_QUAL_QAM_256_7_Q3__W 3

9703

#define QAM_SL_QUAL_QAM_256_7_Q3__M 0xE00

9704

#define QAM_SL_QUAL_QAM_256_7_Q3__PRE 0x200

9705

9706

#define QAM_SL_QUAL_QAM_256_7_Q4__B 12

9707

#define QAM_SL_QUAL_QAM_256_7_Q4__W 3

9708

#define QAM_SL_QUAL_QAM_256_7_Q4__M 0x7000

9709

#define QAM_SL_QUAL_QAM_256_7_Q4__PRE 0x0

9710

9711

#define QAM_SL_QUAL_QAM_256_7H__A 0x1430034

9712

#define QAM_SL_QUAL_QAM_256_7H__W 9

9713

#define QAM_SL_QUAL_QAM_256_7H__M 0x1FF

9714

#define QAM_SL_QUAL_QAM_256_7H__PRE 0x0

9715

9716

#define QAM_SL_QUAL_QAM_256_7H_Q5__B 0

9717

#define QAM_SL_QUAL_QAM_256_7H_Q5__W 3

9718

#define QAM_SL_QUAL_QAM_256_7H_Q5__M 0x7

9719

#define QAM_SL_QUAL_QAM_256_7H_Q5__PRE 0x0

9720

9721

#define QAM_SL_QUAL_QAM_256_7H_Q6__B 3

9722

#define QAM_SL_QUAL_QAM_256_7H_Q6__W 3

9723

#define QAM_SL_QUAL_QAM_256_7H_Q6__M 0x38

9724

#define QAM_SL_QUAL_QAM_256_7H_Q6__PRE 0x0

9725

9726

#define QAM_SL_QUAL_QAM_256_7H_Q7__B 6

9727

#define QAM_SL_QUAL_QAM_256_7H_Q7__W 3

9728

#define QAM_SL_QUAL_QAM_256_7H_Q7__M 0x1C0

9729

#define QAM_SL_QUAL_QAM_256_7H_Q7__PRE 0x0

#define QAM_DQ_COMM_EXEC__A 0x1440000

9734

#define QAM_DQ_COMM_EXEC__W 2

9735

#define QAM_DQ_COMM_EXEC__M 0x3

9736

#define QAM_DQ_COMM_EXEC__PRE 0x0

9737

#define QAM_DQ_COMM_EXEC_STOP 0x0

9738

#define QAM_DQ_COMM_EXEC_ACTIVE 0x1

9739

#define QAM_DQ_COMM_EXEC_HOLD 0x2

9740

9741

#define QAM_DQ_MODE__A 0x1440010

9742

#define QAM_DQ_MODE__W 5

9743

#define QAM_DQ_MODE__M 0x1F

9744

#define QAM_DQ_MODE__PRE 0x0

9745

9746

#define QAM_DQ_MODE_TAPRESET__B 0

9747

#define QAM_DQ_MODE_TAPRESET__W 1

9748

#define QAM_DQ_MODE_TAPRESET__M 0x1

9749

#define QAM_DQ_MODE_TAPRESET__PRE 0x0

9750

#define QAM_DQ_MODE_TAPRESET_RST 0x1

9751

9752

#define QAM_DQ_MODE_TAPLMS__B 1

9753

#define QAM_DQ_MODE_TAPLMS__W 1

9754

#define QAM_DQ_MODE_TAPLMS__M 0x2

9755

#define QAM_DQ_MODE_TAPLMS__PRE 0x0

9756

#define QAM_DQ_MODE_TAPLMS_UPD 0x2

9757

9758

#define QAM_DQ_MODE_TAPDRAIN__B 2

9759

#define QAM_DQ_MODE_TAPDRAIN__W 1

9760

#define QAM_DQ_MODE_TAPDRAIN__M 0x4

9761

#define QAM_DQ_MODE_TAPDRAIN__PRE 0x0

9762

#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x4

9763

9764

#define QAM_DQ_MODE_FB__B 3

9765

#define QAM_DQ_MODE_FB__W 2

9766

#define QAM_DQ_MODE_FB__M 0x18

9767

#define QAM_DQ_MODE_FB__PRE 0x0

9768

#define QAM_DQ_MODE_FB_CMA 0x0

9769

#define QAM_DQ_MODE_FB_RADIUS 0x8

9770

#define QAM_DQ_MODE_FB_DFB 0x10

9771

#define QAM_DQ_MODE_FB_TRELLIS 0x18

9772

9773

9774

#define QAM_DQ_MU_FACTOR__A 0x1440011

9775

#define QAM_DQ_MU_FACTOR__W 3

9776

#define QAM_DQ_MU_FACTOR__M 0x7

9777

#define QAM_DQ_MU_FACTOR__PRE 0x0

9778

9779

#define QAM_DQ_LA_FACTOR__A 0x1440012

9780

#define QAM_DQ_LA_FACTOR__W 4

9781

#define QAM_DQ_LA_FACTOR__M 0xF

9782

#define QAM_DQ_LA_FACTOR__PRE 0xC

9783

9784

#define QAM_DQ_CMA_RATIO__A 0x1440013

9785

#define QAM_DQ_CMA_RATIO__W 14

9786

#define QAM_DQ_CMA_RATIO__M 0x3FFF

9787

#define QAM_DQ_CMA_RATIO__PRE 0x3CF9

9788

#define QAM_DQ_CMA_RATIO_QPSK 0x2000

9789

#define QAM_DQ_CMA_RATIO_QAM16 0x34CD

9790

#define QAM_DQ_CMA_RATIO_QAM64 0x3A00

9791

#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D

9792

#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA0

9793

9794

#define QAM_DQ_QUAL_RADSEL__A 0x1440014

9795

#define QAM_DQ_QUAL_RADSEL__W 3

9796

#define QAM_DQ_QUAL_RADSEL__M 0x7

9797

#define QAM_DQ_QUAL_RADSEL__PRE 0x0

9798

9799

#define QAM_DQ_QUAL_RADSEL_BIT__B 0

9800

#define QAM_DQ_QUAL_RADSEL_BIT__W 3

9801

#define QAM_DQ_QUAL_RADSEL_BIT__M 0x7

9802

#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x0

9803

#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x0

9804

#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x6

9805

9806

#define QAM_DQ_QUAL_ENA__A 0x1440015

9807

#define QAM_DQ_QUAL_ENA__W 1

9808

#define QAM_DQ_QUAL_ENA__M 0x1

9809

#define QAM_DQ_QUAL_ENA__PRE 0x0

9810

9811

#define QAM_DQ_QUAL_ENA_ENA__B 0

9812

#define QAM_DQ_QUAL_ENA_ENA__W 1

9813

#define QAM_DQ_QUAL_ENA_ENA__M 0x1

9814

#define QAM_DQ_QUAL_ENA_ENA__PRE 0x0

9815

#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x1

9816

9817

#define QAM_DQ_QUAL_FUN0__A 0x1440018

9818

#define QAM_DQ_QUAL_FUN0__W 6

9819

#define QAM_DQ_QUAL_FUN0__M 0x3F

9820

#define QAM_DQ_QUAL_FUN0__PRE 0x4

9821

9822

#define QAM_DQ_QUAL_FUN0_BIT__B 0

9823

#define QAM_DQ_QUAL_FUN0_BIT__W 6

9824

#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F

9825

#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x4

9826

9827

#define QAM_DQ_QUAL_FUN1__A 0x1440019

9828

#define QAM_DQ_QUAL_FUN1__W 6

9829

#define QAM_DQ_QUAL_FUN1__M 0x3F

9830

#define QAM_DQ_QUAL_FUN1__PRE 0x4

9831

9832

#define QAM_DQ_QUAL_FUN1_BIT__B 0

9833

#define QAM_DQ_QUAL_FUN1_BIT__W 6

9834

#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F

9835

#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x4

9836

9837

#define QAM_DQ_QUAL_FUN2__A 0x144001A

9838

#define QAM_DQ_QUAL_FUN2__W 6

9839

#define QAM_DQ_QUAL_FUN2__M 0x3F

9840

#define QAM_DQ_QUAL_FUN2__PRE 0x4

9841

9842

#define QAM_DQ_QUAL_FUN2_BIT__B 0

9843

#define QAM_DQ_QUAL_FUN2_BIT__W 6

9844

#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F

9845

#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x4

9846

9847

#define QAM_DQ_QUAL_FUN3__A 0x144001B

9848

#define QAM_DQ_QUAL_FUN3__W 6

9849

#define QAM_DQ_QUAL_FUN3__M 0x3F

9850

#define QAM_DQ_QUAL_FUN3__PRE 0x4

9851

9852

#define QAM_DQ_QUAL_FUN3_BIT__B 0

9853

#define QAM_DQ_QUAL_FUN3_BIT__W 6

9854

#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F

9855

#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x4

9856

9857

#define QAM_DQ_QUAL_FUN4__A 0x144001C

9858

#define QAM_DQ_QUAL_FUN4__W 6

9859

#define QAM_DQ_QUAL_FUN4__M 0x3F

9860

#define QAM_DQ_QUAL_FUN4__PRE 0x6

9861

9862

#define QAM_DQ_QUAL_FUN4_BIT__B 0

9863

#define QAM_DQ_QUAL_FUN4_BIT__W 6

9864

#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F

9865

#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x6

9866

9867

#define QAM_DQ_QUAL_FUN5__A 0x144001D

9868

#define QAM_DQ_QUAL_FUN5__W 6

9869

#define QAM_DQ_QUAL_FUN5__M 0x3F

9870

#define QAM_DQ_QUAL_FUN5__PRE 0x6

9871

9872

#define QAM_DQ_QUAL_FUN5_BIT__B 0

9873

#define QAM_DQ_QUAL_FUN5_BIT__W 6

9874

#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F

9875

#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x6

9876

9877

#define QAM_DQ_RAW_LIM__A 0x144001E

9878

#define QAM_DQ_RAW_LIM__W 5

9879

#define QAM_DQ_RAW_LIM__M 0x1F

9880

#define QAM_DQ_RAW_LIM__PRE 0x1F

9881

9882

#define QAM_DQ_RAW_LIM_BIT__B 0

9883

#define QAM_DQ_RAW_LIM_BIT__W 5

9884

#define QAM_DQ_RAW_LIM_BIT__M 0x1F

9885

#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F

9886

9887

#define QAM_DQ_TAP_RE_EL0__A 0x1440020

9888

#define QAM_DQ_TAP_RE_EL0__W 12

9889

#define QAM_DQ_TAP_RE_EL0__M 0xFFF

9890

#define QAM_DQ_TAP_RE_EL0__PRE 0x2

9891

9892

#define QAM_DQ_TAP_RE_EL0_TAP__B 0

9893

#define QAM_DQ_TAP_RE_EL0_TAP__W 12

9894

#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF

9895

#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x2

9896

9897

#define QAM_DQ_TAP_IM_EL0__A 0x1440021

9898

#define QAM_DQ_TAP_IM_EL0__W 12

9899

#define QAM_DQ_TAP_IM_EL0__M 0xFFF

9900

#define QAM_DQ_TAP_IM_EL0__PRE 0x2

9901

9902

#define QAM_DQ_TAP_IM_EL0_TAP__B 0

9903

#define QAM_DQ_TAP_IM_EL0_TAP__W 12

9904

#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF

9905

#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x2

9906

9907

#define QAM_DQ_TAP_RE_EL1__A 0x1440022

9908

#define QAM_DQ_TAP_RE_EL1__W 12

9909

#define QAM_DQ_TAP_RE_EL1__M 0xFFF

9910

#define QAM_DQ_TAP_RE_EL1__PRE 0x2

9911

9912

#define QAM_DQ_TAP_RE_EL1_TAP__B 0

9913

#define QAM_DQ_TAP_RE_EL1_TAP__W 12

9914

#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF

9915

#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x2

9916

9917

#define QAM_DQ_TAP_IM_EL1__A 0x1440023

9918

#define QAM_DQ_TAP_IM_EL1__W 12

9919

#define QAM_DQ_TAP_IM_EL1__M 0xFFF

9920

#define QAM_DQ_TAP_IM_EL1__PRE 0x2

9921

9922

#define QAM_DQ_TAP_IM_EL1_TAP__B 0

9923

#define QAM_DQ_TAP_IM_EL1_TAP__W 12

9924

#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF

9925

#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x2

9926

9927

#define QAM_DQ_TAP_RE_EL2__A 0x1440024

9928

#define QAM_DQ_TAP_RE_EL2__W 12

9929

#define QAM_DQ_TAP_RE_EL2__M 0xFFF

9930

#define QAM_DQ_TAP_RE_EL2__PRE 0x2

9931

9932

#define QAM_DQ_TAP_RE_EL2_TAP__B 0

9933

#define QAM_DQ_TAP_RE_EL2_TAP__W 12

9934

#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF

9935

#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x2

9936

9937

#define QAM_DQ_TAP_IM_EL2__A 0x1440025

9938

#define QAM_DQ_TAP_IM_EL2__W 12

9939

#define QAM_DQ_TAP_IM_EL2__M 0xFFF

9940

#define QAM_DQ_TAP_IM_EL2__PRE 0x2

9941

9942

#define QAM_DQ_TAP_IM_EL2_TAP__B 0

9943

#define QAM_DQ_TAP_IM_EL2_TAP__W 12

9944

#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF

9945

#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x2

9946

9947

#define QAM_DQ_TAP_RE_EL3__A 0x1440026

9948

#define QAM_DQ_TAP_RE_EL3__W 12

9949

#define QAM_DQ_TAP_RE_EL3__M 0xFFF

9950

#define QAM_DQ_TAP_RE_EL3__PRE 0x2

9951

9952

#define QAM_DQ_TAP_RE_EL3_TAP__B 0

9953

#define QAM_DQ_TAP_RE_EL3_TAP__W 12

9954

#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF

9955

#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x2

9956

9957

#define QAM_DQ_TAP_IM_EL3__A 0x1440027

9958

#define QAM_DQ_TAP_IM_EL3__W 12

9959

#define QAM_DQ_TAP_IM_EL3__M 0xFFF

9960

#define QAM_DQ_TAP_IM_EL3__PRE 0x2

9961

9962

#define QAM_DQ_TAP_IM_EL3_TAP__B 0

9963

#define QAM_DQ_TAP_IM_EL3_TAP__W 12

9964

#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF

9965

#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x2

9966

9967

#define QAM_DQ_TAP_RE_EL4__A 0x1440028

9968

#define QAM_DQ_TAP_RE_EL4__W 12

9969

#define QAM_DQ_TAP_RE_EL4__M 0xFFF

9970

#define QAM_DQ_TAP_RE_EL4__PRE 0x2

9971

9972

#define QAM_DQ_TAP_RE_EL4_TAP__B 0

9973

#define QAM_DQ_TAP_RE_EL4_TAP__W 12

9974

#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF

9975

#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x2

9976

9977

#define QAM_DQ_TAP_IM_EL4__A 0x1440029

9978

#define QAM_DQ_TAP_IM_EL4__W 12

9979

#define QAM_DQ_TAP_IM_EL4__M 0xFFF

9980

#define QAM_DQ_TAP_IM_EL4__PRE 0x2

9981

9982

#define QAM_DQ_TAP_IM_EL4_TAP__B 0

9983

#define QAM_DQ_TAP_IM_EL4_TAP__W 12

9984

#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF

9985

#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x2

9986

9987

#define QAM_DQ_TAP_RE_EL5__A 0x144002A

9988

#define QAM_DQ_TAP_RE_EL5__W 12

9989

#define QAM_DQ_TAP_RE_EL5__M 0xFFF

9990

#define QAM_DQ_TAP_RE_EL5__PRE 0x2

9991

9992

#define QAM_DQ_TAP_RE_EL5_TAP__B 0

9993

#define QAM_DQ_TAP_RE_EL5_TAP__W 12

9994

#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF

9995

#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x2

9996

9997

#define QAM_DQ_TAP_IM_EL5__A 0x144002B

9998

#define QAM_DQ_TAP_IM_EL5__W 12

9999

#define QAM_DQ_TAP_IM_EL5__M 0xFFF

10000

#define QAM_DQ_TAP_IM_EL5__PRE 0x2

10001

10002

#define QAM_DQ_TAP_IM_EL5_TAP__B 0

10003

#define QAM_DQ_TAP_IM_EL5_TAP__W 12

10004

#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF

10005

#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x2

10006

10007

#define QAM_DQ_TAP_RE_EL6__A 0x144002C

10008

#define QAM_DQ_TAP_RE_EL6__W 12

10009

#define QAM_DQ_TAP_RE_EL6__M 0xFFF

10010

#define QAM_DQ_TAP_RE_EL6__PRE 0x2

10011

10012

#define QAM_DQ_TAP_RE_EL6_TAP__B 0

10013

#define QAM_DQ_TAP_RE_EL6_TAP__W 12

10014

#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF

10015

#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x2

10016

10017

#define QAM_DQ_TAP_IM_EL6__A 0x144002D

10018

#define QAM_DQ_TAP_IM_EL6__W 12

10019

#define QAM_DQ_TAP_IM_EL6__M 0xFFF

10020

#define QAM_DQ_TAP_IM_EL6__PRE 0x2

10021

10022

#define QAM_DQ_TAP_IM_EL6_TAP__B 0

10023

#define QAM_DQ_TAP_IM_EL6_TAP__W 12

10024

#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF

10025

#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x2

10026

10027

#define QAM_DQ_TAP_RE_EL7__A 0x144002E

10028

#define QAM_DQ_TAP_RE_EL7__W 12

10029

#define QAM_DQ_TAP_RE_EL7__M 0xFFF

10030

#define QAM_DQ_TAP_RE_EL7__PRE 0x2

10031

10032

#define QAM_DQ_TAP_RE_EL7_TAP__B 0

10033

#define QAM_DQ_TAP_RE_EL7_TAP__W 12

10034

#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF

10035

#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x2

10036

10037

#define QAM_DQ_TAP_IM_EL7__A 0x144002F

10038

#define QAM_DQ_TAP_IM_EL7__W 12

10039

#define QAM_DQ_TAP_IM_EL7__M 0xFFF

10040

#define QAM_DQ_TAP_IM_EL7__PRE 0x2

10041

10042

#define QAM_DQ_TAP_IM_EL7_TAP__B 0

10043

#define QAM_DQ_TAP_IM_EL7_TAP__W 12

10044

#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF

10045

#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x2

10046

10047

#define QAM_DQ_TAP_RE_EL8__A 0x1440030

10048

#define QAM_DQ_TAP_RE_EL8__W 12

10049

#define QAM_DQ_TAP_RE_EL8__M 0xFFF

10050

#define QAM_DQ_TAP_RE_EL8__PRE 0x2

10051

10052

#define QAM_DQ_TAP_RE_EL8_TAP__B 0

10053

#define QAM_DQ_TAP_RE_EL8_TAP__W 12

10054

#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF

10055

#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x2

10056

10057

#define QAM_DQ_TAP_IM_EL8__A 0x1440031

10058

#define QAM_DQ_TAP_IM_EL8__W 12

10059

#define QAM_DQ_TAP_IM_EL8__M 0xFFF

10060

#define QAM_DQ_TAP_IM_EL8__PRE 0x2

10061

10062

#define QAM_DQ_TAP_IM_EL8_TAP__B 0

10063

#define QAM_DQ_TAP_IM_EL8_TAP__W 12

10064

#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF

10065

#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x2

10066

10067

#define QAM_DQ_TAP_RE_EL9__A 0x1440032

10068

#define QAM_DQ_TAP_RE_EL9__W 12

10069

#define QAM_DQ_TAP_RE_EL9__M 0xFFF

10070

#define QAM_DQ_TAP_RE_EL9__PRE 0x2

10071

10072

#define QAM_DQ_TAP_RE_EL9_TAP__B 0

10073

#define QAM_DQ_TAP_RE_EL9_TAP__W 12

10074

#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF

10075

#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x2

10076

10077

#define QAM_DQ_TAP_IM_EL9__A 0x1440033

10078

#define QAM_DQ_TAP_IM_EL9__W 12

10079

#define QAM_DQ_TAP_IM_EL9__M 0xFFF

10080

#define QAM_DQ_TAP_IM_EL9__PRE 0x2

10081

10082

#define QAM_DQ_TAP_IM_EL9_TAP__B 0

10083

#define QAM_DQ_TAP_IM_EL9_TAP__W 12

10084

#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF

10085

#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x2

10086

10087

#define QAM_DQ_TAP_RE_EL10__A 0x1440034

10088

#define QAM_DQ_TAP_RE_EL10__W 12

10089

#define QAM_DQ_TAP_RE_EL10__M 0xFFF

10090

#define QAM_DQ_TAP_RE_EL10__PRE 0x2

10091

10092

#define QAM_DQ_TAP_RE_EL10_TAP__B 0

10093

#define QAM_DQ_TAP_RE_EL10_TAP__W 12

10094

#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF

10095

#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x2

10096

10097

#define QAM_DQ_TAP_IM_EL10__A 0x1440035

10098

#define QAM_DQ_TAP_IM_EL10__W 12

10099

#define QAM_DQ_TAP_IM_EL10__M 0xFFF

10100

#define QAM_DQ_TAP_IM_EL10__PRE 0x2

10101

10102

#define QAM_DQ_TAP_IM_EL10_TAP__B 0

10103

#define QAM_DQ_TAP_IM_EL10_TAP__W 12

10104

#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF

10105

#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x2

10106

10107

#define QAM_DQ_TAP_RE_EL11__A 0x1440036

10108

#define QAM_DQ_TAP_RE_EL11__W 12

10109

#define QAM_DQ_TAP_RE_EL11__M 0xFFF

10110

#define QAM_DQ_TAP_RE_EL11__PRE 0x2

10111

10112

#define QAM_DQ_TAP_RE_EL11_TAP__B 0

10113

#define QAM_DQ_TAP_RE_EL11_TAP__W 12

10114

#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF

10115

#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x2

10116

10117

#define QAM_DQ_TAP_IM_EL11__A 0x1440037

10118

#define QAM_DQ_TAP_IM_EL11__W 12

10119

#define QAM_DQ_TAP_IM_EL11__M 0xFFF

10120

#define QAM_DQ_TAP_IM_EL11__PRE 0x2

10121

10122

#define QAM_DQ_TAP_IM_EL11_TAP__B 0

10123

#define QAM_DQ_TAP_IM_EL11_TAP__W 12

10124

#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF

10125

#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x2

10126

10127

#define QAM_DQ_TAP_RE_EL12__A 0x1440038

10128

#define QAM_DQ_TAP_RE_EL12__W 12

10129

#define QAM_DQ_TAP_RE_EL12__M 0xFFF

10130

#define QAM_DQ_TAP_RE_EL12__PRE 0x2

10131

10132

#define QAM_DQ_TAP_RE_EL12_TAP__B 0

10133

#define QAM_DQ_TAP_RE_EL12_TAP__W 12

10134

#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF

10135

#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x2

10136

10137

#define QAM_DQ_TAP_IM_EL12__A 0x1440039

10138

#define QAM_DQ_TAP_IM_EL12__W 12

10139

#define QAM_DQ_TAP_IM_EL12__M 0xFFF

10140

#define QAM_DQ_TAP_IM_EL12__PRE 0x2

10141

10142

#define QAM_DQ_TAP_IM_EL12_TAP__B 0

10143

#define QAM_DQ_TAP_IM_EL12_TAP__W 12

10144

#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF

10145

#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x2

10146

10147

#define QAM_DQ_TAP_RE_EL13__A 0x144003A

10148

#define QAM_DQ_TAP_RE_EL13__W 12

10149

#define QAM_DQ_TAP_RE_EL13__M 0xFFF

10150

#define QAM_DQ_TAP_RE_EL13__PRE 0x2

10151

10152

#define QAM_DQ_TAP_RE_EL13_TAP__B 0

10153

#define QAM_DQ_TAP_RE_EL13_TAP__W 12

10154

#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF

10155

#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x2

10156

10157

#define QAM_DQ_TAP_IM_EL13__A 0x144003B

10158

#define QAM_DQ_TAP_IM_EL13__W 12

10159

#define QAM_DQ_TAP_IM_EL13__M 0xFFF

10160

#define QAM_DQ_TAP_IM_EL13__PRE 0x2

10161

10162

#define QAM_DQ_TAP_IM_EL13_TAP__B 0

10163

#define QAM_DQ_TAP_IM_EL13_TAP__W 12

10164

#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF

10165

#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x2

10166

10167

#define QAM_DQ_TAP_RE_EL14__A 0x144003C

10168

#define QAM_DQ_TAP_RE_EL14__W 12

10169

#define QAM_DQ_TAP_RE_EL14__M 0xFFF

10170

#define QAM_DQ_TAP_RE_EL14__PRE 0x2

10171

10172

#define QAM_DQ_TAP_RE_EL14_TAP__B 0

10173

#define QAM_DQ_TAP_RE_EL14_TAP__W 12

10174

#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF

10175

#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x2

10176

10177

#define QAM_DQ_TAP_IM_EL14__A 0x144003D

10178

#define QAM_DQ_TAP_IM_EL14__W 12

10179

#define QAM_DQ_TAP_IM_EL14__M 0xFFF

10180

#define QAM_DQ_TAP_IM_EL14__PRE 0x2

10181

10182

#define QAM_DQ_TAP_IM_EL14_TAP__B 0

10183

#define QAM_DQ_TAP_IM_EL14_TAP__W 12

10184

#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF

10185

#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x2

10186

10187

#define QAM_DQ_TAP_RE_EL15__A 0x144003E

10188

#define QAM_DQ_TAP_RE_EL15__W 12

10189

#define QAM_DQ_TAP_RE_EL15__M 0xFFF

10190

#define QAM_DQ_TAP_RE_EL15__PRE 0x2

10191

10192

#define QAM_DQ_TAP_RE_EL15_TAP__B 0

10193

#define QAM_DQ_TAP_RE_EL15_TAP__W 12

10194

#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF

10195

#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x2

10196

10197

#define QAM_DQ_TAP_IM_EL15__A 0x144003F

10198

#define QAM_DQ_TAP_IM_EL15__W 12

10199

#define QAM_DQ_TAP_IM_EL15__M 0xFFF

10200

#define QAM_DQ_TAP_IM_EL15__PRE 0x2

10201

10202

#define QAM_DQ_TAP_IM_EL15_TAP__B 0

10203

#define QAM_DQ_TAP_IM_EL15_TAP__W 12

10204

#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF

10205

#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x2

10206

10207

#define QAM_DQ_TAP_RE_EL16__A 0x1440040

10208

#define QAM_DQ_TAP_RE_EL16__W 12

10209

#define QAM_DQ_TAP_RE_EL16__M 0xFFF

10210

#define QAM_DQ_TAP_RE_EL16__PRE 0x2

10211

10212

#define QAM_DQ_TAP_RE_EL16_TAP__B 0

10213

#define QAM_DQ_TAP_RE_EL16_TAP__W 12

10214

#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF

10215

#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x2

10216

10217

#define QAM_DQ_TAP_IM_EL16__A 0x1440041

10218

#define QAM_DQ_TAP_IM_EL16__W 12

10219

#define QAM_DQ_TAP_IM_EL16__M 0xFFF

10220

#define QAM_DQ_TAP_IM_EL16__PRE 0x2

10221

10222

#define QAM_DQ_TAP_IM_EL16_TAP__B 0

10223

#define QAM_DQ_TAP_IM_EL16_TAP__W 12

10224

#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF

10225

#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x2

10226

10227

#define QAM_DQ_TAP_RE_EL17__A 0x1440042

10228

#define QAM_DQ_TAP_RE_EL17__W 12

10229

#define QAM_DQ_TAP_RE_EL17__M 0xFFF

10230

#define QAM_DQ_TAP_RE_EL17__PRE 0x2

10231

10232

#define QAM_DQ_TAP_RE_EL17_TAP__B 0

10233

#define QAM_DQ_TAP_RE_EL17_TAP__W 12

10234

#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF

10235

#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x2

10236

10237

#define QAM_DQ_TAP_IM_EL17__A 0x1440043

10238

#define QAM_DQ_TAP_IM_EL17__W 12

10239

#define QAM_DQ_TAP_IM_EL17__M 0xFFF

10240

#define QAM_DQ_TAP_IM_EL17__PRE 0x2

10241

10242

#define QAM_DQ_TAP_IM_EL17_TAP__B 0

10243

#define QAM_DQ_TAP_IM_EL17_TAP__W 12

10244

#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF

10245

#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x2

10246

10247

#define QAM_DQ_TAP_RE_EL18__A 0x1440044

10248

#define QAM_DQ_TAP_RE_EL18__W 12

10249

#define QAM_DQ_TAP_RE_EL18__M 0xFFF

10250

#define QAM_DQ_TAP_RE_EL18__PRE 0x2

10251

10252

#define QAM_DQ_TAP_RE_EL18_TAP__B 0

10253

#define QAM_DQ_TAP_RE_EL18_TAP__W 12

10254

#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF

10255

#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x2

10256

10257

#define QAM_DQ_TAP_IM_EL18__A 0x1440045

10258

#define QAM_DQ_TAP_IM_EL18__W 12

10259

#define QAM_DQ_TAP_IM_EL18__M 0xFFF

10260

#define QAM_DQ_TAP_IM_EL18__PRE 0x2

10261

10262

#define QAM_DQ_TAP_IM_EL18_TAP__B 0

10263

#define QAM_DQ_TAP_IM_EL18_TAP__W 12

10264

#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF

10265

#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x2

10266

10267

#define QAM_DQ_TAP_RE_EL19__A 0x1440046

10268

#define QAM_DQ_TAP_RE_EL19__W 12

10269

#define QAM_DQ_TAP_RE_EL19__M 0xFFF

10270

#define QAM_DQ_TAP_RE_EL19__PRE 0x2

10271

10272

#define QAM_DQ_TAP_RE_EL19_TAP__B 0

10273

#define QAM_DQ_TAP_RE_EL19_TAP__W 12

10274

#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF

10275

#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x2

10276

10277

#define QAM_DQ_TAP_IM_EL19__A 0x1440047

10278

#define QAM_DQ_TAP_IM_EL19__W 12

10279

#define QAM_DQ_TAP_IM_EL19__M 0xFFF

10280

#define QAM_DQ_TAP_IM_EL19__PRE 0x2

10281

10282

#define QAM_DQ_TAP_IM_EL19_TAP__B 0

10283

#define QAM_DQ_TAP_IM_EL19_TAP__W 12

10284

#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF

10285

#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x2

10286

10287

#define QAM_DQ_TAP_RE_EL20__A 0x1440048

10288

#define QAM_DQ_TAP_RE_EL20__W 12

10289

#define QAM_DQ_TAP_RE_EL20__M 0xFFF

10290

#define QAM_DQ_TAP_RE_EL20__PRE 0x2

10291

10292

#define QAM_DQ_TAP_RE_EL20_TAP__B 0

10293

#define QAM_DQ_TAP_RE_EL20_TAP__W 12

10294

#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF

10295

#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x2

10296

10297

#define QAM_DQ_TAP_IM_EL20__A 0x1440049

10298

#define QAM_DQ_TAP_IM_EL20__W 12

10299

#define QAM_DQ_TAP_IM_EL20__M 0xFFF

10300

#define QAM_DQ_TAP_IM_EL20__PRE 0x2

10301

10302

#define QAM_DQ_TAP_IM_EL20_TAP__B 0

10303

#define QAM_DQ_TAP_IM_EL20_TAP__W 12

10304

#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF

10305

#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x2

10306

10307

#define QAM_DQ_TAP_RE_EL21__A 0x144004A

10308

#define QAM_DQ_TAP_RE_EL21__W 12

10309

#define QAM_DQ_TAP_RE_EL21__M 0xFFF

10310

#define QAM_DQ_TAP_RE_EL21__PRE 0x2

10311

10312

#define QAM_DQ_TAP_RE_EL21_TAP__B 0

10313

#define QAM_DQ_TAP_RE_EL21_TAP__W 12

10314

#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF

10315

#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x2

10316

10317

#define QAM_DQ_TAP_IM_EL21__A 0x144004B

10318

#define QAM_DQ_TAP_IM_EL21__W 12

10319

#define QAM_DQ_TAP_IM_EL21__M 0xFFF

10320

#define QAM_DQ_TAP_IM_EL21__PRE 0x2

10321

10322

#define QAM_DQ_TAP_IM_EL21_TAP__B 0

10323

#define QAM_DQ_TAP_IM_EL21_TAP__W 12

10324

#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF

10325

#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x2

10326

10327

#define QAM_DQ_TAP_RE_EL22__A 0x144004C

10328

#define QAM_DQ_TAP_RE_EL22__W 12

10329

#define QAM_DQ_TAP_RE_EL22__M 0xFFF

10330

#define QAM_DQ_TAP_RE_EL22__PRE 0x2

10331

10332

#define QAM_DQ_TAP_RE_EL22_TAP__B 0

10333

#define QAM_DQ_TAP_RE_EL22_TAP__W 12

10334

#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF

10335

#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x2

10336

10337

#define QAM_DQ_TAP_IM_EL22__A 0x144004D

10338

#define QAM_DQ_TAP_IM_EL22__W 12

10339

#define QAM_DQ_TAP_IM_EL22__M 0xFFF

10340

#define QAM_DQ_TAP_IM_EL22__PRE 0x2

10341

10342

#define QAM_DQ_TAP_IM_EL22_TAP__B 0

10343

#define QAM_DQ_TAP_IM_EL22_TAP__W 12

10344

#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF

10345

#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x2

10346

10347

#define QAM_DQ_TAP_RE_EL23__A 0x144004E

10348

#define QAM_DQ_TAP_RE_EL23__W 12

10349

#define QAM_DQ_TAP_RE_EL23__M 0xFFF

10350

#define QAM_DQ_TAP_RE_EL23__PRE 0x2

10351

10352

#define QAM_DQ_TAP_RE_EL23_TAP__B 0

10353

#define QAM_DQ_TAP_RE_EL23_TAP__W 12

10354

#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF

10355

#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x2

10356

10357

#define QAM_DQ_TAP_IM_EL23__A 0x144004F

10358

#define QAM_DQ_TAP_IM_EL23__W 12

10359

#define QAM_DQ_TAP_IM_EL23__M 0xFFF

10360

#define QAM_DQ_TAP_IM_EL23__PRE 0x2

10361

10362

#define QAM_DQ_TAP_IM_EL23_TAP__B 0

10363

#define QAM_DQ_TAP_IM_EL23_TAP__W 12

10364

#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF

10365

#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x2

10366

10367

#define QAM_DQ_TAP_RE_EL24__A 0x1440050

10368

#define QAM_DQ_TAP_RE_EL24__W 12

10369

#define QAM_DQ_TAP_RE_EL24__M 0xFFF

10370

#define QAM_DQ_TAP_RE_EL24__PRE 0x2

10371

10372

#define QAM_DQ_TAP_RE_EL24_TAP__B 0

10373

#define QAM_DQ_TAP_RE_EL24_TAP__W 12

10374

#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF

10375

#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x2

10376

10377

#define QAM_DQ_TAP_IM_EL24__A 0x1440051

10378

#define QAM_DQ_TAP_IM_EL24__W 12

10379

#define QAM_DQ_TAP_IM_EL24__M 0xFFF

10380

#define QAM_DQ_TAP_IM_EL24__PRE 0x2

10381

10382

#define QAM_DQ_TAP_IM_EL24_TAP__B 0

10383

#define QAM_DQ_TAP_IM_EL24_TAP__W 12

10384

#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF

10385

#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x2

10386

10387

#define QAM_DQ_TAP_RE_EL25__A 0x1440052

10388

#define QAM_DQ_TAP_RE_EL25__W 12

10389

#define QAM_DQ_TAP_RE_EL25__M 0xFFF

10390

#define QAM_DQ_TAP_RE_EL25__PRE 0x2

10391

10392

#define QAM_DQ_TAP_RE_EL25_TAP__B 0

10393

#define QAM_DQ_TAP_RE_EL25_TAP__W 12

10394

#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF

10395

#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x2

10396

10397

#define QAM_DQ_TAP_IM_EL25__A 0x1440053

10398

#define QAM_DQ_TAP_IM_EL25__W 12

10399

#define QAM_DQ_TAP_IM_EL25__M 0xFFF

10400

#define QAM_DQ_TAP_IM_EL25__PRE 0x2

10401

10402

#define QAM_DQ_TAP_IM_EL25_TAP__B 0

10403

#define QAM_DQ_TAP_IM_EL25_TAP__W 12

10404

#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF

10405

#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x2

10406

10407

#define QAM_DQ_TAP_RE_EL26__A 0x1440054

10408

#define QAM_DQ_TAP_RE_EL26__W 12

10409

#define QAM_DQ_TAP_RE_EL26__M 0xFFF

10410

#define QAM_DQ_TAP_RE_EL26__PRE 0x2

10411

10412

#define QAM_DQ_TAP_RE_EL26_TAP__B 0

10413

#define QAM_DQ_TAP_RE_EL26_TAP__W 12

10414

#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF

10415

#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x2

10416

10417

#define QAM_DQ_TAP_IM_EL26__A 0x1440055

10418

#define QAM_DQ_TAP_IM_EL26__W 12

10419

#define QAM_DQ_TAP_IM_EL26__M 0xFFF

10420

#define QAM_DQ_TAP_IM_EL26__PRE 0x2

10421

10422

#define QAM_DQ_TAP_IM_EL26_TAP__B 0

10423

#define QAM_DQ_TAP_IM_EL26_TAP__W 12

10424

#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF

10425

#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x2

10426

10427

#define QAM_DQ_TAP_RE_EL27__A 0x1440056

10428

#define QAM_DQ_TAP_RE_EL27__W 12

10429

#define QAM_DQ_TAP_RE_EL27__M 0xFFF

10430

#define QAM_DQ_TAP_RE_EL27__PRE 0x2

10431

10432

#define QAM_DQ_TAP_RE_EL27_TAP__B 0

10433

#define QAM_DQ_TAP_RE_EL27_TAP__W 12

10434

#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF

10435

#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x2

10436

10437

#define QAM_DQ_TAP_IM_EL27__A 0x1440057

10438

#define QAM_DQ_TAP_IM_EL27__W 12

10439

#define QAM_DQ_TAP_IM_EL27__M 0xFFF

10440

#define QAM_DQ_TAP_IM_EL27__PRE 0x2

10441

10442

#define QAM_DQ_TAP_IM_EL27_TAP__B 0

10443

#define QAM_DQ_TAP_IM_EL27_TAP__W 12

10444

#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF

10445

#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x2

#define QAM_LC_COMM_EXEC__A 0x1450000

10450

#define QAM_LC_COMM_EXEC__W 2

10451

#define QAM_LC_COMM_EXEC__M 0x3

10452

#define QAM_LC_COMM_EXEC__PRE 0x0

10453

#define QAM_LC_COMM_EXEC_STOP 0x0

10454

#define QAM_LC_COMM_EXEC_ACTIVE 0x1

10455

#define QAM_LC_COMM_EXEC_HOLD 0x2

10456

10457

#define QAM_LC_COMM_MB__A 0x1450002

10458

#define QAM_LC_COMM_MB__W 2

10459

#define QAM_LC_COMM_MB__M 0x3

10460

#define QAM_LC_COMM_MB__PRE 0x0

10461

#define QAM_LC_COMM_MB_CTL__B 0

10462

#define QAM_LC_COMM_MB_CTL__W 1

10463

#define QAM_LC_COMM_MB_CTL__M 0x1

10464

#define QAM_LC_COMM_MB_CTL__PRE 0x0

10465

#define QAM_LC_COMM_MB_CTL_OFF 0x0

10466

#define QAM_LC_COMM_MB_CTL_ON 0x1

10467

#define QAM_LC_COMM_MB_OBS__B 1

10468

#define QAM_LC_COMM_MB_OBS__W 1

10469

#define QAM_LC_COMM_MB_OBS__M 0x2

10470

#define QAM_LC_COMM_MB_OBS__PRE 0x0

10471

#define QAM_LC_COMM_MB_OBS_OFF 0x0

10472

#define QAM_LC_COMM_MB_OBS_ON 0x2

10473

10474

#define QAM_LC_COMM_INT_REQ__A 0x1450003

10475

#define QAM_LC_COMM_INT_REQ__W 1

10476

#define QAM_LC_COMM_INT_REQ__M 0x1

10477

#define QAM_LC_COMM_INT_REQ__PRE 0x0

10478

#define QAM_LC_COMM_INT_STA__A 0x1450005

10479

#define QAM_LC_COMM_INT_STA__W 3

10480

#define QAM_LC_COMM_INT_STA__M 0x7

10481

#define QAM_LC_COMM_INT_STA__PRE 0x0

10482

10483

#define QAM_LC_COMM_INT_STA_READY__B 0

10484

#define QAM_LC_COMM_INT_STA_READY__W 1

10485

#define QAM_LC_COMM_INT_STA_READY__M 0x1

10486

#define QAM_LC_COMM_INT_STA_READY__PRE 0x0

10487

10488

#define QAM_LC_COMM_INT_STA_OVERFLOW__B 1

10489

#define QAM_LC_COMM_INT_STA_OVERFLOW__W 1

10490

#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x2

10491

#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x0

10492

10493

#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 2

10494

#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 1

10495

#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x4

10496

#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x0

10497

10498

#define QAM_LC_COMM_INT_MSK__A 0x1450006

10499

#define QAM_LC_COMM_INT_MSK__W 3

10500

#define QAM_LC_COMM_INT_MSK__M 0x7

10501

#define QAM_LC_COMM_INT_MSK__PRE 0x0

10502

#define QAM_LC_COMM_INT_MSK_READY__B 0

10503

#define QAM_LC_COMM_INT_MSK_READY__W 1

10504

#define QAM_LC_COMM_INT_MSK_READY__M 0x1

10505

#define QAM_LC_COMM_INT_MSK_READY__PRE 0x0

10506

#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 1

10507

#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 1

10508

#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x2

10509

#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x0

10510

#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 2

10511

#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 1

10512

#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x4

10513

#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x0

10514

10515

#define QAM_LC_COMM_INT_STM__A 0x1450007

10516

#define QAM_LC_COMM_INT_STM__W 3

10517

#define QAM_LC_COMM_INT_STM__M 0x7

10518

#define QAM_LC_COMM_INT_STM__PRE 0x0

10519

#define QAM_LC_COMM_INT_STM_READY__B 0

10520

#define QAM_LC_COMM_INT_STM_READY__W 1

10521

#define QAM_LC_COMM_INT_STM_READY__M 0x1

10522

#define QAM_LC_COMM_INT_STM_READY__PRE 0x0

10523

#define QAM_LC_COMM_INT_STM_OVERFLOW__B 1

10524

#define QAM_LC_COMM_INT_STM_OVERFLOW__W 1

10525

#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x2

10526

#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x0

10527

#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 2

10528

#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 1

10529

#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x4

10530

#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x0

10531

10532

#define QAM_LC_MODE__A 0x1450010

10533

#define QAM_LC_MODE__W 4

10534

#define QAM_LC_MODE__M 0xF

10535

#define QAM_LC_MODE__PRE 0xE

10536

10537

#define QAM_LC_MODE_ENABLE_A__B 0

10538

#define QAM_LC_MODE_ENABLE_A__W 1

10539

#define QAM_LC_MODE_ENABLE_A__M 0x1

10540

#define QAM_LC_MODE_ENABLE_A__PRE 0x0

10541

10542

#define QAM_LC_MODE_ENABLE_F__B 1

10543

#define QAM_LC_MODE_ENABLE_F__W 1

10544

#define QAM_LC_MODE_ENABLE_F__M 0x2

10545

#define QAM_LC_MODE_ENABLE_F__PRE 0x2

10546

10547

#define QAM_LC_MODE_ENABLE_R__B 2

10548

#define QAM_LC_MODE_ENABLE_R__W 1

10549

#define QAM_LC_MODE_ENABLE_R__M 0x4

10550

#define QAM_LC_MODE_ENABLE_R__PRE 0x4

10551

10552

#define QAM_LC_MODE_ENABLE_PQUAL__B 3

10553

#define QAM_LC_MODE_ENABLE_PQUAL__W 1

10554

#define QAM_LC_MODE_ENABLE_PQUAL__M 0x8

10555

#define QAM_LC_MODE_ENABLE_PQUAL__PRE 0x8

10556

10557

#define QAM_LC_CA__A 0x1450011

10558

#define QAM_LC_CA__W 6

10559

#define QAM_LC_CA__M 0x3F

10560

#define QAM_LC_CA__PRE 0x28

10561

10562

#define QAM_LC_CA_COEF__B 0

10563

#define QAM_LC_CA_COEF__W 6

10564

#define QAM_LC_CA_COEF__M 0x3F

10565

#define QAM_LC_CA_COEF__PRE 0x28

10566

10567

#define QAM_LC_CF__A 0x1450012

10568

#define QAM_LC_CF__W 8

10569

#define QAM_LC_CF__M 0xFF

10570

#define QAM_LC_CF__PRE 0x30

10571

10572

#define QAM_LC_CF_COEF__B 0

10573

#define QAM_LC_CF_COEF__W 8

10574

#define QAM_LC_CF_COEF__M 0xFF

10575

#define QAM_LC_CF_COEF__PRE 0x30

10576

10577

#define QAM_LC_CF1__A 0x1450013

10578

#define QAM_LC_CF1__W 8

10579

#define QAM_LC_CF1__M 0xFF

10580

#define QAM_LC_CF1__PRE 0x14

10581

10582

#define QAM_LC_CF1_COEF__B 0

10583

#define QAM_LC_CF1_COEF__W 8

10584

#define QAM_LC_CF1_COEF__M 0xFF

10585

#define QAM_LC_CF1_COEF__PRE 0x14

10586

10587

#define QAM_LC_CP__A 0x1450014

10588

#define QAM_LC_CP__W 8

10589

#define QAM_LC_CP__M 0xFF

10590

#define QAM_LC_CP__PRE 0x64

10591

10592

#define QAM_LC_CP_COEF__B 0

10593

#define QAM_LC_CP_COEF__W 8

10594

#define QAM_LC_CP_COEF__M 0xFF

10595

#define QAM_LC_CP_COEF__PRE 0x64

10596

10597

#define QAM_LC_CI__A 0x1450015

10598

#define QAM_LC_CI__W 8

10599

#define QAM_LC_CI__M 0xFF

10600

#define QAM_LC_CI__PRE 0x32

10601

10602

#define QAM_LC_CI_COEF__B 0

10603

#define QAM_LC_CI_COEF__W 8

10604

#define QAM_LC_CI_COEF__M 0xFF

10605

#define QAM_LC_CI_COEF__PRE 0x32

10606

10607

#define QAM_LC_EP__A 0x1450016

10608

#define QAM_LC_EP__W 6

10609

#define QAM_LC_EP__M 0x3F

10610

#define QAM_LC_EP__PRE 0x0

10611

10612

#define QAM_LC_EP_COEF__B 0

10613

#define QAM_LC_EP_COEF__W 6

10614

#define QAM_LC_EP_COEF__M 0x3F

10615

#define QAM_LC_EP_COEF__PRE 0x0

10616

10617

#define QAM_LC_EI__A 0x1450017

10618

#define QAM_LC_EI__W 6

10619

#define QAM_LC_EI__M 0x3F

10620

#define QAM_LC_EI__PRE 0x0

10621

10622

#define QAM_LC_EI_COEF__B 0

10623

#define QAM_LC_EI_COEF__W 6

10624

#define QAM_LC_EI_COEF__M 0x3F

10625

#define QAM_LC_EI_COEF__PRE 0x0

10626

10627

#define QAM_LC_QUAL_TAB0__A 0x1450018

10628

#define QAM_LC_QUAL_TAB0__W 5

10629

#define QAM_LC_QUAL_TAB0__M 0x1F

10630

#define QAM_LC_QUAL_TAB0__PRE 0x0

10631

10632

#define QAM_LC_QUAL_TAB0_VALUE__B 0

10633

#define QAM_LC_QUAL_TAB0_VALUE__W 5

10634

#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F

10635

#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x0

10636

10637

#define QAM_LC_QUAL_TAB1__A 0x1450019

10638

#define QAM_LC_QUAL_TAB1__W 5

10639

#define QAM_LC_QUAL_TAB1__M 0x1F

10640

#define QAM_LC_QUAL_TAB1__PRE 0x1

10641

10642

#define QAM_LC_QUAL_TAB1_VALUE__B 0

10643

#define QAM_LC_QUAL_TAB1_VALUE__W 5

10644

#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F

10645

#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x1

10646

10647

#define QAM_LC_QUAL_TAB2__A 0x145001A

10648

#define QAM_LC_QUAL_TAB2__W 5

10649

#define QAM_LC_QUAL_TAB2__M 0x1F

10650

#define QAM_LC_QUAL_TAB2__PRE 0x2

10651

10652

#define QAM_LC_QUAL_TAB2_VALUE__B 0

10653

#define QAM_LC_QUAL_TAB2_VALUE__W 5

10654

#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F

10655

#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x2

10656

10657

#define QAM_LC_QUAL_TAB3__A 0x145001B

10658

#define QAM_LC_QUAL_TAB3__W 5

10659

#define QAM_LC_QUAL_TAB3__M 0x1F

10660

#define QAM_LC_QUAL_TAB3__PRE 0x3

10661

10662

#define QAM_LC_QUAL_TAB3_VALUE__B 0

10663

#define QAM_LC_QUAL_TAB3_VALUE__W 5

10664

#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F

10665

#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x3

10666

10667

#define QAM_LC_QUAL_TAB4__A 0x145001C

10668

#define QAM_LC_QUAL_TAB4__W 5

10669

#define QAM_LC_QUAL_TAB4__M 0x1F

10670

#define QAM_LC_QUAL_TAB4__PRE 0x4

10671

10672

#define QAM_LC_QUAL_TAB4_VALUE__B 0

10673

#define QAM_LC_QUAL_TAB4_VALUE__W 5

10674

#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F

10675

#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x4

10676

10677

#define QAM_LC_QUAL_TAB5__A 0x145001D

10678

#define QAM_LC_QUAL_TAB5__W 5

10679

#define QAM_LC_QUAL_TAB5__M 0x1F

10680

#define QAM_LC_QUAL_TAB5__PRE 0x5

10681

10682

#define QAM_LC_QUAL_TAB5_VALUE__B 0

10683

#define QAM_LC_QUAL_TAB5_VALUE__W 5

10684

#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F

10685

#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x5

10686

10687

#define QAM_LC_QUAL_TAB6__A 0x145001E

10688

#define QAM_LC_QUAL_TAB6__W 5

10689

#define QAM_LC_QUAL_TAB6__M 0x1F

10690

#define QAM_LC_QUAL_TAB6__PRE 0x6

10691

10692

#define QAM_LC_QUAL_TAB6_VALUE__B 0

10693

#define QAM_LC_QUAL_TAB6_VALUE__W 5

10694

#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F

10695

#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x6

10696

10697

#define QAM_LC_QUAL_TAB8__A 0x145001F

10698

#define QAM_LC_QUAL_TAB8__W 5

10699

#define QAM_LC_QUAL_TAB8__M 0x1F

10700

#define QAM_LC_QUAL_TAB8__PRE 0x8

10701

10702

#define QAM_LC_QUAL_TAB8_VALUE__B 0

10703

#define QAM_LC_QUAL_TAB8_VALUE__W 5

10704

#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F

10705

#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x8

10706

10707

#define QAM_LC_QUAL_TAB9__A 0x1450020

10708

#define QAM_LC_QUAL_TAB9__W 5

10709

#define QAM_LC_QUAL_TAB9__M 0x1F

10710

#define QAM_LC_QUAL_TAB9__PRE 0x9

10711

10712

#define QAM_LC_QUAL_TAB9_VALUE__B 0

10713

#define QAM_LC_QUAL_TAB9_VALUE__W 5

10714

#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F

10715

#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x9

10716

10717

#define QAM_LC_QUAL_TAB10__A 0x1450021

10718

#define QAM_LC_QUAL_TAB10__W 5

10719

#define QAM_LC_QUAL_TAB10__M 0x1F

10720

#define QAM_LC_QUAL_TAB10__PRE 0xA

10721

10722

#define QAM_LC_QUAL_TAB10_VALUE__B 0

10723

#define QAM_LC_QUAL_TAB10_VALUE__W 5

10724

#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F

10725

#define QAM_LC_QUAL_TAB10_VALUE__PRE 0xA

10726

10727

#define QAM_LC_QUAL_TAB12__A 0x1450022

10728

#define QAM_LC_QUAL_TAB12__W 5

10729

#define QAM_LC_QUAL_TAB12__M 0x1F

10730

#define QAM_LC_QUAL_TAB12__PRE 0xC

10731

10732

#define QAM_LC_QUAL_TAB12_VALUE__B 0

10733

#define QAM_LC_QUAL_TAB12_VALUE__W 5

10734

#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F

10735

#define QAM_LC_QUAL_TAB12_VALUE__PRE 0xC

10736

10737

#define QAM_LC_QUAL_TAB15__A 0x1450023

10738

#define QAM_LC_QUAL_TAB15__W 5

10739

#define QAM_LC_QUAL_TAB15__M 0x1F

10740

#define QAM_LC_QUAL_TAB15__PRE 0xF

10741

10742

#define QAM_LC_QUAL_TAB15_VALUE__B 0

10743

#define QAM_LC_QUAL_TAB15_VALUE__W 5

10744

#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F

10745

#define QAM_LC_QUAL_TAB15_VALUE__PRE 0xF

10746

10747

#define QAM_LC_QUAL_TAB16__A 0x1450024

10748

#define QAM_LC_QUAL_TAB16__W 5

10749

#define QAM_LC_QUAL_TAB16__M 0x1F

10750

#define QAM_LC_QUAL_TAB16__PRE 0x10

10751

10752

#define QAM_LC_QUAL_TAB16_VALUE__B 0

10753

#define QAM_LC_QUAL_TAB16_VALUE__W 5

10754

#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F

10755

#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x10

10756

10757

#define QAM_LC_QUAL_TAB20__A 0x1450025

10758

#define QAM_LC_QUAL_TAB20__W 5

10759

#define QAM_LC_QUAL_TAB20__M 0x1F

10760

#define QAM_LC_QUAL_TAB20__PRE 0x14

10761

10762

#define QAM_LC_QUAL_TAB20_VALUE__B 0

10763

#define QAM_LC_QUAL_TAB20_VALUE__W 5

10764

#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F

10765

#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x14

10766

10767

#define QAM_LC_QUAL_TAB25__A 0x1450026

10768

#define QAM_LC_QUAL_TAB25__W 5

10769

#define QAM_LC_QUAL_TAB25__M 0x1F

10770

#define QAM_LC_QUAL_TAB25__PRE 0x19

10771

10772

#define QAM_LC_QUAL_TAB25_VALUE__B 0

10773

#define QAM_LC_QUAL_TAB25_VALUE__W 5

10774

#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F

10775

#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x19

10776

10777

#define QAM_LC_EQ_TIMING__A 0x1450027

10778

#define QAM_LC_EQ_TIMING__W 10

10779

#define QAM_LC_EQ_TIMING__M 0x3FF

10780

#define QAM_LC_EQ_TIMING__PRE 0x0

10781

10782

#define QAM_LC_EQ_TIMING_OFFS__B 0

10783

#define QAM_LC_EQ_TIMING_OFFS__W 10

10784

#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF

10785

#define QAM_LC_EQ_TIMING_OFFS__PRE 0x0

10786

10787

#define QAM_LC_LPF_FACTORP__A 0x1450028

10788

#define QAM_LC_LPF_FACTORP__W 3

10789

#define QAM_LC_LPF_FACTORP__M 0x7

10790

#define QAM_LC_LPF_FACTORP__PRE 0x3

10791

10792

#define QAM_LC_LPF_FACTORP_FACTOR__B 0

10793

#define QAM_LC_LPF_FACTORP_FACTOR__W 3

10794

#define QAM_LC_LPF_FACTORP_FACTOR__M 0x7

10795

#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x3

10796

10797

#define QAM_LC_LPF_FACTORI__A 0x1450029

10798

#define QAM_LC_LPF_FACTORI__W 3

10799

#define QAM_LC_LPF_FACTORI__M 0x7

10800

#define QAM_LC_LPF_FACTORI__PRE 0x3

10801

10802

#define QAM_LC_LPF_FACTORI_FACTOR__B 0

10803

#define QAM_LC_LPF_FACTORI_FACTOR__W 3

10804

#define QAM_LC_LPF_FACTORI_FACTOR__M 0x7

10805

#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x3

10806

10807

#define QAM_LC_RATE_LIMIT__A 0x145002A

10808

#define QAM_LC_RATE_LIMIT__W 2

10809

#define QAM_LC_RATE_LIMIT__M 0x3

10810

#define QAM_LC_RATE_LIMIT__PRE 0x3

10811

10812

#define QAM_LC_RATE_LIMIT_LIMIT__B 0

10813

#define QAM_LC_RATE_LIMIT_LIMIT__W 2

10814

#define QAM_LC_RATE_LIMIT_LIMIT__M 0x3

10815

#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x3

10816

10817

#define QAM_LC_SYMBOL_FREQ__A 0x145002B

10818

#define QAM_LC_SYMBOL_FREQ__W 10

10819

#define QAM_LC_SYMBOL_FREQ__M 0x3FF

10820

#define QAM_LC_SYMBOL_FREQ__PRE 0x1FF

10821

10822

#define QAM_LC_SYMBOL_FREQ_FREQ__B 0

10823

#define QAM_LC_SYMBOL_FREQ_FREQ__W 10

10824

#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF

10825

#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1FF

10826

10827

#define QAM_LC_MTA_LENGTH__A 0x145002C

10828

#define QAM_LC_MTA_LENGTH__W 2

10829

#define QAM_LC_MTA_LENGTH__M 0x3

10830

#define QAM_LC_MTA_LENGTH__PRE 0x2

10831

10832

#define QAM_LC_MTA_LENGTH_LENGTH__B 0

10833

#define QAM_LC_MTA_LENGTH_LENGTH__W 2

10834

#define QAM_LC_MTA_LENGTH_LENGTH__M 0x3

10835

#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x2

10836

10837

#define QAM_LC_AMP_ACCU__A 0x145002D

10838

#define QAM_LC_AMP_ACCU__W 14

10839

#define QAM_LC_AMP_ACCU__M 0x3FFF

10840

#define QAM_LC_AMP_ACCU__PRE 0x600

10841

10842

#define QAM_LC_AMP_ACCU_ACCU__B 0

10843

#define QAM_LC_AMP_ACCU_ACCU__W 14

10844

#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF

10845

#define QAM_LC_AMP_ACCU_ACCU__PRE 0x600

10846

10847

#define QAM_LC_FREQ_ACCU__A 0x145002E

10848

#define QAM_LC_FREQ_ACCU__W 10

10849

#define QAM_LC_FREQ_ACCU__M 0x3FF

10850

#define QAM_LC_FREQ_ACCU__PRE 0x0

10851

10852

#define QAM_LC_FREQ_ACCU_ACCU__B 0

10853

#define QAM_LC_FREQ_ACCU_ACCU__W 10

10854

#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF

10855

#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x0

10856

10857

#define QAM_LC_RATE_ACCU__A 0x145002F

10858

#define QAM_LC_RATE_ACCU__W 10

10859

#define QAM_LC_RATE_ACCU__M 0x3FF

10860

#define QAM_LC_RATE_ACCU__PRE 0x0

10861

10862

#define QAM_LC_RATE_ACCU_ACCU__B 0

10863

#define QAM_LC_RATE_ACCU_ACCU__W 10

10864

#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF

10865

#define QAM_LC_RATE_ACCU_ACCU__PRE 0x0

10866

10867

#define QAM_LC_AMPLITUDE__A 0x1450030

10868

#define QAM_LC_AMPLITUDE__W 10

10869

#define QAM_LC_AMPLITUDE__M 0x3FF

10870

#define QAM_LC_AMPLITUDE__PRE 0x0

10871

10872

#define QAM_LC_AMPLITUDE_SIZE__B 0

10873

#define QAM_LC_AMPLITUDE_SIZE__W 10

10874

#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF

10875

#define QAM_LC_AMPLITUDE_SIZE__PRE 0x0

10876

10877

#define QAM_LC_RAD_ERROR__A 0x1450031

10878

#define QAM_LC_RAD_ERROR__W 10

10879

#define QAM_LC_RAD_ERROR__M 0x3FF

10880

#define QAM_LC_RAD_ERROR__PRE 0x0

10881

10882

#define QAM_LC_RAD_ERROR_SIZE__B 0

10883

#define QAM_LC_RAD_ERROR_SIZE__W 10

10884

#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF

10885

#define QAM_LC_RAD_ERROR_SIZE__PRE 0x0

10886

10887

#define QAM_LC_FREQ_OFFS__A 0x1450032

10888

#define QAM_LC_FREQ_OFFS__W 10

10889

#define QAM_LC_FREQ_OFFS__M 0x3FF

10890

#define QAM_LC_FREQ_OFFS__PRE 0x0

10891

10892

#define QAM_LC_FREQ_OFFS_OFFS__B 0

10893

#define QAM_LC_FREQ_OFFS_OFFS__W 10

10894

#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF

10895

#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x0

10896

10897

#define QAM_LC_PHASE_ERROR__A 0x1450033

10898

#define QAM_LC_PHASE_ERROR__W 10

10899

#define QAM_LC_PHASE_ERROR__M 0x3FF

10900

#define QAM_LC_PHASE_ERROR__PRE 0x0

10901

10902

#define QAM_LC_PHASE_ERROR_SIZE__B 0

10903

#define QAM_LC_PHASE_ERROR_SIZE__W 10

10904

#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF

10905

#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x0

#define QAM_SY_COMM_EXEC__A 0x1470000

10910

#define QAM_SY_COMM_EXEC__W 2

10911

#define QAM_SY_COMM_EXEC__M 0x3

10912

#define QAM_SY_COMM_EXEC__PRE 0x0

10913

#define QAM_SY_COMM_EXEC_STOP 0x0

10914

#define QAM_SY_COMM_EXEC_ACTIVE 0x1

10915

#define QAM_SY_COMM_EXEC_HOLD 0x2

10916

10917

#define QAM_SY_COMM_MB__A 0x1470002

10918

#define QAM_SY_COMM_MB__W 4

10919

#define QAM_SY_COMM_MB__M 0xF

10920

#define QAM_SY_COMM_MB__PRE 0x0

10921

#define QAM_SY_COMM_MB_CTL__B 0

10922

#define QAM_SY_COMM_MB_CTL__W 1

10923

#define QAM_SY_COMM_MB_CTL__M 0x1

10924

#define QAM_SY_COMM_MB_CTL__PRE 0x0

10925

#define QAM_SY_COMM_MB_CTL_OFF 0x0

10926

#define QAM_SY_COMM_MB_CTL_ON 0x1

10927

#define QAM_SY_COMM_MB_OBS__B 1

10928

#define QAM_SY_COMM_MB_OBS__W 1

10929

#define QAM_SY_COMM_MB_OBS__M 0x2

10930

#define QAM_SY_COMM_MB_OBS__PRE 0x0

10931

#define QAM_SY_COMM_MB_OBS_OFF 0x0

10932

#define QAM_SY_COMM_MB_OBS_ON 0x2

10933

#define QAM_SY_COMM_MB_MUX_CTL__B 2

10934

#define QAM_SY_COMM_MB_MUX_CTL__W 1

10935

#define QAM_SY_COMM_MB_MUX_CTL__M 0x4

10936

#define QAM_SY_COMM_MB_MUX_CTL__PRE 0x0

10937

#define QAM_SY_COMM_MB_MUX_CTL_MB0 0x0

10938

#define QAM_SY_COMM_MB_MUX_CTL_MB1 0x4

10939

#define QAM_SY_COMM_MB_MUX_OBS__B 3

10940

#define QAM_SY_COMM_MB_MUX_OBS__W 1

10941

#define QAM_SY_COMM_MB_MUX_OBS__M 0x8

10942

#define QAM_SY_COMM_MB_MUX_OBS__PRE 0x0

10943

#define QAM_SY_COMM_MB_MUX_OBS_MB0 0x0

10944

#define QAM_SY_COMM_MB_MUX_OBS_MB1 0x8

10945

10946

#define QAM_SY_COMM_INT_REQ__A 0x1470003

10947

#define QAM_SY_COMM_INT_REQ__W 1

10948

#define QAM_SY_COMM_INT_REQ__M 0x1

10949

#define QAM_SY_COMM_INT_REQ__PRE 0x0

10950

#define QAM_SY_COMM_INT_STA__A 0x1470005

10951

#define QAM_SY_COMM_INT_STA__W 4

10952

#define QAM_SY_COMM_INT_STA__M 0xF

10953

#define QAM_SY_COMM_INT_STA__PRE 0x0

10954

10955

#define QAM_SY_COMM_INT_STA_LOCK_INT__B 0

10956

#define QAM_SY_COMM_INT_STA_LOCK_INT__W 1

10957

#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x1

10958

#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x0

10959

10960

#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 1

10961

#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 1

10962

#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x2

10963

#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x0

10964

10965

#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 2

10966

#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 1

10967

#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x4

10968

#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x0

10969

10970

#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 3

10971

#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 1

10972

#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x8

10973

#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x0

10974

10975

#define QAM_SY_COMM_INT_MSK__A 0x1470006

10976

#define QAM_SY_COMM_INT_MSK__W 4

10977

#define QAM_SY_COMM_INT_MSK__M 0xF

10978

#define QAM_SY_COMM_INT_MSK__PRE 0x0

10979

#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 0

10980

#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 1

10981

#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x1

10982

#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x0

10983

#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 1

10984

#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 1

10985

#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x2

10986

#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x0

10987

#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 2

10988

#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 1

10989

#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x4

10990

#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x0

10991

#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 3

10992

#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 1

10993

#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x8

10994

#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x0

10995

10996

#define QAM_SY_COMM_INT_STM__A 0x1470007

10997

#define QAM_SY_COMM_INT_STM__W 4

10998

#define QAM_SY_COMM_INT_STM__M 0xF

10999

#define QAM_SY_COMM_INT_STM__PRE 0x0

11000

#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 0

11001

#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 1

11002

#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x1

11003

#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x0

11004

#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 1

11005

#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 1

11006

#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x2

11007

#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x0

11008

#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 2

11009

#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 1

11010

#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x4

11011

#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x0

11012

#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 3

11013

#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 1

11014

#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x8

11015

#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x0

11016

11017

#define QAM_SY_STATUS__A 0x1470010

11018

#define QAM_SY_STATUS__W 2

11019

#define QAM_SY_STATUS__M 0x3

11020

#define QAM_SY_STATUS__PRE 0x0

11021

11022

#define QAM_SY_STATUS_SYNC_STATE__B 0

11023

#define QAM_SY_STATUS_SYNC_STATE__W 2

11024

#define QAM_SY_STATUS_SYNC_STATE__M 0x3

11025

#define QAM_SY_STATUS_SYNC_STATE__PRE 0x0

11026

11027

11028

#define QAM_SY_TIMEOUT__A 0x1470011

11029

#define QAM_SY_TIMEOUT__W 16

11030

#define QAM_SY_TIMEOUT__M 0xFFFF

11031

#define QAM_SY_TIMEOUT__PRE 0x3A98

11032

11033

#define QAM_SY_SYNC_LWM__A 0x1470012

11034

#define QAM_SY_SYNC_LWM__W 4

11035

#define QAM_SY_SYNC_LWM__M 0xF

11036

#define QAM_SY_SYNC_LWM__PRE 0x2

11037

11038

#define QAM_SY_SYNC_AWM__A 0x1470013

11039

#define QAM_SY_SYNC_AWM__W 4

11040

#define QAM_SY_SYNC_AWM__M 0xF

11041

#define QAM_SY_SYNC_AWM__PRE 0x3

11042

11043

#define QAM_SY_SYNC_HWM__A 0x1470014

11044

#define QAM_SY_SYNC_HWM__W 4

11045

#define QAM_SY_SYNC_HWM__M 0xF

11046

#define QAM_SY_SYNC_HWM__PRE 0x5

11047

11048

#define QAM_SY_UNLOCK__A 0x1470015

11049

#define QAM_SY_UNLOCK__W 1

11050

#define QAM_SY_UNLOCK__M 0x1

11051

#define QAM_SY_UNLOCK__PRE 0x0

11052

#define QAM_SY_CONTROL_WORD__A 0x1470016

11053

#define QAM_SY_CONTROL_WORD__W 4

11054

#define QAM_SY_CONTROL_WORD__M 0xF

11055

#define QAM_SY_CONTROL_WORD__PRE 0x0

11056

11057

#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 0

11058

#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 4

11059

#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF

11060

#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x0

11061

11062

11063

#define QAM_SY_SP_INV__A 0x1470017

11064

#define QAM_SY_SP_INV__W 1

11065

#define QAM_SY_SP_INV__M 0x1

11066

#define QAM_SY_SP_INV__PRE 0x0

11067

#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0

11068

#define QAM_SY_SP_INV_SPECTRUM_INV_ENA 0x1

#define QAM_VD_ISS_RAM__A 0x1480000

#define QAM_VD_QSS_RAM__A 0x1490000

#define QAM_VD_SYM_RAM__A 0x14A0000

#define SCU_COMM_EXEC__A 0x800000

11087

#define SCU_COMM_EXEC__W 2

11088

#define SCU_COMM_EXEC__M 0x3

11089

#define SCU_COMM_EXEC__PRE 0x0

11090

#define SCU_COMM_EXEC_STOP 0x0

11091

#define SCU_COMM_EXEC_ACTIVE 0x1

11092

#define SCU_COMM_EXEC_HOLD 0x2

11093

11094

#define SCU_COMM_STATE__A 0x800001

11095

#define SCU_COMM_STATE__W 16

11096

#define SCU_COMM_STATE__M 0xFFFF

11097

#define SCU_COMM_STATE__PRE 0x0

11098

11099

#define SCU_COMM_STATE_COMM_STATE__B 0

11100

#define SCU_COMM_STATE_COMM_STATE__W 16

11101

#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF

11102

#define SCU_COMM_STATE_COMM_STATE__PRE 0x0

#define SCU_TOP_COMM_EXEC__A 0x810000

11107

#define SCU_TOP_COMM_EXEC__W 2

11108

#define SCU_TOP_COMM_EXEC__M 0x3

11109

#define SCU_TOP_COMM_EXEC__PRE 0x0

11110

#define SCU_TOP_COMM_EXEC_STOP 0x0

11111

#define SCU_TOP_COMM_EXEC_ACTIVE 0x1

11112

#define SCU_TOP_COMM_EXEC_HOLD 0x2

11113

11114

11115

#define SCU_TOP_COMM_STATE__A 0x810001

11116

#define SCU_TOP_COMM_STATE__W 16

11117

#define SCU_TOP_COMM_STATE__M 0xFFFF

11118

#define SCU_TOP_COMM_STATE__PRE 0x0

11119

#define SCU_TOP_MWAIT_CTR__A 0x810010

11120

#define SCU_TOP_MWAIT_CTR__W 2

11121

#define SCU_TOP_MWAIT_CTR__M 0x3

11122

#define SCU_TOP_MWAIT_CTR__PRE 0x0

11123

11124

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 0

11125

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 1

11126

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x1

11127

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x0

11128

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x0

11129

#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x1

11130

11131

#define SCU_TOP_MWAIT_CTR_READY_DIS__B 1

11132

#define SCU_TOP_MWAIT_CTR_READY_DIS__W 1

11133

#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x2

11134

#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x0

11135

#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x0

11136

#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x2

#define SCU_LOW_RAM__A 0x820000

11141

11142

#define SCU_LOW_RAM_LOW__B 0

11143

#define SCU_LOW_RAM_LOW__W 16

11144

#define SCU_LOW_RAM_LOW__M 0xFFFF

11145

#define SCU_LOW_RAM_LOW__PRE 0x0

#define SCU_HIGH_RAM__A 0x830000

11150

11151

#define SCU_HIGH_RAM_HIGH__B 0

11152

#define SCU_HIGH_RAM_HIGH__W 16

11153

#define SCU_HIGH_RAM_HIGH__M 0xFFFF

11154

#define SCU_HIGH_RAM_HIGH__PRE 0x0

#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF

11162

#define SCU_RAM_DRIVER_DEBUG__W 16

11163

#define SCU_RAM_DRIVER_DEBUG__M 0xFFFF

11164

#define SCU_RAM_DRIVER_DEBUG__PRE 0x0

11165

11166

#define SCU_RAM_SP__A 0x831EC0

11167

#define SCU_RAM_SP__W 16

11168

#define SCU_RAM_SP__M 0xFFFF

11169

#define SCU_RAM_SP__PRE 0x0

11170

11171

#define SCU_RAM_QAM_NEVERLOCK_CNT__A 0x831EC1

11172

#define SCU_RAM_QAM_NEVERLOCK_CNT__W 16

11173

#define SCU_RAM_QAM_NEVERLOCK_CNT__M 0xFFFF

11174

#define SCU_RAM_QAM_NEVERLOCK_CNT__PRE 0x0

11175

11176

#define SCU_RAM_QAM_WRONG_RATE_CNT__A 0x831EC2

11177

#define SCU_RAM_QAM_WRONG_RATE_CNT__W 16

11178

#define SCU_RAM_QAM_WRONG_RATE_CNT__M 0xFFFF

11179

#define SCU_RAM_QAM_WRONG_RATE_CNT__PRE 0x0

11180

11181

#define SCU_RAM_QAM_NO_ACQ_CNT__A 0x831EC3

11182

#define SCU_RAM_QAM_NO_ACQ_CNT__W 16

11183

#define SCU_RAM_QAM_NO_ACQ_CNT__M 0xFFFF

11184

#define SCU_RAM_QAM_NO_ACQ_CNT__PRE 0x0

11185

11186

#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4

11187

#define SCU_RAM_QAM_FSM_STEP_PERIOD__W 16

11188

#define SCU_RAM_QAM_FSM_STEP_PERIOD__M 0xFFFF

11189

#define SCU_RAM_QAM_FSM_STEP_PERIOD__PRE 0x4B0

11190

11191

#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC5

11192

#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 16

11193

#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF

11194

#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x8000

11195

11196

#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC6

11197

#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 16

11198

#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF

11199

#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x0

11200

#define SCU_RAM_GPIO__A 0x831EC7

11201

#define SCU_RAM_GPIO__W 2

11202

#define SCU_RAM_GPIO__M 0x3

11203

#define SCU_RAM_GPIO__PRE 0x0

11204

11205

#define SCU_RAM_GPIO_HW_LOCK_IND__B 0

11206

#define SCU_RAM_GPIO_HW_LOCK_IND__W 1

11207

#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x1

11208

#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x0

11209

#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0

11210

#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x1

11211

11212

#define SCU_RAM_GPIO_VSYNC_IND__B 1

11213

#define SCU_RAM_GPIO_VSYNC_IND__W 1

11214

#define SCU_RAM_GPIO_VSYNC_IND__M 0x2

11215

#define SCU_RAM_GPIO_VSYNC_IND__PRE 0x0

11216

#define SCU_RAM_GPIO_VSYNC_IND_DISABLE 0x0

11217

#define SCU_RAM_GPIO_VSYNC_IND_ENABLE 0x2

11218

11219

#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8

11220

#define SCU_RAM_AGC_CLP_CTRL_MODE__W 8

11221

#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF

11222

#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x0

11223

11224

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 0

11225

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 1

11226

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x1

11227

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x0

11228

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_FALSE 0x0

11229

#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_TRUE 0x1

11230

11231

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 1

11232

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 1

11233

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x2

11234

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x0

11235

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x0

11236

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x2

11237

11238

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 2

11239

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 1

11240

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x4

11241

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x0

11242

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x0

11243

#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x4

11244

11245

11246

#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC9

11247

#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 16

11248

#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF

11249

#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x8000

11250

11251

#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA

11252

#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 16

11253

#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF

11254

#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x0

11255

11256

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB

11257

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 16

11258

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF

11259

#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x0

11260

11261

#define SCU_RAM_INHIBIT_1__A 0x831ECC

11262

#define SCU_RAM_INHIBIT_1__W 16

11263

#define SCU_RAM_INHIBIT_1__M 0xFFFF

11264

#define SCU_RAM_INHIBIT_1__PRE 0x0

11265

11266

#define SCU_RAM_HTOL_BUF_0__A 0x831ECD

11267

#define SCU_RAM_HTOL_BUF_0__W 16

11268

#define SCU_RAM_HTOL_BUF_0__M 0xFFFF

11269

#define SCU_RAM_HTOL_BUF_0__PRE 0x0

11270

11271

#define SCU_RAM_HTOL_BUF_1__A 0x831ECE

11272

#define SCU_RAM_HTOL_BUF_1__W 16

11273

#define SCU_RAM_HTOL_BUF_1__M 0xFFFF

11274

#define SCU_RAM_HTOL_BUF_1__PRE 0x0

11275

11276

#define SCU_RAM_INHIBIT_2__A 0x831ECF

11277

#define SCU_RAM_INHIBIT_2__W 16

11278

#define SCU_RAM_INHIBIT_2__M 0xFFFF

11279

#define SCU_RAM_INHIBIT_2__PRE 0x0

11280

11281

#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED0

11282

#define SCU_RAM_TR_SHORT_BUF_0__W 16

11283

#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF

11284

#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x0

11285

11286

#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED1

11287

#define SCU_RAM_TR_SHORT_BUF_1__W 16

11288

#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF

11289

#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x0

11290

11291

#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED2

11292

#define SCU_RAM_TR_LONG_BUF_0__W 16

11293

#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF

11294

#define SCU_RAM_TR_LONG_BUF_0__PRE 0x0

11295

11296

#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED3

11297

#define SCU_RAM_TR_LONG_BUF_1__W 16

11298

#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF

11299

#define SCU_RAM_TR_LONG_BUF_1__PRE 0x0

11300

11301

#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED4

11302

#define SCU_RAM_TR_LONG_BUF_2__W 16

11303

#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF

11304

#define SCU_RAM_TR_LONG_BUF_2__PRE 0x0

11305

11306

#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED5

11307

#define SCU_RAM_TR_LONG_BUF_3__W 16

11308

#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF

11309

#define SCU_RAM_TR_LONG_BUF_3__PRE 0x0

11310

11311

#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED6

11312

#define SCU_RAM_TR_LONG_BUF_4__W 16

11313

#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF

11314

#define SCU_RAM_TR_LONG_BUF_4__PRE 0x0

11315

11316

#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED7

11317

#define SCU_RAM_TR_LONG_BUF_5__W 16

11318

#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF

11319

#define SCU_RAM_TR_LONG_BUF_5__PRE 0x0

11320

11321

#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED8

11322

#define SCU_RAM_TR_LONG_BUF_6__W 16

11323

#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF

11324

#define SCU_RAM_TR_LONG_BUF_6__PRE 0x0

11325

11326

#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED9

11327

#define SCU_RAM_TR_LONG_BUF_7__W 16

11328

#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF

11329

#define SCU_RAM_TR_LONG_BUF_7__PRE 0x0

11330

11331

#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA

11332

#define SCU_RAM_TR_LONG_BUF_8__W 16

11333

#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF

11334

#define SCU_RAM_TR_LONG_BUF_8__PRE 0x0

11335

11336

#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB

11337

#define SCU_RAM_TR_LONG_BUF_9__W 16

11338

#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF

11339

#define SCU_RAM_TR_LONG_BUF_9__PRE 0x0

11340

11341

#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC

11342

#define SCU_RAM_TR_LONG_BUF_10__W 16

11343

#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF

11344

#define SCU_RAM_TR_LONG_BUF_10__PRE 0x0

11345

11346

#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD

11347

#define SCU_RAM_TR_LONG_BUF_11__W 16

11348

#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF

11349

#define SCU_RAM_TR_LONG_BUF_11__PRE 0x0

11350

11351

#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE

11352

#define SCU_RAM_TR_LONG_BUF_12__W 16

11353

#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF

11354

#define SCU_RAM_TR_LONG_BUF_12__PRE 0x0

11355

11356

#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF

11357

#define SCU_RAM_TR_LONG_BUF_13__W 16

11358

#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF

11359

#define SCU_RAM_TR_LONG_BUF_13__PRE 0x0

11360

11361

#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE0

11362

#define SCU_RAM_TR_LONG_BUF_14__W 16

11363

#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF

11364

#define SCU_RAM_TR_LONG_BUF_14__PRE 0x0

11365

11366

#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE1

11367

#define SCU_RAM_TR_LONG_BUF_15__W 16

11368

#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF

11369

#define SCU_RAM_TR_LONG_BUF_15__PRE 0x0

11370

11371

#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE2

11372

#define SCU_RAM_TR_LONG_BUF_16__W 16

11373

#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF

11374

#define SCU_RAM_TR_LONG_BUF_16__PRE 0x0

11375

11376

#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE3

11377

#define SCU_RAM_TR_LONG_BUF_17__W 16

11378

#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF

11379

#define SCU_RAM_TR_LONG_BUF_17__PRE 0x0

11380

11381

#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE4

11382

#define SCU_RAM_TR_LONG_BUF_18__W 16

11383

#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF

11384

#define SCU_RAM_TR_LONG_BUF_18__PRE 0x0

11385

11386

#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE5

11387

#define SCU_RAM_TR_LONG_BUF_19__W 16

11388

#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF

11389

#define SCU_RAM_TR_LONG_BUF_19__PRE 0x0

11390

11391

#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE6

11392

#define SCU_RAM_TR_LONG_BUF_20__W 16

11393

#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF

11394

#define SCU_RAM_TR_LONG_BUF_20__PRE 0x0

11395

11396

#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE7

11397

#define SCU_RAM_TR_LONG_BUF_21__W 16

11398

#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF

11399

#define SCU_RAM_TR_LONG_BUF_21__PRE 0x0

11400

11401

#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE8

11402

#define SCU_RAM_TR_LONG_BUF_22__W 16

11403

#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF

11404

#define SCU_RAM_TR_LONG_BUF_22__PRE 0x0

11405

11406

#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE9

11407

#define SCU_RAM_TR_LONG_BUF_23__W 16

11408

#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF

11409

#define SCU_RAM_TR_LONG_BUF_23__PRE 0x0

11410

11411

#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA

11412

#define SCU_RAM_TR_LONG_BUF_24__W 16

11413

#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF

11414

#define SCU_RAM_TR_LONG_BUF_24__PRE 0x0

11415

11416

#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB

11417

#define SCU_RAM_TR_LONG_BUF_25__W 16

11418

#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF

11419

#define SCU_RAM_TR_LONG_BUF_25__PRE 0x0

11420

11421

#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC

11422

#define SCU_RAM_TR_LONG_BUF_26__W 16

11423

#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF

11424

#define SCU_RAM_TR_LONG_BUF_26__PRE 0x0

11425

11426

#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED

11427

#define SCU_RAM_TR_LONG_BUF_27__W 16

11428

#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF

11429

#define SCU_RAM_TR_LONG_BUF_27__PRE 0x0

11430

11431

#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE

11432

#define SCU_RAM_TR_LONG_BUF_28__W 16

11433

#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF

11434

#define SCU_RAM_TR_LONG_BUF_28__PRE 0x0

11435

11436

#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF

11437

#define SCU_RAM_TR_LONG_BUF_29__W 16

11438

#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF

11439

#define SCU_RAM_TR_LONG_BUF_29__PRE 0x0

11440

11441

#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF0

11442

#define SCU_RAM_TR_LONG_BUF_30__W 16

11443

#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF

11444

#define SCU_RAM_TR_LONG_BUF_30__PRE 0x0

11445

11446

#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF1

11447

#define SCU_RAM_TR_LONG_BUF_31__W 16

11448

#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF

11449

#define SCU_RAM_TR_LONG_BUF_31__PRE 0x0

11450

#define SCU_RAM_ATV_AMS_MAX__A 0x831EF2

11451

#define SCU_RAM_ATV_AMS_MAX__W 11

11452

#define SCU_RAM_ATV_AMS_MAX__M 0x7FF

11453

#define SCU_RAM_ATV_AMS_MAX__PRE 0x0

11454

11455

#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 0

11456

#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 11

11457

#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF

11458

#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x0

11459

11460

#define SCU_RAM_ATV_AMS_MIN__A 0x831EF3

11461

#define SCU_RAM_ATV_AMS_MIN__W 11

11462

#define SCU_RAM_ATV_AMS_MIN__M 0x7FF

11463

#define SCU_RAM_ATV_AMS_MIN__PRE 0x7FF

11464

11465

#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 0

11466

#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 11

11467

#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF

11468

#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x7FF

11469

11470

#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF4

11471

#define SCU_RAM_ATV_FIELD_CNT__W 9

11472

#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF

11473

#define SCU_RAM_ATV_FIELD_CNT__PRE 0x0

11474

11475

#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 0

11476

#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 9

11477

#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF

11478

#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x0

11479

11480

#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF5

11481

#define SCU_RAM_ATV_AAGC_FAST__W 1

11482

#define SCU_RAM_ATV_AAGC_FAST__M 0x1

11483

#define SCU_RAM_ATV_AAGC_FAST__PRE 0x0

11484

11485

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 0

11486

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 1

11487

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x1

11488

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x0

11489

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x0

11490

#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x1

11491

11492

#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF6

11493

#define SCU_RAM_ATV_AAGC_LP2__W 16

11494

#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF

11495

#define SCU_RAM_ATV_AAGC_LP2__PRE 0x0

11496

11497

#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 0

11498

#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 16

11499

#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF

11500

#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x0

11501

11502

#define SCU_RAM_ATV_BP_LVL__A 0x831EF7

11503

#define SCU_RAM_ATV_BP_LVL__W 11

11504

#define SCU_RAM_ATV_BP_LVL__M 0x7FF

11505

#define SCU_RAM_ATV_BP_LVL__PRE 0x0

11506

11507

#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 0

11508

#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 11

11509

#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF

11510

#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x0

11511

11512

#define SCU_RAM_ATV_BP_RELY__A 0x831EF8

11513

#define SCU_RAM_ATV_BP_RELY__W 8

11514

#define SCU_RAM_ATV_BP_RELY__M 0xFF

11515

#define SCU_RAM_ATV_BP_RELY__PRE 0x0

11516

11517

#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 0

11518

#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 8

11519

#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF

11520

#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x0

11521

11522

#define SCU_RAM_ATV_BP_MTA__A 0x831EF9

11523

#define SCU_RAM_ATV_BP_MTA__W 14

11524

#define SCU_RAM_ATV_BP_MTA__M 0x3FFF

11525

#define SCU_RAM_ATV_BP_MTA__PRE 0x0

11526

11527

#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 0

11528

#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 14

11529

#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF

11530

#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x0

11531

11532

#define SCU_RAM_ATV_BP_REF__A 0x831EFA

11533

#define SCU_RAM_ATV_BP_REF__W 11

11534

#define SCU_RAM_ATV_BP_REF__M 0x7FF

11535

#define SCU_RAM_ATV_BP_REF__PRE 0x0

11536

11537

#define SCU_RAM_ATV_BP_REF_BP_REF__B 0

11538

#define SCU_RAM_ATV_BP_REF_BP_REF__W 11

11539

#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF

11540

#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x0

11541

11542

#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB

11543

#define SCU_RAM_ATV_BP_REF_MIN__W 11

11544

#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF

11545

#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x64

11546

11547

#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 0

11548

#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 11

11549

#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF

11550

#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x64

11551

11552

#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC

11553

#define SCU_RAM_ATV_BP_REF_MAX__W 11

11554

#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF

11555

#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x104

11556

11557

#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 0

11558

#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 11

11559

#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF

11560

#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x104

11561

11562

#define SCU_RAM_ATV_BP_CNT__A 0x831EFD

11563

#define SCU_RAM_ATV_BP_CNT__W 8

11564

#define SCU_RAM_ATV_BP_CNT__M 0xFF

11565

#define SCU_RAM_ATV_BP_CNT__PRE 0x0

11566

11567

#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 0

11568

#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 8

11569

#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF

11570

#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x0

11571

11572

#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE

11573

#define SCU_RAM_ATV_BP_XD_CNT__W 12

11574

#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF

11575

#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x0

11576

11577

#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 0

11578

#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 12

11579

#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF

11580

#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x0

11581

11582

#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF

11583

#define SCU_RAM_ATV_PAGC_KI_MIN__W 12

11584

#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF

11585

#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x445

11586

11587

#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 0

11588

#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 12

11589

#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF

11590

#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x445

11591

11592

#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F00

11593

#define SCU_RAM_ATV_BPC_KI_MIN__W 12

11594

#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF

11595

#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x223

11596

11597

#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 0

11598

#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 12

11599

#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF

11600

#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x223

11601

11602

11603

#define SCU_RAM_OFDM_AGC_POW_TGT__A 0x831F01

11604

#define SCU_RAM_OFDM_AGC_POW_TGT__W 15

11605

#define SCU_RAM_OFDM_AGC_POW_TGT__M 0x7FFF

11606

#define SCU_RAM_OFDM_AGC_POW_TGT__PRE 0x5848

11607

11608

#define SCU_RAM_OFDM_RSV_01__A 0x831F02

11609

#define SCU_RAM_OFDM_RSV_01__W 16

11610

#define SCU_RAM_OFDM_RSV_01__M 0xFFFF

11611

#define SCU_RAM_OFDM_RSV_01__PRE 0x0

11612

11613

#define SCU_RAM_OFDM_RSV_02__A 0x831F03

11614

#define SCU_RAM_OFDM_RSV_02__W 16

11615

#define SCU_RAM_OFDM_RSV_02__M 0xFFFF

11616

#define SCU_RAM_OFDM_RSV_02__PRE 0x0

11617

#define SCU_RAM_FEC_PRE_RS_BER__A 0x831F04

11618

#define SCU_RAM_FEC_PRE_RS_BER__W 16

11619

#define SCU_RAM_FEC_PRE_RS_BER__M 0xFFFF

11620

#define SCU_RAM_FEC_PRE_RS_BER__PRE 0x0

11621

11622

#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__B 0

11623

#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__W 16

11624

#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__M 0xFFFF

11625

#define SCU_RAM_FEC_PRE_RS_BER_SCU_RAM_GENERAL__PRE 0x0

11626

11627

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05

11628

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__W 16

11629

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__M 0xFFFF

11630

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__PRE 0x0

11631

11632

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__B 0

11633

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__W 16

11634

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__M 0xFFFF

11635

#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH_SCU_RAM_GENERAL__PRE 0x0

11636

11637

#define SCU_RAM_ATV_VSYNC_LINE_CNT__A 0x831F06

11638

#define SCU_RAM_ATV_VSYNC_LINE_CNT__W 16

11639

#define SCU_RAM_ATV_VSYNC_LINE_CNT__M 0xFFFF

11640

#define SCU_RAM_ATV_VSYNC_LINE_CNT__PRE 0x0

11641

11642

#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__B 0

11643

#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__W 16

11644

#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__M 0xFFFF

11645

#define SCU_RAM_ATV_VSYNC_LINE_CNT_SCU_RAM_ATV__PRE 0x0

11646

11647

#define SCU_RAM_ATV_VSYNC_PERIOD__A 0x831F07

11648

#define SCU_RAM_ATV_VSYNC_PERIOD__W 16

11649

#define SCU_RAM_ATV_VSYNC_PERIOD__M 0xFFFF

11650

#define SCU_RAM_ATV_VSYNC_PERIOD__PRE 0x0

11651

11652

#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__B 0

11653

#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__W 16

11654

#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__M 0xFFFF

11655

#define SCU_RAM_ATV_VSYNC_PERIOD_SCU_RAM_ATV__PRE 0x0

11656

11657

#define SCU_RAM_FREE_7944__A 0x831F08

11658

#define SCU_RAM_FREE_7944__W 16

11659

#define SCU_RAM_FREE_7944__M 0xFFFF

11660

#define SCU_RAM_FREE_7944__PRE 0x0

11661

11662

#define SCU_RAM_FREE_7944_SCU_RAM_FREE__B 0

11663

#define SCU_RAM_FREE_7944_SCU_RAM_FREE__W 16

11664

#define SCU_RAM_FREE_7944_SCU_RAM_FREE__M 0xFFFF

11665

#define SCU_RAM_FREE_7944_SCU_RAM_FREE__PRE 0x0

11666

11667

#define SCU_RAM_FREE_7945__A 0x831F09

11668

#define SCU_RAM_FREE_7945__W 16

11669

#define SCU_RAM_FREE_7945__M 0xFFFF

11670

#define SCU_RAM_FREE_7945__PRE 0x0

11671

11672

#define SCU_RAM_FREE_7945_SCU_RAM_FREE__B 0

11673

#define SCU_RAM_FREE_7945_SCU_RAM_FREE__W 16

11674

#define SCU_RAM_FREE_7945_SCU_RAM_FREE__M 0xFFFF

11675

#define SCU_RAM_FREE_7945_SCU_RAM_FREE__PRE 0x0

11676

11677

#define SCU_RAM_FREE_7946__A 0x831F0A

11678

#define SCU_RAM_FREE_7946__W 16

11679

#define SCU_RAM_FREE_7946__M 0xFFFF

11680

#define SCU_RAM_FREE_7946__PRE 0x0

11681

11682

#define SCU_RAM_FREE_7946_SCU_RAM_FREE__B 0

11683

#define SCU_RAM_FREE_7946_SCU_RAM_FREE__W 16

11684

#define SCU_RAM_FREE_7946_SCU_RAM_FREE__M 0xFFFF

11685

#define SCU_RAM_FREE_7946_SCU_RAM_FREE__PRE 0x0

11686

11687

#define SCU_RAM_FREE_7947__A 0x831F0B

11688

#define SCU_RAM_FREE_7947__W 16

11689

#define SCU_RAM_FREE_7947__M 0xFFFF

11690

#define SCU_RAM_FREE_7947__PRE 0x0

11691

11692

#define SCU_RAM_FREE_7947_SCU_RAM_FREE__B 0

11693

#define SCU_RAM_FREE_7947_SCU_RAM_FREE__W 16

11694

#define SCU_RAM_FREE_7947_SCU_RAM_FREE__M 0xFFFF

11695

#define SCU_RAM_FREE_7947_SCU_RAM_FREE__PRE 0x0

11696

11697

#define SCU_RAM_FREE_7948__A 0x831F0C

11698

#define SCU_RAM_FREE_7948__W 16

11699

#define SCU_RAM_FREE_7948__M 0xFFFF

11700

#define SCU_RAM_FREE_7948__PRE 0x0

11701

11702

#define SCU_RAM_FREE_7948_SCU_RAM_FREE__B 0

11703

#define SCU_RAM_FREE_7948_SCU_RAM_FREE__W 16

11704

#define SCU_RAM_FREE_7948_SCU_RAM_FREE__M 0xFFFF

11705

#define SCU_RAM_FREE_7948_SCU_RAM_FREE__PRE 0x0

11706

11707

#define SCU_RAM_FREE_7949__A 0x831F0D

11708

#define SCU_RAM_FREE_7949__W 16

11709

#define SCU_RAM_FREE_7949__M 0xFFFF

11710

#define SCU_RAM_FREE_7949__PRE 0x0

11711

11712

#define SCU_RAM_FREE_7949_SCU_RAM_FREE__B 0

11713

#define SCU_RAM_FREE_7949_SCU_RAM_FREE__W 16

11714

#define SCU_RAM_FREE_7949_SCU_RAM_FREE__M 0xFFFF

11715

#define SCU_RAM_FREE_7949_SCU_RAM_FREE__PRE 0x0

11716

11717

#define SCU_RAM_FREE_7950__A 0x831F0E

11718

#define SCU_RAM_FREE_7950__W 16

11719

#define SCU_RAM_FREE_7950__M 0xFFFF

11720

#define SCU_RAM_FREE_7950__PRE 0x0

11721

11722

#define SCU_RAM_FREE_7950_SCU_RAM_FREE__B 0

11723

#define SCU_RAM_FREE_7950_SCU_RAM_FREE__W 16

11724

#define SCU_RAM_FREE_7950_SCU_RAM_FREE__M 0xFFFF

11725

#define SCU_RAM_FREE_7950_SCU_RAM_FREE__PRE 0x0

11726

11727

#define SCU_RAM_FREE_7951__A 0x831F0F

11728

#define SCU_RAM_FREE_7951__W 16

11729

#define SCU_RAM_FREE_7951__M 0xFFFF

11730

#define SCU_RAM_FREE_7951__PRE 0x0

11731

11732

#define SCU_RAM_FREE_7951_SCU_RAM_FREE__B 0

11733

#define SCU_RAM_FREE_7951_SCU_RAM_FREE__W 16

11734

#define SCU_RAM_FREE_7951_SCU_RAM_FREE__M 0xFFFF

11735

#define SCU_RAM_FREE_7951_SCU_RAM_FREE__PRE 0x0

11736

11737

#define SCU_RAM_FREE_7952__A 0x831F10

11738

#define SCU_RAM_FREE_7952__W 16

11739

#define SCU_RAM_FREE_7952__M 0xFFFF

11740

#define SCU_RAM_FREE_7952__PRE 0x0

11741

11742

#define SCU_RAM_FREE_7952_SCU_RAM_FREE__B 0

11743

#define SCU_RAM_FREE_7952_SCU_RAM_FREE__W 16

11744

#define SCU_RAM_FREE_7952_SCU_RAM_FREE__M 0xFFFF

11745

#define SCU_RAM_FREE_7952_SCU_RAM_FREE__PRE 0x0

11746

11747

#define SCU_RAM_FREE_7953__A 0x831F11

11748

#define SCU_RAM_FREE_7953__W 16

11749

#define SCU_RAM_FREE_7953__M 0xFFFF

11750

#define SCU_RAM_FREE_7953__PRE 0x0

11751

11752

#define SCU_RAM_FREE_7953_SCU_RAM_FREE__B 0

11753

#define SCU_RAM_FREE_7953_SCU_RAM_FREE__W 16

11754

#define SCU_RAM_FREE_7953_SCU_RAM_FREE__M 0xFFFF

11755

#define SCU_RAM_FREE_7953_SCU_RAM_FREE__PRE 0x0

11756

11757

#define SCU_RAM_FREE_7954__A 0x831F12

11758

#define SCU_RAM_FREE_7954__W 16

11759

#define SCU_RAM_FREE_7954__M 0xFFFF

11760

#define SCU_RAM_FREE_7954__PRE 0x0

11761

11762

#define SCU_RAM_FREE_7954_SCU_RAM_FREE__B 0

11763

#define SCU_RAM_FREE_7954_SCU_RAM_FREE__W 16

11764

#define SCU_RAM_FREE_7954_SCU_RAM_FREE__M 0xFFFF

11765

#define SCU_RAM_FREE_7954_SCU_RAM_FREE__PRE 0x0

11766

11767

#define SCU_RAM_FREE_7955__A 0x831F13

11768

#define SCU_RAM_FREE_7955__W 16

11769

#define SCU_RAM_FREE_7955__M 0xFFFF

11770

#define SCU_RAM_FREE_7955__PRE 0x0

11771

11772

#define SCU_RAM_FREE_7955_SCU_RAM_FREE__B 0

11773

#define SCU_RAM_FREE_7955_SCU_RAM_FREE__W 16

11774

#define SCU_RAM_FREE_7955_SCU_RAM_FREE__M 0xFFFF

11775

#define SCU_RAM_FREE_7955_SCU_RAM_FREE__PRE 0x0

11776

11777

11778

#define SCU_RAM_ADC_COMP_CONTROL__A 0x831F14

11779

#define SCU_RAM_ADC_COMP_CONTROL__W 3

11780

#define SCU_RAM_ADC_COMP_CONTROL__M 0x7

11781

#define SCU_RAM_ADC_COMP_CONTROL__PRE 0x0

11782

#define SCU_RAM_ADC_COMP_CONTROL_CONFIG 0x0

11783

#define SCU_RAM_ADC_COMP_CONTROL_DO_AGC 0x1

11784

#define SCU_RAM_ADC_COMP_CONTROL_SET_ADJUST 0x2

11785

#define SCU_RAM_ADC_COMP_CONTROL_SET_ACTIVE 0x3

11786

11787

11788

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15

11789

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 16

11790

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF

11791

#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x32

11792

11793

#define SCU_RAM_AGC_KI_CYCCNT__A 0x831F16

11794

#define SCU_RAM_AGC_KI_CYCCNT__W 16

11795

#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF

11796

#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x0

11797

11798

#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17

11799

#define SCU_RAM_AGC_KI_CYCLEN__W 16

11800

#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF

11801

#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x1F4

11802

11803

#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18

11804

#define SCU_RAM_AGC_SNS_CYCLEN__W 16

11805

#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF

11806

#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x1F4

11807

11808

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19

11809

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 16

11810

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF

11811

#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x3FF

11812

11813

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A

11814

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 16

11815

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF

11816

#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0xFC01

11817

11818

#define SCU_RAM_AGC_RF_MAX__A 0x831F1B

11819

#define SCU_RAM_AGC_RF_MAX__W 15

11820

#define SCU_RAM_AGC_RF_MAX__M 0x7FFF

11821

#define SCU_RAM_AGC_RF_MAX__PRE 0x7FFF

11822

#define SCU_RAM_FREE_7964__A 0x831F1C

11823

#define SCU_RAM_FREE_7964__W 16

11824

#define SCU_RAM_FREE_7964__M 0xFFFF

11825

#define SCU_RAM_FREE_7964__PRE 0x0

11826

11827

#define SCU_RAM_FREE_7964_SCU_RAM_FREE__B 0

11828

#define SCU_RAM_FREE_7964_SCU_RAM_FREE__W 16

11829

#define SCU_RAM_FREE_7964_SCU_RAM_FREE__M 0xFFFF

11830

#define SCU_RAM_FREE_7964_SCU_RAM_FREE__PRE 0x0

11831

11832

#define SCU_RAM_FREE_7965__A 0x831F1D

11833

#define SCU_RAM_FREE_7965__W 16

11834

#define SCU_RAM_FREE_7965__M 0xFFFF

11835

#define SCU_RAM_FREE_7965__PRE 0x0

11836

11837

#define SCU_RAM_FREE_7965_SCU_RAM_FREE__B 0

11838

#define SCU_RAM_FREE_7965_SCU_RAM_FREE__W 16

11839

#define SCU_RAM_FREE_7965_SCU_RAM_FREE__M 0xFFFF

11840

#define SCU_RAM_FREE_7965_SCU_RAM_FREE__PRE 0x0

11841

11842

#define SCU_RAM_FREE_7966__A 0x831F1E

11843

#define SCU_RAM_FREE_7966__W 16

11844

#define SCU_RAM_FREE_7966__M 0xFFFF

11845

#define SCU_RAM_FREE_7966__PRE 0x0

11846

11847

#define SCU_RAM_FREE_7966_SCU_RAM_FREE__B 0

11848

#define SCU_RAM_FREE_7966_SCU_RAM_FREE__W 16

11849

#define SCU_RAM_FREE_7966_SCU_RAM_FREE__M 0xFFFF

11850

#define SCU_RAM_FREE_7966_SCU_RAM_FREE__PRE 0x0

11851

11852

#define SCU_RAM_FREE_7967__A 0x831F1F

11853

#define SCU_RAM_FREE_7967__W 16

11854

#define SCU_RAM_FREE_7967__M 0xFFFF

11855

#define SCU_RAM_FREE_7967__PRE 0x0

11856

11857

#define SCU_RAM_FREE_7967_SCU_RAM_FREE__B 0

11858

#define SCU_RAM_FREE_7967_SCU_RAM_FREE__W 16

11859

#define SCU_RAM_FREE_7967_SCU_RAM_FREE__M 0xFFFF

11860

#define SCU_RAM_FREE_7967_SCU_RAM_FREE__PRE 0x0

11861

11862

#define SCU_RAM_QAM_PARAM_MIRRORING__A 0x831F20

11863

#define SCU_RAM_QAM_PARAM_MIRRORING__W 8

11864

#define SCU_RAM_QAM_PARAM_MIRRORING__M 0xFF

11865

#define SCU_RAM_QAM_PARAM_MIRRORING__PRE 0x0

11866

11867

#define SCU_RAM_QAM_PARAM_MIRRORING_SET__B 0

11868

#define SCU_RAM_QAM_PARAM_MIRRORING_SET__W 1

11869

#define SCU_RAM_QAM_PARAM_MIRRORING_SET__M 0x1

11870

#define SCU_RAM_QAM_PARAM_MIRRORING_SET__PRE 0x0

11871

#define SCU_RAM_QAM_PARAM_MIRRORING_SET_NORMAL 0x0

11872

#define SCU_RAM_QAM_PARAM_MIRRORING_SET_MIRRORED 0x1

11873

11874

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__B 1

11875

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__W 1

11876

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__M 0x2

11877

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO__PRE 0x0

11878

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_OFF 0x0

11879

#define SCU_RAM_QAM_PARAM_MIRRORING_AUTO_ON 0x2

11880

11881

#define SCU_RAM_QAM_PARAM_MIRRORING_DET__B 2

11882

#define SCU_RAM_QAM_PARAM_MIRRORING_DET__W 1

11883

#define SCU_RAM_QAM_PARAM_MIRRORING_DET__M 0x4

11884

#define SCU_RAM_QAM_PARAM_MIRRORING_DET__PRE 0x0

11885

#define SCU_RAM_QAM_PARAM_MIRRORING_DET_NORMAL 0x0

11886

#define SCU_RAM_QAM_PARAM_MIRRORING_DET_MIRRORED 0x4

11887

11888

#define SCU_RAM_QAM_PARAM_OPTIONS__A 0x831F21

11889

#define SCU_RAM_QAM_PARAM_OPTIONS__W 8

11890

#define SCU_RAM_QAM_PARAM_OPTIONS__M 0xFF

11891

#define SCU_RAM_QAM_PARAM_OPTIONS__PRE 0x0

11892

11893

#define SCU_RAM_QAM_PARAM_OPTIONS_SET__B 0

11894

#define SCU_RAM_QAM_PARAM_OPTIONS_SET__W 1

11895

#define SCU_RAM_QAM_PARAM_OPTIONS_SET__M 0x1

11896

#define SCU_RAM_QAM_PARAM_OPTIONS_SET__PRE 0x0

11897

#define SCU_RAM_QAM_PARAM_OPTIONS_SET_NORMAL 0x0

11898

#define SCU_RAM_QAM_PARAM_OPTIONS_SET_MIRRORED 0x1

11899

11900

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__B 1

11901

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__W 1

11902

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__M 0x2

11903

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO__PRE 0x0

11904

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_OFF 0x0

11905

#define SCU_RAM_QAM_PARAM_OPTIONS_AUTO_ON 0x2

11906

11907

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__B 4

11908

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__W 1

11909

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__M 0x10

11910

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE__PRE 0x0

11911

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_EXTENDED 0x0

11912

#define SCU_RAM_QAM_PARAM_OPTIONS_RANGE_NORMAL 0x10

11913

11914

#define SCU_RAM_FREE_7970__A 0x831F22

11915

#define SCU_RAM_FREE_7970__W 16

11916

#define SCU_RAM_FREE_7970__M 0xFFFF

11917

#define SCU_RAM_FREE_7970__PRE 0x0

11918

11919

#define SCU_RAM_FREE_7970_SCU_RAM_FREE__B 0

11920

#define SCU_RAM_FREE_7970_SCU_RAM_FREE__W 16

11921

#define SCU_RAM_FREE_7970_SCU_RAM_FREE__M 0xFFFF

11922

#define SCU_RAM_FREE_7970_SCU_RAM_FREE__PRE 0x0

11923

11924

#define SCU_RAM_FREE_7971__A 0x831F23

11925

#define SCU_RAM_FREE_7971__W 16

11926

#define SCU_RAM_FREE_7971__M 0xFFFF

11927

#define SCU_RAM_FREE_7971__PRE 0x0

11928

11929

#define SCU_RAM_FREE_7971_SCU_RAM_FREE__B 0

11930

#define SCU_RAM_FREE_7971_SCU_RAM_FREE__W 16

11931

#define SCU_RAM_FREE_7971_SCU_RAM_FREE__M 0xFFFF

11932

#define SCU_RAM_FREE_7971_SCU_RAM_FREE__PRE 0x0

11933

11934

#define SCU_RAM_AGC_CONFIG__A 0x831F24

11935

#define SCU_RAM_AGC_CONFIG__W 16

11936

#define SCU_RAM_AGC_CONFIG__M 0xFFFF

11937

#define SCU_RAM_AGC_CONFIG__PRE 0x0

11938

11939

#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__B 0

11940

#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__W 1

11941

#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1

11942

#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__PRE 0x0

11943

11944

#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__B 1

11945

#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__W 1

11946

#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2

11947

#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__PRE 0x0

11948

11949

#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__B 2

11950

#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__W 1

11951

#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__M 0x4

11952

#define SCU_RAM_AGC_CONFIG_DISABLE_INNER_AGC__PRE 0x0

11953

11954

#define SCU_RAM_AGC_CONFIG_INV_IF_POL__B 8

11955

#define SCU_RAM_AGC_CONFIG_INV_IF_POL__W 1

11956

#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100

11957

#define SCU_RAM_AGC_CONFIG_INV_IF_POL__PRE 0x0

11958

11959

#define SCU_RAM_AGC_CONFIG_INV_RF_POL__B 9

11960

#define SCU_RAM_AGC_CONFIG_INV_RF_POL__W 1

11961

#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200

11962

#define SCU_RAM_AGC_CONFIG_INV_RF_POL__PRE 0x0

11963

11964

#define SCU_RAM_AGC_KI__A 0x831F25

11965

#define SCU_RAM_AGC_KI__W 15

11966

#define SCU_RAM_AGC_KI__M 0x7FFF

11967

#define SCU_RAM_AGC_KI__PRE 0x22A

11968

11969

#define SCU_RAM_AGC_KI_DGAIN__B 0

11970

#define SCU_RAM_AGC_KI_DGAIN__W 4

11971

#define SCU_RAM_AGC_KI_DGAIN__M 0xF

11972

#define SCU_RAM_AGC_KI_DGAIN__PRE 0xA

11973

11974

#define SCU_RAM_AGC_KI_RF__B 4

11975

#define SCU_RAM_AGC_KI_RF__W 4

11976

#define SCU_RAM_AGC_KI_RF__M 0xF0

11977

#define SCU_RAM_AGC_KI_RF__PRE 0x20

11978

11979

#define SCU_RAM_AGC_KI_IF__B 8

11980

#define SCU_RAM_AGC_KI_IF__W 4

11981

#define SCU_RAM_AGC_KI_IF__M 0xF00

11982

#define SCU_RAM_AGC_KI_IF__PRE 0x200

11983

11984

#define SCU_RAM_AGC_KI_RED__A 0x831F26

11985

#define SCU_RAM_AGC_KI_RED__W 6

11986

#define SCU_RAM_AGC_KI_RED__M 0x3F

11987

#define SCU_RAM_AGC_KI_RED__PRE 0x0

11988

11989

#define SCU_RAM_AGC_KI_RED_INNER_RED__B 0

11990

#define SCU_RAM_AGC_KI_RED_INNER_RED__W 2

11991

#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x3

11992

#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x0

11993

11994

#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2

11995

#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 2

11996

#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC

11997

#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x0

11998

11999

#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4

12000

#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 2

12001

#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30

12002

#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x0

12003

12004

12005

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27

12006

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 16

12007

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF

12008

#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x0

12009

12010

#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28

12011

#define SCU_RAM_AGC_KI_MINGAIN__W 16

12012

#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF

12013

#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x8000

12014

12015

#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29

12016

#define SCU_RAM_AGC_KI_MAXGAIN__W 16

12017

#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF

12018

#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x0

12019

12020

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A

12021

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 16

12022

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF

12023

#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x0

12024

#define SCU_RAM_AGC_KI_MIN__A 0x831F2B

12025

#define SCU_RAM_AGC_KI_MIN__W 12

12026

#define SCU_RAM_AGC_KI_MIN__M 0xFFF

12027

#define SCU_RAM_AGC_KI_MIN__PRE 0x111

12028

12029

#define SCU_RAM_AGC_KI_MIN_DGAIN__B 0

12030

#define SCU_RAM_AGC_KI_MIN_DGAIN__W 4

12031

#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF

12032

#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x1

12033

12034

#define SCU_RAM_AGC_KI_MIN_RF__B 4

12035

#define SCU_RAM_AGC_KI_MIN_RF__W 4

12036

#define SCU_RAM_AGC_KI_MIN_RF__M 0xF0

12037

#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x10

12038

12039

#define SCU_RAM_AGC_KI_MIN_IF__B 8

12040

#define SCU_RAM_AGC_KI_MIN_IF__W 4

12041

#define SCU_RAM_AGC_KI_MIN_IF__M 0xF00

12042

#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x100

12043

12044

#define SCU_RAM_AGC_KI_MAX__A 0x831F2C

12045

#define SCU_RAM_AGC_KI_MAX__W 12

12046

#define SCU_RAM_AGC_KI_MAX__M 0xFFF

12047

#define SCU_RAM_AGC_KI_MAX__PRE 0xFFF

12048

12049

#define SCU_RAM_AGC_KI_MAX_DGAIN__B 0

12050

#define SCU_RAM_AGC_KI_MAX_DGAIN__W 4

12051

#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF

12052

#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0xF

12053

12054

#define SCU_RAM_AGC_KI_MAX_RF__B 4

12055

#define SCU_RAM_AGC_KI_MAX_RF__W 4

12056

#define SCU_RAM_AGC_KI_MAX_RF__M 0xF0

12057

#define SCU_RAM_AGC_KI_MAX_RF__PRE 0xF0

12058

12059

#define SCU_RAM_AGC_KI_MAX_IF__B 8

12060

#define SCU_RAM_AGC_KI_MAX_IF__W 4

12061

#define SCU_RAM_AGC_KI_MAX_IF__M 0xF00

12062

#define SCU_RAM_AGC_KI_MAX_IF__PRE 0xF00

12063

12064

12065

#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D

12066

#define SCU_RAM_AGC_CLP_SUM__W 16

12067

#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF

12068

#define SCU_RAM_AGC_CLP_SUM__PRE 0x0

12069

12070

#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E

12071

#define SCU_RAM_AGC_CLP_SUM_MIN__W 16

12072

#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF

12073

#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x8

12074

12075

#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F

12076

#define SCU_RAM_AGC_CLP_SUM_MAX__W 16

12077

#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF

12078

#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x400

12079

12080

#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30

12081

#define SCU_RAM_AGC_CLP_CYCLEN__W 16

12082

#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF

12083

#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x1F4

12084

12085

#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31

12086

#define SCU_RAM_AGC_CLP_CYCCNT__W 16

12087

#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF

12088

#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x0

12089

12090

#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32

12091

#define SCU_RAM_AGC_CLP_DIR_TO__W 8

12092

#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF

12093

#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0xFC

12094

12095

#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33

12096

#define SCU_RAM_AGC_CLP_DIR_WD__W 8

12097

#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF

12098

#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x0

12099

12100

#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34

12101

#define SCU_RAM_AGC_CLP_DIR_STP__W 16

12102

#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF

12103

#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x1

12104

12105

#define SCU_RAM_AGC_SNS_SUM__A 0x831F35

12106

#define SCU_RAM_AGC_SNS_SUM__W 16

12107

#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF

12108

#define SCU_RAM_AGC_SNS_SUM__PRE 0x0

12109

12110

#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36

12111

#define SCU_RAM_AGC_SNS_SUM_MIN__W 16

12112

#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF

12113

#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x8

12114

12115

#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37

12116

#define SCU_RAM_AGC_SNS_SUM_MAX__W 16

12117

#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF

12118

#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x400

12119

12120

#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38

12121

#define SCU_RAM_AGC_SNS_CYCCNT__W 16

12122

#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF

12123

#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x0

12124

12125

#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39

12126

#define SCU_RAM_AGC_SNS_DIR_TO__W 8

12127

#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF

12128

#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0xFC

12129

12130

#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A

12131

#define SCU_RAM_AGC_SNS_DIR_WD__W 8

12132

#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF

12133

#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x0

12134

12135

#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B

12136

#define SCU_RAM_AGC_SNS_DIR_STP__W 16

12137

#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF

12138

#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x1

12139

12140

#define SCU_RAM_AGC_INGAIN__A 0x831F3C

12141

#define SCU_RAM_AGC_INGAIN__W 16

12142

#define SCU_RAM_AGC_INGAIN__M 0xFFFF

12143

#define SCU_RAM_AGC_INGAIN__PRE 0x708

12144

12145

#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D

12146

#define SCU_RAM_AGC_INGAIN_TGT__W 15

12147

#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF

12148

#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x708

12149

12150

#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E

12151

#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 15

12152

#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF

12153

#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x708

12154

12155

#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F

12156

#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 15

12157

#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF

12158

#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x3FFF

12159

12160

#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40

12161

#define SCU_RAM_AGC_IF_IACCU_HI__W 16

12162

#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF

12163

#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x0

12164

12165

#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41

12166

#define SCU_RAM_AGC_IF_IACCU_LO__W 8

12167

#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF

12168

#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x0

12169

12170

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42

12171

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 15

12172

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF

12173

#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x2008

12174

12175

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43

12176

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 15

12177

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF

12178

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x0

12179

12180

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44

12181

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 15

12182

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF

12183

#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x251C

12184

12185

#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45

12186

#define SCU_RAM_AGC_RF_IACCU_HI__W 16

12187

#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF

12188

#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x0

12189

12190

#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46

12191

#define SCU_RAM_AGC_RF_IACCU_LO__W 8

12192

#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF

12193

#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x0

12194

12195

#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47

12196

#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 16

12197

#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF

12198

#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x0

12199

#define SCU_RAM_ATV_STANDARD__A 0x831F48

12200

#define SCU_RAM_ATV_STANDARD__W 12

12201

#define SCU_RAM_ATV_STANDARD__M 0xFFF

12202

#define SCU_RAM_ATV_STANDARD__PRE 0x2

12203

12204

#define SCU_RAM_ATV_STANDARD_STANDARD__B 0

12205

#define SCU_RAM_ATV_STANDARD_STANDARD__W 12

12206

#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF

12207

#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x2

12208

#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x2

12209

#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x103

12210

#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x3

12211

#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x4

12212

#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x9

12213

#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x109

12214

#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA

12215

#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x40

12216

12217

#define SCU_RAM_ATV_DETECT__A 0x831F49

12218

#define SCU_RAM_ATV_DETECT__W 1

12219

#define SCU_RAM_ATV_DETECT__M 0x1

12220

#define SCU_RAM_ATV_DETECT__PRE 0x0

12221

12222

#define SCU_RAM_ATV_DETECT_DETECT__B 0

12223

#define SCU_RAM_ATV_DETECT_DETECT__W 1

12224

#define SCU_RAM_ATV_DETECT_DETECT__M 0x1

12225

#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x0

12226

#define SCU_RAM_ATV_DETECT_DETECT_FALSE 0x0

12227

#define SCU_RAM_ATV_DETECT_DETECT_TRUE 0x1

12228

12229

#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A

12230

#define SCU_RAM_ATV_DETECT_TH__W 8

12231

#define SCU_RAM_ATV_DETECT_TH__M 0xFF

12232

#define SCU_RAM_ATV_DETECT_TH__PRE 0x7F

12233

12234

#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 0

12235

#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 8

12236

#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF

12237

#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x7F

12238

12239

#define SCU_RAM_ATV_LOCK__A 0x831F4B

12240

#define SCU_RAM_ATV_LOCK__W 2

12241

#define SCU_RAM_ATV_LOCK__M 0x3

12242

#define SCU_RAM_ATV_LOCK__PRE 0x0

12243

12244

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 0

12245

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 1

12246

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x1

12247

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x0

12248

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x0

12249

#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x1

12250

12251

#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 1

12252

#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 1

12253

#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x2

12254

#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x0

12255

#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x0

12256

#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x2

12257

12258

#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C

12259

#define SCU_RAM_ATV_CR_LOCK__W 11

12260

#define SCU_RAM_ATV_CR_LOCK__M 0x7FF

12261

#define SCU_RAM_ATV_CR_LOCK__PRE 0x0

12262

12263

#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 0

12264

#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 11

12265

#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF

12266

#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x0

12267

12268

#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D

12269

#define SCU_RAM_ATV_AGC_MODE__W 8

12270

#define SCU_RAM_ATV_AGC_MODE__M 0xFF

12271

#define SCU_RAM_ATV_AGC_MODE__PRE 0x50

12272

12273

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 2

12274

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 1

12275

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x4

12276

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x0

12277

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x0

12278

#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x4

12279

12280

#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 3

12281

#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 1

12282

#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x8

12283

#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x0

12284

#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x0

12285

#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x8

12286

12287

#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 4

12288

#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 2

12289

#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x30

12290

#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x10

12291

#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x0

12292

#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x10

12293

#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x20

12294

12295

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 6

12296

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 1

12297

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x40

12298

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x40

12299

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x0

12300

#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x40

12301

12302

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 7

12303

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 1

12304

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x80

12305

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x0

12306

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x0

12307

#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x80

12308

12309

12310

#define SCU_RAM_ATV_RSV_01__A 0x831F4E

12311

#define SCU_RAM_ATV_RSV_01__W 16

12312

#define SCU_RAM_ATV_RSV_01__M 0xFFFF

12313

#define SCU_RAM_ATV_RSV_01__PRE 0x0

12314

12315

#define SCU_RAM_ATV_RSV_02__A 0x831F4F

12316

#define SCU_RAM_ATV_RSV_02__W 16

12317

#define SCU_RAM_ATV_RSV_02__M 0xFFFF

12318

#define SCU_RAM_ATV_RSV_02__PRE 0x0

12319

12320

#define SCU_RAM_ATV_RSV_03__A 0x831F50

12321

#define SCU_RAM_ATV_RSV_03__W 16

12322

#define SCU_RAM_ATV_RSV_03__M 0xFFFF

12323

#define SCU_RAM_ATV_RSV_03__PRE 0x0

12324

12325

#define SCU_RAM_ATV_RSV_04__A 0x831F51

12326

#define SCU_RAM_ATV_RSV_04__W 16

12327

#define SCU_RAM_ATV_RSV_04__M 0xFFFF

12328

#define SCU_RAM_ATV_RSV_04__PRE 0x0

12329

#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F52

12330

#define SCU_RAM_ATV_FAGC_TH_RED__W 8

12331

#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF

12332

#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0xA

12333

12334

#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 0

12335

#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 8

12336

#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF

12337

#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0xA

12338

12339

#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F53

12340

#define SCU_RAM_ATV_AMS_MAX_REF__W 11

12341

#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF

12342

#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x2BC

12343

12344

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 0

12345

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 11

12346

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF

12347

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x2BC

12348

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC

12349

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D0

12350

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x314

12351

#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A

12352

12353

#define SCU_RAM_ATV_ACT_AMX__A 0x831F54

12354

#define SCU_RAM_ATV_ACT_AMX__W 11

12355

#define SCU_RAM_ATV_ACT_AMX__M 0x7FF

12356

#define SCU_RAM_ATV_ACT_AMX__PRE 0x0

12357

12358

#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 0

12359

#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 11

12360

#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF

12361

#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x0

12362

12363

#define SCU_RAM_ATV_ACT_AMI__A 0x831F55

12364

#define SCU_RAM_ATV_ACT_AMI__W 11

12365

#define SCU_RAM_ATV_ACT_AMI__M 0x7FF

12366

#define SCU_RAM_ATV_ACT_AMI__PRE 0x0

12367

12368

#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 0

12369

#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 11

12370

#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF

12371

#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x0

12372

12373

#define SCU_RAM_ATV_BPC_REF_PERIOD__A 0x831F56

12374

#define SCU_RAM_ATV_BPC_REF_PERIOD__W 16

12375

#define SCU_RAM_ATV_BPC_REF_PERIOD__M 0xFFFF

12376

#define SCU_RAM_ATV_BPC_REF_PERIOD__PRE 0x0

12377

12378

#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__B 0

12379

#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__W 16

12380

#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__M 0xFFFF

12381

#define SCU_RAM_ATV_BPC_REF_PERIOD_BPC_REF_PERIOD__PRE 0x0

12382

12383

#define SCU_RAM_ATV_BPC_REF_CNT__A 0x831F57

12384

#define SCU_RAM_ATV_BPC_REF_CNT__W 16

12385

#define SCU_RAM_ATV_BPC_REF_CNT__M 0xFFFF

12386

#define SCU_RAM_ATV_BPC_REF_CNT__PRE 0x0

12387

12388

#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__B 0

12389

#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__W 16

12390

#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__M 0xFFFF

12391

#define SCU_RAM_ATV_BPC_REF_CNT_BPC_REF_CNT__PRE 0x0

12392

12393

12394

#define SCU_RAM_ATV_RSV_07__A 0x831F58

12395

#define SCU_RAM_ATV_RSV_07__W 16

12396

#define SCU_RAM_ATV_RSV_07__M 0xFFFF

12397

#define SCU_RAM_ATV_RSV_07__PRE 0x0

12398

12399

#define SCU_RAM_ATV_RSV_08__A 0x831F59

12400

#define SCU_RAM_ATV_RSV_08__W 16

12401

#define SCU_RAM_ATV_RSV_08__M 0xFFFF

12402

#define SCU_RAM_ATV_RSV_08__PRE 0x0

12403

12404

#define SCU_RAM_ATV_RSV_09__A 0x831F5A

12405

#define SCU_RAM_ATV_RSV_09__W 16

12406

#define SCU_RAM_ATV_RSV_09__M 0xFFFF

12407

#define SCU_RAM_ATV_RSV_09__PRE 0x0

12408

12409

#define SCU_RAM_ATV_RSV_10__A 0x831F5B

12410

#define SCU_RAM_ATV_RSV_10__W 16

12411

#define SCU_RAM_ATV_RSV_10__M 0xFFFF

12412

#define SCU_RAM_ATV_RSV_10__PRE 0x0

12413

12414

#define SCU_RAM_ATV_RSV_11__A 0x831F5C

12415

#define SCU_RAM_ATV_RSV_11__W 16

12416

#define SCU_RAM_ATV_RSV_11__M 0xFFFF

12417

#define SCU_RAM_ATV_RSV_11__PRE 0x0

12418

12419

#define SCU_RAM_ATV_RSV_12__A 0x831F5D

12420

#define SCU_RAM_ATV_RSV_12__W 16

12421

#define SCU_RAM_ATV_RSV_12__M 0xFFFF

12422

#define SCU_RAM_ATV_RSV_12__PRE 0x0

12423

#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E

12424

#define SCU_RAM_ATV_VID_GAIN_HI__W 16

12425

#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF

12426

#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x1000

12427

12428

#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 0

12429

#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 16

12430

#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF

12431

#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x1000

12432

12433

#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F

12434

#define SCU_RAM_ATV_VID_GAIN_LO__W 8

12435

#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF

12436

#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x0

12437

12438

#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 0

12439

#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 8

12440

#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF

12441

#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x0

12442

12443

12444

#define SCU_RAM_ATV_RSV_13__A 0x831F60

12445

#define SCU_RAM_ATV_RSV_13__W 16

12446

#define SCU_RAM_ATV_RSV_13__M 0xFFFF

12447

#define SCU_RAM_ATV_RSV_13__PRE 0x0

12448

12449

#define SCU_RAM_ATV_RSV_14__A 0x831F61

12450

#define SCU_RAM_ATV_RSV_14__W 16

12451

#define SCU_RAM_ATV_RSV_14__M 0xFFFF

12452

#define SCU_RAM_ATV_RSV_14__PRE 0x0

12453

12454

#define SCU_RAM_ATV_RSV_15__A 0x831F62

12455

#define SCU_RAM_ATV_RSV_15__W 16

12456

#define SCU_RAM_ATV_RSV_15__M 0xFFFF

12457

#define SCU_RAM_ATV_RSV_15__PRE 0x0

12458

12459

#define SCU_RAM_ATV_RSV_16__A 0x831F63

12460

#define SCU_RAM_ATV_RSV_16__W 16

12461

#define SCU_RAM_ATV_RSV_16__M 0xFFFF

12462

#define SCU_RAM_ATV_RSV_16__PRE 0x0

12463

#define SCU_RAM_ATV_AAGC_CNT__A 0x831F64

12464

#define SCU_RAM_ATV_AAGC_CNT__W 8

12465

#define SCU_RAM_ATV_AAGC_CNT__M 0xFF

12466

#define SCU_RAM_ATV_AAGC_CNT__PRE 0x7

12467

12468

#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 0

12469

#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 8

12470

#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF

12471

#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x7

12472

12473

#define SCU_RAM_ATV_SIF_GAIN__A 0x831F65

12474

#define SCU_RAM_ATV_SIF_GAIN__W 11

12475

#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF

12476

#define SCU_RAM_ATV_SIF_GAIN__PRE 0x80

12477

12478

#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 0

12479

#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 11

12480

#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF

12481

#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x80

12482

12483

12484

#define SCU_RAM_ATV_RSV_17__A 0x831F66

12485

#define SCU_RAM_ATV_RSV_17__W 16

12486

#define SCU_RAM_ATV_RSV_17__M 0xFFFF

12487

#define SCU_RAM_ATV_RSV_17__PRE 0x0

12488

12489

#define SCU_RAM_ATV_RSV_18__A 0x831F67

12490

#define SCU_RAM_ATV_RSV_18__W 16

12491

#define SCU_RAM_ATV_RSV_18__M 0xFFFF

12492

#define SCU_RAM_ATV_RSV_18__PRE 0x0

12493

12494

#define SCU_RAM_ATV_RATE_OFS__A 0x831F68

12495

#define SCU_RAM_ATV_RATE_OFS__W 12

12496

#define SCU_RAM_ATV_RATE_OFS__M 0xFFF

12497

#define SCU_RAM_ATV_RATE_OFS__PRE 0x0

12498

12499

#define SCU_RAM_ATV_LO_INCR__A 0x831F69

12500

#define SCU_RAM_ATV_LO_INCR__W 12

12501

#define SCU_RAM_ATV_LO_INCR__M 0xFFF

12502

#define SCU_RAM_ATV_LO_INCR__PRE 0x0

12503

12504

#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A

12505

#define SCU_RAM_ATV_IIR_CRIT__W 12

12506

#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF

12507

#define SCU_RAM_ATV_IIR_CRIT__PRE 0x0

12508

12509

#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B

12510

#define SCU_RAM_ATV_DEF_RATE_OFS__W 12

12511

#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF

12512

#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x0

12513

12514

#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C

12515

#define SCU_RAM_ATV_DEF_LO_INCR__W 12

12516

#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF

12517

#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x0

12518

12519

#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D

12520

#define SCU_RAM_ATV_ENABLE_IIR_WA__W 1

12521

#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x1

12522

#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x0

12523

#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E

12524

#define SCU_RAM_ATV_MOD_CONTROL__W 12

12525

#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF

12526

#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x0

12527

12528

#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__B 0

12529

#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__W 12

12530

#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__M 0xFFF

12531

#define SCU_RAM_ATV_MOD_CONTROL_SCU_RAM_ATV__PRE 0x0

12532

12533

#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F

12534

#define SCU_RAM_ATV_PAGC_KI_MAX__W 12

12535

#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF

12536

#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x667

12537

12538

#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__B 0

12539

#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__W 12

12540

#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF

12541

#define SCU_RAM_ATV_PAGC_KI_MAX_SCU_RAM_ATV__PRE 0x667

12542

12543

#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F70

12544

#define SCU_RAM_ATV_BPC_KI_MAX__W 12

12545

#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF

12546

#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x337

12547

12548

#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__B 0

12549

#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__W 12

12550

#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__M 0xFFF

12551

#define SCU_RAM_ATV_BPC_KI_MAX_SCU_RAM_ATV__PRE 0x337

12552

12553

#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F71

12554

#define SCU_RAM_ATV_NAGC_KI_MAX__W 12

12555

#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF

12556

#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x447

12557

12558

#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__B 0

12559

#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__W 12

12560

#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__M 0xFFF

12561

#define SCU_RAM_ATV_NAGC_KI_MAX_SCU_RAM_ATV__PRE 0x447

12562

12563

#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F72

12564

#define SCU_RAM_ATV_NAGC_KI_MIN__W 12

12565

#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF

12566

#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x225

12567

12568

#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 0

12569

#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 12

12570

#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF

12571

#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x225

12572

12573

#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F73

12574

#define SCU_RAM_ATV_KI_CHANGE_TH__W 8

12575

#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF

12576

#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x14

12577

12578

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 0

12579

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 8

12580

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF

12581

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x14

12582

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x14

12583

#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x28

12584

12585

#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F74

12586

#define SCU_RAM_QAM_PARAM_ANNEX__W 2

12587

#define SCU_RAM_QAM_PARAM_ANNEX__M 0x3

12588

#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x1

12589

12590

#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 0

12591

#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 2

12592

#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x3

12593

#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x1

12594

#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x0

12595

#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x1

12596

#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x2

12597

#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x3

12598

12599

#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F75

12600

#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 3

12601

#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x7

12602

#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x5

12603

12604

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 0

12605

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 3

12606

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x7

12607

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x5

12608

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x0

12609

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x3

12610

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x4

12611

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x5

12612

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x6

12613

#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x7

12614

12615

#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F76

12616

#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 8

12617

#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF

12618

#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x1

12619

12620

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 0

12621

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 8

12622

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF

12623

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x1

12624

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x0

12625

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x1

12626

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x2

12627

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x3

12628

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x4

12629

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x5

12630

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x6

12631

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x7

12632

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x8

12633

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x9

12634

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA

12635

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC

12636

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE

12637

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x10

12638

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x11

12639

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE

12640

#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF

12641

12642

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F77

12643

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 16

12644

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF

12645

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x0

12646

12647

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 0

12648

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 16

12649

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF

12650

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x0

12651

12652

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F78

12653

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 16

12654

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF

12655

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x0

12656

12657

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 0

12658

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 16

12659

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF

12660

#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x0

12661

12662

#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F79

12663

#define SCU_RAM_QAM_EQ_CENTERTAP__W 16

12664

#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF

12665

#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x13

12666

12667

#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 0

12668

#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 8

12669

#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF

12670

#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x13

12671

12672

#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A

12673

#define SCU_RAM_QAM_WR_RSV_0__W 16

12674

#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF

12675

#define SCU_RAM_QAM_WR_RSV_0__PRE 0x0

12676

12677

#define SCU_RAM_QAM_WR_RSV_0_BIT__B 0

12678

#define SCU_RAM_QAM_WR_RSV_0_BIT__W 16

12679

#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF

12680

#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x0

12681

12682

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B

12683

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 16

12684

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF

12685

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x0

12686

12687

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 0

12688

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 16

12689

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF

12690

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x0

12691

12692

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C

12693

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 16

12694

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF

12695

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x0

12696

12697

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 0

12698

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 16

12699

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF

12700

#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x0

12701

12702

#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D

12703

#define SCU_RAM_QAM_WR_RSV_5__W 16

12704

#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF

12705

#define SCU_RAM_QAM_WR_RSV_5__PRE 0x0

12706

12707

#define SCU_RAM_QAM_WR_RSV_5_BIT__B 0

12708

#define SCU_RAM_QAM_WR_RSV_5_BIT__W 16

12709

#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF

12710

#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x0

12711

12712

#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E

12713

#define SCU_RAM_QAM_WR_RSV_6__W 16

12714

#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF

12715

#define SCU_RAM_QAM_WR_RSV_6__PRE 0x0

12716

12717

#define SCU_RAM_QAM_WR_RSV_6_BIT__B 0

12718

#define SCU_RAM_QAM_WR_RSV_6_BIT__W 16

12719

#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF

12720

#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x0

12721

12722

#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F

12723

#define SCU_RAM_QAM_WR_RSV_7__W 16

12724

#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF

12725

#define SCU_RAM_QAM_WR_RSV_7__PRE 0x0

12726

12727

#define SCU_RAM_QAM_WR_RSV_7_BIT__B 0

12728

#define SCU_RAM_QAM_WR_RSV_7_BIT__W 16

12729

#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF

12730

#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x0

12731

12732

#define SCU_RAM_QAM_WR_RSV_8__A 0x831F80

12733

#define SCU_RAM_QAM_WR_RSV_8__W 16

12734

#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF

12735

#define SCU_RAM_QAM_WR_RSV_8__PRE 0x0

12736

12737

#define SCU_RAM_QAM_WR_RSV_8_BIT__B 0

12738

#define SCU_RAM_QAM_WR_RSV_8_BIT__W 16

12739

#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF

12740

#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x0

12741

12742

#define SCU_RAM_QAM_WR_RSV_9__A 0x831F81

12743

#define SCU_RAM_QAM_WR_RSV_9__W 16

12744

#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF

12745

#define SCU_RAM_QAM_WR_RSV_9__PRE 0x0

12746

12747

#define SCU_RAM_QAM_WR_RSV_9_BIT__B 0

12748

#define SCU_RAM_QAM_WR_RSV_9_BIT__W 16

12749

#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF

12750

#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x0

12751

12752

#define SCU_RAM_QAM_WR_RSV_10__A 0x831F82

12753

#define SCU_RAM_QAM_WR_RSV_10__W 16

12754

#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF

12755

#define SCU_RAM_QAM_WR_RSV_10__PRE 0x0

12756

12757

#define SCU_RAM_QAM_WR_RSV_10_BIT__B 0

12758

#define SCU_RAM_QAM_WR_RSV_10_BIT__W 16

12759

#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF

12760

#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x0

12761

12762

#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F83

12763

#define SCU_RAM_QAM_FSM_FMHUM_TO__W 16

12764

#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF

12765

#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x258

12766

12767

#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 0

12768

#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 16

12769

#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF

12770

#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x258

12771

#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x0

12772

12773

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84

12774

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 16

12775

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF

12776

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x0

12777

12778

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 0

12779

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 16

12780

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF

12781

#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x0

12782

12783

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85

12784

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 16

12785

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF

12786

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x0

12787

12788

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 0

12789

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 16

12790

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF

12791

#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x0

12792

12793

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86

12794

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 16

12795

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF

12796

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x0

12797

12798

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 0

12799

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 16

12800

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF

12801

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x0

12802

12803

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87

12804

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 16

12805

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF

12806

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x0

12807

12808

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 0

12809

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 16

12810

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF

12811

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x0

12812

12813

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88

12814

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 16

12815

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF

12816

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x0

12817

12818

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 0

12819

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 16

12820

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF

12821

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x0

12822

12823

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89

12824

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 16

12825

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF

12826

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x0

12827

12828

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 0

12829

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 16

12830

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF

12831

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x0

12832

12833

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A

12834

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 16

12835

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF

12836

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x0

12837

12838

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 0

12839

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 16

12840

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF

12841

#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x0

12842

12843

#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B

12844

#define SCU_RAM_QAM_FSM_STATE_TGT__W 4

12845

#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF

12846

#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x0

12847

12848

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 0

12849

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 4

12850

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF

12851

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x0

12852

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x0

12853

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x1

12854

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x2

12855

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x3

12856

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x4

12857

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x5

12858

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x6

12859

#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x7

12860

12861

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C

12862

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 9

12863

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF

12864

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x0

12865

12866

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 0

12867

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 1

12868

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x1

12869

#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x0

12870

12871

#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D

12872

#define SCU_RAM_QAM_FSM_ATH__W 16

12873

#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF

12874

#define SCU_RAM_QAM_FSM_ATH__PRE 0x0

12875

12876

#define SCU_RAM_QAM_FSM_ATH_BIT__B 0

12877

#define SCU_RAM_QAM_FSM_ATH_BIT__W 16

12878

#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF

12879

#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x0

12880

12881

#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E

12882

#define SCU_RAM_QAM_FSM_RTH__W 16

12883

#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF

12884

#define SCU_RAM_QAM_FSM_RTH__PRE 0x4B

12885

12886

#define SCU_RAM_QAM_FSM_RTH_BIT__B 0

12887

#define SCU_RAM_QAM_FSM_RTH_BIT__W 16

12888

#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF

12889

#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x4B

12890

#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C

12891

#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x50

12892

#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E

12893

#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x32

12894

#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D

12895

12896

#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F

12897

#define SCU_RAM_QAM_FSM_FTH__W 16

12898

#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF

12899

#define SCU_RAM_QAM_FSM_FTH__PRE 0x3C

12900

12901

#define SCU_RAM_QAM_FSM_FTH_BIT__B 0

12902

#define SCU_RAM_QAM_FSM_FTH_BIT__W 16

12903

#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF

12904

#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x3C

12905

#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x32

12906

#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E

12907

#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E

12908

#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x14

12909

#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x14

12910

12911

#define SCU_RAM_QAM_FSM_PTH__A 0x831F90

12912

#define SCU_RAM_QAM_FSM_PTH__W 16

12913

#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF

12914

#define SCU_RAM_QAM_FSM_PTH__PRE 0x64

12915

12916

#define SCU_RAM_QAM_FSM_PTH_BIT__B 0

12917

#define SCU_RAM_QAM_FSM_PTH_BIT__W 16

12918

#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF

12919

#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x64

12920

#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC8

12921

#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x96

12922

#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C

12923

#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x64

12924

#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x64

12925

12926

#define SCU_RAM_QAM_FSM_MTH__A 0x831F91

12927

#define SCU_RAM_QAM_FSM_MTH__W 16

12928

#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF

12929

#define SCU_RAM_QAM_FSM_MTH__PRE 0x6E

12930

12931

#define SCU_RAM_QAM_FSM_MTH_BIT__B 0

12932

#define SCU_RAM_QAM_FSM_MTH_BIT__W 16

12933

#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF

12934

#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x6E

12935

#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A

12936

#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x50

12937

#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x46

12938

#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C

12939

#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x50

12940

12941

#define SCU_RAM_QAM_FSM_CTH__A 0x831F92

12942

#define SCU_RAM_QAM_FSM_CTH__W 16

12943

#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF

12944

#define SCU_RAM_QAM_FSM_CTH__PRE 0x50

12945

12946

#define SCU_RAM_QAM_FSM_CTH_BIT__B 0

12947

#define SCU_RAM_QAM_FSM_CTH_BIT__W 16

12948

#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF

12949

#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x50

12950

#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA0

12951

#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C

12952

#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C

12953

#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C

12954

#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C

12955

12956

#define SCU_RAM_QAM_FSM_QTH__A 0x831F93

12957

#define SCU_RAM_QAM_FSM_QTH__W 16

12958

#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF

12959

#define SCU_RAM_QAM_FSM_QTH__PRE 0x96

12960

12961

#define SCU_RAM_QAM_FSM_QTH_BIT__B 0

12962

#define SCU_RAM_QAM_FSM_QTH_BIT__W 16

12963

#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF

12964

#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x96

12965

#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE6

12966

#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA

12967

#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC3

12968

#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C

12969

#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x96

12970

12971

#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94

12972

#define SCU_RAM_QAM_FSM_RATE_LIM__W 16

12973

#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF

12974

#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x28

12975

12976

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 0

12977

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 16

12978

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF

12979

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x28

12980

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x46

12981

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x46

12982

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x46

12983

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x46

12984

#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x46

12985

12986

#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95

12987

#define SCU_RAM_QAM_FSM_FREQ_LIM__W 16

12988

#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF

12989

#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0xF

12990

12991

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 0

12992

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 16

12993

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF

12994

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0xF

12995

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E

12996

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x14

12997

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x28

12998

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x8

12999

#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x28

13000

13001

#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96

13002

#define SCU_RAM_QAM_FSM_COUNT_LIM__W 16

13003

#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF

13004

#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x4

13005

13006

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 0

13007

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 16

13008

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF

13009

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x4

13010

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x4

13011

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x6

13012

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x6

13013

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x7

13014

#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x6

13015

13016

#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97

13017

#define SCU_RAM_QAM_LC_CA_COARSE__W 16

13018

#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF

13019

#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x28

13020

13021

#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 0

13022

#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 8

13023

#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF

13024

#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x28

13025

13026

#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F98

13027

#define SCU_RAM_QAM_LC_CA_MEDIUM__W 16

13028

#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF

13029

#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x28

13030

13031

#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 0

13032

#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 8

13033

#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF

13034

#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x28

13035

13036

#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99

13037

#define SCU_RAM_QAM_LC_CA_FINE__W 16

13038

#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF

13039

#define SCU_RAM_QAM_LC_CA_FINE__PRE 0xF

13040

13041

#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 0

13042

#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 8

13043

#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF

13044

#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0xF

13045

13046

#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A

13047

#define SCU_RAM_QAM_LC_CP_COARSE__W 16

13048

#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF

13049

#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x64

13050

13051

#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 0

13052

#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 8

13053

#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF

13054

#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x64

13055

13056

#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B

13057

#define SCU_RAM_QAM_LC_CP_MEDIUM__W 16

13058

#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF

13059

#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x1E

13060

13061

#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 0

13062

#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 8

13063

#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF

13064

#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x1E

13065

13066

#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C

13067

#define SCU_RAM_QAM_LC_CP_FINE__W 16

13068

#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF

13069

#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x5

13070

13071

#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 0

13072

#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 8

13073

#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF

13074

#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x5

13075

13076

#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D

13077

#define SCU_RAM_QAM_LC_CI_COARSE__W 16

13078

#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF

13079

#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x32

13080

13081

#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 0

13082

#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 8

13083

#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF

13084

#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x32

13085

13086

#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E

13087

#define SCU_RAM_QAM_LC_CI_MEDIUM__W 16

13088

#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF

13089

#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x1E

13090

13091

#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 0

13092

#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 8

13093

#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF

13094

#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x1E

13095

13096

#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F

13097

#define SCU_RAM_QAM_LC_CI_FINE__W 16

13098

#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF

13099

#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x5

13100

13101

#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 0

13102

#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 8

13103

#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF

13104

#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x5

13105

13106

#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0

13107

#define SCU_RAM_QAM_LC_EP_COARSE__W 16

13108

#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF

13109

#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x18

13110

13111

#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 0

13112

#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 8

13113

#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF

13114

#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x18

13115

13116

#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1

13117

#define SCU_RAM_QAM_LC_EP_MEDIUM__W 16

13118

#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF

13119

#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x18

13120

13121

#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 0

13122

#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 8

13123

#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF

13124

#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x18

13125

13126

#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2

13127

#define SCU_RAM_QAM_LC_EP_FINE__W 16

13128

#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF

13129

#define SCU_RAM_QAM_LC_EP_FINE__PRE 0xC

13130

13131

#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 0

13132

#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 8

13133

#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF

13134

#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0xC

13135

13136

#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3

13137

#define SCU_RAM_QAM_LC_EI_COARSE__W 16

13138

#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF

13139

#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x10

13140

13141

#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 0

13142

#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 8

13143

#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF

13144

#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x10

13145

13146

#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4

13147

#define SCU_RAM_QAM_LC_EI_MEDIUM__W 16

13148

#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF

13149

#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x10

13150

13151

#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 0

13152

#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 8

13153

#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF

13154

#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x10

13155

13156

#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5

13157

#define SCU_RAM_QAM_LC_EI_FINE__W 16

13158

#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF

13159

#define SCU_RAM_QAM_LC_EI_FINE__PRE 0xC

13160

13161

#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 0

13162

#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 8

13163

#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF

13164

#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0xC

13165

13166

#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6

13167

#define SCU_RAM_QAM_LC_CF_COARSE__W 16

13168

#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF

13169

#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x30

13170

13171

#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 0

13172

#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 8

13173

#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF

13174

#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x30

13175

13176

#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7

13177

#define SCU_RAM_QAM_LC_CF_MEDIUM__W 16

13178

#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF

13179

#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x19

13180

13181

#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 0

13182

#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 8

13183

#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF

13184

#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x19

13185

13186

#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8

13187

#define SCU_RAM_QAM_LC_CF_FINE__W 16

13188

#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF

13189

#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x10

13190

13191

#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 0

13192

#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 8

13193

#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF

13194

#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x10

13195

13196

#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9

13197

#define SCU_RAM_QAM_LC_CF1_COARSE__W 16

13198

#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF

13199

#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0xA

13200

13201

#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 0

13202

#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 8

13203

#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF

13204

#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0xA

13205

13206

#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA

13207

#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 16

13208

#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF

13209

#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0xA

13210

13211

#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 0

13212

#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 8

13213

#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF

13214

#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0xA

13215

13216

#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB

13217

#define SCU_RAM_QAM_LC_CF1_FINE__W 16

13218

#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF

13219

#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x5

13220

13221

#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 0

13222

#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 8

13223

#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF

13224

#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x5

13225

13226

#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC

13227

#define SCU_RAM_QAM_SL_SIG_POWER__W 16

13228

#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF

13229

#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0xAA00

13230

13231

#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 0

13232

#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 16

13233

#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF

13234

#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0xAA00

13235

13236

#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD

13237

#define SCU_RAM_QAM_EQ_CMA_RAD0__W 14

13238

#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF

13239

#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x3418

13240

13241

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 0

13242

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 14

13243

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF

13244

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x3418

13245

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD

13246

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A33

13247

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x3418

13248

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x1814

13249

#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE

13250

13251

#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE

13252

#define SCU_RAM_QAM_EQ_CMA_RAD1__W 14

13253

#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF

13254

#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x314A

13255

13256

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 0

13257

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 14

13258

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF

13259

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x314A

13260

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD

13261

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A33

13262

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A

13263

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C6

13264

#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F34

13265

13266

#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF

13267

#define SCU_RAM_QAM_EQ_CMA_RAD2__W 14

13268

#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF

13269

#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x2ED4

13270

13271

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 0

13272

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 14

13273

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF

13274

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x2ED4

13275

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD

13276

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A33

13277

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED4

13278

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA

13279

#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF

13280

13281

#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0

13282

#define SCU_RAM_QAM_EQ_CMA_RAD3__W 14

13283

#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF

13284

#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x35F1

13285

13286

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 0

13287

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 14

13288

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF

13289

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x35F1

13290

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD

13291

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A33

13292

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F1

13293

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x1909

13294

#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x3283

13295

13296

#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1

13297

#define SCU_RAM_QAM_EQ_CMA_RAD4__W 14

13298

#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF

13299

#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x35F1

13300

13301

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 0

13302

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 14

13303

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF

13304

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x35F1

13305

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD

13306

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A33

13307

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F1

13308

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A00

13309

#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D

13310

13311

#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2

13312

#define SCU_RAM_QAM_EQ_CMA_RAD5__W 14

13313

#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF

13314

#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x3CF9

13315

13316

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 0

13317

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 14

13318

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF

13319

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x3CF9

13320

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD

13321

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A33

13322

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF9

13323

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C46

13324

#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C19

13325

13326

#define SCU_RAM_QAM_CTL_ENA__A 0x831FB3

13327

#define SCU_RAM_QAM_CTL_ENA__W 16

13328

#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF

13329

#define SCU_RAM_QAM_CTL_ENA__PRE 0x7FF

13330

13331

#define SCU_RAM_QAM_CTL_ENA_AMP__B 0

13332

#define SCU_RAM_QAM_CTL_ENA_AMP__W 1

13333

#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x1

13334

#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x1

13335

13336

#define SCU_RAM_QAM_CTL_ENA_ACQ__B 1

13337

#define SCU_RAM_QAM_CTL_ENA_ACQ__W 1

13338

#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x2

13339

#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x2

13340

13341

#define SCU_RAM_QAM_CTL_ENA_EQU__B 2

13342

#define SCU_RAM_QAM_CTL_ENA_EQU__W 1

13343

#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x4

13344

#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x4

13345

13346

#define SCU_RAM_QAM_CTL_ENA_SLC__B 3

13347

#define SCU_RAM_QAM_CTL_ENA_SLC__W 1

13348

#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x8

13349

#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x8

13350

13351

#define SCU_RAM_QAM_CTL_ENA_LC__B 4

13352

#define SCU_RAM_QAM_CTL_ENA_LC__W 1

13353

#define SCU_RAM_QAM_CTL_ENA_LC__M 0x10

13354

#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x10

13355

13356

#define SCU_RAM_QAM_CTL_ENA_AGC__B 5

13357

#define SCU_RAM_QAM_CTL_ENA_AGC__W 1

13358

#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x20

13359

#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x20

13360

13361

#define SCU_RAM_QAM_CTL_ENA_FEC__B 6

13362

#define SCU_RAM_QAM_CTL_ENA_FEC__W 1

13363

#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x40

13364

#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x40

13365

13366

#define SCU_RAM_QAM_CTL_ENA_AXIS__B 7

13367

#define SCU_RAM_QAM_CTL_ENA_AXIS__W 1

13368

#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x80

13369

#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x80

13370

13371

#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 8

13372

#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 1

13373

#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x100

13374

#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x100

13375

13376

#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 9

13377

#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 1

13378

#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x200

13379

#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x200

13380

13381

#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 10

13382

#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 1

13383

#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x400

13384

#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x400

13385

13386

#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB4

13387

#define SCU_RAM_QAM_WR_RSV_1__W 16

13388

#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF

13389

#define SCU_RAM_QAM_WR_RSV_1__PRE 0x0

13390

13391

#define SCU_RAM_QAM_WR_RSV_1_BIT__B 0

13392

#define SCU_RAM_QAM_WR_RSV_1_BIT__W 16

13393

#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF

13394

#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x0

13395

13396

#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB5

13397

#define SCU_RAM_QAM_WR_RSV_2__W 16

13398

#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF

13399

#define SCU_RAM_QAM_WR_RSV_2__PRE 0x0

13400

13401

#define SCU_RAM_QAM_WR_RSV_2_BIT__B 0

13402

#define SCU_RAM_QAM_WR_RSV_2_BIT__W 16

13403

#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF

13404

#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x0

13405

13406

#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB6

13407

#define SCU_RAM_QAM_WR_RSV_3__W 16

13408

#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF

13409

#define SCU_RAM_QAM_WR_RSV_3__PRE 0x0

13410

13411

#define SCU_RAM_QAM_WR_RSV_3_BIT__B 0

13412

#define SCU_RAM_QAM_WR_RSV_3_BIT__W 16

13413

#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF

13414

#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x0

13415

13416

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB7

13417

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 3

13418

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x7

13419

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x0

13420

13421

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 0

13422

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 3

13423

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x7

13424

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x0

13425

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x0

13426

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x3

13427

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x4

13428

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x5

13429

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x6

13430

#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x7

13431

13432

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB8

13433

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 8

13434

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF

13435

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x1

13436

13437

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 0

13438

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 8

13439

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF

13440

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x1

13441

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x0

13442

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x1

13443

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x2

13444

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x3

13445

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x4

13446

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x5

13447

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x6

13448

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x7

13449

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x8

13450

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x9

13451

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA

13452

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC

13453

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE

13454

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x10

13455

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x11

13456

#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE

13457

13458

#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB9

13459

#define SCU_RAM_QAM_RD_RSV_4__W 16

13460

#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF

13461

#define SCU_RAM_QAM_RD_RSV_4__PRE 0x0

13462

13463

#define SCU_RAM_QAM_RD_RSV_4_BIT__B 0

13464

#define SCU_RAM_QAM_RD_RSV_4_BIT__W 16

13465

#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF

13466

#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x0

13467

13468

#define SCU_RAM_QAM_LOCKED__A 0x831FBA

13469

#define SCU_RAM_QAM_LOCKED__W 16

13470

#define SCU_RAM_QAM_LOCKED__M 0xFFFF

13471

#define SCU_RAM_QAM_LOCKED__PRE 0x0

13472

13473

#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 0

13474

#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 8

13475

#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF

13476

#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x0

13477

#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x0

13478

#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x1

13479

#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x2

13480

#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x3

13481

#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x4

13482

#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x5

13483

#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x6

13484

#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x7

13485

13486

#define SCU_RAM_QAM_LOCKED_LOCKED__B 8

13487

#define SCU_RAM_QAM_LOCKED_LOCKED__W 8

13488

#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF00

13489

#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x0

13490

#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x0

13491

#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000

13492

#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000

13493

#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000

13494

13495

#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB

13496

#define SCU_RAM_QAM_EVENTS_OCC_HI__W 16

13497

#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF

13498

#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x0

13499

13500

#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 0

13501

#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 1

13502

#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x1

13503

#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x0

13504

13505

#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 1

13506

#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 1

13507

#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x2

13508

#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x0

13509

13510

#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 2

13511

#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 1

13512

#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x4

13513

#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x0

13514

13515

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 3

13516

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 1

13517

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x8

13518

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x0

13519

13520

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 4

13521

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 1

13522

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x10

13523

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x0

13524

13525

#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 5

13526

#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 1

13527

#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x20

13528

#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x0

13529

13530

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 6

13531

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 1

13532

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x40

13533

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x0

13534

13535

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 7

13536

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 1

13537

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x80

13538

#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x0

13539

13540

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 8

13541

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 1

13542

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x100

13543

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x0

13544

13545

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 9

13546

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 1

13547

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x200

13548

#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x0

13549

13550

#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 10

13551

#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 1

13552

#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x400

13553

#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x0

13554

13555

#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 11

13556

#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 1

13557

#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x800

13558

#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x0

13559

13560

#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 12

13561

#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 4

13562

#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF000

13563

#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x0

13564

13565

#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC

13566

#define SCU_RAM_QAM_EVENTS_OCC_LO__W 16

13567

#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF

13568

#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x0

13569

13570

#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 0

13571

#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 1

13572

#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x1

13573

#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x0

13574

13575

#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 1

13576

#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 1

13577

#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x2

13578

#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x0

13579

13580

#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 2

13581

#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 1

13582

#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x4

13583

#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x0

13584

13585

#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 3

13586

#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 1

13587

#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x8

13588

#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x0

13589

13590

#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 4

13591

#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 1

13592

#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x10

13593

#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x0

13594

13595

#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 5

13596

#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 1

13597

#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x20

13598

#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x0

13599

13600

#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 6

13601

#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 1

13602

#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x40

13603

#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x0

13604

13605

#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 7

13606

#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 1

13607

#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x80

13608

#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x0

13609

13610

#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 8

13611

#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 1

13612

#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x100

13613

#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x0

13614

13615

#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 9

13616

#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 1

13617

#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x200

13618

#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x0

13619

13620

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 10

13621

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 1

13622

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x400

13623

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x0

13624

13625

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 11

13626

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 1

13627

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x800

13628

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x0

13629

13630

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 12

13631

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 1

13632

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x1000

13633

#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x0

13634

13635

#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 13

13636

#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 1

13637

#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x2000

13638

#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x0

13639

13640

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 14

13641

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 1

13642

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x4000

13643

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x0

13644

13645

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 15

13646

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 1

13647

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x8000

13648

#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x0

13649

13650

#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD

13651

#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 16

13652

#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF

13653

#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x0

13654

13655

#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 0

13656

#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 16

13657

#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF

13658

#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x0

13659

13660

#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE

13661

#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 16

13662

#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF

13663

#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x0

13664

13665

#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 0

13666

#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 16

13667

#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF

13668

#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x0

13669

13670

#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF

13671

#define SCU_RAM_QAM_TASKLETS_SCHED__W 16

13672

#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF

13673

#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x0

13674

13675

#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 0

13676

#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 16

13677

#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF

13678

#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x0

13679

13680

#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC0

13681

#define SCU_RAM_QAM_TASKLETS_RUN__W 16

13682

#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF

13683

#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x0

13684

13685

#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 0

13686

#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 16

13687

#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF

13688

#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x0

13689

13690

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC1

13691

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 16

13692

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF

13693

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x0

13694

13695

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 0

13696

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 16

13697

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF

13698

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x0

13699

13700

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC2

13701

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 16

13702

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF

13703

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x0

13704

13705

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 0

13706

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 16

13707

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF

13708

#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x0

13709

13710

#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC3

13711

#define SCU_RAM_QAM_RD_RSV_5__W 16

13712

#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF

13713

#define SCU_RAM_QAM_RD_RSV_5__PRE 0x0

13714

13715

#define SCU_RAM_QAM_RD_RSV_5_BIT__B 0

13716

#define SCU_RAM_QAM_RD_RSV_5_BIT__W 16

13717

#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF

13718

#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x0

13719

13720

#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC4

13721

#define SCU_RAM_QAM_RD_RSV_6__W 16

13722

#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF

13723

#define SCU_RAM_QAM_RD_RSV_6__PRE 0x0

13724

13725

#define SCU_RAM_QAM_RD_RSV_6_BIT__B 0

13726

#define SCU_RAM_QAM_RD_RSV_6_BIT__W 16

13727

#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF

13728

#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x0

13729

13730

#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC5

13731

#define SCU_RAM_QAM_RD_RSV_7__W 16

13732

#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF

13733

#define SCU_RAM_QAM_RD_RSV_7__PRE 0x0

13734

13735

#define SCU_RAM_QAM_RD_RSV_7_BIT__B 0

13736

#define SCU_RAM_QAM_RD_RSV_7_BIT__W 16

13737

#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF

13738

#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x0

13739

13740

#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC6

13741

#define SCU_RAM_QAM_RD_RSV_8__W 16

13742

#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF

13743

#define SCU_RAM_QAM_RD_RSV_8__PRE 0x0

13744

13745

#define SCU_RAM_QAM_RD_RSV_8_BIT__B 0

13746

#define SCU_RAM_QAM_RD_RSV_8_BIT__W 16

13747

#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF

13748

#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x0

13749

13750

#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC7

13751

#define SCU_RAM_QAM_RD_RSV_9__W 16

13752

#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF

13753

#define SCU_RAM_QAM_RD_RSV_9__PRE 0x0

13754

13755

#define SCU_RAM_QAM_RD_RSV_9_BIT__B 0

13756

#define SCU_RAM_QAM_RD_RSV_9_BIT__W 16

13757

#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF

13758

#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x0

13759

13760

#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC8

13761

#define SCU_RAM_QAM_RD_RSV_10__W 16

13762

#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF

13763

#define SCU_RAM_QAM_RD_RSV_10__PRE 0x0

13764

13765

#define SCU_RAM_QAM_RD_RSV_10_BIT__B 0

13766

#define SCU_RAM_QAM_RD_RSV_10_BIT__W 16

13767

#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF

13768

#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x0

13769

13770

#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC9

13771

#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 16

13772

#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF

13773

#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x0

13774

13775

#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 0

13776

#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 16

13777

#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF

13778

#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x0

13779

13780

#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA

13781

#define SCU_RAM_QAM_FSM_STATE__W 4

13782

#define SCU_RAM_QAM_FSM_STATE__M 0xF

13783

#define SCU_RAM_QAM_FSM_STATE__PRE 0x0

13784

13785

#define SCU_RAM_QAM_FSM_STATE_BIT__B 0

13786

#define SCU_RAM_QAM_FSM_STATE_BIT__W 4

13787

#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF

13788

#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x0

13789

#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x0

13790

#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x1

13791

#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x2

13792

#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x3

13793

#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x4

13794

#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x5

13795

#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x6

13796

#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x7

13797

13798

#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB

13799

#define SCU_RAM_QAM_FSM_STATE_NEW__W 4

13800

#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF

13801

#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x0

13802

13803

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 0

13804

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 4

13805

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF

13806

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x0

13807

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x0

13808

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x1

13809

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x2

13810

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x3

13811

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x4

13812

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x5

13813

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x6

13814

#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x7

13815

13816

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC

13817

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 13

13818

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FFF

13819

#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x0

13820

13821

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 0

13822

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 1

13823

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x1

13824

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x0

13825

13826

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 1

13827

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 1

13828

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x2

13829

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x0

13830

13831

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 2

13832

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 1

13833

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x4

13834

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x0

13835

13836

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 3

13837

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 1

13838

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x8

13839

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x0

13840

13841

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 4

13842

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 1

13843

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x10

13844

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x0

13845

13846

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 5

13847

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 1

13848

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x20

13849

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x0

13850

13851

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 6

13852

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 1

13853

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x40

13854

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x0

13855

13856

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 7

13857

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 1

13858

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x80

13859

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x0

13860

13861

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 8

13862

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 1

13863

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x100

13864

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x0

13865

13866

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__B 9

13867

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__W 1

13868

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__M 0x200

13869

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LOC_EQU__PRE 0x0

13870

13871

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__B 10

13872

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__W 1

13873

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__M 0x400

13874

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_SYNCW__PRE 0x0

13875

13876

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__B 11

13877

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__W 1

13878

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__M 0x800

13879

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FEC__PRE 0x0

13880

13881

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__B 12

13882

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__W 1

13883

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__M 0x1000

13884

#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FSMSAFE__PRE 0x0

13885

13886

#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD

13887

#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 16

13888

#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF

13889

#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x46

13890

13891

#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 0

13892

#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 16

13893

#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF

13894

#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x46

13895

13896

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE

13897

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 16

13898

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF

13899

#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x1E

13900

13901

#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 0

13902

#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 16

13903

#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF

13904

#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x1E

13905

13906

#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF

13907

#define SCU_RAM_QAM_ERR_STATE__W 4

13908

#define SCU_RAM_QAM_ERR_STATE__M 0xF

13909

#define SCU_RAM_QAM_ERR_STATE__PRE 0x0

13910

13911

#define SCU_RAM_QAM_ERR_STATE_BIT__B 0

13912

#define SCU_RAM_QAM_ERR_STATE_BIT__W 4

13913

#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF

13914

#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x0

13915

#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x0

13916

#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x1

13917

#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x2

13918

#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x3

13919

#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x4

13920

#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x5

13921

#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x6

13922

#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x7

13923

13924

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD0

13925

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 9

13926

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF

13927

#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x0

13928

13929

#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 0

13930

#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 1

13931

#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x1

13932

#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x0

13933

13934

#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD1

13935

#define SCU_RAM_QAM_EQ_LOCK__W 1

13936

#define SCU_RAM_QAM_EQ_LOCK__M 0x1

13937

#define SCU_RAM_QAM_EQ_LOCK__PRE 0x0

13938

13939

#define SCU_RAM_QAM_EQ_LOCK_BIT__B 0

13940

#define SCU_RAM_QAM_EQ_LOCK_BIT__W 1

13941

#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x1

13942

#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x0

13943

13944

#define SCU_RAM_QAM_EQ_STATE__A 0x831FD2

13945

#define SCU_RAM_QAM_EQ_STATE__W 16

13946

#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF

13947

#define SCU_RAM_QAM_EQ_STATE__PRE 0x0

13948

13949

#define SCU_RAM_QAM_EQ_STATE_BIT__B 0

13950

#define SCU_RAM_QAM_EQ_STATE_BIT__W 16

13951

#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF

13952

#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x0

13953

13954

#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD3

13955

#define SCU_RAM_QAM_RD_RSV_0__W 16

13956

#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF

13957

#define SCU_RAM_QAM_RD_RSV_0__PRE 0x0

13958

13959

#define SCU_RAM_QAM_RD_RSV_0_BIT__B 0

13960

#define SCU_RAM_QAM_RD_RSV_0_BIT__W 16

13961

#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF

13962

#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x0

13963

13964

#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD4

13965

#define SCU_RAM_QAM_RD_RSV_1__W 16

13966

#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF

13967

#define SCU_RAM_QAM_RD_RSV_1__PRE 0x0

13968

13969

#define SCU_RAM_QAM_RD_RSV_1_BIT__B 0

13970

#define SCU_RAM_QAM_RD_RSV_1_BIT__W 16

13971

#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF

13972

#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x0

13973

13974

#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD5

13975

#define SCU_RAM_QAM_RD_RSV_2__W 16

13976

#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF

13977

#define SCU_RAM_QAM_RD_RSV_2__PRE 0x0

13978

13979

#define SCU_RAM_QAM_RD_RSV_2_BIT__B 0

13980

#define SCU_RAM_QAM_RD_RSV_2_BIT__W 16

13981

#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF

13982

#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x0

13983

13984

#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD6

13985

#define SCU_RAM_QAM_RD_RSV_3__W 16

13986

#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF

13987

#define SCU_RAM_QAM_RD_RSV_3__PRE 0x0

13988

13989

#define SCU_RAM_QAM_RD_RSV_3_BIT__B 0

13990

#define SCU_RAM_QAM_RD_RSV_3_BIT__W 16

13991

#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF

13992

#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x0

13993

13994

13995

#define SCU_RAM_FREE_8151__A 0x831FD7

13996

#define SCU_RAM_FREE_8151__W 16

13997

#define SCU_RAM_FREE_8151__M 0xFFFF

13998

#define SCU_RAM_FREE_8151__PRE 0x0

13999

14000

#define SCU_RAM_FREE_8152__A 0x831FD8

14001

#define SCU_RAM_FREE_8152__W 16

14002

#define SCU_RAM_FREE_8152__M 0xFFFF

14003

#define SCU_RAM_FREE_8152__PRE 0x0

14004

14005

#define SCU_RAM_FREE_8153__A 0x831FD9

14006

#define SCU_RAM_FREE_8153__W 16

14007

#define SCU_RAM_FREE_8153__M 0xFFFF

14008

#define SCU_RAM_FREE_8153__PRE 0x0

14009

14010

#define SCU_RAM_FREE_8154__A 0x831FDA

14011

#define SCU_RAM_FREE_8154__W 16

14012

#define SCU_RAM_FREE_8154__M 0xFFFF

14013

#define SCU_RAM_FREE_8154__PRE 0x0

14014

14015

#define SCU_RAM_FREE_8155__A 0x831FDB

14016

#define SCU_RAM_FREE_8155__W 16

14017

#define SCU_RAM_FREE_8155__M 0xFFFF

14018

#define SCU_RAM_FREE_8155__PRE 0x0

14019

14020

#define SCU_RAM_FREE_8156__A 0x831FDC

14021

#define SCU_RAM_FREE_8156__W 16

14022

#define SCU_RAM_FREE_8156__M 0xFFFF

14023

#define SCU_RAM_FREE_8156__PRE 0x0

14024

14025

#define SCU_RAM_FREE_8157__A 0x831FDD

14026

#define SCU_RAM_FREE_8157__W 16

14027

#define SCU_RAM_FREE_8157__M 0xFFFF

14028

#define SCU_RAM_FREE_8157__PRE 0x0

14029

14030

#define SCU_RAM_FREE_8158__A 0x831FDE

14031

#define SCU_RAM_FREE_8158__W 16

14032

#define SCU_RAM_FREE_8158__M 0xFFFF

14033

#define SCU_RAM_FREE_8158__PRE 0x0

14034

14035

#define SCU_RAM_FREE_8159__A 0x831FDF

14036

#define SCU_RAM_FREE_8159__W 16

14037

#define SCU_RAM_FREE_8159__M 0xFFFF

14038

#define SCU_RAM_FREE_8159__PRE 0x0

14039

14040

#define SCU_RAM_FREE_8160__A 0x831FE0

14041

#define SCU_RAM_FREE_8160__W 16

14042

#define SCU_RAM_FREE_8160__M 0xFFFF

14043

#define SCU_RAM_FREE_8160__PRE 0x0

14044

14045

#define SCU_RAM_FREE_8161__A 0x831FE1

14046

#define SCU_RAM_FREE_8161__W 16

14047

#define SCU_RAM_FREE_8161__M 0xFFFF

14048

#define SCU_RAM_FREE_8161__PRE 0x0

14049

14050

#define SCU_RAM_FREE_8162__A 0x831FE2

14051

#define SCU_RAM_FREE_8162__W 16

14052

#define SCU_RAM_FREE_8162__M 0xFFFF

14053

#define SCU_RAM_FREE_8162__PRE 0x0

14054

14055

#define SCU_RAM_FREE_8163__A 0x831FE3

14056

#define SCU_RAM_FREE_8163__W 16

14057

#define SCU_RAM_FREE_8163__M 0xFFFF

14058

#define SCU_RAM_FREE_8163__PRE 0x0

14059

14060

#define SCU_RAM_FREE_8164__A 0x831FE4

14061

#define SCU_RAM_FREE_8164__W 16

14062

#define SCU_RAM_FREE_8164__M 0xFFFF

14063

#define SCU_RAM_FREE_8164__PRE 0x0

14064

14065

#define SCU_RAM_FREE_8165__A 0x831FE5

14066

#define SCU_RAM_FREE_8165__W 16

14067

#define SCU_RAM_FREE_8165__M 0xFFFF

14068

#define SCU_RAM_FREE_8165__PRE 0x0

14069

14070

#define SCU_RAM_FREE_8166__A 0x831FE6

14071

#define SCU_RAM_FREE_8166__W 16

14072

#define SCU_RAM_FREE_8166__M 0xFFFF

14073

#define SCU_RAM_FREE_8166__PRE 0x0

14074

14075

#define SCU_RAM_FREE_8167__A 0x831FE7

14076

#define SCU_RAM_FREE_8167__W 16

14077

#define SCU_RAM_FREE_8167__M 0xFFFF

14078

#define SCU_RAM_FREE_8167__PRE 0x0

14079

14080

#define SCU_RAM_FREE_8168__A 0x831FE8

14081

#define SCU_RAM_FREE_8168__W 16

14082

#define SCU_RAM_FREE_8168__M 0xFFFF

14083

#define SCU_RAM_FREE_8168__PRE 0x0

14084

14085

#define SCU_RAM_FREE_8169__A 0x831FE9

14086

#define SCU_RAM_FREE_8169__W 16

14087

#define SCU_RAM_FREE_8169__M 0xFFFF

14088

#define SCU_RAM_FREE_8169__PRE 0x0

14089

14090

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA

14091

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 16

14092

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF

14093

#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x1E

14094

14095

#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB

14096

#define SCU_RAM_DRIVER_VER_HI__W 16

14097

#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF

14098

#define SCU_RAM_DRIVER_VER_HI__PRE 0x0

14099

14100

#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC

14101

#define SCU_RAM_DRIVER_VER_LO__W 16

14102

#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF

14103

#define SCU_RAM_DRIVER_VER_LO__PRE 0x0

14104

14105

#define SCU_RAM_PARAM_15__A 0x831FED

14106

#define SCU_RAM_PARAM_15__W 16

14107

#define SCU_RAM_PARAM_15__M 0xFFFF

14108

#define SCU_RAM_PARAM_15__PRE 0x0

14109

14110

#define SCU_RAM_PARAM_14__A 0x831FEE

14111

#define SCU_RAM_PARAM_14__W 16

14112

#define SCU_RAM_PARAM_14__M 0xFFFF

14113

#define SCU_RAM_PARAM_14__PRE 0x0

14114

14115

#define SCU_RAM_PARAM_13__A 0x831FEF

14116

#define SCU_RAM_PARAM_13__W 16

14117

#define SCU_RAM_PARAM_13__M 0xFFFF

14118

#define SCU_RAM_PARAM_13__PRE 0x0

14119

14120

#define SCU_RAM_PARAM_12__A 0x831FF0

14121

#define SCU_RAM_PARAM_12__W 16

14122

#define SCU_RAM_PARAM_12__M 0xFFFF

14123

#define SCU_RAM_PARAM_12__PRE 0x0

14124

14125

#define SCU_RAM_PARAM_11__A 0x831FF1

14126

#define SCU_RAM_PARAM_11__W 16

14127

#define SCU_RAM_PARAM_11__M 0xFFFF

14128

#define SCU_RAM_PARAM_11__PRE 0x0

14129

14130

#define SCU_RAM_PARAM_10__A 0x831FF2

14131

#define SCU_RAM_PARAM_10__W 16

14132

#define SCU_RAM_PARAM_10__M 0xFFFF

14133

#define SCU_RAM_PARAM_10__PRE 0x0

14134

14135

#define SCU_RAM_PARAM_9__A 0x831FF3

14136

#define SCU_RAM_PARAM_9__W 16

14137

#define SCU_RAM_PARAM_9__M 0xFFFF

14138

#define SCU_RAM_PARAM_9__PRE 0x0

14139

14140

#define SCU_RAM_PARAM_8__A 0x831FF4

14141

#define SCU_RAM_PARAM_8__W 16

14142

#define SCU_RAM_PARAM_8__M 0xFFFF

14143

#define SCU_RAM_PARAM_8__PRE 0x0

14144

14145

#define SCU_RAM_PARAM_7__A 0x831FF5

14146

#define SCU_RAM_PARAM_7__W 16

14147

#define SCU_RAM_PARAM_7__M 0xFFFF

14148

#define SCU_RAM_PARAM_7__PRE 0x0

14149

14150

#define SCU_RAM_PARAM_6__A 0x831FF6

14151

#define SCU_RAM_PARAM_6__W 16

14152

#define SCU_RAM_PARAM_6__M 0xFFFF

14153

#define SCU_RAM_PARAM_6__PRE 0x0

14154

14155

#define SCU_RAM_PARAM_5__A 0x831FF7

14156

#define SCU_RAM_PARAM_5__W 16

14157

#define SCU_RAM_PARAM_5__M 0xFFFF

14158

#define SCU_RAM_PARAM_5__PRE 0x0

14159

14160

#define SCU_RAM_PARAM_4__A 0x831FF8

14161

#define SCU_RAM_PARAM_4__W 16

14162

#define SCU_RAM_PARAM_4__M 0xFFFF

14163

#define SCU_RAM_PARAM_4__PRE 0x0

14164

14165

#define SCU_RAM_PARAM_3__A 0x831FF9

14166

#define SCU_RAM_PARAM_3__W 16

14167

#define SCU_RAM_PARAM_3__M 0xFFFF

14168

#define SCU_RAM_PARAM_3__PRE 0x0

14169

14170

#define SCU_RAM_PARAM_2__A 0x831FFA

14171

#define SCU_RAM_PARAM_2__W 16

14172

#define SCU_RAM_PARAM_2__M 0xFFFF

14173

#define SCU_RAM_PARAM_2__PRE 0x0

14174

14175

#define SCU_RAM_PARAM_1__A 0x831FFB

14176

#define SCU_RAM_PARAM_1__W 16

14177

#define SCU_RAM_PARAM_1__M 0xFFFF

14178

#define SCU_RAM_PARAM_1__PRE 0x0

14179

#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x0

14180

#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x4000

14181

#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x8000

14182

#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC000

14183

14184

14185

#define SCU_RAM_PARAM_0__A 0x831FFC

14186

#define SCU_RAM_PARAM_0__W 16

14187

#define SCU_RAM_PARAM_0__M 0xFFFF

14188

#define SCU_RAM_PARAM_0__PRE 0x0

14189

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x2

14190

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x103

14191

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x3

14192

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x4

14193

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x9

14194

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x109

14195

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA

14196

#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x40

14197

#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x0

14198

#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x1

14199

#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x2

14200

#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x3

14201

#define SCU_RAM_PARAM_0_RESULT_OK 0x0

14202

#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF

14203

#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE

14204

#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD

14205

#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC

14206

14207

14208

#define SCU_RAM_COMMAND__A 0x831FFD

14209

#define SCU_RAM_COMMAND__W 16

14210

#define SCU_RAM_COMMAND__M 0xFFFF

14211

#define SCU_RAM_COMMAND__PRE 0x0

14212

#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1

14213

#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2

14214

#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3

14215

#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4

14216

#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5

14217

#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x6

14218

#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x7

14219

#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x8

14220

#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9

14221

#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x80

14222

#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x81

14223

#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x82

14224

#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x83

14225

#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x84

14226

#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x85

14227

#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x80

14228

#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x81

14229

#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x82

14230

#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x83

14231

#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x84

14232

#define SCU_RAM_COMMAND_CMD_DEBUG_ATV_TIMINGS 0x85

14233

#define SCU_RAM_COMMAND_CMD_DEBUG_SET_IRQ_PRI 0x86

14234

#define SCU_RAM_COMMAND_CMD_DEBUG_GET_PSW 0x87

14235

#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF

14236

#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE

14237

#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD

14238

#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC0

14239

#define SCU_RAM_COMMAND_CMD_AUX_ADC_COMP_RESTART 0xC1

14240

14241

#define SCU_RAM_COMMAND_STANDARD__B 8

14242

#define SCU_RAM_COMMAND_STANDARD__W 8

14243

#define SCU_RAM_COMMAND_STANDARD__M 0xFF00

14244

#define SCU_RAM_COMMAND_STANDARD__PRE 0x0

14245

#define SCU_RAM_COMMAND_STANDARD_ATV 0x100

14246

#define SCU_RAM_COMMAND_STANDARD_QAM 0x200

14247

#define SCU_RAM_COMMAND_STANDARD_VSB 0x300

14248

#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400

14249

#define SCU_RAM_COMMAND_STANDARD_OOB 0x8000

14250

#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF00

14251

14252

#define SCU_RAM_VERSION_HI__A 0x831FFE

14253

#define SCU_RAM_VERSION_HI__W 16

14254

#define SCU_RAM_VERSION_HI__M 0xFFFF

14255

#define SCU_RAM_VERSION_HI__PRE 0x0

14256

14257

#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 12

14258

#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 4

14259

#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF000

14260

#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x0

14261

14262

#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 8

14263

#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 4

14264

#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF00

14265

#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x0

14266

14267

#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 4

14268

#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 4

14269

#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF0

14270

#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x0

14271

14272

#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 0

14273

#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 4

14274

#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF

14275

#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x0

14276

14277

#define SCU_RAM_VERSION_LO__A 0x831FFF

14278

#define SCU_RAM_VERSION_LO__W 16

14279

#define SCU_RAM_VERSION_LO__M 0xFFFF

14280

#define SCU_RAM_VERSION_LO__PRE 0x0

14281

14282

#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 12

14283

#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 4

14284

#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF000

14285

#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x0

14286

14287

#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 8

14288

#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 4

14289

#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF00

14290

#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x0

14291

14292

#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 4

14293

#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 4

14294

#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF0

14295

#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x0

14296

14297

#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 0

14298

#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 4

14299

#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF

14300

#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x0

#define SIO_COMM_EXEC__A 0x400000

14307

#define SIO_COMM_EXEC__W 2

14308

#define SIO_COMM_EXEC__M 0x3

14309

#define SIO_COMM_EXEC__PRE 0x0

14310

#define SIO_COMM_EXEC_STOP 0x0

14311

#define SIO_COMM_EXEC_ACTIVE 0x1

14312

#define SIO_COMM_EXEC_HOLD 0x2

14313

14314

#define SIO_COMM_STATE__A 0x400001

14315

#define SIO_COMM_STATE__W 16

14316

#define SIO_COMM_STATE__M 0xFFFF

14317

#define SIO_COMM_STATE__PRE 0x0

14318

#define SIO_COMM_MB__A 0x400002

14319

#define SIO_COMM_MB__W 16

14320

#define SIO_COMM_MB__M 0xFFFF

14321

#define SIO_COMM_MB__PRE 0x0

14322

#define SIO_COMM_INT_REQ__A 0x400003

14323

#define SIO_COMM_INT_REQ__W 16

14324

#define SIO_COMM_INT_REQ__M 0xFFFF

14325

#define SIO_COMM_INT_REQ__PRE 0x0

14326

14327

#define SIO_COMM_INT_REQ_HI_REQ__B 0

14328

#define SIO_COMM_INT_REQ_HI_REQ__W 1

14329

#define SIO_COMM_INT_REQ_HI_REQ__M 0x1

14330

#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x0

14331

14332

#define SIO_COMM_INT_REQ_SA_REQ__B 1

14333

#define SIO_COMM_INT_REQ_SA_REQ__W 1

14334

#define SIO_COMM_INT_REQ_SA_REQ__M 0x2

14335

#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x0

14336

14337

#define SIO_COMM_INT_REQ_BL_REQ__B 2

14338

#define SIO_COMM_INT_REQ_BL_REQ__W 1

14339

#define SIO_COMM_INT_REQ_BL_REQ__M 0x4

14340

#define SIO_COMM_INT_REQ_BL_REQ__PRE 0x0

14341

14342

#define SIO_COMM_INT_STA__A 0x400005

14343

#define SIO_COMM_INT_STA__W 16

14344

#define SIO_COMM_INT_STA__M 0xFFFF

14345

#define SIO_COMM_INT_STA__PRE 0x0

14346

#define SIO_COMM_INT_MSK__A 0x400006

14347

#define SIO_COMM_INT_MSK__W 16

14348

#define SIO_COMM_INT_MSK__M 0xFFFF

14349

#define SIO_COMM_INT_MSK__PRE 0x0

14350

#define SIO_COMM_INT_STM__A 0x400007

14351

#define SIO_COMM_INT_STM__W 16

14352

#define SIO_COMM_INT_STM__M 0xFFFF

14353

#define SIO_COMM_INT_STM__PRE 0x0

#define SIO_TOP_COMM_EXEC__A 0x410000

14358

#define SIO_TOP_COMM_EXEC__W 2

14359

#define SIO_TOP_COMM_EXEC__M 0x3

14360

#define SIO_TOP_COMM_EXEC__PRE 0x0

14361

#define SIO_TOP_COMM_EXEC_STOP 0x0

14362

#define SIO_TOP_COMM_EXEC_ACTIVE 0x1

14363

#define SIO_TOP_COMM_EXEC_HOLD 0x2

14364

14365

14366

#define SIO_TOP_COMM_KEY__A 0x41000F

14367

#define SIO_TOP_COMM_KEY__W 16

14368

#define SIO_TOP_COMM_KEY__M 0xFFFF

14369

#define SIO_TOP_COMM_KEY__PRE 0x0

14370

#define SIO_TOP_COMM_KEY_KEY 0xFABA

14371

14372

14373

#define SIO_TOP_JTAGID_LO__A 0x410012

14374

#define SIO_TOP_JTAGID_LO__W 16

14375

#define SIO_TOP_JTAGID_LO__M 0xFFFF

14376

#define SIO_TOP_JTAGID_LO__PRE 0x0

14377

14378

#define SIO_TOP_JTAGID_HI__A 0x410013

14379

#define SIO_TOP_JTAGID_HI__W 16

14380

#define SIO_TOP_JTAGID_HI__M 0xFFFF

14381

#define SIO_TOP_JTAGID_HI__PRE 0x0

#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x420010

14387

#define SIO_HI_RA_RAM_S0_FLG_SMM__W 1

14388

#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x1

14389

#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x0

14390

14391

#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x420011

14392

#define SIO_HI_RA_RAM_S0_DEV_ID__W 7

14393

#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F

14394

#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x52

14395

14396

#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x420012

14397

#define SIO_HI_RA_RAM_S0_FLG_CRC__W 1

14398

#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x1

14399

#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x0

14400

#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x420013

14401

#define SIO_HI_RA_RAM_S0_FLG_ACC__W 4

14402

#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF

14403

#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x0

14404

14405

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 0

14406

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 2

14407

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x3

14408

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x0

14409

14410

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 2

14411

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 1

14412

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x4

14413

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x0

14414

14415

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 3

14416

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 1

14417

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x8

14418

#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x0

14419

14420

#define SIO_HI_RA_RAM_S0_STATE__A 0x420014

14421

#define SIO_HI_RA_RAM_S0_STATE__W 1

14422

#define SIO_HI_RA_RAM_S0_STATE__M 0x1

14423

#define SIO_HI_RA_RAM_S0_STATE__PRE 0x0

14424

14425

#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 0

14426

#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 1

14427

#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x1

14428

#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x0

14429

14430

#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x420015

14431

#define SIO_HI_RA_RAM_S0_BLK_BNK__W 12

14432

#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF

14433

#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x82

14434

14435

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 0

14436

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 6

14437

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F

14438

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x2

14439

14440

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 6

14441

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 6

14442

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC0

14443

#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x80

14444

14445

#define SIO_HI_RA_RAM_S0_ADDR__A 0x420016

14446

#define SIO_HI_RA_RAM_S0_ADDR__W 16

14447

#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF

14448

#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x0

14449

14450

#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 0

14451

#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 16

14452

#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF

14453

#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x0

14454

14455

14456

#define SIO_HI_RA_RAM_S0_CRC__A 0x420017

14457

#define SIO_HI_RA_RAM_S0_CRC__W 16

14458

#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF

14459

#define SIO_HI_RA_RAM_S0_CRC__PRE 0x0

14460

14461

#define SIO_HI_RA_RAM_S0_BUFFER__A 0x420018

14462

#define SIO_HI_RA_RAM_S0_BUFFER__W 16

14463

#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF

14464

#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x0

14465

14466

#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x420019

14467

#define SIO_HI_RA_RAM_S0_RMWBUF__W 16

14468

#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF

14469

#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x0

14470

14471

#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A

14472

#define SIO_HI_RA_RAM_S0_FLG_VB__W 1

14473

#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x1

14474

#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x0

14475

14476

#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B

14477

#define SIO_HI_RA_RAM_S0_TEMP0__W 16

14478

#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF

14479

#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x0

14480

14481

#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C

14482

#define SIO_HI_RA_RAM_S0_TEMP1__W 16

14483

#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF

14484

#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x0

14485

14486

#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D

14487

#define SIO_HI_RA_RAM_S0_OFFSET__W 16

14488

#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF

14489

#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x0

14490

14491

#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x420020

14492

#define SIO_HI_RA_RAM_S1_FLG_SMM__W 1

14493

#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x1

14494

#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x0

14495

14496

#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x420021

14497

#define SIO_HI_RA_RAM_S1_DEV_ID__W 7

14498

#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F

14499

#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x52

14500

14501

#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x420022

14502

#define SIO_HI_RA_RAM_S1_FLG_CRC__W 1

14503

#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x1

14504

#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x0

14505

#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x420023

14506

#define SIO_HI_RA_RAM_S1_FLG_ACC__W 4

14507

#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF

14508

#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x0

14509

14510

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 0

14511

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 2

14512

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x3

14513

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x0

14514

14515

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 2

14516

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 1

14517

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x4

14518

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x0

14519

14520

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 3

14521

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 1

14522

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x8

14523

#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x0

14524

14525

#define SIO_HI_RA_RAM_S1_STATE__A 0x420024

14526

#define SIO_HI_RA_RAM_S1_STATE__W 1

14527

#define SIO_HI_RA_RAM_S1_STATE__M 0x1

14528

#define SIO_HI_RA_RAM_S1_STATE__PRE 0x0

14529

14530

#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 0

14531

#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 1

14532

#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x1

14533

#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x0

14534

14535

#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x420025

14536

#define SIO_HI_RA_RAM_S1_BLK_BNK__W 12

14537

#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF

14538

#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x82

14539

14540

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 0

14541

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 6

14542

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F

14543

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x2

14544

14545

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 6

14546

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 6

14547

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC0

14548

#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x80

14549

14550

#define SIO_HI_RA_RAM_S1_ADDR__A 0x420026

14551

#define SIO_HI_RA_RAM_S1_ADDR__W 16

14552

#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF

14553

#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x0

14554

14555

#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 0

14556

#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 16

14557

#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF

14558

#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x0

14559

14560

14561

#define SIO_HI_RA_RAM_S1_CRC__A 0x420027

14562

#define SIO_HI_RA_RAM_S1_CRC__W 16

14563

#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF

14564

#define SIO_HI_RA_RAM_S1_CRC__PRE 0x0

14565

14566

#define SIO_HI_RA_RAM_S1_BUFFER__A 0x420028

14567

#define SIO_HI_RA_RAM_S1_BUFFER__W 16

14568

#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF

14569

#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x0

14570

14571

#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x420029

14572

#define SIO_HI_RA_RAM_S1_RMWBUF__W 16

14573

#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF

14574

#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x0

14575

14576

#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A

14577

#define SIO_HI_RA_RAM_S1_FLG_VB__W 1

14578

#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x1

14579

#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x0

14580

14581

#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B

14582

#define SIO_HI_RA_RAM_S1_TEMP0__W 16

14583

#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF

14584

#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x0

14585

14586

#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C

14587

#define SIO_HI_RA_RAM_S1_TEMP1__W 16

14588

#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF

14589

#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x0

14590

14591

#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D

14592

#define SIO_HI_RA_RAM_S1_OFFSET__W 16

14593

#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF

14594

#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x0

14595

#define SIO_HI_RA_RAM_SEMA__A 0x420030

14596

#define SIO_HI_RA_RAM_SEMA__W 1

14597

#define SIO_HI_RA_RAM_SEMA__M 0x1

14598

#define SIO_HI_RA_RAM_SEMA__PRE 0x0

14599

#define SIO_HI_RA_RAM_SEMA_FREE 0x0

14600

#define SIO_HI_RA_RAM_SEMA_BUSY 0x1

14601

14602

#define SIO_HI_RA_RAM_RES__A 0x420031

14603

#define SIO_HI_RA_RAM_RES__W 3

14604

#define SIO_HI_RA_RAM_RES__M 0x7

14605

#define SIO_HI_RA_RAM_RES__PRE 0x0

14606

#define SIO_HI_RA_RAM_RES_OK 0x0

14607

#define SIO_HI_RA_RAM_RES_ERROR 0x1

14608

#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x1

14609

#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x2

14610

#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x3

14611

#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x4

14612

14613

#define SIO_HI_RA_RAM_CMD__A 0x420032

14614

#define SIO_HI_RA_RAM_CMD__W 4

14615

#define SIO_HI_RA_RAM_CMD__M 0xF

14616

#define SIO_HI_RA_RAM_CMD__PRE 0x0

14617

#define SIO_HI_RA_RAM_CMD_NULL 0x0

14618

#define SIO_HI_RA_RAM_CMD_UIO 0x1

14619

#define SIO_HI_RA_RAM_CMD_RESET 0x2

14620

#define SIO_HI_RA_RAM_CMD_CONFIG 0x3

14621

#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x4

14622

#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x5

14623

#define SIO_HI_RA_RAM_CMD_EXEC 0x6

14624

#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7

14625

#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x8

14626

14627

#define SIO_HI_RA_RAM_PAR_1__A 0x420033

14628

#define SIO_HI_RA_RAM_PAR_1__W 16

14629

#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF

14630

#define SIO_HI_RA_RAM_PAR_1__PRE 0x0

14631

#define SIO_HI_RA_RAM_PAR_1_PAR1__B 0

14632

#define SIO_HI_RA_RAM_PAR_1_PAR1__W 16

14633

#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF

14634

#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x0

14635

#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945

14636

14637

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 0

14638

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 6

14639

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F

14640

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x0

14641

14642

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 6

14643

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 6

14644

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC0

14645

#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x0

14646

14647

#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 0

14648

#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 1

14649

#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x1

14650

#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x0

14651

14652

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 1

14653

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 1

14654

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x2

14655

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x0

14656

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x0

14657

#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x2

14658

14659

#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 0

14660

#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 10

14661

#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF

14662

#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x0

14663

14664

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 0

14665

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 6

14666

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F

14667

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x0

14668

14669

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 6

14670

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 6

14671

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC0

14672

#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x0

14673

14674

#define SIO_HI_RA_RAM_PAR_2__A 0x420034

14675

#define SIO_HI_RA_RAM_PAR_2__W 16

14676

#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF

14677

#define SIO_HI_RA_RAM_PAR_2__PRE 0x0

14678

#define SIO_HI_RA_RAM_PAR_2_PAR2__B 0

14679

#define SIO_HI_RA_RAM_PAR_2_PAR2__W 16

14680

#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF

14681

#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x0

14682

14683

#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 0

14684

#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 7

14685

#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F

14686

#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x25

14687

14688

#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 0

14689

#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 16

14690

#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF

14691

#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x0

14692

14693

#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 0

14694

#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 16

14695

#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF

14696

#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x0

14697

14698

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 2

14699

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 1

14700

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x4

14701

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x0

14702

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0

14703

#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4

14704

14705

#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 0

14706

#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 16

14707

#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF

14708

#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x0

14709

14710

#define SIO_HI_RA_RAM_PAR_3__A 0x420035

14711

#define SIO_HI_RA_RAM_PAR_3__W 16

14712

#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF

14713

#define SIO_HI_RA_RAM_PAR_3__PRE 0x0

14714

#define SIO_HI_RA_RAM_PAR_3_PAR3__B 0

14715

#define SIO_HI_RA_RAM_PAR_3_PAR3__W 16

14716

#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF

14717

#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x0

14718

14719

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 0

14720

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 7

14721

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F

14722

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F

14723

14724

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7

14725

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 7

14726

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F80

14727

#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F80

14728

14729

#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 0

14730

#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 16

14731

#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF

14732

#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x0

14733

14734

#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 0

14735

#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 3

14736

#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x7

14737

#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x0

14738

14739

#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 3

14740

#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 1

14741

#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x8

14742

#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x0

14743

#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0

14744

#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8

14745

14746

#define SIO_HI_RA_RAM_PAR_4__A 0x420036

14747

#define SIO_HI_RA_RAM_PAR_4__W 16

14748

#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF

14749

#define SIO_HI_RA_RAM_PAR_4__PRE 0x0

14750

#define SIO_HI_RA_RAM_PAR_4_PAR4__B 0

14751

#define SIO_HI_RA_RAM_PAR_4_PAR4__W 16

14752

#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF

14753

#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x0

14754

14755

#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 0

14756

#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 8

14757

#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF

14758

#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC1

14759

14760

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 0

14761

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 6

14762

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F

14763

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x0

14764

14765

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 6

14766

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 6

14767

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC0

14768

#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x0

14769

14770

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 0

14771

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 6

14772

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F

14773

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x0

14774

14775

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 6

14776

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 6

14777

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC0

14778

#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x0

14779

14780

#define SIO_HI_RA_RAM_PAR_5__A 0x420037

14781

#define SIO_HI_RA_RAM_PAR_5__W 16

14782

#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF

14783

#define SIO_HI_RA_RAM_PAR_5__PRE 0x0

14784

#define SIO_HI_RA_RAM_PAR_5_PAR5__B 0

14785

#define SIO_HI_RA_RAM_PAR_5_PAR5__W 16

14786

#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF

14787

#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x0

14788

14789

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 0

14790

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 1

14791

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x1

14792

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x0

14793

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x0

14794

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1

14795

14796

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 1

14797

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 1

14798

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x2

14799

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x0

14800

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x0

14801

#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x2

14802

14803

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 3

14804

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 1

14805

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8

14806

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x0

14807

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x0

14808

#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8

14809

14810

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 5

14811

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 1

14812

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x20

14813

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x0

14814

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x0

14815

#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x20

14816

14817

#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 0

14818

#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 16

14819

#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF

14820

#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x0

14821

14822

#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 0

14823

#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 16

14824

#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF

14825

#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x0

14826

14827

#define SIO_HI_RA_RAM_PAR_6__A 0x420038

14828

#define SIO_HI_RA_RAM_PAR_6__W 16

14829

#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF

14830

#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF

14831

#define SIO_HI_RA_RAM_PAR_6_PAR6__B 0

14832

#define SIO_HI_RA_RAM_PAR_6_PAR6__W 16

14833

#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF

14834

#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x0

14835

14836

#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 0

14837

#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 8

14838

#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF

14839

#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF

14840

14841

#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 8

14842

#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 8

14843

#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF00

14844

#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x9500

14845

14846

14847

#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E

14848

#define SIO_HI_RA_RAM_AB_TEMP__W 16

14849

#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF

14850

#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x0

14851

14852

#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F

14853

#define SIO_HI_RA_RAM_I2C_CTL__W 16

14854

#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF

14855

#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x0

14856

14857

#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x420070

14858

#define SIO_HI_RA_RAM_VB_ENTRY0__W 16

14859

#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF

14860

#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x0

14861

14862

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 0

14863

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 4

14864

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF

14865

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x0

14866

14867

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 4

14868

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 4

14869

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF0

14870

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x0

14871

14872

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 8

14873

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 4

14874

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF00

14875

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x0

14876

14877

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 12

14878

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 4

14879

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF000

14880

#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x0

14881

14882

#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x420071

14883

#define SIO_HI_RA_RAM_VB_OFFSET0__W 16

14884

#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF

14885

#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x0

14886

14887

#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 0

14888

#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 16

14889

#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF

14890

#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x0

14891

14892

14893

#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x420072

14894

#define SIO_HI_RA_RAM_VB_ENTRY1__W 16

14895

#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF

14896

#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x0

14897

#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x420073

14898

#define SIO_HI_RA_RAM_VB_OFFSET1__W 16

14899

#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF

14900

#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x0

14901

14902

#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 0

14903

#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 16

14904

#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF

14905

#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x0

14906

14907

14908

#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x420074

14909

#define SIO_HI_RA_RAM_VB_ENTRY2__W 16

14910

#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF

14911

#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x0

14912

#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x420075

14913

#define SIO_HI_RA_RAM_VB_OFFSET2__W 16

14914

#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF

14915

#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x0

14916

14917

#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 0

14918

#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 16

14919

#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF

14920

#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x0

14921

14922

14923

#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x420076

14924

#define SIO_HI_RA_RAM_VB_ENTRY3__W 16

14925

#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF

14926

#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x0

14927

#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x420077

14928

#define SIO_HI_RA_RAM_VB_OFFSET3__W 16

14929

#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF

14930

#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x0

14931

14932

#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 0

14933

#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 16

14934

#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF

14935

#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x0

14936

14937

14938

#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x420078

14939

#define SIO_HI_RA_RAM_VB_ENTRY4__W 16

14940

#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF

14941

#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x0

14942

#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x420079

14943

#define SIO_HI_RA_RAM_VB_OFFSET4__W 16

14944

#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF

14945

#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x0

14946

14947

#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 0

14948

#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 16

14949

#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF

14950

#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x0

14951

14952

14953

#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A

14954

#define SIO_HI_RA_RAM_VB_ENTRY5__W 16

14955

#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF

14956

#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x0

14957

#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B

14958

#define SIO_HI_RA_RAM_VB_OFFSET5__W 16

14959

#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF

14960

#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x0

14961

14962

#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 0

14963

#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 16

14964

#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF

14965

#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x0

14966

14967

14968

#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C

14969

#define SIO_HI_RA_RAM_VB_ENTRY6__W 16

14970

#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF

14971

#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x0

14972

#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D

14973

#define SIO_HI_RA_RAM_VB_OFFSET6__W 16

14974

#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF

14975

#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x0

14976

14977

#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 0

14978

#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 16

14979

#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF

14980

#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x0

14981

14982

14983

#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E

14984

#define SIO_HI_RA_RAM_VB_ENTRY7__W 16

14985

#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF

14986

#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x0

14987

#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F

14988

#define SIO_HI_RA_RAM_VB_OFFSET7__W 16

14989

#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF

14990

#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x0

14991

14992

#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 0

14993

#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 16

14994

#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF

14995

#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x0

#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x430000

15000

#define SIO_HI_IF_RAM_TRP_BPT_0__W 12

15001

#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF

15002

#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x0

15003

#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x430001

15004

#define SIO_HI_IF_RAM_TRP_BPT_1__W 12

15005

#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF

15006

#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x0

15007

#define SIO_HI_IF_RAM_TRP_STK_0__A 0x430002

15008

#define SIO_HI_IF_RAM_TRP_STK_0__W 12

15009

#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF

15010

#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x0

15011

#define SIO_HI_IF_RAM_TRP_STK_1__A 0x430003

15012

#define SIO_HI_IF_RAM_TRP_STK_1__W 12

15013

#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF

15014

#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x0

15015

#define SIO_HI_IF_RAM_FUN_BASE__A 0x430300

15016

#define SIO_HI_IF_RAM_FUN_BASE__W 12

15017

#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF

15018

#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x0

#define SIO_HI_IF_COMM_EXEC__A 0x440000

15023

#define SIO_HI_IF_COMM_EXEC__W 2

15024

#define SIO_HI_IF_COMM_EXEC__M 0x3

15025

#define SIO_HI_IF_COMM_EXEC__PRE 0x0

15026

#define SIO_HI_IF_COMM_EXEC_STOP 0x0

15027

#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x1

15028

#define SIO_HI_IF_COMM_EXEC_HOLD 0x2

15029

#define SIO_HI_IF_COMM_EXEC_STEP 0x3

15030

15031

15032

#define SIO_HI_IF_COMM_STATE__A 0x440001

15033

#define SIO_HI_IF_COMM_STATE__W 10

15034

#define SIO_HI_IF_COMM_STATE__M 0x3FF

15035

#define SIO_HI_IF_COMM_STATE__PRE 0x0

15036

#define SIO_HI_IF_COMM_INT_REQ__A 0x440003

15037

#define SIO_HI_IF_COMM_INT_REQ__W 1

15038

#define SIO_HI_IF_COMM_INT_REQ__M 0x1

15039

#define SIO_HI_IF_COMM_INT_REQ__PRE 0x0

15040

#define SIO_HI_IF_COMM_INT_STA__A 0x440005

15041

#define SIO_HI_IF_COMM_INT_STA__W 1

15042

#define SIO_HI_IF_COMM_INT_STA__M 0x1

15043

#define SIO_HI_IF_COMM_INT_STA__PRE 0x0

15044

#define SIO_HI_IF_COMM_INT_STA_STAT__B 0

15045

#define SIO_HI_IF_COMM_INT_STA_STAT__W 1

15046

#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x1

15047

#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x0

15048

15049

#define SIO_HI_IF_COMM_INT_MSK__A 0x440006

15050

#define SIO_HI_IF_COMM_INT_MSK__W 1

15051

#define SIO_HI_IF_COMM_INT_MSK__M 0x1

15052

#define SIO_HI_IF_COMM_INT_MSK__PRE 0x0

15053

#define SIO_HI_IF_COMM_INT_MSK_STAT__B 0

15054

#define SIO_HI_IF_COMM_INT_MSK_STAT__W 1

15055

#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x1

15056

#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x0

15057

15058

#define SIO_HI_IF_COMM_INT_STM__A 0x440007

15059

#define SIO_HI_IF_COMM_INT_STM__W 1

15060

#define SIO_HI_IF_COMM_INT_STM__M 0x1

15061

#define SIO_HI_IF_COMM_INT_STM__PRE 0x0

15062

#define SIO_HI_IF_COMM_INT_STM_STAT__B 0

15063

#define SIO_HI_IF_COMM_INT_STM_STAT__W 1

15064

#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x1

15065

#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x0

15066

15067

#define SIO_HI_IF_STK_0__A 0x440010

15068

#define SIO_HI_IF_STK_0__W 10

15069

#define SIO_HI_IF_STK_0__M 0x3FF

15070

#define SIO_HI_IF_STK_0__PRE 0x2

15071

15072

#define SIO_HI_IF_STK_0_ADDR__B 0

15073

#define SIO_HI_IF_STK_0_ADDR__W 10

15074

#define SIO_HI_IF_STK_0_ADDR__M 0x3FF

15075

#define SIO_HI_IF_STK_0_ADDR__PRE 0x2

15076

15077

#define SIO_HI_IF_STK_1__A 0x440011

15078

#define SIO_HI_IF_STK_1__W 10

15079

#define SIO_HI_IF_STK_1__M 0x3FF

15080

#define SIO_HI_IF_STK_1__PRE 0x2

15081

#define SIO_HI_IF_STK_1_ADDR__B 0

15082

#define SIO_HI_IF_STK_1_ADDR__W 10

15083

#define SIO_HI_IF_STK_1_ADDR__M 0x3FF

15084

#define SIO_HI_IF_STK_1_ADDR__PRE 0x2

15085

15086

#define SIO_HI_IF_STK_2__A 0x440012

15087

#define SIO_HI_IF_STK_2__W 10

15088

#define SIO_HI_IF_STK_2__M 0x3FF

15089

#define SIO_HI_IF_STK_2__PRE 0x2

15090

#define SIO_HI_IF_STK_2_ADDR__B 0

15091

#define SIO_HI_IF_STK_2_ADDR__W 10

15092

#define SIO_HI_IF_STK_2_ADDR__M 0x3FF

15093

#define SIO_HI_IF_STK_2_ADDR__PRE 0x2

15094

15095

#define SIO_HI_IF_STK_3__A 0x440013

15096

#define SIO_HI_IF_STK_3__W 10

15097

#define SIO_HI_IF_STK_3__M 0x3FF

15098

#define SIO_HI_IF_STK_3__PRE 0x2

15099

15100

#define SIO_HI_IF_STK_3_ADDR__B 0

15101

#define SIO_HI_IF_STK_3_ADDR__W 10

15102

#define SIO_HI_IF_STK_3_ADDR__M 0x3FF

15103

#define SIO_HI_IF_STK_3_ADDR__PRE 0x2

15104

15105

#define SIO_HI_IF_BPT_IDX__A 0x44001F

15106

#define SIO_HI_IF_BPT_IDX__W 1

15107

#define SIO_HI_IF_BPT_IDX__M 0x1

15108

#define SIO_HI_IF_BPT_IDX__PRE 0x0

15109

15110

#define SIO_HI_IF_BPT_IDX_ADDR__B 0

15111

#define SIO_HI_IF_BPT_IDX_ADDR__W 1

15112

#define SIO_HI_IF_BPT_IDX_ADDR__M 0x1

15113

#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x0

15114

15115

#define SIO_HI_IF_BPT__A 0x440020

15116

#define SIO_HI_IF_BPT__W 10

15117

#define SIO_HI_IF_BPT__M 0x3FF

15118

#define SIO_HI_IF_BPT__PRE 0x2

15119

15120

#define SIO_HI_IF_BPT_ADDR__B 0

15121

#define SIO_HI_IF_BPT_ADDR__W 10

15122

#define SIO_HI_IF_BPT_ADDR__M 0x3FF

15123

#define SIO_HI_IF_BPT_ADDR__PRE 0x2

#define SIO_CC_COMM_EXEC__A 0x450000

15128

#define SIO_CC_COMM_EXEC__W 2

15129

#define SIO_CC_COMM_EXEC__M 0x3

15130

#define SIO_CC_COMM_EXEC__PRE 0x0

15131

#define SIO_CC_COMM_EXEC_STOP 0x0

15132

#define SIO_CC_COMM_EXEC_ACTIVE 0x1

15133

#define SIO_CC_COMM_EXEC_HOLD 0x2

15134

15135

#define SIO_CC_PLL_MODE__A 0x450010

15136

#define SIO_CC_PLL_MODE__W 6

15137

#define SIO_CC_PLL_MODE__M 0x3F

15138

#define SIO_CC_PLL_MODE__PRE 0x0

15139

15140

#define SIO_CC_PLL_MODE_FREF_SEL__B 0

15141

#define SIO_CC_PLL_MODE_FREF_SEL__W 2

15142

#define SIO_CC_PLL_MODE_FREF_SEL__M 0x3

15143

#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x0

15144

#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x0

15145

#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x1

15146

#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x2

15147

#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x3

15148

15149

#define SIO_CC_PLL_MODE_LOCKSEL__B 2

15150

#define SIO_CC_PLL_MODE_LOCKSEL__W 2

15151

#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC

15152

#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x0

15153

15154

#define SIO_CC_PLL_MODE_BYPASS__B 4

15155

#define SIO_CC_PLL_MODE_BYPASS__W 2

15156

#define SIO_CC_PLL_MODE_BYPASS__M 0x30

15157

#define SIO_CC_PLL_MODE_BYPASS__PRE 0x0

15158

#define SIO_CC_PLL_MODE_BYPASS_OHW 0x0

15159

#define SIO_CC_PLL_MODE_BYPASS_OFF 0x10

15160

#define SIO_CC_PLL_MODE_BYPASS_ON 0x20

15161

15162

15163

#define SIO_CC_PLL_TEST__A 0x450011

15164

#define SIO_CC_PLL_TEST__W 8

15165

#define SIO_CC_PLL_TEST__M 0xFF

15166

#define SIO_CC_PLL_TEST__PRE 0x0

15167

15168

#define SIO_CC_PLL_LOCK__A 0x450012

15169

#define SIO_CC_PLL_LOCK__W 1

15170

#define SIO_CC_PLL_LOCK__M 0x1

15171

#define SIO_CC_PLL_LOCK__PRE 0x0

15172

#define SIO_CC_CLK_TEST__A 0x450013

15173

#define SIO_CC_CLK_TEST__W 8

15174

#define SIO_CC_CLK_TEST__M 0xFF

15175

#define SIO_CC_CLK_TEST__PRE 0x0

15176

15177

#define SIO_CC_CLK_TEST_SEL1__B 0

15178

#define SIO_CC_CLK_TEST_SEL1__W 3

15179

#define SIO_CC_CLK_TEST_SEL1__M 0x7

15180

#define SIO_CC_CLK_TEST_SEL1__PRE 0x0

15181

15182

#define SIO_CC_CLK_TEST_ENAB1__B 3

15183

#define SIO_CC_CLK_TEST_ENAB1__W 1

15184

#define SIO_CC_CLK_TEST_ENAB1__M 0x8

15185

#define SIO_CC_CLK_TEST_ENAB1__PRE 0x0

15186

15187

#define SIO_CC_CLK_TEST_SEL2__B 4

15188

#define SIO_CC_CLK_TEST_SEL2__W 3

15189

#define SIO_CC_CLK_TEST_SEL2__M 0x70

15190

#define SIO_CC_CLK_TEST_SEL2__PRE 0x0

15191

15192

#define SIO_CC_CLK_TEST_ENAB2__B 7

15193

#define SIO_CC_CLK_TEST_ENAB2__W 1

15194

#define SIO_CC_CLK_TEST_ENAB2__M 0x80

15195

#define SIO_CC_CLK_TEST_ENAB2__PRE 0x0

15196

15197

#define SIO_CC_CLK_MODE__A 0x450014

15198

#define SIO_CC_CLK_MODE__W 7

15199

#define SIO_CC_CLK_MODE__M 0x7F

15200

#define SIO_CC_CLK_MODE__PRE 0x0

15201

15202

#define SIO_CC_CLK_MODE_DELAY__B 0

15203

#define SIO_CC_CLK_MODE_DELAY__W 4

15204

#define SIO_CC_CLK_MODE_DELAY__M 0xF

15205

#define SIO_CC_CLK_MODE_DELAY__PRE 0x0

15206

15207

#define SIO_CC_CLK_MODE_INVERT__B 4

15208

#define SIO_CC_CLK_MODE_INVERT__W 1

15209

#define SIO_CC_CLK_MODE_INVERT__M 0x10

15210

#define SIO_CC_CLK_MODE_INVERT__PRE 0x0

15211

15212

#define SIO_CC_CLK_MODE_OFDM_ALIGN__B 5

15213

#define SIO_CC_CLK_MODE_OFDM_ALIGN__W 1

15214

#define SIO_CC_CLK_MODE_OFDM_ALIGN__M 0x20

15215

#define SIO_CC_CLK_MODE_OFDM_ALIGN__PRE 0x0

15216

15217

#define SIO_CC_CLK_MODE_OFDM_DUTYC__B 6

15218

#define SIO_CC_CLK_MODE_OFDM_DUTYC__W 1

15219

#define SIO_CC_CLK_MODE_OFDM_DUTYC__M 0x40

15220

#define SIO_CC_CLK_MODE_OFDM_DUTYC__PRE 0x0

15221

15222

#define SIO_CC_PWD_MODE__A 0x450015

15223

#define SIO_CC_PWD_MODE__W 4

15224

#define SIO_CC_PWD_MODE__M 0xF

15225

#define SIO_CC_PWD_MODE__PRE 0x0

15226

15227

#define SIO_CC_PWD_MODE_LEVEL__B 0

15228

#define SIO_CC_PWD_MODE_LEVEL__W 3

15229

#define SIO_CC_PWD_MODE_LEVEL__M 0x7

15230

#define SIO_CC_PWD_MODE_LEVEL__PRE 0x0

15231

#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0

15232

#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1

15233

#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2

15234

#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3

15235

#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4

15236

15237

#define SIO_CC_PWD_MODE_USE_LOCK__B 3

15238

#define SIO_CC_PWD_MODE_USE_LOCK__W 1

15239

#define SIO_CC_PWD_MODE_USE_LOCK__M 0x8

15240

#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x0

15241

15242

#define SIO_CC_SOFT_RST__A 0x450016

15243

#define SIO_CC_SOFT_RST__W 3

15244

#define SIO_CC_SOFT_RST__M 0x7

15245

#define SIO_CC_SOFT_RST__PRE 0x0

15246

15247

#define SIO_CC_SOFT_RST_OFDM__B 0

15248

#define SIO_CC_SOFT_RST_OFDM__W 1

15249

#define SIO_CC_SOFT_RST_OFDM__M 0x1

15250

#define SIO_CC_SOFT_RST_OFDM__PRE 0x0

15251

15252

#define SIO_CC_SOFT_RST_SYS__B 1

15253

#define SIO_CC_SOFT_RST_SYS__W 1

15254

#define SIO_CC_SOFT_RST_SYS__M 0x2

15255

#define SIO_CC_SOFT_RST_SYS__PRE 0x0

15256

15257

#define SIO_CC_SOFT_RST_OSC__B 2

15258

#define SIO_CC_SOFT_RST_OSC__W 1

15259

#define SIO_CC_SOFT_RST_OSC__M 0x4

15260

#define SIO_CC_SOFT_RST_OSC__PRE 0x0

15261

15262

15263

#define SIO_CC_UPDATE__A 0x450017

15264

#define SIO_CC_UPDATE__W 16

15265

#define SIO_CC_UPDATE__M 0xFFFF

15266

#define SIO_CC_UPDATE__PRE 0x0

15267

#define SIO_CC_UPDATE_KEY 0xFABA

#define SIO_SA_COMM_EXEC__A 0x460000

15272

#define SIO_SA_COMM_EXEC__W 2

15273

#define SIO_SA_COMM_EXEC__M 0x3

15274

#define SIO_SA_COMM_EXEC__PRE 0x0

15275

#define SIO_SA_COMM_EXEC_STOP 0x0

15276

#define SIO_SA_COMM_EXEC_ACTIVE 0x1

15277

#define SIO_SA_COMM_EXEC_HOLD 0x2

15278

15279

#define SIO_SA_COMM_INT_REQ__A 0x460003

15280

#define SIO_SA_COMM_INT_REQ__W 1

15281

#define SIO_SA_COMM_INT_REQ__M 0x1

15282

#define SIO_SA_COMM_INT_REQ__PRE 0x0

15283

#define SIO_SA_COMM_INT_STA__A 0x460005

15284

#define SIO_SA_COMM_INT_STA__W 4

15285

#define SIO_SA_COMM_INT_STA__M 0xF

15286

#define SIO_SA_COMM_INT_STA__PRE 0x0

15287

15288

#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 0

15289

#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 1

15290

#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x1

15291

#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x0

15292

15293

#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 1

15294

#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 1

15295

#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x2

15296

#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x0

15297

15298

#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 2

15299

#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 1

15300

#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x4

15301

#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x0

15302

15303

#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 3

15304

#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 1

15305

#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x8

15306

#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x0

15307

15308

#define SIO_SA_COMM_INT_MSK__A 0x460006

15309

#define SIO_SA_COMM_INT_MSK__W 4

15310

#define SIO_SA_COMM_INT_MSK__M 0xF

15311

#define SIO_SA_COMM_INT_MSK__PRE 0x0

15312

15313

#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 0

15314

#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 1

15315

#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x1

15316

#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x0

15317

15318

#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 1

15319

#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 1

15320

#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x2

15321

#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x0

15322

15323

#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 2

15324

#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 1

15325

#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x4

15326

#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x0

15327

15328

#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 3

15329

#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 1

15330

#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x8

15331

#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x0

15332

15333

#define SIO_SA_COMM_INT_STM__A 0x460007

15334

#define SIO_SA_COMM_INT_STM__W 4

15335

#define SIO_SA_COMM_INT_STM__M 0xF

15336

#define SIO_SA_COMM_INT_STM__PRE 0x0

15337

15338

#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 0

15339

#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 1

15340

#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x1

15341

#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x0

15342

15343

#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 1

15344

#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 1

15345

#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x2

15346

#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x0

15347

15348

#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 2

15349

#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 1

15350

#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x4

15351

#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x0

15352

15353

#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 3

15354

#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 1

15355

#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x8

15356

#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x0

15357

15358

#define SIO_SA_PRESCALER__A 0x460010

15359

#define SIO_SA_PRESCALER__W 13

15360

#define SIO_SA_PRESCALER__M 0x1FFF

15361

#define SIO_SA_PRESCALER__PRE 0x18B7

15362

#define SIO_SA_TX_DATA0__A 0x460011

15363

#define SIO_SA_TX_DATA0__W 16

15364

#define SIO_SA_TX_DATA0__M 0xFFFF

15365

#define SIO_SA_TX_DATA0__PRE 0x0

15366

#define SIO_SA_TX_DATA1__A 0x460012

15367

#define SIO_SA_TX_DATA1__W 16

15368

#define SIO_SA_TX_DATA1__M 0xFFFF

15369

#define SIO_SA_TX_DATA1__PRE 0x0

15370

#define SIO_SA_TX_DATA2__A 0x460013

15371

#define SIO_SA_TX_DATA2__W 16

15372

#define SIO_SA_TX_DATA2__M 0xFFFF

15373

#define SIO_SA_TX_DATA2__PRE 0x0

15374

#define SIO_SA_TX_DATA3__A 0x460014

15375

#define SIO_SA_TX_DATA3__W 16

15376

#define SIO_SA_TX_DATA3__M 0xFFFF

15377

#define SIO_SA_TX_DATA3__PRE 0x0

15378

#define SIO_SA_TX_LENGTH__A 0x460015

15379

#define SIO_SA_TX_LENGTH__W 6

15380

#define SIO_SA_TX_LENGTH__M 0x3F

15381

#define SIO_SA_TX_LENGTH__PRE 0x0

15382

#define SIO_SA_TX_COMMAND__A 0x460016

15383

#define SIO_SA_TX_COMMAND__W 2

15384

#define SIO_SA_TX_COMMAND__M 0x3

15385

#define SIO_SA_TX_COMMAND__PRE 0x3

15386

15387

#define SIO_SA_TX_COMMAND_TX_INVERT__B 0

15388

#define SIO_SA_TX_COMMAND_TX_INVERT__W 1

15389

#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x1

15390

#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x1

15391

15392

#define SIO_SA_TX_COMMAND_TX_ENABLE__B 1

15393

#define SIO_SA_TX_COMMAND_TX_ENABLE__W 1

15394

#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x2

15395

#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x2

15396

15397

#define SIO_SA_TX_STATUS__A 0x460017

15398

#define SIO_SA_TX_STATUS__W 2

15399

#define SIO_SA_TX_STATUS__M 0x3

15400

#define SIO_SA_TX_STATUS__PRE 0x0

15401

15402

#define SIO_SA_TX_STATUS_BUSY__B 0

15403

#define SIO_SA_TX_STATUS_BUSY__W 1

15404

#define SIO_SA_TX_STATUS_BUSY__M 0x1

15405

#define SIO_SA_TX_STATUS_BUSY__PRE 0x0

15406

15407

#define SIO_SA_TX_STATUS_BUFF_FULL__B 1

15408

#define SIO_SA_TX_STATUS_BUFF_FULL__W 1

15409

#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x2

15410

#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x0

15411

15412

#define SIO_SA_RX_DATA0__A 0x460018

15413

#define SIO_SA_RX_DATA0__W 16

15414

#define SIO_SA_RX_DATA0__M 0xFFFF

15415

#define SIO_SA_RX_DATA0__PRE 0x0

15416

#define SIO_SA_RX_DATA1__A 0x460019

15417

#define SIO_SA_RX_DATA1__W 16

15418

#define SIO_SA_RX_DATA1__M 0xFFFF

15419

#define SIO_SA_RX_DATA1__PRE 0x0

15420

#define SIO_SA_RX_LENGTH__A 0x46001A

15421

#define SIO_SA_RX_LENGTH__W 6

15422

#define SIO_SA_RX_LENGTH__M 0x3F

15423

#define SIO_SA_RX_LENGTH__PRE 0x0

15424

#define SIO_SA_RX_COMMAND__A 0x46001B

15425

#define SIO_SA_RX_COMMAND__W 1

15426

#define SIO_SA_RX_COMMAND__M 0x1

15427

#define SIO_SA_RX_COMMAND__PRE 0x1

15428

15429

#define SIO_SA_RX_COMMAND_RX_INVERT__B 0

15430

#define SIO_SA_RX_COMMAND_RX_INVERT__W 1

15431

#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x1

15432

#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x1

15433

15434

#define SIO_SA_RX_STATUS__A 0x46001C

15435

#define SIO_SA_RX_STATUS__W 2

15436

#define SIO_SA_RX_STATUS__M 0x3

15437

#define SIO_SA_RX_STATUS__PRE 0x0

15438

15439

#define SIO_SA_RX_STATUS_BUSY__B 0

15440

#define SIO_SA_RX_STATUS_BUSY__W 1

15441

#define SIO_SA_RX_STATUS_BUSY__M 0x1

15442

#define SIO_SA_RX_STATUS_BUSY__PRE 0x0

15443

15444

#define SIO_SA_RX_STATUS_BUFF_FULL__B 1

15445

#define SIO_SA_RX_STATUS_BUFF_FULL__W 1

15446

#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x2

15447

#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x0

#define SIO_OFDM_SH_COMM_EXEC__A 0x470000

15452

#define SIO_OFDM_SH_COMM_EXEC__W 2

15453

#define SIO_OFDM_SH_COMM_EXEC__M 0x3

15454

#define SIO_OFDM_SH_COMM_EXEC__PRE 0x0

15455

#define SIO_OFDM_SH_COMM_EXEC_STOP 0x0

15456

#define SIO_OFDM_SH_COMM_EXEC_ACTIVE 0x1

15457

#define SIO_OFDM_SH_COMM_EXEC_HOLD 0x2

15458

15459

#define SIO_OFDM_SH_COMM_MB__A 0x470002

15460

#define SIO_OFDM_SH_COMM_MB__W 2

15461

#define SIO_OFDM_SH_COMM_MB__M 0x3

15462

#define SIO_OFDM_SH_COMM_MB__PRE 0x0

15463

#define SIO_OFDM_SH_COMM_MB_CTL__B 0

15464

#define SIO_OFDM_SH_COMM_MB_CTL__W 1

15465

#define SIO_OFDM_SH_COMM_MB_CTL__M 0x1

15466

#define SIO_OFDM_SH_COMM_MB_CTL__PRE 0x0

15467

#define SIO_OFDM_SH_COMM_MB_CTL_OFF 0x0

15468

#define SIO_OFDM_SH_COMM_MB_CTL_ON 0x1

15469

#define SIO_OFDM_SH_COMM_MB_OBS__B 1

15470

#define SIO_OFDM_SH_COMM_MB_OBS__W 1

15471

#define SIO_OFDM_SH_COMM_MB_OBS__M 0x2

15472

#define SIO_OFDM_SH_COMM_MB_OBS__PRE 0x0

15473

#define SIO_OFDM_SH_COMM_MB_OBS_OFF 0x0

15474

#define SIO_OFDM_SH_COMM_MB_OBS_ON 0x2

15475

15476

#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010

15477

#define SIO_OFDM_SH_OFDM_RING_ENABLE__W 1

15478

#define SIO_OFDM_SH_OFDM_RING_ENABLE__M 0x1

15479

#define SIO_OFDM_SH_OFDM_RING_ENABLE__PRE 0x0

15480

#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0

15481

#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1

15482

15483

#define SIO_OFDM_SH_OFDM_MB_CONTROL__A 0x470011

15484

#define SIO_OFDM_SH_OFDM_MB_CONTROL__W 2

15485

#define SIO_OFDM_SH_OFDM_MB_CONTROL__M 0x3

15486

#define SIO_OFDM_SH_OFDM_MB_CONTROL__PRE 0x0

15487

15488

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__B 0

15489

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__W 1

15490

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__M 0x1

15491

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL__PRE 0x0

15492

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OPEN 0x0

15493

#define SIO_OFDM_SH_OFDM_MB_CONTROL_CTL_OFDM 0x1

15494

15495

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__B 1

15496

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__W 1

15497

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__M 0x2

15498

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS__PRE 0x0

15499

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_BYPASS 0x0

15500

#define SIO_OFDM_SH_OFDM_MB_CONTROL_OBS_OFDM 0x2

15501

15502

#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012

15503

#define SIO_OFDM_SH_OFDM_RING_STATUS__W 1

15504

#define SIO_OFDM_SH_OFDM_RING_STATUS__M 0x1

15505

#define SIO_OFDM_SH_OFDM_RING_STATUS__PRE 0x0

15506

#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0

15507

#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1

15508

15509

#define SIO_OFDM_SH_OFDM_MB_FLEN__A 0x470013

15510

#define SIO_OFDM_SH_OFDM_MB_FLEN__W 3

15511

#define SIO_OFDM_SH_OFDM_MB_FLEN__M 0x7

15512

#define SIO_OFDM_SH_OFDM_MB_FLEN__PRE 0x6

15513

#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__B 0

15514

#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__W 3

15515

#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__M 0x7

15516

#define SIO_OFDM_SH_OFDM_MB_FLEN_LEN__PRE 0x6

#define SIO_BL_COMM_EXEC__A 0x480000

15521

#define SIO_BL_COMM_EXEC__W 2

15522

#define SIO_BL_COMM_EXEC__M 0x3

15523

#define SIO_BL_COMM_EXEC__PRE 0x0

15524

#define SIO_BL_COMM_EXEC_STOP 0x0

15525

#define SIO_BL_COMM_EXEC_ACTIVE 0x1

15526

#define SIO_BL_COMM_EXEC_HOLD 0x2

15527

15528

#define SIO_BL_COMM_INT_REQ__A 0x480003

15529

#define SIO_BL_COMM_INT_REQ__W 1

15530

#define SIO_BL_COMM_INT_REQ__M 0x1

15531

#define SIO_BL_COMM_INT_REQ__PRE 0x0

15532

#define SIO_BL_COMM_INT_STA__A 0x480005

15533

#define SIO_BL_COMM_INT_STA__W 1

15534

#define SIO_BL_COMM_INT_STA__M 0x1

15535

#define SIO_BL_COMM_INT_STA__PRE 0x0

15536

15537

#define SIO_BL_COMM_INT_STA_DONE_INT_STA__B 0

15538

#define SIO_BL_COMM_INT_STA_DONE_INT_STA__W 1

15539

#define SIO_BL_COMM_INT_STA_DONE_INT_STA__M 0x1

15540

#define SIO_BL_COMM_INT_STA_DONE_INT_STA__PRE 0x0

15541

15542

#define SIO_BL_COMM_INT_MSK__A 0x480006

15543

#define SIO_BL_COMM_INT_MSK__W 1

15544

#define SIO_BL_COMM_INT_MSK__M 0x1

15545

#define SIO_BL_COMM_INT_MSK__PRE 0x0

15546

15547

#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__B 0

15548

#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__W 1

15549

#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__M 0x1

15550

#define SIO_BL_COMM_INT_MSK_DONE_INT_MSK__PRE 0x0

15551

15552

#define SIO_BL_COMM_INT_STM__A 0x480007

15553

#define SIO_BL_COMM_INT_STM__W 1

15554

#define SIO_BL_COMM_INT_STM__M 0x1

15555

#define SIO_BL_COMM_INT_STM__PRE 0x0

15556

15557

#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__B 0

15558

#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__W 1

15559

#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__M 0x1

15560

#define SIO_BL_COMM_INT_STM_DONE_INT_MSK__PRE 0x0

15561

15562

#define SIO_BL_STATUS__A 0x480010

15563

#define SIO_BL_STATUS__W 1

15564

#define SIO_BL_STATUS__M 0x1

15565

#define SIO_BL_STATUS__PRE 0x0

15566

#define SIO_BL_MODE__A 0x480011

15567

#define SIO_BL_MODE__W 1

15568

#define SIO_BL_MODE__M 0x1

15569

#define SIO_BL_MODE__PRE 0x1

15570

#define SIO_BL_MODE_DIRECT 0x0

15571

#define SIO_BL_MODE_CHAIN 0x1

15572

15573

#define SIO_BL_ENABLE__A 0x480012

15574

#define SIO_BL_ENABLE__W 1

15575

#define SIO_BL_ENABLE__M 0x1

15576

#define SIO_BL_ENABLE__PRE 0x0

15577

#define SIO_BL_ENABLE_OFF 0x0

15578

#define SIO_BL_ENABLE_ON 0x1

15579

15580

#define SIO_BL_TGT_HDR__A 0x480014

15581

#define SIO_BL_TGT_HDR__W 12

15582

#define SIO_BL_TGT_HDR__M 0xFFF

15583

#define SIO_BL_TGT_HDR__PRE 0x0

15584

#define SIO_BL_TGT_HDR_BANK__B 0

15585

#define SIO_BL_TGT_HDR_BANK__W 6

15586

#define SIO_BL_TGT_HDR_BANK__M 0x3F

15587

#define SIO_BL_TGT_HDR_BANK__PRE 0x0

15588

#define SIO_BL_TGT_HDR_BLOCK__B 6

15589

#define SIO_BL_TGT_HDR_BLOCK__W 6

15590

#define SIO_BL_TGT_HDR_BLOCK__M 0xFC0

15591

#define SIO_BL_TGT_HDR_BLOCK__PRE 0x0

15592

15593

#define SIO_BL_TGT_ADDR__A 0x480015

15594

#define SIO_BL_TGT_ADDR__W 16

15595

#define SIO_BL_TGT_ADDR__M 0xFFFF

15596

#define SIO_BL_TGT_ADDR__PRE 0x0

15597

#define SIO_BL_SRC_ADDR__A 0x480016

15598

#define SIO_BL_SRC_ADDR__W 16

15599

#define SIO_BL_SRC_ADDR__M 0xFFFF

15600

#define SIO_BL_SRC_ADDR__PRE 0x0

15601

#define SIO_BL_SRC_LEN__A 0x480017

15602

#define SIO_BL_SRC_LEN__W 16

15603

#define SIO_BL_SRC_LEN__M 0xFFFF

15604

#define SIO_BL_SRC_LEN__PRE 0x0

15605

15606

#define SIO_BL_CHAIN_ADDR__A 0x480018

15607

#define SIO_BL_CHAIN_ADDR__W 16

15608

#define SIO_BL_CHAIN_ADDR__M 0xFFFF

15609

#define SIO_BL_CHAIN_ADDR__PRE 0x0

15610

15611

#define SIO_BL_CHAIN_LEN__A 0x480019

15612

#define SIO_BL_CHAIN_LEN__W 4

15613

#define SIO_BL_CHAIN_LEN__M 0xF

15614

#define SIO_BL_CHAIN_LEN__PRE 0x2

#define SIO_OFDM_SH_TRB_R0_RAM__A 0x4C0000

#define SIO_OFDM_SH_TRB_R1_RAM__A 0x4D0000

#define SIO_BL_ROM__A 0x4E0000

#define SIO_PDR_COMM_EXEC__A 0x7F0000

15631

#define SIO_PDR_COMM_EXEC__W 2

15632

#define SIO_PDR_COMM_EXEC__M 0x3

15633

#define SIO_PDR_COMM_EXEC__PRE 0x0

15634

#define SIO_PDR_COMM_EXEC_STOP 0x0

15635

#define SIO_PDR_COMM_EXEC_ACTIVE 0x1

15636

#define SIO_PDR_COMM_EXEC_HOLD 0x2

15637

15638

#define SIO_PDR_MON_CFG__A 0x7F0010

15639

#define SIO_PDR_MON_CFG__W 4

15640

#define SIO_PDR_MON_CFG__M 0xF

15641

#define SIO_PDR_MON_CFG__PRE 0x0

15642

15643

#define SIO_PDR_MON_CFG_OSEL__B 0

15644

#define SIO_PDR_MON_CFG_OSEL__W 1

15645

#define SIO_PDR_MON_CFG_OSEL__M 0x1

15646

#define SIO_PDR_MON_CFG_OSEL__PRE 0x0

15647

15648

#define SIO_PDR_MON_CFG_IACT__B 1

15649

#define SIO_PDR_MON_CFG_IACT__W 1

15650

#define SIO_PDR_MON_CFG_IACT__M 0x2

15651

#define SIO_PDR_MON_CFG_IACT__PRE 0x0

15652

15653

#define SIO_PDR_MON_CFG_ISEL__B 2

15654

#define SIO_PDR_MON_CFG_ISEL__W 1

15655

#define SIO_PDR_MON_CFG_ISEL__M 0x4

15656

#define SIO_PDR_MON_CFG_ISEL__PRE 0x0

15657

15658

#define SIO_PDR_MON_CFG_INV_CLK__B 3

15659

#define SIO_PDR_MON_CFG_INV_CLK__W 1

15660

#define SIO_PDR_MON_CFG_INV_CLK__M 0x8

15661

#define SIO_PDR_MON_CFG_INV_CLK__PRE 0x0

15662

15663

#define SIO_PDR_SMA_RX_SEL__A 0x7F0012

15664

#define SIO_PDR_SMA_RX_SEL__W 4

15665

#define SIO_PDR_SMA_RX_SEL__M 0xF

15666

#define SIO_PDR_SMA_RX_SEL__PRE 0x0

15667

15668

#define SIO_PDR_SMA_RX_SEL_SEL__B 0

15669

#define SIO_PDR_SMA_RX_SEL_SEL__W 4

15670

#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF

15671

#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x0

15672

15673

#define SIO_PDR_SILENT__A 0x7F0013

15674

#define SIO_PDR_SILENT__W 13

15675

#define SIO_PDR_SILENT__M 0x1FFF

15676

#define SIO_PDR_SILENT__PRE 0x0

15677

15678

#define SIO_PDR_SILENT_I2S_WS__B 0

15679

#define SIO_PDR_SILENT_I2S_WS__W 1

15680

#define SIO_PDR_SILENT_I2S_WS__M 0x1

15681

#define SIO_PDR_SILENT_I2S_WS__PRE 0x0

15682

15683

#define SIO_PDR_SILENT_I2S_DA__B 1

15684

#define SIO_PDR_SILENT_I2S_DA__W 1

15685

#define SIO_PDR_SILENT_I2S_DA__M 0x2

15686

#define SIO_PDR_SILENT_I2S_DA__PRE 0x0

15687

15688

#define SIO_PDR_SILENT_I2S_CL__B 2

15689

#define SIO_PDR_SILENT_I2S_CL__W 1

15690

#define SIO_PDR_SILENT_I2S_CL__M 0x4

15691

#define SIO_PDR_SILENT_I2S_CL__PRE 0x0

15692

15693

#define SIO_PDR_SILENT_I2C_SCL2__B 3

15694

#define SIO_PDR_SILENT_I2C_SCL2__W 1

15695

#define SIO_PDR_SILENT_I2C_SCL2__M 0x8

15696

#define SIO_PDR_SILENT_I2C_SCL2__PRE 0x0

15697

15698

#define SIO_PDR_SILENT_I2C_SDA2__B 4

15699

#define SIO_PDR_SILENT_I2C_SDA2__W 1

15700

#define SIO_PDR_SILENT_I2C_SDA2__M 0x10

15701

#define SIO_PDR_SILENT_I2C_SDA2__PRE 0x0

15702

15703

#define SIO_PDR_SILENT_SMA_TX__B 8

15704

#define SIO_PDR_SILENT_SMA_TX__W 1

15705

#define SIO_PDR_SILENT_SMA_TX__M 0x100

15706

#define SIO_PDR_SILENT_SMA_TX__PRE 0x0

15707

15708

#define SIO_PDR_SILENT_SMA_RX__B 9

15709

#define SIO_PDR_SILENT_SMA_RX__W 1

15710

#define SIO_PDR_SILENT_SMA_RX__M 0x200

15711

#define SIO_PDR_SILENT_SMA_RX__PRE 0x0

15712

15713

#define SIO_PDR_SILENT_GPIO__B 10

15714

#define SIO_PDR_SILENT_GPIO__W 1

15715

#define SIO_PDR_SILENT_GPIO__M 0x400

15716

#define SIO_PDR_SILENT_GPIO__PRE 0x0

15717

15718

#define SIO_PDR_SILENT_VSYNC__B 11

15719

#define SIO_PDR_SILENT_VSYNC__W 1

15720

#define SIO_PDR_SILENT_VSYNC__M 0x800

15721

#define SIO_PDR_SILENT_VSYNC__PRE 0x0

15722

15723

#define SIO_PDR_SILENT_IRQN__B 12

15724

#define SIO_PDR_SILENT_IRQN__W 1

15725

#define SIO_PDR_SILENT_IRQN__M 0x1000

15726

#define SIO_PDR_SILENT_IRQN__PRE 0x0

15727

15728

#define SIO_PDR_UIO_IN_LO__A 0x7F0014

15729

#define SIO_PDR_UIO_IN_LO__W 16

15730

#define SIO_PDR_UIO_IN_LO__M 0xFFFF

15731

#define SIO_PDR_UIO_IN_LO__PRE 0x0

15732

#define SIO_PDR_UIO_IN_LO_DATA__B 0

15733

#define SIO_PDR_UIO_IN_LO_DATA__W 16

15734

#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF

15735

#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x0

15736

15737

#define SIO_PDR_UIO_IN_HI__A 0x7F0015

15738

#define SIO_PDR_UIO_IN_HI__W 14

15739

#define SIO_PDR_UIO_IN_HI__M 0x3FFF

15740

#define SIO_PDR_UIO_IN_HI__PRE 0x0

15741

#define SIO_PDR_UIO_IN_HI_DATA__B 0

15742

#define SIO_PDR_UIO_IN_HI_DATA__W 14

15743

#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF

15744

#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x0

15745

15746

#define SIO_PDR_UIO_OUT_LO__A 0x7F0016

15747

#define SIO_PDR_UIO_OUT_LO__W 16

15748

#define SIO_PDR_UIO_OUT_LO__M 0xFFFF

15749

#define SIO_PDR_UIO_OUT_LO__PRE 0x0

15750

#define SIO_PDR_UIO_OUT_LO_DATA__B 0

15751

#define SIO_PDR_UIO_OUT_LO_DATA__W 16

15752

#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF

15753

#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x0

15754

15755

#define SIO_PDR_UIO_OUT_HI__A 0x7F0017

15756

#define SIO_PDR_UIO_OUT_HI__W 14

15757

#define SIO_PDR_UIO_OUT_HI__M 0x3FFF

15758

#define SIO_PDR_UIO_OUT_HI__PRE 0x0

15759

#define SIO_PDR_UIO_OUT_HI_DATA__B 0

15760

#define SIO_PDR_UIO_OUT_HI_DATA__W 14

15761

#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF

15762

#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x0

15763

15764

#define SIO_PDR_PWM1_MODE__A 0x7F0018

15765

#define SIO_PDR_PWM1_MODE__W 2

15766

#define SIO_PDR_PWM1_MODE__M 0x3

15767

#define SIO_PDR_PWM1_MODE__PRE 0x0

15768

#define SIO_PDR_PWM1_PRESCALE__A 0x7F0019

15769

#define SIO_PDR_PWM1_PRESCALE__W 6

15770

#define SIO_PDR_PWM1_PRESCALE__M 0x3F

15771

#define SIO_PDR_PWM1_PRESCALE__PRE 0x0

15772

#define SIO_PDR_PWM1_VALUE__A 0x7F001A

15773

#define SIO_PDR_PWM1_VALUE__W 11

15774

#define SIO_PDR_PWM1_VALUE__M 0x7FF

15775

#define SIO_PDR_PWM1_VALUE__PRE 0x0

15776

15777

#define SIO_PDR_IRQN_SEL__A 0x7F001B

15778

#define SIO_PDR_IRQN_SEL__W 4

15779

#define SIO_PDR_IRQN_SEL__M 0xF

15780

#define SIO_PDR_IRQN_SEL__PRE 0x3

15781

#define SIO_PDR_PWM2_MODE__A 0x7F001C

15782

#define SIO_PDR_PWM2_MODE__W 2

15783

#define SIO_PDR_PWM2_MODE__M 0x3

15784

#define SIO_PDR_PWM2_MODE__PRE 0x0

15785

#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D

15786

#define SIO_PDR_PWM2_PRESCALE__W 6

15787

#define SIO_PDR_PWM2_PRESCALE__M 0x3F

15788

#define SIO_PDR_PWM2_PRESCALE__PRE 0x0

15789

#define SIO_PDR_PWM2_VALUE__A 0x7F001E

15790

#define SIO_PDR_PWM2_VALUE__W 11

15791

#define SIO_PDR_PWM2_VALUE__M 0x7FF

15792

#define SIO_PDR_PWM2_VALUE__PRE 0x0

15793

#define SIO_PDR_OHW_CFG__A 0x7F001F

15794

#define SIO_PDR_OHW_CFG__W 7

15795

#define SIO_PDR_OHW_CFG__M 0x7F

15796

#define SIO_PDR_OHW_CFG__PRE 0x0

15797

15798

#define SIO_PDR_OHW_CFG_FREF_SEL__B 0

15799

#define SIO_PDR_OHW_CFG_FREF_SEL__W 2

15800

#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3

15801

#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x0

15802

15803

#define SIO_PDR_OHW_CFG_BYPASS__B 2

15804

#define SIO_PDR_OHW_CFG_BYPASS__W 1

15805

#define SIO_PDR_OHW_CFG_BYPASS__M 0x4

15806

#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x0

15807

15808

#define SIO_PDR_OHW_CFG_ASEL__B 3

15809

#define SIO_PDR_OHW_CFG_ASEL__W 3

15810

#define SIO_PDR_OHW_CFG_ASEL__M 0x38

15811

#define SIO_PDR_OHW_CFG_ASEL__PRE 0x0

15812

15813

#define SIO_PDR_OHW_CFG_SPEED__B 6

15814

#define SIO_PDR_OHW_CFG_SPEED__W 1

15815

#define SIO_PDR_OHW_CFG_SPEED__M 0x40

15816

#define SIO_PDR_OHW_CFG_SPEED__PRE 0x0

15817

15818

#define SIO_PDR_I2S_WS_CFG__A 0x7F0020

15819

#define SIO_PDR_I2S_WS_CFG__W 9

15820

#define SIO_PDR_I2S_WS_CFG__M 0x1FF

15821

#define SIO_PDR_I2S_WS_CFG__PRE 0x10

15822

#define SIO_PDR_I2S_WS_CFG_MODE__B 0

15823

#define SIO_PDR_I2S_WS_CFG_MODE__W 3

15824

#define SIO_PDR_I2S_WS_CFG_MODE__M 0x7

15825

#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x0

15826

#define SIO_PDR_I2S_WS_CFG_DRIVE__B 3

15827

#define SIO_PDR_I2S_WS_CFG_DRIVE__W 3

15828

#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x38

15829

#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x10

15830

#define SIO_PDR_I2S_WS_CFG_KEEP__B 6

15831

#define SIO_PDR_I2S_WS_CFG_KEEP__W 2

15832

#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC0

15833

#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x0

15834

#define SIO_PDR_I2S_WS_CFG_UIO__B 8

15835

#define SIO_PDR_I2S_WS_CFG_UIO__W 1

15836

#define SIO_PDR_I2S_WS_CFG_UIO__M 0x100

15837

#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x0

15838

15839

#define SIO_PDR_GPIO_CFG__A 0x7F0021

15840

#define SIO_PDR_GPIO_CFG__W 9

15841

#define SIO_PDR_GPIO_CFG__M 0x1FF

15842

#define SIO_PDR_GPIO_CFG__PRE 0x10

15843

#define SIO_PDR_GPIO_CFG_MODE__B 0

15844

#define SIO_PDR_GPIO_CFG_MODE__W 3

15845

#define SIO_PDR_GPIO_CFG_MODE__M 0x7

15846

#define SIO_PDR_GPIO_CFG_MODE__PRE 0x0

15847

#define SIO_PDR_GPIO_CFG_DRIVE__B 3

15848

#define SIO_PDR_GPIO_CFG_DRIVE__W 3

15849

#define SIO_PDR_GPIO_CFG_DRIVE__M 0x38

15850

#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x10

15851

#define SIO_PDR_GPIO_CFG_KEEP__B 6

15852

#define SIO_PDR_GPIO_CFG_KEEP__W 2

15853

#define SIO_PDR_GPIO_CFG_KEEP__M 0xC0

15854

#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x0

15855

#define SIO_PDR_GPIO_CFG_UIO__B 8

15856

#define SIO_PDR_GPIO_CFG_UIO__W 1

15857

#define SIO_PDR_GPIO_CFG_UIO__M 0x100

15858

#define SIO_PDR_GPIO_CFG_UIO__PRE 0x0

15859

15860

#define SIO_PDR_MSTRT_CFG__A 0x7F0025

15861

#define SIO_PDR_MSTRT_CFG__W 9

15862

#define SIO_PDR_MSTRT_CFG__M 0x1FF

15863

#define SIO_PDR_MSTRT_CFG__PRE 0x50

15864

#define SIO_PDR_MSTRT_CFG_MODE__B 0

15865

#define SIO_PDR_MSTRT_CFG_MODE__W 3

15866

#define SIO_PDR_MSTRT_CFG_MODE__M 0x7

15867

#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x0

15868

#define SIO_PDR_MSTRT_CFG_DRIVE__B 3

15869

#define SIO_PDR_MSTRT_CFG_DRIVE__W 3

15870

#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x38

15871

#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x10

15872

#define SIO_PDR_MSTRT_CFG_KEEP__B 6

15873

#define SIO_PDR_MSTRT_CFG_KEEP__W 2

15874

#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC0

15875

#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x40

15876

#define SIO_PDR_MSTRT_CFG_UIO__B 8

15877

#define SIO_PDR_MSTRT_CFG_UIO__W 1

15878

#define SIO_PDR_MSTRT_CFG_UIO__M 0x100

15879

#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x0

15880

15881

#define SIO_PDR_MERR_CFG__A 0x7F0026

15882

#define SIO_PDR_MERR_CFG__W 9

15883

#define SIO_PDR_MERR_CFG__M 0x1FF

15884

#define SIO_PDR_MERR_CFG__PRE 0x50

15885

#define SIO_PDR_MERR_CFG_MODE__B 0

15886

#define SIO_PDR_MERR_CFG_MODE__W 3

15887

#define SIO_PDR_MERR_CFG_MODE__M 0x7

15888

#define SIO_PDR_MERR_CFG_MODE__PRE 0x0

15889

#define SIO_PDR_MERR_CFG_DRIVE__B 3

15890

#define SIO_PDR_MERR_CFG_DRIVE__W 3

15891

#define SIO_PDR_MERR_CFG_DRIVE__M 0x38

15892

#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x10

15893

#define SIO_PDR_MERR_CFG_KEEP__B 6

15894

#define SIO_PDR_MERR_CFG_KEEP__W 2

15895

#define SIO_PDR_MERR_CFG_KEEP__M 0xC0

15896

#define SIO_PDR_MERR_CFG_KEEP__PRE 0x40

15897

#define SIO_PDR_MERR_CFG_UIO__B 8

15898

#define SIO_PDR_MERR_CFG_UIO__W 1

15899

#define SIO_PDR_MERR_CFG_UIO__M 0x100

15900

#define SIO_PDR_MERR_CFG_UIO__PRE 0x0

15901

15902

#define SIO_PDR_MCLK_CFG__A 0x7F0028

15903

#define SIO_PDR_MCLK_CFG__W 9

15904

#define SIO_PDR_MCLK_CFG__M 0x1FF

15905

#define SIO_PDR_MCLK_CFG__PRE 0x50

15906

#define SIO_PDR_MCLK_CFG_MODE__B 0

15907

#define SIO_PDR_MCLK_CFG_MODE__W 3

15908

#define SIO_PDR_MCLK_CFG_MODE__M 0x7

15909

#define SIO_PDR_MCLK_CFG_MODE__PRE 0x0

15910

#define SIO_PDR_MCLK_CFG_DRIVE__B 3

15911

#define SIO_PDR_MCLK_CFG_DRIVE__W 3

15912

#define SIO_PDR_MCLK_CFG_DRIVE__M 0x38

15913

#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x10

15914

#define SIO_PDR_MCLK_CFG_KEEP__B 6

15915

#define SIO_PDR_MCLK_CFG_KEEP__W 2

15916

#define SIO_PDR_MCLK_CFG_KEEP__M 0xC0

15917

#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x40

15918

#define SIO_PDR_MCLK_CFG_UIO__B 8

15919

#define SIO_PDR_MCLK_CFG_UIO__W 1

15920

#define SIO_PDR_MCLK_CFG_UIO__M 0x100

15921

#define SIO_PDR_MCLK_CFG_UIO__PRE 0x0

15922

15923

#define SIO_PDR_MVAL_CFG__A 0x7F0029

15924

#define SIO_PDR_MVAL_CFG__W 9

15925

#define SIO_PDR_MVAL_CFG__M 0x1FF

15926

#define SIO_PDR_MVAL_CFG__PRE 0x50

15927

#define SIO_PDR_MVAL_CFG_MODE__B 0

15928

#define SIO_PDR_MVAL_CFG_MODE__W 3

15929

#define SIO_PDR_MVAL_CFG_MODE__M 0x7

15930

#define SIO_PDR_MVAL_CFG_MODE__PRE 0x0

15931

#define SIO_PDR_MVAL_CFG_DRIVE__B 3

15932

#define SIO_PDR_MVAL_CFG_DRIVE__W 3

15933

#define SIO_PDR_MVAL_CFG_DRIVE__M 0x38

15934

#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x10

15935

#define SIO_PDR_MVAL_CFG_KEEP__B 6

15936

#define SIO_PDR_MVAL_CFG_KEEP__W 2

15937

#define SIO_PDR_MVAL_CFG_KEEP__M 0xC0

15938

#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x40

15939

#define SIO_PDR_MVAL_CFG_UIO__B 8

15940

#define SIO_PDR_MVAL_CFG_UIO__W 1

15941

#define SIO_PDR_MVAL_CFG_UIO__M 0x100

15942

#define SIO_PDR_MVAL_CFG_UIO__PRE 0x0

15943

15944

#define SIO_PDR_MD0_CFG__A 0x7F002A

15945

#define SIO_PDR_MD0_CFG__W 9

15946

#define SIO_PDR_MD0_CFG__M 0x1FF

15947

#define SIO_PDR_MD0_CFG__PRE 0x50

15948

#define SIO_PDR_MD0_CFG_MODE__B 0

15949

#define SIO_PDR_MD0_CFG_MODE__W 3

15950

#define SIO_PDR_MD0_CFG_MODE__M 0x7

15951

#define SIO_PDR_MD0_CFG_MODE__PRE 0x0

15952

#define SIO_PDR_MD0_CFG_DRIVE__B 3

15953

#define SIO_PDR_MD0_CFG_DRIVE__W 3

15954

#define SIO_PDR_MD0_CFG_DRIVE__M 0x38

15955

#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x10

15956

#define SIO_PDR_MD0_CFG_KEEP__B 6

15957

#define SIO_PDR_MD0_CFG_KEEP__W 2

15958

#define SIO_PDR_MD0_CFG_KEEP__M 0xC0

15959

#define SIO_PDR_MD0_CFG_KEEP__PRE 0x40

15960

#define SIO_PDR_MD0_CFG_UIO__B 8

15961

#define SIO_PDR_MD0_CFG_UIO__W 1

15962

#define SIO_PDR_MD0_CFG_UIO__M 0x100

15963

#define SIO_PDR_MD0_CFG_UIO__PRE 0x0

15964

15965

#define SIO_PDR_MD1_CFG__A 0x7F002B

15966

#define SIO_PDR_MD1_CFG__W 9

15967

#define SIO_PDR_MD1_CFG__M 0x1FF

15968

#define SIO_PDR_MD1_CFG__PRE 0x50

15969

#define SIO_PDR_MD1_CFG_MODE__B 0

15970

#define SIO_PDR_MD1_CFG_MODE__W 3

15971

#define SIO_PDR_MD1_CFG_MODE__M 0x7

15972

#define SIO_PDR_MD1_CFG_MODE__PRE 0x0

15973

#define SIO_PDR_MD1_CFG_DRIVE__B 3

15974

#define SIO_PDR_MD1_CFG_DRIVE__W 3

15975

#define SIO_PDR_MD1_CFG_DRIVE__M 0x38

15976

#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x10

15977

#define SIO_PDR_MD1_CFG_KEEP__B 6

15978

#define SIO_PDR_MD1_CFG_KEEP__W 2

15979

#define SIO_PDR_MD1_CFG_KEEP__M 0xC0

15980

#define SIO_PDR_MD1_CFG_KEEP__PRE 0x40

15981

#define SIO_PDR_MD1_CFG_UIO__B 8

15982

#define SIO_PDR_MD1_CFG_UIO__W 1

15983

#define SIO_PDR_MD1_CFG_UIO__M 0x100

15984

#define SIO_PDR_MD1_CFG_UIO__PRE 0x0

15985

15986

#define SIO_PDR_MD2_CFG__A 0x7F002C

15987

#define SIO_PDR_MD2_CFG__W 9

15988

#define SIO_PDR_MD2_CFG__M 0x1FF

15989

#define SIO_PDR_MD2_CFG__PRE 0x50

15990

#define SIO_PDR_MD2_CFG_MODE__B 0

15991

#define SIO_PDR_MD2_CFG_MODE__W 3

15992

#define SIO_PDR_MD2_CFG_MODE__M 0x7

15993

#define SIO_PDR_MD2_CFG_MODE__PRE 0x0

15994

#define SIO_PDR_MD2_CFG_DRIVE__B 3

15995

#define SIO_PDR_MD2_CFG_DRIVE__W 3

15996

#define SIO_PDR_MD2_CFG_DRIVE__M 0x38

15997

#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x10

15998

#define SIO_PDR_MD2_CFG_KEEP__B 6

15999

#define SIO_PDR_MD2_CFG_KEEP__W 2

16000

#define SIO_PDR_MD2_CFG_KEEP__M 0xC0

16001

#define SIO_PDR_MD2_CFG_KEEP__PRE 0x40

16002

#define SIO_PDR_MD2_CFG_UIO__B 8

16003

#define SIO_PDR_MD2_CFG_UIO__W 1

16004

#define SIO_PDR_MD2_CFG_UIO__M 0x100

16005

#define SIO_PDR_MD2_CFG_UIO__PRE 0x0

16006

16007

#define SIO_PDR_MD3_CFG__A 0x7F002D

16008

#define SIO_PDR_MD3_CFG__W 9

16009

#define SIO_PDR_MD3_CFG__M 0x1FF

16010

#define SIO_PDR_MD3_CFG__PRE 0x50

16011

#define SIO_PDR_MD3_CFG_MODE__B 0

16012

#define SIO_PDR_MD3_CFG_MODE__W 3

16013

#define SIO_PDR_MD3_CFG_MODE__M 0x7

16014

#define SIO_PDR_MD3_CFG_MODE__PRE 0x0

16015

#define SIO_PDR_MD3_CFG_DRIVE__B 3

16016

#define SIO_PDR_MD3_CFG_DRIVE__W 3

16017

#define SIO_PDR_MD3_CFG_DRIVE__M 0x38

16018

#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x10

16019

#define SIO_PDR_MD3_CFG_KEEP__B 6

16020

#define SIO_PDR_MD3_CFG_KEEP__W 2

16021

#define SIO_PDR_MD3_CFG_KEEP__M 0xC0

16022

#define SIO_PDR_MD3_CFG_KEEP__PRE 0x40

16023

#define SIO_PDR_MD3_CFG_UIO__B 8

16024

#define SIO_PDR_MD3_CFG_UIO__W 1

16025

#define SIO_PDR_MD3_CFG_UIO__M 0x100

16026

#define SIO_PDR_MD3_CFG_UIO__PRE 0x0

16027

16028

#define SIO_PDR_MD4_CFG__A 0x7F002F

16029

#define SIO_PDR_MD4_CFG__W 9

16030

#define SIO_PDR_MD4_CFG__M 0x1FF

16031

#define SIO_PDR_MD4_CFG__PRE 0x50

16032

#define SIO_PDR_MD4_CFG_MODE__B 0

16033

#define SIO_PDR_MD4_CFG_MODE__W 3

16034

#define SIO_PDR_MD4_CFG_MODE__M 0x7

16035

#define SIO_PDR_MD4_CFG_MODE__PRE 0x0

16036

#define SIO_PDR_MD4_CFG_DRIVE__B 3

16037

#define SIO_PDR_MD4_CFG_DRIVE__W 3

16038

#define SIO_PDR_MD4_CFG_DRIVE__M 0x38

16039

#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x10

16040

#define SIO_PDR_MD4_CFG_KEEP__B 6

16041

#define SIO_PDR_MD4_CFG_KEEP__W 2

16042

#define SIO_PDR_MD4_CFG_KEEP__M 0xC0

16043

#define SIO_PDR_MD4_CFG_KEEP__PRE 0x40

16044

#define SIO_PDR_MD4_CFG_UIO__B 8

16045

#define SIO_PDR_MD4_CFG_UIO__W 1

16046

#define SIO_PDR_MD4_CFG_UIO__M 0x100

16047

#define SIO_PDR_MD4_CFG_UIO__PRE 0x0

16048

16049

#define SIO_PDR_MD5_CFG__A 0x7F0030

16050

#define SIO_PDR_MD5_CFG__W 9

16051

#define SIO_PDR_MD5_CFG__M 0x1FF

16052

#define SIO_PDR_MD5_CFG__PRE 0x50

16053

#define SIO_PDR_MD5_CFG_MODE__B 0

16054

#define SIO_PDR_MD5_CFG_MODE__W 3

16055

#define SIO_PDR_MD5_CFG_MODE__M 0x7

16056

#define SIO_PDR_MD5_CFG_MODE__PRE 0x0

16057

#define SIO_PDR_MD5_CFG_DRIVE__B 3

16058

#define SIO_PDR_MD5_CFG_DRIVE__W 3

16059

#define SIO_PDR_MD5_CFG_DRIVE__M 0x38

16060

#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x10

16061

#define SIO_PDR_MD5_CFG_KEEP__B 6

16062

#define SIO_PDR_MD5_CFG_KEEP__W 2

16063

#define SIO_PDR_MD5_CFG_KEEP__M 0xC0

16064

#define SIO_PDR_MD5_CFG_KEEP__PRE 0x40

16065

#define SIO_PDR_MD5_CFG_UIO__B 8

16066

#define SIO_PDR_MD5_CFG_UIO__W 1

16067

#define SIO_PDR_MD5_CFG_UIO__M 0x100

16068

#define SIO_PDR_MD5_CFG_UIO__PRE 0x0

16069

16070

#define SIO_PDR_MD6_CFG__A 0x7F0031

16071

#define SIO_PDR_MD6_CFG__W 9

16072

#define SIO_PDR_MD6_CFG__M 0x1FF

16073

#define SIO_PDR_MD6_CFG__PRE 0x50

16074

#define SIO_PDR_MD6_CFG_MODE__B 0

16075

#define SIO_PDR_MD6_CFG_MODE__W 3

16076

#define SIO_PDR_MD6_CFG_MODE__M 0x7

16077

#define SIO_PDR_MD6_CFG_MODE__PRE 0x0

16078

#define SIO_PDR_MD6_CFG_DRIVE__B 3

16079

#define SIO_PDR_MD6_CFG_DRIVE__W 3

16080

#define SIO_PDR_MD6_CFG_DRIVE__M 0x38

16081

#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x10

16082

#define SIO_PDR_MD6_CFG_KEEP__B 6

16083

#define SIO_PDR_MD6_CFG_KEEP__W 2

16084

#define SIO_PDR_MD6_CFG_KEEP__M 0xC0

16085

#define SIO_PDR_MD6_CFG_KEEP__PRE 0x40

16086

#define SIO_PDR_MD6_CFG_UIO__B 8

16087

#define SIO_PDR_MD6_CFG_UIO__W 1

16088

#define SIO_PDR_MD6_CFG_UIO__M 0x100

16089

#define SIO_PDR_MD6_CFG_UIO__PRE 0x0

16090

16091

#define SIO_PDR_MD7_CFG__A 0x7F0032

16092

#define SIO_PDR_MD7_CFG__W 9

16093

#define SIO_PDR_MD7_CFG__M 0x1FF

16094

#define SIO_PDR_MD7_CFG__PRE 0x50

16095

#define SIO_PDR_MD7_CFG_MODE__B 0

16096

#define SIO_PDR_MD7_CFG_MODE__W 3

16097

#define SIO_PDR_MD7_CFG_MODE__M 0x7

16098

#define SIO_PDR_MD7_CFG_MODE__PRE 0x0

16099

#define SIO_PDR_MD7_CFG_DRIVE__B 3

16100

#define SIO_PDR_MD7_CFG_DRIVE__W 3

16101

#define SIO_PDR_MD7_CFG_DRIVE__M 0x38

16102

#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x10

16103

#define SIO_PDR_MD7_CFG_KEEP__B 6

16104

#define SIO_PDR_MD7_CFG_KEEP__W 2

16105

#define SIO_PDR_MD7_CFG_KEEP__M 0xC0

16106

#define SIO_PDR_MD7_CFG_KEEP__PRE 0x40

16107

#define SIO_PDR_MD7_CFG_UIO__B 8

16108

#define SIO_PDR_MD7_CFG_UIO__W 1

16109

#define SIO_PDR_MD7_CFG_UIO__M 0x100

16110

#define SIO_PDR_MD7_CFG_UIO__PRE 0x0

16111

16112

#define SIO_PDR_I2C_SCL1_CFG__A 0x7F0033

16113

#define SIO_PDR_I2C_SCL1_CFG__W 9

16114

#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF

16115

#define SIO_PDR_I2C_SCL1_CFG__PRE 0x11

16116

#define SIO_PDR_I2C_SCL1_CFG_MODE__B 0

16117

#define SIO_PDR_I2C_SCL1_CFG_MODE__W 3

16118

#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x7

16119

#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x1

16120

#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 3

16121

#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 3

16122

#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x38

16123

#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x10

16124

#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 6

16125

#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 2

16126

#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC0

16127

#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x0

16128

#define SIO_PDR_I2C_SCL1_CFG_UIO__B 8

16129

#define SIO_PDR_I2C_SCL1_CFG_UIO__W 1

16130

#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x100

16131

#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x0

16132

16133

#define SIO_PDR_I2C_SDA1_CFG__A 0x7F0034

16134

#define SIO_PDR_I2C_SDA1_CFG__W 9

16135

#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF

16136

#define SIO_PDR_I2C_SDA1_CFG__PRE 0x11

16137

#define SIO_PDR_I2C_SDA1_CFG_MODE__B 0

16138

#define SIO_PDR_I2C_SDA1_CFG_MODE__W 3

16139

#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x7

16140

#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x1

16141

#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 3

16142

#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 3

16143

#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x38

16144

#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x10

16145

#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 6

16146

#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 2

16147

#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC0

16148

#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x0

16149

#define SIO_PDR_I2C_SDA1_CFG_UIO__B 8

16150

#define SIO_PDR_I2C_SDA1_CFG_UIO__W 1

16151

#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x100

16152

#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x0

16153

16154

#define SIO_PDR_VSYNC_CFG__A 0x7F0036

16155

#define SIO_PDR_VSYNC_CFG__W 9

16156

#define SIO_PDR_VSYNC_CFG__M 0x1FF

16157

#define SIO_PDR_VSYNC_CFG__PRE 0x10

16158

#define SIO_PDR_VSYNC_CFG_MODE__B 0

16159

#define SIO_PDR_VSYNC_CFG_MODE__W 3

16160

#define SIO_PDR_VSYNC_CFG_MODE__M 0x7

16161

#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x0

16162

#define SIO_PDR_VSYNC_CFG_DRIVE__B 3

16163

#define SIO_PDR_VSYNC_CFG_DRIVE__W 3

16164

#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x38

16165

#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x10

16166

#define SIO_PDR_VSYNC_CFG_KEEP__B 6

16167

#define SIO_PDR_VSYNC_CFG_KEEP__W 2

16168

#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC0

16169

#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x0

16170

#define SIO_PDR_VSYNC_CFG_UIO__B 8

16171

#define SIO_PDR_VSYNC_CFG_UIO__W 1

16172

#define SIO_PDR_VSYNC_CFG_UIO__M 0x100

16173

#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x0

16174

16175

#define SIO_PDR_SMA_RX_CFG__A 0x7F0037

16176

#define SIO_PDR_SMA_RX_CFG__W 9

16177

#define SIO_PDR_SMA_RX_CFG__M 0x1FF

16178

#define SIO_PDR_SMA_RX_CFG__PRE 0x10

16179

#define SIO_PDR_SMA_RX_CFG_MODE__B 0

16180

#define SIO_PDR_SMA_RX_CFG_MODE__W 3

16181

#define SIO_PDR_SMA_RX_CFG_MODE__M 0x7

16182

#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x0

16183

#define SIO_PDR_SMA_RX_CFG_DRIVE__B 3

16184

#define SIO_PDR_SMA_RX_CFG_DRIVE__W 3

16185

#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x38

16186

#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x10

16187

#define SIO_PDR_SMA_RX_CFG_KEEP__B 6

16188

#define SIO_PDR_SMA_RX_CFG_KEEP__W 2

16189

#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC0

16190

#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x0

16191

#define SIO_PDR_SMA_RX_CFG_UIO__B 8

16192

#define SIO_PDR_SMA_RX_CFG_UIO__W 1

16193

#define SIO_PDR_SMA_RX_CFG_UIO__M 0x100

16194

#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x0

16195

16196

#define SIO_PDR_SMA_TX_CFG__A 0x7F0038

16197

#define SIO_PDR_SMA_TX_CFG__W 9

16198

#define SIO_PDR_SMA_TX_CFG__M 0x1FF

16199

#define SIO_PDR_SMA_TX_CFG__PRE 0x90

16200

#define SIO_PDR_SMA_TX_CFG_MODE__B 0

16201

#define SIO_PDR_SMA_TX_CFG_MODE__W 3

16202

#define SIO_PDR_SMA_TX_CFG_MODE__M 0x7

16203

#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x0

16204

#define SIO_PDR_SMA_TX_CFG_DRIVE__B 3

16205

#define SIO_PDR_SMA_TX_CFG_DRIVE__W 3

16206

#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x38

16207

#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x10

16208

#define SIO_PDR_SMA_TX_CFG_KEEP__B 6

16209

#define SIO_PDR_SMA_TX_CFG_KEEP__W 2

16210

#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC0

16211

#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x80

16212

#define SIO_PDR_SMA_TX_CFG_UIO__B 8

16213

#define SIO_PDR_SMA_TX_CFG_UIO__W 1

16214

#define SIO_PDR_SMA_TX_CFG_UIO__M 0x100

16215

#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x0

16216

16217

#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F

16218

#define SIO_PDR_I2C_SDA2_CFG__W 9

16219

#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF

16220

#define SIO_PDR_I2C_SDA2_CFG__PRE 0x11

16221

#define SIO_PDR_I2C_SDA2_CFG_MODE__B 0

16222

#define SIO_PDR_I2C_SDA2_CFG_MODE__W 3

16223

#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x7

16224

#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x1

16225

#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 3

16226

#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 3

16227

#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x38

16228

#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x10

16229

#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 6

16230

#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 2

16231

#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC0

16232

#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x0

16233

#define SIO_PDR_I2C_SDA2_CFG_UIO__B 8

16234

#define SIO_PDR_I2C_SDA2_CFG_UIO__W 1

16235

#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x100

16236

#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x0

16237

16238

#define SIO_PDR_I2C_SCL2_CFG__A 0x7F0040

16239

#define SIO_PDR_I2C_SCL2_CFG__W 9

16240

#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF

16241

#define SIO_PDR_I2C_SCL2_CFG__PRE 0x11

16242

#define SIO_PDR_I2C_SCL2_CFG_MODE__B 0

16243

#define SIO_PDR_I2C_SCL2_CFG_MODE__W 3

16244

#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x7

16245

#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x1

16246

#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 3

16247

#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 3

16248

#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x38

16249

#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x10

16250

#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 6

16251

#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 2

16252

#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC0

16253

#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x0

16254

#define SIO_PDR_I2C_SCL2_CFG_UIO__B 8

16255

#define SIO_PDR_I2C_SCL2_CFG_UIO__W 1

16256

#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x100

16257

#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x0

16258

16259

#define SIO_PDR_I2S_CL_CFG__A 0x7F0041

16260

#define SIO_PDR_I2S_CL_CFG__W 9

16261

#define SIO_PDR_I2S_CL_CFG__M 0x1FF

16262

#define SIO_PDR_I2S_CL_CFG__PRE 0x10

16263

#define SIO_PDR_I2S_CL_CFG_MODE__B 0

16264

#define SIO_PDR_I2S_CL_CFG_MODE__W 3

16265

#define SIO_PDR_I2S_CL_CFG_MODE__M 0x7

16266

#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x0

16267

#define SIO_PDR_I2S_CL_CFG_DRIVE__B 3

16268

#define SIO_PDR_I2S_CL_CFG_DRIVE__W 3

16269

#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x38

16270

#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x10

16271

#define SIO_PDR_I2S_CL_CFG_KEEP__B 6

16272

#define SIO_PDR_I2S_CL_CFG_KEEP__W 2

16273

#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC0

16274

#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x0

16275

#define SIO_PDR_I2S_CL_CFG_UIO__B 8

16276

#define SIO_PDR_I2S_CL_CFG_UIO__W 1

16277

#define SIO_PDR_I2S_CL_CFG_UIO__M 0x100

16278

#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x0

16279

16280

#define SIO_PDR_I2S_DA_CFG__A 0x7F0042

16281

#define SIO_PDR_I2S_DA_CFG__W 9

16282

#define SIO_PDR_I2S_DA_CFG__M 0x1FF

16283

#define SIO_PDR_I2S_DA_CFG__PRE 0x10

16284

#define SIO_PDR_I2S_DA_CFG_MODE__B 0

16285

#define SIO_PDR_I2S_DA_CFG_MODE__W 3

16286

#define SIO_PDR_I2S_DA_CFG_MODE__M 0x7

16287

#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x0

16288

#define SIO_PDR_I2S_DA_CFG_DRIVE__B 3

16289

#define SIO_PDR_I2S_DA_CFG_DRIVE__W 3

16290

#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x38

16291

#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x10

16292

#define SIO_PDR_I2S_DA_CFG_KEEP__B 6

16293

#define SIO_PDR_I2S_DA_CFG_KEEP__W 2

16294

#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC0

16295

#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x0

16296

#define SIO_PDR_I2S_DA_CFG_UIO__B 8

16297

#define SIO_PDR_I2S_DA_CFG_UIO__W 1

16298

#define SIO_PDR_I2S_DA_CFG_UIO__M 0x100

16299

#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x0

16300

16301

#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F0050

16302

#define SIO_PDR_GPIO_GPIO_FNC__W 2

16303

#define SIO_PDR_GPIO_GPIO_FNC__M 0x3

16304

#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x0

16305

#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 0

16306

#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 2

16307

#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x3

16308

#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x0

16309

16310

#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F0052

16311

#define SIO_PDR_MSTRT_GPIO_FNC__W 2

16312

#define SIO_PDR_MSTRT_GPIO_FNC__M 0x3

16313

#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x0

16314

#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 0

16315

#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 2

16316

#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x3

16317

#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x0

16318

16319

#define SIO_PDR_MERR_GPIO_FNC__A 0x7F0053

16320

#define SIO_PDR_MERR_GPIO_FNC__W 2

16321

#define SIO_PDR_MERR_GPIO_FNC__M 0x3

16322

#define SIO_PDR_MERR_GPIO_FNC__PRE 0x0

16323

#define SIO_PDR_MERR_GPIO_FNC_SEL__B 0

16324

#define SIO_PDR_MERR_GPIO_FNC_SEL__W 2

16325

#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x3

16326

#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x0

16327

16328

#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F0054

16329

#define SIO_PDR_MCLK_GPIO_FNC__W 2

16330

#define SIO_PDR_MCLK_GPIO_FNC__M 0x3

16331

#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x0

16332

#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 0

16333

#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 2

16334

#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x3

16335

#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x0

16336

16337

#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F0055

16338

#define SIO_PDR_MVAL_GPIO_FNC__W 2

16339

#define SIO_PDR_MVAL_GPIO_FNC__M 0x3

16340

#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x0

16341

#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 0

16342

#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 2

16343

#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x3

16344

#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x0

16345

16346

#define SIO_PDR_MD0_GPIO_FNC__A 0x7F0056

16347

#define SIO_PDR_MD0_GPIO_FNC__W 2

16348

#define SIO_PDR_MD0_GPIO_FNC__M 0x3

16349

#define SIO_PDR_MD0_GPIO_FNC__PRE 0x0

16350

#define SIO_PDR_MD0_GPIO_FNC_SEL__B 0

16351

#define SIO_PDR_MD0_GPIO_FNC_SEL__W 2

16352

#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x3

16353

#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x0

16354

16355

#define SIO_PDR_MD1_GPIO_FNC__A 0x7F0057

16356

#define SIO_PDR_MD1_GPIO_FNC__W 2

16357

#define SIO_PDR_MD1_GPIO_FNC__M 0x3

16358

#define SIO_PDR_MD1_GPIO_FNC__PRE 0x0

16359

#define SIO_PDR_MD1_GPIO_FNC_SEL__B 0

16360

#define SIO_PDR_MD1_GPIO_FNC_SEL__W 2

16361

#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x3

16362

#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x0

16363

16364

#define SIO_PDR_MD2_GPIO_FNC__A 0x7F0058

16365

#define SIO_PDR_MD2_GPIO_FNC__W 2

16366

#define SIO_PDR_MD2_GPIO_FNC__M 0x3

16367

#define SIO_PDR_MD2_GPIO_FNC__PRE 0x0

16368

#define SIO_PDR_MD2_GPIO_FNC_SEL__B 0

16369

#define SIO_PDR_MD2_GPIO_FNC_SEL__W 2

16370

#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x3

16371

#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x0

16372

16373

#define SIO_PDR_MD3_GPIO_FNC__A 0x7F0059

16374

#define SIO_PDR_MD3_GPIO_FNC__W 2

16375

#define SIO_PDR_MD3_GPIO_FNC__M 0x3

16376

#define SIO_PDR_MD3_GPIO_FNC__PRE 0x0

16377

#define SIO_PDR_MD3_GPIO_FNC_SEL__B 0

16378

#define SIO_PDR_MD3_GPIO_FNC_SEL__W 2

16379

#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x3

16380

#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x0

16381

16382

#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A

16383

#define SIO_PDR_MD4_GPIO_FNC__W 2

16384

#define SIO_PDR_MD4_GPIO_FNC__M 0x3

16385

#define SIO_PDR_MD4_GPIO_FNC__PRE 0x0

16386

#define SIO_PDR_MD4_GPIO_FNC_SEL__B 0

16387

#define SIO_PDR_MD4_GPIO_FNC_SEL__W 2

16388

#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x3

16389

#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x0

16390

16391

#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B

16392

#define SIO_PDR_MD5_GPIO_FNC__W 2

16393

#define SIO_PDR_MD5_GPIO_FNC__M 0x3

16394

#define SIO_PDR_MD5_GPIO_FNC__PRE 0x0

16395

#define SIO_PDR_MD5_GPIO_FNC_SEL__B 0

16396

#define SIO_PDR_MD5_GPIO_FNC_SEL__W 2

16397

#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x3

16398

#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x0

16399

16400

#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C

16401

#define SIO_PDR_MD6_GPIO_FNC__W 2

16402

#define SIO_PDR_MD6_GPIO_FNC__M 0x3

16403

#define SIO_PDR_MD6_GPIO_FNC__PRE 0x0

16404

#define SIO_PDR_MD6_GPIO_FNC_SEL__B 0

16405

#define SIO_PDR_MD6_GPIO_FNC_SEL__W 2

16406

#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x3

16407

#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x0

16408

16409

#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D

16410

#define SIO_PDR_MD7_GPIO_FNC__W 2

16411

#define SIO_PDR_MD7_GPIO_FNC__M 0x3

16412

#define SIO_PDR_MD7_GPIO_FNC__PRE 0x0

16413

#define SIO_PDR_MD7_GPIO_FNC_SEL__B 0

16414

#define SIO_PDR_MD7_GPIO_FNC_SEL__W 2

16415

#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x3

16416

#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x0

16417

16418

#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E

16419

#define SIO_PDR_SMA_RX_GPIO_FNC__W 2

16420

#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x3

16421

#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x0

16422

#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 0

16423

#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 2

16424

#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x3

16425

#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x0

16426

16427

#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F

16428

#define SIO_PDR_SMA_TX_GPIO_FNC__W 2

16429

#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x3

16430

#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x0

16431

#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 0

16432

#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 2

16433

#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x3

16434

#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x0

#endif