blob: c81f136ae670f1c616ac0fee867b9c2ed08351e0 [file] [log] [blame]
Michael Barkowski0cefeeb2007-05-11 18:24:51 -05001/*
2 * Driver for ICPlus PHYs
3 *
4 * Copyright (c) 2007 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 */
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/errno.h>
15#include <linux/unistd.h>
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050016#include <linux/interrupt.h>
17#include <linux/init.h>
18#include <linux/delay.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/skbuff.h>
22#include <linux/spinlock.h>
23#include <linux/mm.h>
24#include <linux/module.h>
25#include <linux/mii.h>
26#include <linux/ethtool.h>
27#include <linux/phy.h>
28
29#include <asm/io.h>
30#include <asm/irq.h>
31#include <asm/uaccess.h>
32
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +000033MODULE_DESCRIPTION("ICPlus IP175C/IP101A/IC1001 PHY drivers");
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050034MODULE_AUTHOR("Michael Barkowski");
35MODULE_LICENSE("GPL");
36
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +000037/* IP101A/IP1001 */
38#define IP10XX_SPEC_CTRL_STATUS 16 /* Spec. Control Register */
39#define IP1001_SPEC_CTRL_STATUS_2 20 /* IP1001 Spec. Control Reg 2 */
40#define IP1001_PHASE_SEL_MASK 3 /* IP1001 RX/TXPHASE_SEL */
41#define IP1001_APS_ON 11 /* IP1001 APS Mode bit */
42#define IP101A_APS_ON 2 /* IP101A APS Mode bit */
43
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050044static int ip175c_config_init(struct phy_device *phydev)
45{
46 int err, i;
47 static int full_reset_performed = 0;
48
49 if (full_reset_performed == 0) {
50
51 /* master reset */
David Daney76231e02011-09-30 12:17:48 +000052 err = mdiobus_write(phydev->bus, 30, 0, 0x175c);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050053 if (err < 0)
54 return err;
55
56 /* ensure no bus delays overlap reset period */
David Daney76231e02011-09-30 12:17:48 +000057 err = mdiobus_read(phydev->bus, 30, 0);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050058
59 /* data sheet specifies reset period is 2 msec */
60 mdelay(2);
61
62 /* enable IP175C mode */
David Daney76231e02011-09-30 12:17:48 +000063 err = mdiobus_write(phydev->bus, 29, 31, 0x175c);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050064 if (err < 0)
65 return err;
66
67 /* Set MII0 speed and duplex (in PHY mode) */
David Daney76231e02011-09-30 12:17:48 +000068 err = mdiobus_write(phydev->bus, 29, 22, 0x420);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050069 if (err < 0)
70 return err;
71
72 /* reset switch ports */
73 for (i = 0; i < 5; i++) {
David Daney76231e02011-09-30 12:17:48 +000074 err = mdiobus_write(phydev->bus, i,
75 MII_BMCR, BMCR_RESET);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050076 if (err < 0)
77 return err;
78 }
79
80 for (i = 0; i < 5; i++)
David Daney76231e02011-09-30 12:17:48 +000081 err = mdiobus_read(phydev->bus, i, MII_BMCR);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -050082
83 mdelay(2);
84
85 full_reset_performed = 1;
86 }
87
88 if (phydev->addr != 4) {
89 phydev->state = PHY_RUNNING;
90 phydev->speed = SPEED_100;
91 phydev->duplex = DUPLEX_FULL;
92 phydev->link = 1;
93 netif_carrier_on(phydev->attached_dev);
94 }
95
96 return 0;
97}
98
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +000099static int ip1xx_reset(struct phy_device *phydev)
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000100{
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000101 int err, bmcr;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000102
103 /* Software Reset PHY */
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000104 bmcr = phy_read(phydev, MII_BMCR);
105 bmcr |= BMCR_RESET;
106 err = phy_write(phydev, MII_BMCR, bmcr);
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000107 if (err < 0)
108 return err;
109
110 do {
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000111 bmcr = phy_read(phydev, MII_BMCR);
112 } while (bmcr & BMCR_RESET);
113
114 return err;
115}
116
117static int ip1001_config_init(struct phy_device *phydev)
118{
119 int c;
120
121 c = ip1xx_reset(phydev);
122 if (c < 0)
123 return c;
124
125 /* Enable Auto Power Saving mode */
126 c = phy_read(phydev, IP1001_SPEC_CTRL_STATUS_2);
127 c |= IP1001_APS_ON;
128 if (c < 0)
129 return c;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000130
Giuseppe CAVALLAROa4886d52011-10-10 21:37:56 +0000131 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
132 /* Additional delay (2ns) used to adjust RX clock phase
133 * at RGMII interface */
134 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
135 c |= IP1001_PHASE_SEL_MASK;
136 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c);
137 }
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000138
Giuseppe CAVALLAROa4886d52011-10-10 21:37:56 +0000139 return c;
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000140}
141
142static int ip101a_config_init(struct phy_device *phydev)
143{
144 int c;
145
146 c = ip1xx_reset(phydev);
147 if (c < 0)
148 return c;
149
150 /* Enable Auto Power Saving mode */
151 c = phy_read(phydev, IP10XX_SPEC_CTRL_STATUS);
152 c |= IP101A_APS_ON;
153 return c;
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000154}
155
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500156static int ip175c_read_status(struct phy_device *phydev)
157{
158 if (phydev->addr == 4) /* WAN port */
159 genphy_read_status(phydev);
160 else
161 /* Don't need to read status for switch ports */
162 phydev->irq = PHY_IGNORE_INTERRUPT;
163
164 return 0;
165}
166
167static int ip175c_config_aneg(struct phy_device *phydev)
168{
169 if (phydev->addr == 4) /* WAN port */
170 genphy_config_aneg(phydev);
171
172 return 0;
173}
174
175static struct phy_driver ip175c_driver = {
176 .phy_id = 0x02430d80,
177 .name = "ICPlus IP175C",
178 .phy_id_mask = 0x0ffffff0,
179 .features = PHY_BASIC_FEATURES,
180 .config_init = &ip175c_config_init,
181 .config_aneg = &ip175c_config_aneg,
182 .read_status = &ip175c_read_status,
Giuseppe Cavallarodab10862010-07-20 13:24:25 -0700183 .suspend = genphy_suspend,
184 .resume = genphy_resume,
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500185 .driver = { .owner = THIS_MODULE,},
186};
187
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000188static struct phy_driver ip1001_driver = {
189 .phy_id = 0x02430d90,
190 .name = "ICPlus IP1001",
191 .phy_id_mask = 0x0ffffff0,
192 .features = PHY_GBIT_FEATURES | SUPPORTED_Pause |
193 SUPPORTED_Asym_Pause,
194 .config_init = &ip1001_config_init,
195 .config_aneg = &genphy_config_aneg,
196 .read_status = &genphy_read_status,
197 .suspend = genphy_suspend,
198 .resume = genphy_resume,
199 .driver = { .owner = THIS_MODULE,},
200};
201
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000202static struct phy_driver ip101a_driver = {
203 .phy_id = 0x02430c54,
204 .name = "ICPlus IP101A",
205 .phy_id_mask = 0x0ffffff0,
206 .features = PHY_BASIC_FEATURES | SUPPORTED_Pause |
207 SUPPORTED_Asym_Pause,
208 .config_init = &ip101a_config_init,
209 .config_aneg = &genphy_config_aneg,
210 .read_status = &genphy_read_status,
211 .suspend = genphy_suspend,
212 .resume = genphy_resume,
213 .driver = { .owner = THIS_MODULE,},
214};
215
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000216static int __init icplus_init(void)
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500217{
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000218 int ret = 0;
219
220 ret = phy_driver_register(&ip1001_driver);
221 if (ret < 0)
222 return -ENODEV;
223
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000224 ret = phy_driver_register(&ip101a_driver);
225 if (ret < 0)
226 return -ENODEV;
227
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500228 return phy_driver_register(&ip175c_driver);
229}
230
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000231static void __exit icplus_exit(void)
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500232{
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000233 phy_driver_unregister(&ip1001_driver);
Giuseppe CAVALLARO9c9b1f22011-09-06 20:14:50 +0000234 phy_driver_unregister(&ip101a_driver);
Michael Barkowski0cefeeb2007-05-11 18:24:51 -0500235 phy_driver_unregister(&ip175c_driver);
236}
237
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000238module_init(icplus_init);
239module_exit(icplus_exit);
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000240
Uwe Kleine-Königcf93c942010-10-03 23:43:32 +0000241static struct mdio_device_id __maybe_unused icplus_tbl[] = {
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000242 { 0x02430d80, 0x0ffffff0 },
Giuseppe CAVALLARO377ecca2010-12-08 23:05:13 +0000243 { 0x02430d90, 0x0ffffff0 },
David Woodhouse4e4f10f2010-04-02 01:05:56 +0000244 { }
245};
246
247MODULE_DEVICE_TABLE(mdio, icplus_tbl);