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gerrit-public.fairphone.software / kernel / msm-4.19 / 3b151526eda87901532390e11bba0dd59119f667 / . / drivers / usb / musb / musbhsdma.h
blob: 1299d92dc83f0174e03c7c6a2d039ca4d5305b1e [file] [log] [blame]
Bryan Wu6995eb62008-12-02 21:33:47 +0200[diff] [blame]1/*
2 * MUSB OTG driver - support for Mentor's DMA controller
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2007 by Texas Instruments
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
35#include "omap2430.h"
36#endif
37
38#ifndef CONFIG_BLACKFIN
39
40#define MUSB_HSDMA_BASE 0x200
41#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
42#define MUSB_HSDMA_CONTROL 0x4
43#define MUSB_HSDMA_ADDRESS 0x8
44#define MUSB_HSDMA_COUNT 0xc
45
46#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
47 (MUSB_HSDMA_BASE + (_bchannel << 4) + _offset)
48
49#define musb_read_hsdma_addr(mbase, bchannel) \
50 musb_readl(mbase, \
51 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS))
52
53#define musb_write_hsdma_addr(mbase, bchannel, addr) \
54 musb_writel(mbase, \
55 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDRESS), \
56 addr)
57
58#define musb_write_hsdma_count(mbase, bchannel, len) \
59 musb_writel(mbase, \
60 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT), \
61 len)
62#else
63
64#define MUSB_HSDMA_BASE 0x400
65#define MUSB_HSDMA_INTR (MUSB_HSDMA_BASE + 0)
66#define MUSB_HSDMA_CONTROL 0x04
67#define MUSB_HSDMA_ADDR_LOW 0x08
68#define MUSB_HSDMA_ADDR_HIGH 0x0C
69#define MUSB_HSDMA_COUNT_LOW 0x10
70#define MUSB_HSDMA_COUNT_HIGH 0x14
71
72#define MUSB_HSDMA_CHANNEL_OFFSET(_bchannel, _offset) \
73 (MUSB_HSDMA_BASE + (_bchannel * 0x20) + _offset)
74
75static inline u32 musb_read_hsdma_addr(void __iomem *mbase, u8 bchannel)
76{
77 u32 addr = musb_readw(mbase,
78 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH));
79
80 addr = addr << 16;
81
82 addr |= musb_readw(mbase,
83 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW));
84
85 return addr;
86}
87
88static inline void musb_write_hsdma_addr(void __iomem *mbase,
89 u8 bchannel, dma_addr_t dma_addr)
90{
91 musb_writew(mbase,
92 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_LOW),
93 ((u16)((u32) dma_addr & 0xFFFF)));
94 musb_writew(mbase,
95 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_ADDR_HIGH),
96 ((u16)(((u32) dma_addr >> 16) & 0xFFFF)));
97}
98
99static inline void musb_write_hsdma_count(void __iomem *mbase,
100 u8 bchannel, u32 len)
101{
102 musb_writew(mbase,
103 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_LOW),
104 ((u16)((u32) len & 0xFFFF)));
105 musb_writew(mbase,
106 MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_COUNT_HIGH),
107 ((u16)(((u32) len >> 16) & 0xFFFF)));
108}
109
110#endif /* CONFIG_BLACKFIN */
111
112/* control register (16-bit): */
113#define MUSB_HSDMA_ENABLE_SHIFT 0
114#define MUSB_HSDMA_TRANSMIT_SHIFT 1
115#define MUSB_HSDMA_MODE1_SHIFT 2
116#define MUSB_HSDMA_IRQENABLE_SHIFT 3
117#define MUSB_HSDMA_ENDPOINT_SHIFT 4
118#define MUSB_HSDMA_BUSERROR_SHIFT 8
119#define MUSB_HSDMA_BURSTMODE_SHIFT 9
120#define MUSB_HSDMA_BURSTMODE (3 << MUSB_HSDMA_BURSTMODE_SHIFT)
121#define MUSB_HSDMA_BURSTMODE_UNSPEC 0
122#define MUSB_HSDMA_BURSTMODE_INCR4 1
123#define MUSB_HSDMA_BURSTMODE_INCR8 2
124#define MUSB_HSDMA_BURSTMODE_INCR16 3
125
126#define MUSB_HSDMA_CHANNELS 8
127
128struct musb_dma_controller;
129
130struct musb_dma_channel {
131 struct dma_channel channel;
132 struct musb_dma_controller *controller;
133 u32 start_addr;
134 u32 len;
135 u16 max_packet_sz;
136 u8 idx;
137 u8 epnum;
138 u8 transmit;
139};
140
141struct musb_dma_controller {
142 struct dma_controller controller;
143 struct musb_dma_channel channel[MUSB_HSDMA_CHANNELS];
144 void *private_data;
145 void __iomem *base;
146 u8 channel_count;
147 u8 used_channels;
148 u8 irq;
149};