Maxime Ripard | 5f91077 | 2014-04-18 18:53:02 +0200 | [diff] [blame] | 1 | if ARCH_SUNXI |
2 | |||||
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 3 | config PINCTRL_SUNXI_COMMON |
4 | bool | ||||
Maxime Ripard | 5f91077 | 2014-04-18 18:53:02 +0200 | [diff] [blame] | 5 | select PINMUX |
6 | select GENERIC_PINCONF | ||||
7 | |||||
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 8 | config PINCTRL_SUN4I_A10 |
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 9 | def_bool MACH_SUN4I |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 10 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 11 | |
12 | config PINCTRL_SUN5I_A10S | ||||
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 13 | def_bool MACH_SUN5I |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 14 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 15 | |
16 | config PINCTRL_SUN5I_A13 | ||||
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 17 | def_bool MACH_SUN5I |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 18 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 19 | |
20 | config PINCTRL_SUN6I_A31 | ||||
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 21 | def_bool MACH_SUN6I |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 22 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 23 | |
Hans de Goede | 47cf4b3 | 2014-12-17 18:18:13 +0100 | [diff] [blame] | 24 | config PINCTRL_SUN6I_A31S |
25 | def_bool MACH_SUN6I | ||||
26 | select PINCTRL_SUNXI_COMMON | ||||
27 | |||||
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 28 | config PINCTRL_SUN6I_A31_R |
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 29 | def_bool MACH_SUN6I |
Maxime Ripard | de5af04 | 2014-05-23 20:50:43 +0200 | [diff] [blame] | 30 | depends on RESET_CONTROLLER |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 31 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 32 | |
33 | config PINCTRL_SUN7I_A20 | ||||
Maxime Ripard | d9ff081 | 2014-06-29 15:58:19 +0200 | [diff] [blame] | 34 | def_bool MACH_SUN7I |
Maxime Ripard | 118c565 | 2014-05-22 16:47:12 +0200 | [diff] [blame] | 35 | select PINCTRL_SUNXI_COMMON |
Maxime Ripard | 340ba6c | 2014-04-26 17:06:57 +0200 | [diff] [blame] | 36 | |
Chen-Yu Tsai | 4c821d1 | 2014-06-17 22:52:51 +0800 | [diff] [blame] | 37 | config PINCTRL_SUN8I_A23 |
38 | def_bool MACH_SUN8I | ||||
39 | select PINCTRL_SUNXI_COMMON | ||||
40 | |||||
Vishnu Patekar | 7164873 | 2015-06-02 11:08:40 +0200 | [diff] [blame] | 41 | config PINCTRL_SUN8I_A33 |
42 | def_bool MACH_SUN8I | ||||
43 | select PINCTRL_SUNXI_COMMON | ||||
44 | |||||
Chen-Yu Tsai | d22bf40 | 2014-06-17 22:52:52 +0800 | [diff] [blame] | 45 | config PINCTRL_SUN8I_A23_R |
46 | def_bool MACH_SUN8I | ||||
47 | depends on RESET_CONTROLLER | ||||
48 | select PINCTRL_SUNXI_COMMON | ||||
49 | |||||
Maxime Ripard | d5e9fb3 | 2014-10-28 22:41:27 +0100 | [diff] [blame] | 50 | config PINCTRL_SUN9I_A80 |
51 | def_bool MACH_SUN9I | ||||
52 | select PINCTRL_SUNXI_COMMON | ||||
53 | |||||
Maxime Ripard | 5f91077 | 2014-04-18 18:53:02 +0200 | [diff] [blame] | 54 | endif |