blob: 523d6cbd4f087a6996d653c1f143502cac83cf93 [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef RADEON_MODE_H
31#define RADEON_MODE_H
32
33#include <drm_crtc.h>
34#include <drm_mode.h>
35#include <drm_edid.h>
36#include <linux/i2c.h>
37#include <linux/i2c-id.h>
38#include <linux/i2c-algo-bit.h>
Jerome Glissec93bb852009-07-13 21:04:08 +020039#include "radeon_fixed.h"
40
41struct radeon_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +020042
43#define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
44#define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
45#define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
46#define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
47
48enum radeon_connector_type {
49 CONNECTOR_NONE,
50 CONNECTOR_VGA,
51 CONNECTOR_DVI_I,
52 CONNECTOR_DVI_D,
53 CONNECTOR_DVI_A,
54 CONNECTOR_STV,
55 CONNECTOR_CTV,
56 CONNECTOR_LVDS,
57 CONNECTOR_DIGITAL,
58 CONNECTOR_SCART,
59 CONNECTOR_HDMI_TYPE_A,
60 CONNECTOR_HDMI_TYPE_B,
61 CONNECTOR_0XC,
62 CONNECTOR_0XD,
63 CONNECTOR_DIN,
64 CONNECTOR_DISPLAY_PORT,
65 CONNECTOR_UNSUPPORTED
66};
67
68enum radeon_dvi_type {
69 DVI_AUTO,
70 DVI_DIGITAL,
71 DVI_ANALOG
72};
73
74enum radeon_rmx_type {
75 RMX_OFF,
76 RMX_FULL,
77 RMX_CENTER,
78 RMX_ASPECT
79};
80
81enum radeon_tv_std {
82 TV_STD_NTSC,
83 TV_STD_PAL,
84 TV_STD_PAL_M,
85 TV_STD_PAL_60,
86 TV_STD_NTSC_J,
87 TV_STD_SCART_PAL,
88 TV_STD_SECAM,
89 TV_STD_PAL_CN,
90};
91
92struct radeon_i2c_bus_rec {
93 bool valid;
94 uint32_t mask_clk_reg;
95 uint32_t mask_data_reg;
96 uint32_t a_clk_reg;
97 uint32_t a_data_reg;
98 uint32_t put_clk_reg;
99 uint32_t put_data_reg;
100 uint32_t get_clk_reg;
101 uint32_t get_data_reg;
102 uint32_t mask_clk_mask;
103 uint32_t mask_data_mask;
104 uint32_t put_clk_mask;
105 uint32_t put_data_mask;
106 uint32_t get_clk_mask;
107 uint32_t get_data_mask;
108 uint32_t a_clk_mask;
109 uint32_t a_data_mask;
110};
111
112struct radeon_tmds_pll {
113 uint32_t freq;
114 uint32_t value;
115};
116
117#define RADEON_MAX_BIOS_CONNECTOR 16
118
119#define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
120#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
121#define RADEON_PLL_USE_REF_DIV (1 << 2)
122#define RADEON_PLL_LEGACY (1 << 3)
123#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
124#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
125#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
126#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
127#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
128#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
129#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
Alex Deucherd0e275a2009-07-13 11:08:18 -0400130#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200131
132struct radeon_pll {
133 uint16_t reference_freq;
134 uint16_t reference_div;
135 uint32_t pll_in_min;
136 uint32_t pll_in_max;
137 uint32_t pll_out_min;
138 uint32_t pll_out_max;
139 uint16_t xclk;
140
141 uint32_t min_ref_div;
142 uint32_t max_ref_div;
143 uint32_t min_post_div;
144 uint32_t max_post_div;
145 uint32_t min_feedback_div;
146 uint32_t max_feedback_div;
147 uint32_t min_frac_feedback_div;
148 uint32_t max_frac_feedback_div;
149 uint32_t best_vco;
150};
151
152struct radeon_i2c_chan {
153 struct drm_device *dev;
154 struct i2c_adapter adapter;
155 struct i2c_algo_bit_data algo;
156 struct radeon_i2c_bus_rec rec;
157};
158
159/* mostly for macs, but really any system without connector tables */
160enum radeon_connector_table {
161 CT_NONE,
162 CT_GENERIC,
163 CT_IBOOK,
164 CT_POWERBOOK_EXTERNAL,
165 CT_POWERBOOK_INTERNAL,
166 CT_POWERBOOK_VGA,
167 CT_MINI_EXTERNAL,
168 CT_MINI_INTERNAL,
169 CT_IMAC_G5_ISIGHT,
170 CT_EMAC,
171};
172
173struct radeon_mode_info {
174 struct atom_context *atom_context;
175 enum radeon_connector_table connector_table;
176 bool mode_config_initialized;
Jerome Glissec93bb852009-07-13 21:04:08 +0200177 struct radeon_crtc *crtcs[2];
178};
179
180struct radeon_native_mode {
181 /* preferred mode */
182 uint32_t panel_xres, panel_yres;
183 uint32_t hoverplus, hsync_width;
184 uint32_t hblank;
185 uint32_t voverplus, vsync_width;
186 uint32_t vblank;
187 uint32_t dotclock;
188 uint32_t flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200189};
190
Dave Airlie4ce001a2009-08-13 16:32:14 +1000191#define MAX_H_CODE_TIMING_LEN 32
192#define MAX_V_CODE_TIMING_LEN 32
193
194/* need to store these as reading
195 back code tables is excessive */
196struct radeon_tv_regs {
197 uint32_t tv_uv_adr;
198 uint32_t timing_cntl;
199 uint32_t hrestart;
200 uint32_t vrestart;
201 uint32_t frestart;
202 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
203 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
204};
205
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200206struct radeon_crtc {
207 struct drm_crtc base;
208 int crtc_id;
209 u16 lut_r[256], lut_g[256], lut_b[256];
210 bool enabled;
211 bool can_tile;
212 uint32_t crtc_offset;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200213 struct drm_gem_object *cursor_bo;
214 uint64_t cursor_addr;
215 int cursor_width;
216 int cursor_height;
Dave Airlie41623382009-07-09 15:04:19 +1000217 uint32_t legacy_display_base_addr;
Alex Deucherc836e862009-07-13 13:51:03 -0400218 uint32_t legacy_cursor_offset;
Jerome Glissec93bb852009-07-13 21:04:08 +0200219 enum radeon_rmx_type rmx_type;
Jerome Glissec93bb852009-07-13 21:04:08 +0200220 fixed20_12 vsc;
221 fixed20_12 hsc;
222 struct radeon_native_mode native_mode;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200223};
224
225struct radeon_encoder_primary_dac {
226 /* legacy primary dac */
227 uint32_t ps2_pdac_adj;
228};
229
230struct radeon_encoder_lvds {
231 /* legacy lvds */
232 uint16_t panel_vcc_delay;
233 uint8_t panel_pwr_delay;
234 uint8_t panel_digon_delay;
235 uint8_t panel_blon_delay;
236 uint16_t panel_ref_divider;
237 uint8_t panel_post_divider;
238 uint16_t panel_fb_divider;
239 bool use_bios_dividers;
240 uint32_t lvds_gen_cntl;
241 /* panel mode */
242 struct radeon_native_mode native_mode;
243};
244
245struct radeon_encoder_tv_dac {
246 /* legacy tv dac */
247 uint32_t ps2_tvdac_adj;
248 uint32_t ntsc_tvdac_adj;
249 uint32_t pal_tvdac_adj;
250
Dave Airlie4ce001a2009-08-13 16:32:14 +1000251 int h_pos;
252 int v_pos;
253 int h_size;
254 int supported_tv_stds;
255 bool tv_on;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256 enum radeon_tv_std tv_std;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000257 struct radeon_tv_regs tv;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200258};
259
260struct radeon_encoder_int_tmds {
261 /* legacy int tmds */
262 struct radeon_tmds_pll tmds_pll[4];
263};
264
265struct radeon_encoder_atom_dig {
266 /* atom dig */
267 bool coherent_mode;
268 int dig_block;
269 /* atom lvds */
270 uint32_t lvds_misc;
271 uint16_t panel_pwr_delay;
272 /* panel mode */
273 struct radeon_native_mode native_mode;
274};
275
Dave Airlie4ce001a2009-08-13 16:32:14 +1000276struct radeon_encoder_atom_dac {
277 enum radeon_tv_std tv_std;
278};
279
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200280struct radeon_encoder {
281 struct drm_encoder base;
282 uint32_t encoder_id;
283 uint32_t devices;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000284 uint32_t active_device;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200285 uint32_t flags;
286 uint32_t pixel_clock;
287 enum radeon_rmx_type rmx_type;
288 struct radeon_native_mode native_mode;
289 void *enc_priv;
290};
291
292struct radeon_connector_atom_dig {
293 uint32_t igp_lane_info;
294 bool linkb;
295};
296
297struct radeon_connector {
298 struct drm_connector base;
299 uint32_t connector_id;
300 uint32_t devices;
301 struct radeon_i2c_chan *ddc_bus;
Dave Airlie4ce001a2009-08-13 16:32:14 +1000302 bool use_digital;
303 /* we need to mind the EDID between detect
304 and get modes due to analog/digital/tvencoder */
305 struct edid *edid;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306 void *con_priv;
307};
308
309struct radeon_framebuffer {
310 struct drm_framebuffer base;
311 struct drm_gem_object *obj;
312};
313
314extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
315 struct radeon_i2c_bus_rec *rec,
316 const char *name);
317extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
318extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector);
319extern int radeon_ddc_get_modes(struct radeon_connector *radeon_connector);
320
321extern struct drm_encoder *radeon_best_encoder(struct drm_connector *connector);
322
323extern void radeon_compute_pll(struct radeon_pll *pll,
324 uint64_t freq,
325 uint32_t *dot_clock_p,
326 uint32_t *fb_div_p,
327 uint32_t *frac_fb_div_p,
328 uint32_t *ref_div_p,
329 uint32_t *post_div_p,
330 int flags);
331
332struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
333struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
334struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
335struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
336struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
337extern void atombios_external_tmds_setup(struct drm_encoder *encoder, int action);
338extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000339extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200340
341extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
342extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
343 struct drm_framebuffer *old_fb);
344extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
345 struct drm_display_mode *mode,
346 struct drm_display_mode *adjusted_mode,
347 int x, int y,
348 struct drm_framebuffer *old_fb);
349extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
350
351extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
352 struct drm_framebuffer *old_fb);
353extern void radeon_legacy_atom_set_surface(struct drm_crtc *crtc);
354
355extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
356 struct drm_file *file_priv,
357 uint32_t handle,
358 uint32_t width,
359 uint32_t height);
360extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
361 int x, int y);
362
363extern bool radeon_atom_get_clock_info(struct drm_device *dev);
364extern bool radeon_combios_get_clock_info(struct drm_device *dev);
365extern struct radeon_encoder_atom_dig *
366radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
367extern struct radeon_encoder_int_tmds *
368radeon_atombios_get_tmds_info(struct radeon_encoder *encoder);
Alex Deucher6fe7ac32009-06-12 17:26:08 +0000369extern struct radeon_encoder_primary_dac *
370radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
371extern struct radeon_encoder_tv_dac *
372radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200373extern struct radeon_encoder_lvds *
374radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
375extern struct radeon_encoder_int_tmds *
376radeon_combios_get_tmds_info(struct radeon_encoder *encoder);
377extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
378extern struct radeon_encoder_tv_dac *
379radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
380extern struct radeon_encoder_primary_dac *
381radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
382extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
383extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
384extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
385extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
386extern void
387radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
388extern void
389radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
390extern void
391radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
392extern void
393radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
394extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
395 u16 blue, int regno);
396struct drm_framebuffer *radeon_framebuffer_create(struct drm_device *dev,
397 struct drm_mode_fb_cmd *mode_cmd,
398 struct drm_gem_object *obj);
399
400int radeonfb_probe(struct drm_device *dev);
401
402int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
403bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
404bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
405void radeon_atombios_init_crtc(struct drm_device *dev,
406 struct radeon_crtc *radeon_crtc);
407void radeon_legacy_init_crtc(struct drm_device *dev,
408 struct radeon_crtc *radeon_crtc);
409void radeon_i2c_do_lock(struct radeon_connector *radeon_connector, int lock_state);
410
411void radeon_get_clock_info(struct drm_device *dev);
412
413extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
414extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
415
416void radeon_rmx_mode_fixup(struct drm_encoder *encoder,
417 struct drm_display_mode *mode,
418 struct drm_display_mode *adjusted_mode);
419void radeon_enc_destroy(struct drm_encoder *encoder);
420void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
421void radeon_combios_asic_init(struct drm_device *dev);
422extern int radeon_static_clocks_init(struct drm_device *dev);
Jerome Glissec93bb852009-07-13 21:04:08 +0200423bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
424 struct drm_display_mode *mode,
425 struct drm_display_mode *adjusted_mode);
Dave Airlie4ce001a2009-08-13 16:32:14 +1000426void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200427
Dave Airlie4ce001a2009-08-13 16:32:14 +1000428/* legacy tv */
429void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
430 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
431 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
432void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
433 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
434 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
435void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
436 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
437 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
438void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
439 struct drm_display_mode *mode,
440 struct drm_display_mode *adjusted_mode);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200441#endif