Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2014 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/kernel.h> |
| 25 | |
| 26 | #include <drm/drmP.h> |
| 27 | #include <drm/drm_edid.h> |
| 28 | #include "intel_drv.h" |
| 29 | #include "i915_drv.h" |
| 30 | |
Jani Nikula | 87fcb2a | 2014-10-27 16:26:44 +0200 | [diff] [blame] | 31 | static const struct { |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 32 | int clock; |
| 33 | u32 config; |
| 34 | } hdmi_audio_clock[] = { |
| 35 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, |
| 36 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ |
| 37 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, |
| 38 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, |
| 39 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, |
| 40 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, |
| 41 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, |
| 42 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, |
| 43 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, |
| 44 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, |
| 45 | }; |
| 46 | |
| 47 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ |
| 48 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) |
| 49 | { |
| 50 | int i; |
| 51 | |
| 52 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { |
| 53 | if (mode->clock == hdmi_audio_clock[i].clock) |
| 54 | break; |
| 55 | } |
| 56 | |
| 57 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { |
| 58 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); |
| 59 | i = 1; |
| 60 | } |
| 61 | |
| 62 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", |
| 63 | hdmi_audio_clock[i].clock, |
| 64 | hdmi_audio_clock[i].config); |
| 65 | |
| 66 | return hdmi_audio_clock[i].config; |
| 67 | } |
| 68 | |
| 69 | static bool intel_eld_uptodate(struct drm_connector *connector, |
| 70 | int reg_eldv, uint32_t bits_eldv, |
| 71 | int reg_elda, uint32_t bits_elda, |
| 72 | int reg_edid) |
| 73 | { |
| 74 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 75 | uint8_t *eld = connector->eld; |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 76 | uint32_t tmp; |
| 77 | int i; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 78 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 79 | tmp = I915_READ(reg_eldv); |
| 80 | tmp &= bits_eldv; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 81 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 82 | if (!tmp) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 83 | return false; |
| 84 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 85 | tmp = I915_READ(reg_elda); |
| 86 | tmp &= ~bits_elda; |
| 87 | I915_WRITE(reg_elda, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 88 | |
| 89 | for (i = 0; i < eld[2]; i++) |
| 90 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) |
| 91 | return false; |
| 92 | |
| 93 | return true; |
| 94 | } |
| 95 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 96 | static void g4x_audio_codec_enable(struct drm_connector *connector, |
| 97 | struct intel_encoder *encoder, |
| 98 | struct drm_display_mode *mode) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 99 | { |
| 100 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
| 101 | uint8_t *eld = connector->eld; |
| 102 | uint32_t eldv; |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 103 | uint32_t tmp; |
| 104 | int len, i; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 105 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 106 | tmp = I915_READ(G4X_AUD_VID_DID); |
| 107 | if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 108 | eldv = G4X_ELDV_DEVCL_DEVBLC; |
| 109 | else |
| 110 | eldv = G4X_ELDV_DEVCTG; |
| 111 | |
| 112 | if (intel_eld_uptodate(connector, |
| 113 | G4X_AUD_CNTL_ST, eldv, |
Jani Nikula | c46f111 | 2014-10-27 16:26:52 +0200 | [diff] [blame] | 114 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK, |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 115 | G4X_HDMIW_HDMIEDID)) |
| 116 | return; |
| 117 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 118 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
Jani Nikula | c46f111 | 2014-10-27 16:26:52 +0200 | [diff] [blame] | 119 | tmp &= ~(eldv | G4X_ELD_ADDR_MASK); |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 120 | len = (tmp >> 9) & 0x1f; /* ELD buffer size */ |
| 121 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 122 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 123 | len = min_t(int, eld[2], len); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 124 | DRM_DEBUG_DRIVER("ELD size %d\n", len); |
| 125 | for (i = 0; i < len; i++) |
| 126 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); |
| 127 | |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 128 | tmp = I915_READ(G4X_AUD_CNTL_ST); |
| 129 | tmp |= eldv; |
| 130 | I915_WRITE(G4X_AUD_CNTL_ST, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 131 | } |
| 132 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 133 | static void hsw_audio_codec_disable(struct intel_encoder *encoder) |
| 134 | { |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 135 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 136 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
| 137 | enum pipe pipe = intel_crtc->pipe; |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 138 | uint32_t tmp; |
| 139 | |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 140 | DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe)); |
| 141 | |
| 142 | /* Disable timestamps */ |
| 143 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
| 144 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 145 | tmp |= AUD_CONFIG_N_PROG_ENABLE; |
| 146 | tmp &= ~AUD_CONFIG_UPPER_N_MASK; |
| 147 | tmp &= ~AUD_CONFIG_LOWER_N_MASK; |
| 148 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 149 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 150 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
| 151 | |
| 152 | /* Invalidate ELD */ |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 153 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 154 | tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4)); |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 155 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
| 156 | } |
| 157 | |
| 158 | static void hsw_audio_codec_enable(struct drm_connector *connector, |
| 159 | struct intel_encoder *encoder, |
| 160 | struct drm_display_mode *mode) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 161 | { |
| 162 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Jani Nikula | 820d2d7 | 2014-10-27 16:26:47 +0200 | [diff] [blame] | 163 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 164 | enum pipe pipe = intel_crtc->pipe; |
| 165 | const uint8_t *eld = connector->eld; |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 166 | uint32_t tmp; |
| 167 | int len, i; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 168 | |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 169 | DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", |
| 170 | pipe_name(pipe), eld[2]); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 171 | |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 172 | /* Enable audio presence detect, invalidate ELD */ |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 173 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 174 | tmp |= AUDIO_OUTPUT_ENABLE_A << (pipe * 4); |
| 175 | tmp &= ~(AUDIO_ELD_VALID_A << (pipe * 4)); |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 176 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
Jani Nikula | 5fad84a | 2014-11-04 10:30:23 +0200 | [diff] [blame] | 177 | |
| 178 | /* |
| 179 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
| 180 | * disabled during the mode set. The proper fix would be to push the |
| 181 | * rest of the setup into a vblank work item, queued here, but the |
| 182 | * infrastructure is not there yet. |
| 183 | */ |
| 184 | |
| 185 | /* Reset ELD write address */ |
| 186 | tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe)); |
| 187 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
| 188 | I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); |
| 189 | |
| 190 | /* Up to 84 bytes of hw ELD buffer */ |
| 191 | len = min_t(int, eld[2], 21); |
| 192 | for (i = 0; i < len; i++) |
| 193 | I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); |
| 194 | |
| 195 | /* ELD valid */ |
| 196 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
| 197 | tmp |= AUDIO_ELD_VALID_A << (pipe * 4); |
| 198 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); |
| 199 | |
| 200 | /* Enable timestamps */ |
| 201 | tmp = I915_READ(HSW_AUD_CFG(pipe)); |
| 202 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 203 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
| 204 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
| 205 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 206 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 207 | else |
| 208 | tmp |= audio_config_hdmi_pixel_clock(mode); |
| 209 | I915_WRITE(HSW_AUD_CFG(pipe), tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 210 | } |
| 211 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 212 | static void ilk_audio_codec_enable(struct drm_connector *connector, |
| 213 | struct intel_encoder *encoder, |
| 214 | struct drm_display_mode *mode) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 215 | { |
| 216 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Jani Nikula | 820d2d7 | 2014-10-27 16:26:47 +0200 | [diff] [blame] | 217 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 218 | struct intel_digital_port *intel_dig_port = |
| 219 | enc_to_dig_port(&encoder->base); |
| 220 | enum port port = intel_dig_port->port; |
| 221 | enum pipe pipe = intel_crtc->pipe; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 222 | uint8_t *eld = connector->eld; |
| 223 | uint32_t eldv; |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 224 | uint32_t tmp; |
| 225 | int len, i; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 226 | int hdmiw_hdmiedid; |
| 227 | int aud_config; |
| 228 | int aud_cntl_st; |
| 229 | int aud_cntrl_st2; |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 230 | |
| 231 | DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", |
| 232 | port_name(port), pipe_name(pipe), eld[2]); |
| 233 | |
| 234 | /* |
| 235 | * FIXME: We're supposed to wait for vblank here, but we have vblanks |
| 236 | * disabled during the mode set. The proper fix would be to push the |
| 237 | * rest of the setup into a vblank work item, queued here, but the |
| 238 | * infrastructure is not there yet. |
| 239 | */ |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 240 | |
| 241 | if (HAS_PCH_IBX(connector->dev)) { |
| 242 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
| 243 | aud_config = IBX_AUD_CFG(pipe); |
| 244 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); |
| 245 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
| 246 | } else if (IS_VALLEYVIEW(connector->dev)) { |
| 247 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); |
| 248 | aud_config = VLV_AUD_CFG(pipe); |
| 249 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); |
| 250 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; |
| 251 | } else { |
| 252 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
| 253 | aud_config = CPT_AUD_CFG(pipe); |
| 254 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); |
| 255 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
| 256 | } |
| 257 | |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 258 | if (WARN_ON(!port)) { |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 259 | eldv = IBX_ELD_VALIDB; |
| 260 | eldv |= IBX_ELD_VALIDB << 4; |
| 261 | eldv |= IBX_ELD_VALIDB << 8; |
| 262 | } else { |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 263 | eldv = IBX_ELD_VALIDB << ((port - 1) * 4); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 264 | } |
| 265 | |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 266 | /* Invalidate ELD */ |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 267 | tmp = I915_READ(aud_cntrl_st2); |
| 268 | tmp &= ~eldv; |
| 269 | I915_WRITE(aud_cntrl_st2, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 270 | |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 271 | /* Reset ELD write address */ |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 272 | tmp = I915_READ(aud_cntl_st); |
Jani Nikula | c46f111 | 2014-10-27 16:26:52 +0200 | [diff] [blame] | 273 | tmp &= ~IBX_ELD_ADDRESS_MASK; |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 274 | I915_WRITE(aud_cntl_st, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 275 | |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 276 | /* Up to 84 bytes of hw ELD buffer */ |
| 277 | len = min_t(int, eld[2], 21); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 278 | for (i = 0; i < len; i++) |
| 279 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); |
| 280 | |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 281 | /* ELD valid */ |
Jani Nikula | f9f682a | 2014-10-27 16:26:45 +0200 | [diff] [blame] | 282 | tmp = I915_READ(aud_cntrl_st2); |
| 283 | tmp |= eldv; |
| 284 | I915_WRITE(aud_cntrl_st2, tmp); |
Jani Nikula | c6bde93 | 2014-11-04 10:31:28 +0200 | [diff] [blame^] | 285 | |
| 286 | /* Enable timestamps */ |
| 287 | tmp = I915_READ(aud_config); |
| 288 | tmp &= ~AUD_CONFIG_N_VALUE_INDEX; |
| 289 | tmp &= ~AUD_CONFIG_N_PROG_ENABLE; |
| 290 | tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; |
| 291 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 292 | tmp |= AUD_CONFIG_N_VALUE_INDEX; |
| 293 | else |
| 294 | tmp |= audio_config_hdmi_pixel_clock(mode); |
| 295 | I915_WRITE(aud_config, tmp); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 296 | } |
| 297 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 298 | /** |
| 299 | * intel_audio_codec_enable - Enable the audio codec for HD audio |
| 300 | * @intel_encoder: encoder on which to enable audio |
| 301 | * |
| 302 | * The enable sequences may only be performed after enabling the transcoder and |
| 303 | * port, and after completed link training. |
| 304 | */ |
| 305 | void intel_audio_codec_enable(struct intel_encoder *intel_encoder) |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 306 | { |
Jani Nikula | 33d1e7c6 | 2014-10-27 16:26:46 +0200 | [diff] [blame] | 307 | struct drm_encoder *encoder = &intel_encoder->base; |
| 308 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
| 309 | struct drm_display_mode *mode = &crtc->config.adjusted_mode; |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 310 | struct drm_connector *connector; |
| 311 | struct drm_device *dev = encoder->dev; |
| 312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 313 | |
| 314 | connector = drm_select_eld(encoder, mode); |
| 315 | if (!connector) |
| 316 | return; |
| 317 | |
| 318 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
| 319 | connector->base.id, |
| 320 | connector->name, |
| 321 | connector->encoder->base.id, |
| 322 | connector->encoder->name); |
| 323 | |
Jani Nikula | 6189b03 | 2014-10-28 13:53:01 +0200 | [diff] [blame] | 324 | /* ELD Conn_Type */ |
| 325 | connector->eld[5] &= ~(3 << 2); |
| 326 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) |
| 327 | connector->eld[5] |= (1 << 2); |
| 328 | |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 329 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; |
| 330 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 331 | if (dev_priv->display.audio_codec_enable) |
| 332 | dev_priv->display.audio_codec_enable(connector, intel_encoder, mode); |
| 333 | } |
| 334 | |
| 335 | /** |
| 336 | * intel_audio_codec_disable - Disable the audio codec for HD audio |
| 337 | * @encoder: encoder on which to disable audio |
| 338 | * |
| 339 | * The disable sequences must be performed before disabling the transcoder or |
| 340 | * port. |
| 341 | */ |
| 342 | void intel_audio_codec_disable(struct intel_encoder *encoder) |
| 343 | { |
| 344 | struct drm_device *dev = encoder->base.dev; |
| 345 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 346 | |
| 347 | if (dev_priv->display.audio_codec_disable) |
| 348 | dev_priv->display.audio_codec_disable(encoder); |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 349 | } |
| 350 | |
| 351 | /** |
| 352 | * intel_init_audio - Set up chip specific audio functions |
| 353 | * @dev: drm device |
| 354 | */ |
| 355 | void intel_init_audio(struct drm_device *dev) |
| 356 | { |
| 357 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 358 | |
Jani Nikula | 69bfe1a | 2014-10-27 16:26:50 +0200 | [diff] [blame] | 359 | if (IS_G4X(dev)) { |
| 360 | dev_priv->display.audio_codec_enable = g4x_audio_codec_enable; |
| 361 | } else if (IS_VALLEYVIEW(dev)) { |
| 362 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
| 363 | } else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) { |
| 364 | dev_priv->display.audio_codec_enable = hsw_audio_codec_enable; |
| 365 | dev_priv->display.audio_codec_disable = hsw_audio_codec_disable; |
| 366 | } else if (HAS_PCH_SPLIT(dev)) { |
| 367 | dev_priv->display.audio_codec_enable = ilk_audio_codec_enable; |
| 368 | } |
Jani Nikula | 7c10a2b | 2014-10-27 16:26:43 +0200 | [diff] [blame] | 369 | } |