Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
| 4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | #include <linux/module.h> |
| 12 | #include <linux/moduleparam.h> |
| 13 | #include <linux/init.h> |
| 14 | #include <linux/ioport.h> |
| 15 | #include <linux/device.h> |
| 16 | #include <linux/interrupt.h> |
| 17 | #include <linux/delay.h> |
| 18 | #include <linux/err.h> |
| 19 | #include <linux/highmem.h> |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 20 | #include <linux/log2.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 21 | #include <linux/mmc/host.h> |
Russell King | a62c80e | 2006-01-07 13:52:45 +0000 | [diff] [blame] | 22 | #include <linux/amba/bus.h> |
Russell King | f8ce254 | 2006-01-07 16:15:52 +0000 | [diff] [blame] | 23 | #include <linux/clk.h> |
Jens Axboe | bd6dee6 | 2007-10-24 09:01:09 +0200 | [diff] [blame] | 24 | #include <linux/scatterlist.h> |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 25 | #include <linux/gpio.h> |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 26 | #include <linux/amba/mmci.h> |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 27 | #include <linux/regulator/consumer.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 28 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 29 | #include <asm/div64.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <asm/io.h> |
Russell King | c6b8fda | 2005-10-28 14:05:16 +0100 | [diff] [blame] | 31 | #include <asm/sizes.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
| 33 | #include "mmci.h" |
| 34 | |
| 35 | #define DRIVER_NAME "mmci-pl18x" |
| 36 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 37 | static unsigned int fmax = 515633; |
| 38 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 39 | /* |
| 40 | * This must be called with host->lock held |
| 41 | */ |
| 42 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) |
| 43 | { |
| 44 | u32 clk = 0; |
| 45 | |
| 46 | if (desired) { |
| 47 | if (desired >= host->mclk) { |
| 48 | clk = MCI_CLK_BYPASS; |
| 49 | host->cclk = host->mclk; |
| 50 | } else { |
| 51 | clk = host->mclk / (2 * desired) - 1; |
| 52 | if (clk >= 256) |
| 53 | clk = 255; |
| 54 | host->cclk = host->mclk / (2 * (clk + 1)); |
| 55 | } |
Linus Walleij | b43149c | 2009-11-10 08:33:01 +0100 | [diff] [blame] | 56 | if (host->hw_designer == AMBA_VENDOR_ST) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 57 | clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 58 | clk |= MCI_CLK_ENABLE; |
| 59 | /* This hasn't proven to be worthwhile */ |
| 60 | /* clk |= MCI_CLK_PWRSAVE; */ |
| 61 | } |
| 62 | |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 63 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
Linus Walleij | 771dc15 | 2010-04-08 07:38:52 +0100 | [diff] [blame] | 64 | clk |= MCI_4BIT_BUS; |
| 65 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 66 | clk |= MCI_ST_8BIT_BUS; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 67 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 68 | writel(clk, host->base + MMCICLOCK); |
| 69 | } |
| 70 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 71 | static void |
| 72 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) |
| 73 | { |
| 74 | writel(0, host->base + MMCICOMMAND); |
| 75 | |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 76 | BUG_ON(host->data); |
| 77 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 78 | host->mrq = NULL; |
| 79 | host->cmd = NULL; |
| 80 | |
| 81 | if (mrq->data) |
| 82 | mrq->data->bytes_xfered = host->data_xfered; |
| 83 | |
| 84 | /* |
| 85 | * Need to drop the host lock here; mmc_request_done may call |
| 86 | * back into the driver... |
| 87 | */ |
| 88 | spin_unlock(&host->lock); |
| 89 | mmc_request_done(host->mmc, mrq); |
| 90 | spin_lock(&host->lock); |
| 91 | } |
| 92 | |
| 93 | static void mmci_stop_data(struct mmci_host *host) |
| 94 | { |
| 95 | writel(0, host->base + MMCIDATACTRL); |
| 96 | writel(0, host->base + MMCIMASK1); |
| 97 | host->data = NULL; |
| 98 | } |
| 99 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 100 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
| 101 | { |
| 102 | unsigned int flags = SG_MITER_ATOMIC; |
| 103 | |
| 104 | if (data->flags & MMC_DATA_READ) |
| 105 | flags |= SG_MITER_TO_SG; |
| 106 | else |
| 107 | flags |= SG_MITER_FROM_SG; |
| 108 | |
| 109 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
| 110 | } |
| 111 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 112 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
| 113 | { |
| 114 | unsigned int datactrl, timeout, irqmask; |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 115 | unsigned long long clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | void __iomem *base; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 117 | int blksz_bits; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 119 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
| 120 | data->blksz, data->blocks, data->flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 121 | |
| 122 | host->data = data; |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 123 | host->size = data->blksz; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 124 | host->data_xfered = 0; |
| 125 | |
| 126 | mmci_init_sg(host, data); |
| 127 | |
Russell King | 7b09cda | 2005-07-01 12:02:59 +0100 | [diff] [blame] | 128 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
| 129 | do_div(clks, 1000000000UL); |
| 130 | |
| 131 | timeout = data->timeout_clks + (unsigned int)clks; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 132 | |
| 133 | base = host->base; |
| 134 | writel(timeout, base + MMCIDATATIMER); |
| 135 | writel(host->size, base + MMCIDATALENGTH); |
| 136 | |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 137 | blksz_bits = ffs(data->blksz) - 1; |
| 138 | BUG_ON(1 << blksz_bits != data->blksz); |
| 139 | |
| 140 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | if (data->flags & MMC_DATA_READ) { |
| 142 | datactrl |= MCI_DPSM_DIRECTION; |
| 143 | irqmask = MCI_RXFIFOHALFFULLMASK; |
Russell King | 0425a14 | 2006-02-16 16:48:31 +0000 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * If we have less than a FIFOSIZE of bytes to transfer, |
| 147 | * trigger a PIO interrupt as soon as any data is available. |
| 148 | */ |
| 149 | if (host->size < MCI_FIFOSIZE) |
| 150 | irqmask |= MCI_RXDATAAVLBLMASK; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | } else { |
| 152 | /* |
| 153 | * We don't actually need to include "FIFO empty" here |
| 154 | * since its implicit in "FIFO half empty". |
| 155 | */ |
| 156 | irqmask = MCI_TXFIFOHALFEMPTYMASK; |
| 157 | } |
| 158 | |
| 159 | writel(datactrl, base + MMCIDATACTRL); |
| 160 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
| 161 | writel(irqmask, base + MMCIMASK1); |
| 162 | } |
| 163 | |
| 164 | static void |
| 165 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) |
| 166 | { |
| 167 | void __iomem *base = host->base; |
| 168 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 169 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 170 | cmd->opcode, cmd->arg, cmd->flags); |
| 171 | |
| 172 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { |
| 173 | writel(0, base + MMCICOMMAND); |
| 174 | udelay(1); |
| 175 | } |
| 176 | |
| 177 | c |= cmd->opcode | MCI_CPSM_ENABLE; |
Russell King | e922517 | 2006-02-02 12:23:12 +0000 | [diff] [blame] | 178 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 179 | if (cmd->flags & MMC_RSP_136) |
| 180 | c |= MCI_CPSM_LONGRSP; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 181 | c |= MCI_CPSM_RESPONSE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 182 | } |
| 183 | if (/*interrupt*/0) |
| 184 | c |= MCI_CPSM_INTERRUPT; |
| 185 | |
| 186 | host->cmd = cmd; |
| 187 | |
| 188 | writel(cmd->arg, base + MMCIARGUMENT); |
| 189 | writel(c, base + MMCICOMMAND); |
| 190 | } |
| 191 | |
| 192 | static void |
| 193 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, |
| 194 | unsigned int status) |
| 195 | { |
| 196 | if (status & MCI_DATABLOCKEND) { |
Russell King | 3bc87f2 | 2006-08-27 13:51:28 +0100 | [diff] [blame] | 197 | host->data_xfered += data->blksz; |
Linus Walleij | f28e8a4 | 2010-01-25 07:14:46 +0100 | [diff] [blame] | 198 | #ifdef CONFIG_ARCH_U300 |
| 199 | /* |
| 200 | * On the U300 some signal or other is |
| 201 | * badly routed so that a data write does |
| 202 | * not properly terminate with a MCI_DATAEND |
| 203 | * status flag. This quirk will make writes |
| 204 | * work again. |
| 205 | */ |
| 206 | if (data->flags & MMC_DATA_WRITE) |
| 207 | status |= MCI_DATAEND; |
| 208 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 209 | } |
| 210 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 211 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | if (status & MCI_DATACRCFAIL) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 213 | data->error = -EILSEQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | else if (status & MCI_DATATIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 215 | data->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 216 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 217 | data->error = -EIO; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | status |= MCI_DATAEND; |
Russell King | e9c091b | 2006-01-04 16:24:05 +0000 | [diff] [blame] | 219 | |
| 220 | /* |
| 221 | * We hit an error condition. Ensure that any data |
| 222 | * partially written to a page is properly coherent. |
| 223 | */ |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 224 | if (data->flags & MMC_DATA_READ) { |
| 225 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
| 226 | unsigned long flags; |
| 227 | |
| 228 | local_irq_save(flags); |
| 229 | if (sg_miter_next(sg_miter)) { |
| 230 | flush_dcache_page(sg_miter->page); |
| 231 | sg_miter_stop(sg_miter); |
| 232 | } |
| 233 | local_irq_restore(flags); |
| 234 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 235 | } |
| 236 | if (status & MCI_DATAEND) { |
| 237 | mmci_stop_data(host); |
| 238 | |
| 239 | if (!data->stop) { |
| 240 | mmci_request_end(host, data->mrq); |
| 241 | } else { |
| 242 | mmci_start_command(host, data->stop, 0); |
| 243 | } |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | static void |
| 248 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, |
| 249 | unsigned int status) |
| 250 | { |
| 251 | void __iomem *base = host->base; |
| 252 | |
| 253 | host->cmd = NULL; |
| 254 | |
| 255 | cmd->resp[0] = readl(base + MMCIRESPONSE0); |
| 256 | cmd->resp[1] = readl(base + MMCIRESPONSE1); |
| 257 | cmd->resp[2] = readl(base + MMCIRESPONSE2); |
| 258 | cmd->resp[3] = readl(base + MMCIRESPONSE3); |
| 259 | |
| 260 | if (status & MCI_CMDTIMEOUT) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 261 | cmd->error = -ETIMEDOUT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 262 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 263 | cmd->error = -EILSEQ; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | } |
| 265 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 266 | if (!cmd->data || cmd->error) { |
Russell King | e47c222 | 2007-01-08 16:42:51 +0000 | [diff] [blame] | 267 | if (host->data) |
| 268 | mmci_stop_data(host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | mmci_request_end(host, cmd->mrq); |
| 270 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { |
| 271 | mmci_start_data(host, cmd->data); |
| 272 | } |
| 273 | } |
| 274 | |
| 275 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
| 276 | { |
| 277 | void __iomem *base = host->base; |
| 278 | char *ptr = buffer; |
| 279 | u32 status; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 280 | int host_remain = host->size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | |
| 282 | do { |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 283 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 284 | |
| 285 | if (count > remain) |
| 286 | count = remain; |
| 287 | |
| 288 | if (count <= 0) |
| 289 | break; |
| 290 | |
| 291 | readsl(base + MMCIFIFO, ptr, count >> 2); |
| 292 | |
| 293 | ptr += count; |
| 294 | remain -= count; |
Linus Walleij | 26eed9a | 2008-04-26 23:39:44 +0100 | [diff] [blame] | 295 | host_remain -= count; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | |
| 297 | if (remain == 0) |
| 298 | break; |
| 299 | |
| 300 | status = readl(base + MMCISTATUS); |
| 301 | } while (status & MCI_RXDATAAVLBL); |
| 302 | |
| 303 | return ptr - buffer; |
| 304 | } |
| 305 | |
| 306 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) |
| 307 | { |
| 308 | void __iomem *base = host->base; |
| 309 | char *ptr = buffer; |
| 310 | |
| 311 | do { |
| 312 | unsigned int count, maxcnt; |
| 313 | |
| 314 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; |
| 315 | count = min(remain, maxcnt); |
| 316 | |
| 317 | writesl(base + MMCIFIFO, ptr, count >> 2); |
| 318 | |
| 319 | ptr += count; |
| 320 | remain -= count; |
| 321 | |
| 322 | if (remain == 0) |
| 323 | break; |
| 324 | |
| 325 | status = readl(base + MMCISTATUS); |
| 326 | } while (status & MCI_TXFIFOHALFEMPTY); |
| 327 | |
| 328 | return ptr - buffer; |
| 329 | } |
| 330 | |
| 331 | /* |
| 332 | * PIO data transfer IRQ handler. |
| 333 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 334 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 335 | { |
| 336 | struct mmci_host *host = dev_id; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 337 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 338 | void __iomem *base = host->base; |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 339 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | u32 status; |
| 341 | |
| 342 | status = readl(base + MMCISTATUS); |
| 343 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 344 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 345 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 346 | local_irq_save(flags); |
| 347 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | do { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | unsigned int remain, len; |
| 350 | char *buffer; |
| 351 | |
| 352 | /* |
| 353 | * For write, we only need to test the half-empty flag |
| 354 | * here - if the FIFO is completely empty, then by |
| 355 | * definition it is more than half empty. |
| 356 | * |
| 357 | * For read, check for data available. |
| 358 | */ |
| 359 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) |
| 360 | break; |
| 361 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 362 | if (!sg_miter_next(sg_miter)) |
| 363 | break; |
| 364 | |
| 365 | buffer = sg_miter->addr; |
| 366 | remain = sg_miter->length; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 367 | |
| 368 | len = 0; |
| 369 | if (status & MCI_RXACTIVE) |
| 370 | len = mmci_pio_read(host, buffer, remain); |
| 371 | if (status & MCI_TXACTIVE) |
| 372 | len = mmci_pio_write(host, buffer, remain, status); |
| 373 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 374 | sg_miter->consumed = len; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 375 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | host->size -= len; |
| 377 | remain -= len; |
| 378 | |
| 379 | if (remain) |
| 380 | break; |
| 381 | |
Russell King | e9c091b | 2006-01-04 16:24:05 +0000 | [diff] [blame] | 382 | if (status & MCI_RXACTIVE) |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 383 | flush_dcache_page(sg_miter->page); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | |
| 385 | status = readl(base + MMCISTATUS); |
| 386 | } while (1); |
| 387 | |
Rabin Vincent | 4ce1d6c | 2010-07-21 12:44:58 +0100 | [diff] [blame^] | 388 | sg_miter_stop(sg_miter); |
| 389 | |
| 390 | local_irq_restore(flags); |
| 391 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 392 | /* |
| 393 | * If we're nearing the end of the read, switch to |
| 394 | * "any data available" mode. |
| 395 | */ |
| 396 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) |
| 397 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); |
| 398 | |
| 399 | /* |
| 400 | * If we run out of data, disable the data IRQs; this |
| 401 | * prevents a race where the FIFO becomes empty before |
| 402 | * the chip itself has disabled the data path, and |
| 403 | * stops us racing with our data end IRQ. |
| 404 | */ |
| 405 | if (host->size == 0) { |
| 406 | writel(0, base + MMCIMASK1); |
| 407 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
| 408 | } |
| 409 | |
| 410 | return IRQ_HANDLED; |
| 411 | } |
| 412 | |
| 413 | /* |
| 414 | * Handle completion of command and data transfers. |
| 415 | */ |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 416 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 417 | { |
| 418 | struct mmci_host *host = dev_id; |
| 419 | u32 status; |
| 420 | int ret = 0; |
| 421 | |
| 422 | spin_lock(&host->lock); |
| 423 | |
| 424 | do { |
| 425 | struct mmc_command *cmd; |
| 426 | struct mmc_data *data; |
| 427 | |
| 428 | status = readl(host->base + MMCISTATUS); |
| 429 | status &= readl(host->base + MMCIMASK0); |
| 430 | writel(status, host->base + MMCICLEAR); |
| 431 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 432 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | |
| 434 | data = host->data; |
| 435 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| |
| 436 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) |
| 437 | mmci_data_irq(host, data, status); |
| 438 | |
| 439 | cmd = host->cmd; |
| 440 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) |
| 441 | mmci_cmd_irq(host, cmd, status); |
| 442 | |
| 443 | ret = 1; |
| 444 | } while (status); |
| 445 | |
| 446 | spin_unlock(&host->lock); |
| 447 | |
| 448 | return IRQ_RETVAL(ret); |
| 449 | } |
| 450 | |
| 451 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 452 | { |
| 453 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 454 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 455 | |
| 456 | WARN_ON(host->mrq != NULL); |
| 457 | |
Nicolas Pitre | 019a5f5 | 2007-10-11 01:06:03 -0400 | [diff] [blame] | 458 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 459 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
| 460 | mrq->data->blksz); |
Pierre Ossman | 255d01a | 2007-07-24 20:38:53 +0200 | [diff] [blame] | 461 | mrq->cmd->error = -EINVAL; |
| 462 | mmc_request_done(mmc, mrq); |
| 463 | return; |
| 464 | } |
| 465 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 466 | spin_lock_irqsave(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 467 | |
| 468 | host->mrq = mrq; |
| 469 | |
| 470 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
| 471 | mmci_start_data(host, mrq->data); |
| 472 | |
| 473 | mmci_start_command(host, mrq->cmd, 0); |
| 474 | |
Linus Walleij | 9e94302 | 2008-10-24 21:17:50 +0100 | [diff] [blame] | 475 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 476 | } |
| 477 | |
| 478 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 479 | { |
| 480 | struct mmci_host *host = mmc_priv(mmc); |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 481 | u32 pwr = 0; |
| 482 | unsigned long flags; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 483 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 484 | switch (ios->power_mode) { |
| 485 | case MMC_POWER_OFF: |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 486 | if(host->vcc && |
| 487 | regulator_is_enabled(host->vcc)) |
| 488 | regulator_disable(host->vcc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 489 | break; |
| 490 | case MMC_POWER_UP: |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 491 | #ifdef CONFIG_REGULATOR |
| 492 | if (host->vcc) |
| 493 | /* This implicitly enables the regulator */ |
| 494 | mmc_regulator_set_ocr(host->vcc, ios->vdd); |
| 495 | #endif |
| 496 | /* |
| 497 | * The translate_vdd function is not used if you have |
| 498 | * an external regulator, or your design is really weird. |
| 499 | * Using it would mean sending in power control BOTH using |
| 500 | * a regulator AND the 4 MMCIPWR bits. If we don't have |
| 501 | * a regulator, we might have some other platform specific |
| 502 | * power control behind this translate function. |
| 503 | */ |
| 504 | if (!host->vcc && host->plat->translate_vdd) |
| 505 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 506 | /* The ST version does not have this, fall through to POWER_ON */ |
Linus Walleij | f17a1f0 | 2009-08-04 01:01:02 +0100 | [diff] [blame] | 507 | if (host->hw_designer != AMBA_VENDOR_ST) { |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 508 | pwr |= MCI_PWR_UP; |
| 509 | break; |
| 510 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 511 | case MMC_POWER_ON: |
| 512 | pwr |= MCI_PWR_ON; |
| 513 | break; |
| 514 | } |
| 515 | |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 516 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
Linus Walleij | f17a1f0 | 2009-08-04 01:01:02 +0100 | [diff] [blame] | 517 | if (host->hw_designer != AMBA_VENDOR_ST) |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 518 | pwr |= MCI_ROD; |
| 519 | else { |
| 520 | /* |
| 521 | * The ST Micro variant use the ROD bit for something |
| 522 | * else and only has OD (Open Drain). |
| 523 | */ |
| 524 | pwr |= MCI_OD; |
| 525 | } |
| 526 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 527 | |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 528 | spin_lock_irqsave(&host->lock, flags); |
| 529 | |
| 530 | mmci_set_clkreg(host, ios->clock); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 531 | |
| 532 | if (host->pwr != pwr) { |
| 533 | host->pwr = pwr; |
| 534 | writel(pwr, host->base + MMCIPOWER); |
| 535 | } |
Linus Walleij | a6a6464 | 2009-09-14 12:56:14 +0100 | [diff] [blame] | 536 | |
| 537 | spin_unlock_irqrestore(&host->lock, flags); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 538 | } |
| 539 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 540 | static int mmci_get_ro(struct mmc_host *mmc) |
| 541 | { |
| 542 | struct mmci_host *host = mmc_priv(mmc); |
| 543 | |
| 544 | if (host->gpio_wp == -ENOSYS) |
| 545 | return -ENOSYS; |
| 546 | |
| 547 | return gpio_get_value(host->gpio_wp); |
| 548 | } |
| 549 | |
| 550 | static int mmci_get_cd(struct mmc_host *mmc) |
| 551 | { |
| 552 | struct mmci_host *host = mmc_priv(mmc); |
| 553 | unsigned int status; |
| 554 | |
| 555 | if (host->gpio_cd == -ENOSYS) |
| 556 | status = host->plat->status(mmc_dev(host->mmc)); |
| 557 | else |
| 558 | status = gpio_get_value(host->gpio_cd); |
| 559 | |
| 560 | return !status; |
| 561 | } |
| 562 | |
David Brownell | ab7aefd | 2006-11-12 17:55:30 -0800 | [diff] [blame] | 563 | static const struct mmc_host_ops mmci_ops = { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 564 | .request = mmci_request, |
| 565 | .set_ios = mmci_set_ios, |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 566 | .get_ro = mmci_get_ro, |
| 567 | .get_cd = mmci_get_cd, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | }; |
| 569 | |
| 570 | static void mmci_check_status(unsigned long data) |
| 571 | { |
| 572 | struct mmci_host *host = (struct mmci_host *)data; |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 573 | unsigned int status = mmci_get_cd(host->mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 574 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | if (status ^ host->oldstat) |
Richard Purdie | 8dc0033 | 2005-09-08 17:53:01 +0100 | [diff] [blame] | 576 | mmc_detect_change(host->mmc, 0); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 577 | |
| 578 | host->oldstat = status; |
| 579 | mod_timer(&host->timer, jiffies + HZ); |
| 580 | } |
| 581 | |
Alessandro Rubini | 03fbdb1 | 2009-05-20 22:39:08 +0100 | [diff] [blame] | 582 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | { |
Linus Walleij | 6ef297f | 2009-09-22 14:29:36 +0100 | [diff] [blame] | 584 | struct mmci_platform_data *plat = dev->dev.platform_data; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 585 | struct mmci_host *host; |
| 586 | struct mmc_host *mmc; |
| 587 | int ret; |
| 588 | |
| 589 | /* must have platform data */ |
| 590 | if (!plat) { |
| 591 | ret = -EINVAL; |
| 592 | goto out; |
| 593 | } |
| 594 | |
| 595 | ret = amba_request_regions(dev, DRIVER_NAME); |
| 596 | if (ret) |
| 597 | goto out; |
| 598 | |
| 599 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
| 600 | if (!mmc) { |
| 601 | ret = -ENOMEM; |
| 602 | goto rel_regions; |
| 603 | } |
| 604 | |
| 605 | host = mmc_priv(mmc); |
Rabin Vincent | 4ea580f | 2009-04-17 08:44:19 +0530 | [diff] [blame] | 606 | host->mmc = mmc; |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 607 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 608 | host->gpio_wp = -ENOSYS; |
| 609 | host->gpio_cd = -ENOSYS; |
| 610 | |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 611 | host->hw_designer = amba_manf(dev); |
| 612 | host->hw_revision = amba_rev(dev); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 613 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
| 614 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); |
Russell King | 012b7d3 | 2009-07-09 15:13:56 +0100 | [diff] [blame] | 615 | |
Russell King | ee569c4 | 2008-11-30 17:38:14 +0000 | [diff] [blame] | 616 | host->clk = clk_get(&dev->dev, NULL); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 617 | if (IS_ERR(host->clk)) { |
| 618 | ret = PTR_ERR(host->clk); |
| 619 | host->clk = NULL; |
| 620 | goto host_free; |
| 621 | } |
| 622 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 623 | ret = clk_enable(host->clk); |
| 624 | if (ret) |
Russell King | a8d3584 | 2006-01-03 18:41:37 +0000 | [diff] [blame] | 625 | goto clk_free; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 626 | |
| 627 | host->plat = plat; |
| 628 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 629 | /* |
| 630 | * According to the spec, mclk is max 100 MHz, |
| 631 | * so we try to adjust the clock down to this, |
| 632 | * (if possible). |
| 633 | */ |
| 634 | if (host->mclk > 100000000) { |
| 635 | ret = clk_set_rate(host->clk, 100000000); |
| 636 | if (ret < 0) |
| 637 | goto clk_disable; |
| 638 | host->mclk = clk_get_rate(host->clk); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 639 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
| 640 | host->mclk); |
Linus Walleij | c8df9a5 | 2008-04-29 09:34:07 +0100 | [diff] [blame] | 641 | } |
Linus Walleij | dc890c2 | 2009-06-07 23:27:31 +0100 | [diff] [blame] | 642 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 643 | if (!host->base) { |
| 644 | ret = -ENOMEM; |
| 645 | goto clk_disable; |
| 646 | } |
| 647 | |
| 648 | mmc->ops = &mmci_ops; |
| 649 | mmc->f_min = (host->mclk + 511) / 512; |
Linus Walleij | 808d97c | 2010-04-08 07:39:38 +0100 | [diff] [blame] | 650 | /* |
| 651 | * If the platform data supplies a maximum operating |
| 652 | * frequency, this takes precedence. Else, we fall back |
| 653 | * to using the module parameter, which has a (low) |
| 654 | * default value in case it is not specified. Either |
| 655 | * value must not exceed the clock rate into the block, |
| 656 | * of course. |
| 657 | */ |
| 658 | if (plat->f_max) |
| 659 | mmc->f_max = min(host->mclk, plat->f_max); |
| 660 | else |
| 661 | mmc->f_max = min(host->mclk, fmax); |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 662 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
| 663 | |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 664 | #ifdef CONFIG_REGULATOR |
| 665 | /* If we're using the regulator framework, try to fetch a regulator */ |
| 666 | host->vcc = regulator_get(&dev->dev, "vmmc"); |
| 667 | if (IS_ERR(host->vcc)) |
| 668 | host->vcc = NULL; |
| 669 | else { |
| 670 | int mask = mmc_regulator_get_ocrmask(host->vcc); |
| 671 | |
| 672 | if (mask < 0) |
| 673 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", |
| 674 | mask); |
| 675 | else { |
| 676 | host->mmc->ocr_avail = (u32) mask; |
| 677 | if (plat->ocr_mask) |
| 678 | dev_warn(&dev->dev, |
| 679 | "Provided ocr_mask/setpower will not be used " |
| 680 | "(using regulator instead)\n"); |
| 681 | } |
| 682 | } |
| 683 | #endif |
| 684 | /* Fall back to platform data if no regulator is found */ |
| 685 | if (host->vcc == NULL) |
| 686 | mmc->ocr_avail = plat->ocr_mask; |
Linus Walleij | 9e6c82c | 2009-09-14 12:57:11 +0100 | [diff] [blame] | 687 | mmc->caps = plat->capabilities; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 688 | |
| 689 | /* |
| 690 | * We can do SGIO |
| 691 | */ |
| 692 | mmc->max_hw_segs = 16; |
| 693 | mmc->max_phys_segs = NR_SG; |
| 694 | |
| 695 | /* |
| 696 | * Since we only have a 16-bit data length register, we must |
| 697 | * ensure that we don't exceed 2^16-1 bytes in a single request. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 699 | mmc->max_req_size = 65535; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 700 | |
| 701 | /* |
| 702 | * Set the maximum segment size. Since we aren't doing DMA |
| 703 | * (yet) we are only limited by the data length register. |
| 704 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 705 | mmc->max_seg_size = mmc->max_req_size; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 706 | |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 707 | /* |
| 708 | * Block size can be up to 2048 bytes, but must be a power of two. |
| 709 | */ |
| 710 | mmc->max_blk_size = 2048; |
| 711 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 712 | /* |
| 713 | * No limit on the number of blocks transferred. |
| 714 | */ |
| 715 | mmc->max_blk_count = mmc->max_req_size; |
| 716 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 717 | spin_lock_init(&host->lock); |
| 718 | |
| 719 | writel(0, host->base + MMCIMASK0); |
| 720 | writel(0, host->base + MMCIMASK1); |
| 721 | writel(0xfff, host->base + MMCICLEAR); |
| 722 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 723 | if (gpio_is_valid(plat->gpio_cd)) { |
| 724 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); |
| 725 | if (ret == 0) |
| 726 | ret = gpio_direction_input(plat->gpio_cd); |
| 727 | if (ret == 0) |
| 728 | host->gpio_cd = plat->gpio_cd; |
| 729 | else if (ret != -ENOSYS) |
| 730 | goto err_gpio_cd; |
| 731 | } |
| 732 | if (gpio_is_valid(plat->gpio_wp)) { |
| 733 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); |
| 734 | if (ret == 0) |
| 735 | ret = gpio_direction_input(plat->gpio_wp); |
| 736 | if (ret == 0) |
| 737 | host->gpio_wp = plat->gpio_wp; |
| 738 | else if (ret != -ENOSYS) |
| 739 | goto err_gpio_wp; |
| 740 | } |
| 741 | |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 742 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 743 | if (ret) |
| 744 | goto unmap; |
| 745 | |
Thomas Gleixner | dace145 | 2006-07-01 19:29:38 -0700 | [diff] [blame] | 746 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 747 | if (ret) |
| 748 | goto irq0_free; |
| 749 | |
| 750 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
| 751 | |
| 752 | amba_set_drvdata(dev, mmc); |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 753 | host->oldstat = mmci_get_cd(host->mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | |
| 755 | mmc_add_host(mmc); |
| 756 | |
Linus Walleij | 64de028 | 2010-02-19 01:09:10 +0100 | [diff] [blame] | 757 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
Russell King | d366b64 | 2005-08-19 09:40:08 +0100 | [diff] [blame] | 758 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
Greg Kroah-Hartman | e29419f | 2006-06-12 15:20:16 -0700 | [diff] [blame] | 759 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 760 | |
| 761 | init_timer(&host->timer); |
| 762 | host->timer.data = (unsigned long)host; |
| 763 | host->timer.function = mmci_check_status; |
| 764 | host->timer.expires = jiffies + HZ; |
| 765 | add_timer(&host->timer); |
| 766 | |
| 767 | return 0; |
| 768 | |
| 769 | irq0_free: |
| 770 | free_irq(dev->irq[0], host); |
| 771 | unmap: |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 772 | if (host->gpio_wp != -ENOSYS) |
| 773 | gpio_free(host->gpio_wp); |
| 774 | err_gpio_wp: |
| 775 | if (host->gpio_cd != -ENOSYS) |
| 776 | gpio_free(host->gpio_cd); |
| 777 | err_gpio_cd: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 778 | iounmap(host->base); |
| 779 | clk_disable: |
| 780 | clk_disable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 781 | clk_free: |
| 782 | clk_put(host->clk); |
| 783 | host_free: |
| 784 | mmc_free_host(mmc); |
| 785 | rel_regions: |
| 786 | amba_release_regions(dev); |
| 787 | out: |
| 788 | return ret; |
| 789 | } |
| 790 | |
Linus Walleij | 6dc4a47 | 2009-03-07 00:23:52 +0100 | [diff] [blame] | 791 | static int __devexit mmci_remove(struct amba_device *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | { |
| 793 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 794 | |
| 795 | amba_set_drvdata(dev, NULL); |
| 796 | |
| 797 | if (mmc) { |
| 798 | struct mmci_host *host = mmc_priv(mmc); |
| 799 | |
| 800 | del_timer_sync(&host->timer); |
| 801 | |
| 802 | mmc_remove_host(mmc); |
| 803 | |
| 804 | writel(0, host->base + MMCIMASK0); |
| 805 | writel(0, host->base + MMCIMASK1); |
| 806 | |
| 807 | writel(0, host->base + MMCICOMMAND); |
| 808 | writel(0, host->base + MMCIDATACTRL); |
| 809 | |
| 810 | free_irq(dev->irq[0], host); |
| 811 | free_irq(dev->irq[1], host); |
| 812 | |
Russell King | 8900144 | 2009-07-09 15:16:07 +0100 | [diff] [blame] | 813 | if (host->gpio_wp != -ENOSYS) |
| 814 | gpio_free(host->gpio_wp); |
| 815 | if (host->gpio_cd != -ENOSYS) |
| 816 | gpio_free(host->gpio_cd); |
| 817 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 818 | iounmap(host->base); |
| 819 | clk_disable(host->clk); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 820 | clk_put(host->clk); |
| 821 | |
Linus Walleij | 34e84f3 | 2009-09-22 14:41:40 +0100 | [diff] [blame] | 822 | if (regulator_is_enabled(host->vcc)) |
| 823 | regulator_disable(host->vcc); |
| 824 | regulator_put(host->vcc); |
| 825 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 826 | mmc_free_host(mmc); |
| 827 | |
| 828 | amba_release_regions(dev); |
| 829 | } |
| 830 | |
| 831 | return 0; |
| 832 | } |
| 833 | |
| 834 | #ifdef CONFIG_PM |
Pavel Machek | e5378ca | 2005-04-16 15:25:29 -0700 | [diff] [blame] | 835 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | { |
| 837 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 838 | int ret = 0; |
| 839 | |
| 840 | if (mmc) { |
| 841 | struct mmci_host *host = mmc_priv(mmc); |
| 842 | |
Matt Fleming | 1a13f8f | 2010-05-26 14:42:08 -0700 | [diff] [blame] | 843 | ret = mmc_suspend_host(mmc); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | if (ret == 0) |
| 845 | writel(0, host->base + MMCIMASK0); |
| 846 | } |
| 847 | |
| 848 | return ret; |
| 849 | } |
| 850 | |
| 851 | static int mmci_resume(struct amba_device *dev) |
| 852 | { |
| 853 | struct mmc_host *mmc = amba_get_drvdata(dev); |
| 854 | int ret = 0; |
| 855 | |
| 856 | if (mmc) { |
| 857 | struct mmci_host *host = mmc_priv(mmc); |
| 858 | |
| 859 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
| 860 | |
| 861 | ret = mmc_resume_host(mmc); |
| 862 | } |
| 863 | |
| 864 | return ret; |
| 865 | } |
| 866 | #else |
| 867 | #define mmci_suspend NULL |
| 868 | #define mmci_resume NULL |
| 869 | #endif |
| 870 | |
| 871 | static struct amba_id mmci_ids[] = { |
| 872 | { |
| 873 | .id = 0x00041180, |
| 874 | .mask = 0x000fffff, |
| 875 | }, |
| 876 | { |
| 877 | .id = 0x00041181, |
| 878 | .mask = 0x000fffff, |
| 879 | }, |
Linus Walleij | cc30d60 | 2009-01-04 15:18:54 +0100 | [diff] [blame] | 880 | /* ST Micro variants */ |
| 881 | { |
| 882 | .id = 0x00180180, |
| 883 | .mask = 0x00ffffff, |
| 884 | }, |
| 885 | { |
| 886 | .id = 0x00280180, |
| 887 | .mask = 0x00ffffff, |
| 888 | }, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | { 0, 0 }, |
| 890 | }; |
| 891 | |
| 892 | static struct amba_driver mmci_driver = { |
| 893 | .drv = { |
| 894 | .name = DRIVER_NAME, |
| 895 | }, |
| 896 | .probe = mmci_probe, |
Linus Walleij | 6dc4a47 | 2009-03-07 00:23:52 +0100 | [diff] [blame] | 897 | .remove = __devexit_p(mmci_remove), |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 898 | .suspend = mmci_suspend, |
| 899 | .resume = mmci_resume, |
| 900 | .id_table = mmci_ids, |
| 901 | }; |
| 902 | |
| 903 | static int __init mmci_init(void) |
| 904 | { |
| 905 | return amba_driver_register(&mmci_driver); |
| 906 | } |
| 907 | |
| 908 | static void __exit mmci_exit(void) |
| 909 | { |
| 910 | amba_driver_unregister(&mmci_driver); |
| 911 | } |
| 912 | |
| 913 | module_init(mmci_init); |
| 914 | module_exit(mmci_exit); |
| 915 | module_param(fmax, uint, 0444); |
| 916 | |
| 917 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); |
| 918 | MODULE_LICENSE("GPL"); |