Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs |
| 3 | * Copyright (C) 2013, Intel Corporation |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | */ |
| 9 | |
| 10 | #ifndef SPI_PXA2XX_H |
| 11 | #define SPI_PXA2XX_H |
| 12 | |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 13 | #include <linux/atomic.h> |
| 14 | #include <linux/dmaengine.h> |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 15 | #include <linux/errno.h> |
| 16 | #include <linux/io.h> |
| 17 | #include <linux/interrupt.h> |
| 18 | #include <linux/platform_device.h> |
| 19 | #include <linux/pxa2xx_ssp.h> |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 20 | #include <linux/scatterlist.h> |
| 21 | #include <linux/sizes.h> |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 22 | #include <linux/spi/spi.h> |
| 23 | #include <linux/spi/pxa2xx_spi.h> |
| 24 | |
| 25 | struct driver_data { |
| 26 | /* Driver model hookup */ |
| 27 | struct platform_device *pdev; |
| 28 | |
| 29 | /* SSP Info */ |
| 30 | struct ssp_device *ssp; |
| 31 | |
| 32 | /* SPI framework hookup */ |
| 33 | enum pxa_ssp_type ssp_type; |
| 34 | struct spi_master *master; |
| 35 | |
| 36 | /* PXA hookup */ |
| 37 | struct pxa2xx_spi_master *master_info; |
| 38 | |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 39 | /* SSP register addresses */ |
| 40 | void __iomem *ioaddr; |
| 41 | u32 ssdr_physical; |
| 42 | |
| 43 | /* SSP masks*/ |
| 44 | u32 dma_cr1; |
| 45 | u32 int_cr1; |
| 46 | u32 clear_sr; |
| 47 | u32 mask_sr; |
| 48 | |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 49 | /* Message Transfer pump */ |
| 50 | struct tasklet_struct pump_transfers; |
| 51 | |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 52 | /* DMA engine support */ |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 53 | atomic_t dma_running; |
| 54 | |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 55 | /* Current message transfer state info */ |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 56 | struct spi_transfer *cur_transfer; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 57 | size_t len; |
| 58 | void *tx; |
| 59 | void *tx_end; |
| 60 | void *rx; |
| 61 | void *rx_end; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 62 | u8 n_bytes; |
| 63 | int (*write)(struct driver_data *drv_data); |
| 64 | int (*read)(struct driver_data *drv_data); |
| 65 | irqreturn_t (*transfer_handler)(struct driver_data *drv_data); |
| 66 | void (*cs_control)(u32 command); |
Mika Westerberg | a0d2642 | 2013-01-22 12:26:32 +0200 | [diff] [blame] | 67 | |
| 68 | void __iomem *lpss_base; |
Mika Westerberg | 99f499c | 2016-09-26 15:19:50 +0300 | [diff] [blame] | 69 | |
| 70 | /* GPIOs for chip selects */ |
| 71 | struct gpio_desc **cs_gpiods; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 72 | }; |
| 73 | |
| 74 | struct chip_data { |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 75 | u32 cr1; |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 76 | u32 dds_rate; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 77 | u32 timeout; |
| 78 | u8 n_bytes; |
| 79 | u32 dma_burst_size; |
| 80 | u32 threshold; |
| 81 | u32 dma_threshold; |
Mika Westerberg | a0d2642 | 2013-01-22 12:26:32 +0200 | [diff] [blame] | 82 | u16 lpss_rx_threshold; |
| 83 | u16 lpss_tx_threshold; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 84 | u8 enable_dma; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 85 | union { |
| 86 | int gpio_cs; |
| 87 | unsigned int frm; |
| 88 | }; |
| 89 | int gpio_cs_inverted; |
| 90 | int (*write)(struct driver_data *drv_data); |
| 91 | int (*read)(struct driver_data *drv_data); |
| 92 | void (*cs_control)(u32 command); |
| 93 | }; |
| 94 | |
Jarkko Nikula | c039dd2 | 2014-12-18 15:04:23 +0200 | [diff] [blame] | 95 | static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data, |
| 96 | unsigned reg) |
| 97 | { |
| 98 | return __raw_readl(drv_data->ioaddr + reg); |
| 99 | } |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 100 | |
Jarkko Nikula | c039dd2 | 2014-12-18 15:04:23 +0200 | [diff] [blame] | 101 | static inline void pxa2xx_spi_write(const struct driver_data *drv_data, |
| 102 | unsigned reg, u32 val) |
| 103 | { |
| 104 | __raw_writel(val, drv_data->ioaddr + reg); |
| 105 | } |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 106 | |
| 107 | #define START_STATE ((void *)0) |
| 108 | #define RUNNING_STATE ((void *)1) |
| 109 | #define DONE_STATE ((void *)2) |
| 110 | #define ERROR_STATE ((void *)-1) |
| 111 | |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 112 | #define DMA_ALIGNMENT 8 |
| 113 | |
| 114 | static inline int pxa25x_ssp_comp(struct driver_data *drv_data) |
| 115 | { |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 116 | switch (drv_data->ssp_type) { |
| 117 | case PXA25x_SSP: |
| 118 | case CE4100_SSP: |
| 119 | case QUARK_X1000_SSP: |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 120 | return 1; |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 121 | default: |
| 122 | return 0; |
| 123 | } |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 124 | } |
| 125 | |
| 126 | static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val) |
| 127 | { |
Weike Chen | e5262d0 | 2014-11-26 02:35:10 -0800 | [diff] [blame] | 128 | if (drv_data->ssp_type == CE4100_SSP || |
| 129 | drv_data->ssp_type == QUARK_X1000_SSP) |
Jarkko Nikula | c039dd2 | 2014-12-18 15:04:23 +0200 | [diff] [blame] | 130 | val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK; |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 131 | |
Jarkko Nikula | c039dd2 | 2014-12-18 15:04:23 +0200 | [diff] [blame] | 132 | pxa2xx_spi_write(drv_data, SSSR, val); |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 133 | } |
| 134 | |
| 135 | extern int pxa2xx_spi_flush(struct driver_data *drv_data); |
| 136 | extern void *pxa2xx_spi_next_transfer(struct driver_data *drv_data); |
| 137 | |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 138 | #define MAX_DMA_LEN SZ_64K |
| 139 | #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL) |
Mika Westerberg | 5928808 | 2013-01-22 12:26:29 +0200 | [diff] [blame] | 140 | |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 141 | extern irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data); |
| 142 | extern int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst); |
| 143 | extern void pxa2xx_spi_dma_start(struct driver_data *drv_data); |
| 144 | extern int pxa2xx_spi_dma_setup(struct driver_data *drv_data); |
| 145 | extern void pxa2xx_spi_dma_release(struct driver_data *drv_data); |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 146 | extern int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip, |
| 147 | struct spi_device *spi, |
| 148 | u8 bits_per_word, |
| 149 | u32 *burst_code, |
| 150 | u32 *threshold); |
Mika Westerberg | cd7bed0 | 2013-01-22 12:26:28 +0200 | [diff] [blame] | 151 | |
| 152 | #endif /* SPI_PXA2XX_H */ |