blob: 3475f65aeec692c4f7102492f028a3cf05e2d06c [file] [log] [blame]
Mark Brownbe2de992011-05-10 15:42:08 +02001/*
Mark Brownb3748dd2009-06-15 11:23:20 +01002 * Copyright 2009 Wolfson Microelectronics plc
3 *
4 * S3C64xx CPUfreq Support
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/init.h>
14#include <linux/cpufreq.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/regulator/consumer.h>
Mark Browna6ee8772011-07-29 16:19:26 +010018#include <linux/module.h>
Mark Brownb3748dd2009-06-15 11:23:20 +010019
20static struct clk *armclk;
21static struct regulator *vddarm;
Mark Brown43f10692009-11-03 14:42:11 +000022static unsigned long regulator_latency;
Mark Brownb3748dd2009-06-15 11:23:20 +010023
24#ifdef CONFIG_CPU_S3C6410
25struct s3c64xx_dvfs {
26 unsigned int vddarm_min;
27 unsigned int vddarm_max;
28};
29
30static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
Mark Browne9c08f02009-11-03 14:42:12 +000031 [0] = { 1000000, 1150000 },
32 [1] = { 1050000, 1150000 },
33 [2] = { 1100000, 1150000 },
34 [3] = { 1200000, 1350000 },
Mark Brownc6e2d682011-06-08 14:49:15 +010035 [4] = { 1300000, 1350000 },
Mark Brownb3748dd2009-06-15 11:23:20 +010036};
37
38static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
39 { 0, 66000 },
Mark Brownef993ef82011-06-28 20:26:49 -070040 { 0, 100000 },
Mark Brownb3748dd2009-06-15 11:23:20 +010041 { 0, 133000 },
Mark Brownef993ef82011-06-28 20:26:49 -070042 { 1, 200000 },
Mark Brownb3748dd2009-06-15 11:23:20 +010043 { 1, 222000 },
44 { 1, 266000 },
45 { 2, 333000 },
46 { 2, 400000 },
Mark Browne9c08f02009-11-03 14:42:12 +000047 { 2, 532000 },
48 { 2, 533000 },
49 { 3, 667000 },
Mark Brownc6e2d682011-06-08 14:49:15 +010050 { 4, 800000 },
Mark Brownb3748dd2009-06-15 11:23:20 +010051 { 0, CPUFREQ_TABLE_END },
52};
53#endif
54
55static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
56{
57 if (policy->cpu != 0)
58 return -EINVAL;
59
60 return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
61}
62
63static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
64{
65 if (cpu != 0)
66 return 0;
67
68 return clk_get_rate(armclk) / 1000;
69}
70
71static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
72 unsigned int target_freq,
73 unsigned int relation)
74{
75 int ret;
76 unsigned int i;
77 struct cpufreq_freqs freqs;
78 struct s3c64xx_dvfs *dvfs;
79
80 ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
81 target_freq, relation, &i);
82 if (ret != 0)
83 return ret;
84
85 freqs.cpu = 0;
86 freqs.old = clk_get_rate(armclk) / 1000;
87 freqs.new = s3c64xx_freq_table[i].frequency;
88 freqs.flags = 0;
89 dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
90
91 if (freqs.old == freqs.new)
92 return 0;
93
94 pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
95
96 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
97
98#ifdef CONFIG_REGULATOR
99 if (vddarm && freqs.new > freqs.old) {
100 ret = regulator_set_voltage(vddarm,
101 dvfs->vddarm_min,
102 dvfs->vddarm_max);
103 if (ret != 0) {
104 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
105 freqs.new, ret);
106 goto err;
107 }
108 }
109#endif
110
111 ret = clk_set_rate(armclk, freqs.new * 1000);
112 if (ret < 0) {
113 pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
114 freqs.new, ret);
115 goto err;
116 }
117
Mark Brownfb3b1fe2011-06-22 15:08:56 +0100118 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
119
Mark Brownb3748dd2009-06-15 11:23:20 +0100120#ifdef CONFIG_REGULATOR
121 if (vddarm && freqs.new < freqs.old) {
122 ret = regulator_set_voltage(vddarm,
123 dvfs->vddarm_min,
124 dvfs->vddarm_max);
125 if (ret != 0) {
126 pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
127 freqs.new, ret);
128 goto err_clk;
129 }
130 }
131#endif
132
Mark Brownb3748dd2009-06-15 11:23:20 +0100133 pr_debug("cpufreq: Set actual frequency %lukHz\n",
134 clk_get_rate(armclk) / 1000);
135
136 return 0;
137
138err_clk:
139 if (clk_set_rate(armclk, freqs.old * 1000) < 0)
140 pr_err("Failed to restore original clock rate\n");
141err:
142 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
143
144 return ret;
145}
146
147#ifdef CONFIG_REGULATOR
Mark Brown43f10692009-11-03 14:42:11 +0000148static void __init s3c64xx_cpufreq_config_regulator(void)
Mark Brownb3748dd2009-06-15 11:23:20 +0100149{
150 int count, v, i, found;
151 struct cpufreq_frequency_table *freq;
152 struct s3c64xx_dvfs *dvfs;
153
154 count = regulator_count_voltages(vddarm);
155 if (count < 0) {
156 pr_err("cpufreq: Unable to check supported voltages\n");
Mark Brownb3748dd2009-06-15 11:23:20 +0100157 }
158
159 freq = s3c64xx_freq_table;
Mark Brown43f10692009-11-03 14:42:11 +0000160 while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
Mark Brownb3748dd2009-06-15 11:23:20 +0100161 if (freq->frequency == CPUFREQ_ENTRY_INVALID)
162 continue;
163
164 dvfs = &s3c64xx_dvfs_table[freq->index];
165 found = 0;
166
167 for (i = 0; i < count; i++) {
168 v = regulator_list_voltage(vddarm, i);
169 if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
170 found = 1;
171 }
172
173 if (!found) {
174 pr_debug("cpufreq: %dkHz unsupported by regulator\n",
175 freq->frequency);
176 freq->frequency = CPUFREQ_ENTRY_INVALID;
177 }
178
179 freq++;
180 }
Mark Brown43f10692009-11-03 14:42:11 +0000181
182 /* Guess based on having to do an I2C/SPI write; in future we
183 * will be able to query the regulator performance here. */
184 regulator_latency = 1 * 1000 * 1000;
Mark Brownb3748dd2009-06-15 11:23:20 +0100185}
186#endif
187
Mark Brown6d0de152011-03-11 16:10:03 +0900188static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
Mark Brownb3748dd2009-06-15 11:23:20 +0100189{
190 int ret;
191 struct cpufreq_frequency_table *freq;
192
193 if (policy->cpu != 0)
194 return -EINVAL;
195
196 if (s3c64xx_freq_table == NULL) {
197 pr_err("cpufreq: No frequency information for this CPU\n");
198 return -ENODEV;
199 }
200
201 armclk = clk_get(NULL, "armclk");
202 if (IS_ERR(armclk)) {
203 pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
204 PTR_ERR(armclk));
205 return PTR_ERR(armclk);
206 }
207
208#ifdef CONFIG_REGULATOR
209 vddarm = regulator_get(NULL, "vddarm");
210 if (IS_ERR(vddarm)) {
211 ret = PTR_ERR(vddarm);
212 pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
213 pr_err("cpufreq: Only frequency scaling available\n");
214 vddarm = NULL;
215 } else {
Mark Brown43f10692009-11-03 14:42:11 +0000216 s3c64xx_cpufreq_config_regulator();
Mark Brownb3748dd2009-06-15 11:23:20 +0100217 }
218#endif
219
220 freq = s3c64xx_freq_table;
221 while (freq->frequency != CPUFREQ_TABLE_END) {
222 unsigned long r;
223
224 /* Check for frequencies we can generate */
225 r = clk_round_rate(armclk, freq->frequency * 1000);
226 r /= 1000;
Mark Brown383af9c2009-11-03 14:42:07 +0000227 if (r != freq->frequency) {
228 pr_debug("cpufreq: %dkHz unsupported by clock\n",
229 freq->frequency);
Mark Brownb3748dd2009-06-15 11:23:20 +0100230 freq->frequency = CPUFREQ_ENTRY_INVALID;
Mark Brown383af9c2009-11-03 14:42:07 +0000231 }
Mark Brownb3748dd2009-06-15 11:23:20 +0100232
233 /* If we have no regulator then assume startup
234 * frequency is the maximum we can support. */
235 if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
236 freq->frequency = CPUFREQ_ENTRY_INVALID;
237
238 freq++;
239 }
240
241 policy->cur = clk_get_rate(armclk) / 1000;
242
Mark Brown43f10692009-11-03 14:42:11 +0000243 /* Datasheet says PLL stabalisation time (if we were to use
244 * the PLLs, which we don't currently) is ~300us worst case,
245 * but add some fudge.
246 */
247 policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
Mark Brownb3748dd2009-06-15 11:23:20 +0100248
249 ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
250 if (ret != 0) {
251 pr_err("cpufreq: Failed to configure frequency table: %d\n",
252 ret);
253 regulator_put(vddarm);
254 clk_put(armclk);
255 }
256
257 return ret;
258}
259
260static struct cpufreq_driver s3c64xx_cpufreq_driver = {
261 .owner = THIS_MODULE,
262 .flags = 0,
263 .verify = s3c64xx_cpufreq_verify_speed,
264 .target = s3c64xx_cpufreq_set_target,
265 .get = s3c64xx_cpufreq_get_speed,
266 .init = s3c64xx_cpufreq_driver_init,
267 .name = "s3c",
268};
269
270static int __init s3c64xx_cpufreq_init(void)
271{
272 return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
273}
274module_init(s3c64xx_cpufreq_init);