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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2** System Bus Adapter (SBA) I/O MMU manager
3**
4** (c) Copyright 2000-2004 Grant Grundler <grundler @ parisc-linux x org>
5** (c) Copyright 2004 Naresh Kumar Inna <knaresh at india x hp x com>
6** (c) Copyright 2000-2004 Hewlett-Packard Company
7**
8** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
9**
10** This program is free software; you can redistribute it and/or modify
11** it under the terms of the GNU General Public License as published by
12** the Free Software Foundation; either version 2 of the License, or
13** (at your option) any later version.
14**
15**
16** This module initializes the IOC (I/O Controller) found on B1000/C3000/
17** J5000/J7000/N-class/L-class machines and their successors.
18**
19** FIXME: add DMA hint support programming in both sba and lba modules.
20*/
21
22#include <linux/config.h>
23#include <linux/types.h>
24#include <linux/kernel.h>
25#include <linux/spinlock.h>
26#include <linux/slab.h>
27#include <linux/init.h>
28
29#include <linux/mm.h>
30#include <linux/string.h>
31#include <linux/pci.h>
32
33#include <asm/byteorder.h>
34#include <asm/io.h>
35#include <asm/dma.h> /* for DMA_CHUNK_SIZE */
36
37#include <asm/hardware.h> /* for register_parisc_driver() stuff */
38
39#include <linux/proc_fs.h>
Kyle McMartin7ec14e42006-02-06 10:10:15 -070040#include <linux/seq_file.h>
41
Linus Torvalds1da177e2005-04-16 15:20:36 -070042#include <asm/runway.h> /* for proc_runway_root */
43#include <asm/pdc.h> /* for PDC_MODEL_* */
44#include <asm/pdcpat.h> /* for is_pdc_pat() */
45#include <asm/parisc-device.h>
46
47
48/* declared in arch/parisc/kernel/setup.c */
49extern struct proc_dir_entry * proc_mckinley_root;
50
51#define MODULE_NAME "SBA"
52
53#ifdef CONFIG_PROC_FS
54/* depends on proc fs support. But costs CPU performance */
55#undef SBA_COLLECT_STATS
56#endif
57
58/*
59** The number of debug flags is a clue - this code is fragile.
60** Don't even think about messing with it unless you have
61** plenty of 710's to sacrifice to the computer gods. :^)
62*/
63#undef DEBUG_SBA_INIT
64#undef DEBUG_SBA_RUN
65#undef DEBUG_SBA_RUN_SG
66#undef DEBUG_SBA_RESOURCE
67#undef ASSERT_PDIR_SANITY
68#undef DEBUG_LARGE_SG_ENTRIES
69#undef DEBUG_DMB_TRAP
70
71#ifdef DEBUG_SBA_INIT
72#define DBG_INIT(x...) printk(x)
73#else
74#define DBG_INIT(x...)
75#endif
76
77#ifdef DEBUG_SBA_RUN
78#define DBG_RUN(x...) printk(x)
79#else
80#define DBG_RUN(x...)
81#endif
82
83#ifdef DEBUG_SBA_RUN_SG
84#define DBG_RUN_SG(x...) printk(x)
85#else
86#define DBG_RUN_SG(x...)
87#endif
88
89
90#ifdef DEBUG_SBA_RESOURCE
91#define DBG_RES(x...) printk(x)
92#else
93#define DBG_RES(x...)
94#endif
95
Grant Grundler64908ad2005-10-21 22:37:20 -040096#if defined(CONFIG_64BIT)
97/* "low end" PA8800 machines use ZX1 chipset: PAT PDC and only run 64-bit */
Linus Torvalds1da177e2005-04-16 15:20:36 -070098#define ZX1_SUPPORT
99#endif
100
101#define SBA_INLINE __inline__
102
103
104/*
105** The number of pdir entries to "free" before issueing
106** a read to PCOM register to flush out PCOM writes.
107** Interacts with allocation granularity (ie 4 or 8 entries
108** allocated and free'd/purged at a time might make this
109** less interesting).
110*/
111#define DELAYED_RESOURCE_CNT 16
112
113#define DEFAULT_DMA_HINT_REG 0
114
115#define ASTRO_RUNWAY_PORT 0x582
116#define IKE_MERCED_PORT 0x803
117#define REO_MERCED_PORT 0x804
118#define REOG_MERCED_PORT 0x805
119#define PLUTO_MCKINLEY_PORT 0x880
120
121#define SBA_FUNC_ID 0x0000 /* function id */
122#define SBA_FCLASS 0x0008 /* function class, bist, header, rev... */
123
124#define IS_ASTRO(id) ((id)->hversion == ASTRO_RUNWAY_PORT)
125#define IS_IKE(id) ((id)->hversion == IKE_MERCED_PORT)
126#define IS_PLUTO(id) ((id)->hversion == PLUTO_MCKINLEY_PORT)
127
128#define SBA_FUNC_SIZE 4096 /* SBA configuration function reg set */
129
130#define ASTRO_IOC_OFFSET (32 * SBA_FUNC_SIZE)
131#define PLUTO_IOC_OFFSET (1 * SBA_FUNC_SIZE)
132/* Ike's IOC's occupy functions 2 and 3 */
133#define IKE_IOC_OFFSET(p) ((p+2) * SBA_FUNC_SIZE)
134
135#define IOC_CTRL 0x8 /* IOC_CTRL offset */
136#define IOC_CTRL_TC (1 << 0) /* TOC Enable */
137#define IOC_CTRL_CE (1 << 1) /* Coalesce Enable */
138#define IOC_CTRL_DE (1 << 2) /* Dillon Enable */
139#define IOC_CTRL_RM (1 << 8) /* Real Mode */
140#define IOC_CTRL_NC (1 << 9) /* Non Coherent Mode */
141#define IOC_CTRL_D4 (1 << 11) /* Disable 4-byte coalescing */
142#define IOC_CTRL_DD (1 << 13) /* Disable distr. LMMIO range coalescing */
143
144#define MAX_IOC 2 /* per Ike. Pluto/Astro only have 1. */
145
146#define ROPES_PER_IOC 8 /* per Ike half or Pluto/Astro */
147
148
149/*
150** Offsets into MBIB (Function 0 on Ike and hopefully Astro)
151** Firmware programs this stuff. Don't touch it.
152*/
153#define LMMIO_DIRECT0_BASE 0x300
154#define LMMIO_DIRECT0_MASK 0x308
155#define LMMIO_DIRECT0_ROUTE 0x310
156
157#define LMMIO_DIST_BASE 0x360
158#define LMMIO_DIST_MASK 0x368
159#define LMMIO_DIST_ROUTE 0x370
160
161#define IOS_DIST_BASE 0x390
162#define IOS_DIST_MASK 0x398
163#define IOS_DIST_ROUTE 0x3A0
164
165#define IOS_DIRECT_BASE 0x3C0
166#define IOS_DIRECT_MASK 0x3C8
167#define IOS_DIRECT_ROUTE 0x3D0
168
169/*
170** Offsets into I/O TLB (Function 2 and 3 on Ike)
171*/
172#define ROPE0_CTL 0x200 /* "regbus pci0" */
173#define ROPE1_CTL 0x208
174#define ROPE2_CTL 0x210
175#define ROPE3_CTL 0x218
176#define ROPE4_CTL 0x220
177#define ROPE5_CTL 0x228
178#define ROPE6_CTL 0x230
179#define ROPE7_CTL 0x238
180
181#define HF_ENABLE 0x40
182
183
184#define IOC_IBASE 0x300 /* IO TLB */
185#define IOC_IMASK 0x308
186#define IOC_PCOM 0x310
187#define IOC_TCNFG 0x318
188#define IOC_PDIR_BASE 0x320
189
190/* AGP GART driver looks for this */
191#define SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
192
193
194/*
195** IOC supports 4/8/16/64KB page sizes (see TCNFG register)
196** It's safer (avoid memory corruption) to keep DMA page mappings
197** equivalently sized to VM PAGE_SIZE.
198**
199** We really can't avoid generating a new mapping for each
200** page since the Virtual Coherence Index has to be generated
201** and updated for each page.
202**
203** PAGE_SIZE could be greater than IOVP_SIZE. But not the inverse.
204*/
205#define IOVP_SIZE PAGE_SIZE
206#define IOVP_SHIFT PAGE_SHIFT
207#define IOVP_MASK PAGE_MASK
208
209#define SBA_PERF_CFG 0x708 /* Performance Counter stuff */
210#define SBA_PERF_MASK1 0x718
211#define SBA_PERF_MASK2 0x730
212
213
214/*
215** Offsets into PCI Performance Counters (functions 12 and 13)
216** Controlled by PERF registers in function 2 & 3 respectively.
217*/
218#define SBA_PERF_CNT1 0x200
219#define SBA_PERF_CNT2 0x208
220#define SBA_PERF_CNT3 0x210
221
222
223struct ioc {
224 void __iomem *ioc_hpa; /* I/O MMU base address */
225 char *res_map; /* resource map, bit == pdir entry */
226 u64 *pdir_base; /* physical base address */
227 unsigned long ibase; /* pdir IOV Space base - shared w/lba_pci */
228 unsigned long imask; /* pdir IOV Space mask - shared w/lba_pci */
229#ifdef ZX1_SUPPORT
230 unsigned long iovp_mask; /* help convert IOVA to IOVP */
231#endif
232 unsigned long *res_hint; /* next avail IOVP - circular search */
233 spinlock_t res_lock;
234 unsigned int res_bitshift; /* from the LEFT! */
235 unsigned int res_size; /* size of resource map in bytes */
Grant Grundler64908ad2005-10-21 22:37:20 -0400236#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237/* FIXME : DMA HINTs not used */
238 unsigned long hint_mask_pdir; /* bits used for DMA hints */
239 unsigned int hint_shift_pdir;
240#endif
241#if DELAYED_RESOURCE_CNT > 0
242 int saved_cnt;
243 struct sba_dma_pair {
244 dma_addr_t iova;
245 size_t size;
246 } saved[DELAYED_RESOURCE_CNT];
247#endif
248
249#ifdef SBA_COLLECT_STATS
250#define SBA_SEARCH_SAMPLE 0x100
251 unsigned long avg_search[SBA_SEARCH_SAMPLE];
252 unsigned long avg_idx; /* current index into avg_search */
253 unsigned long used_pages;
254 unsigned long msingle_calls;
255 unsigned long msingle_pages;
256 unsigned long msg_calls;
257 unsigned long msg_pages;
258 unsigned long usingle_calls;
259 unsigned long usingle_pages;
260 unsigned long usg_calls;
261 unsigned long usg_pages;
262#endif
263
264 /* STUFF We don't need in performance path */
265 unsigned int pdir_size; /* in bytes, determined by IOV Space size */
266};
267
268struct sba_device {
269 struct sba_device *next; /* list of SBA's in system */
270 struct parisc_device *dev; /* dev found in bus walk */
271 struct parisc_device_id *iodc; /* data about dev from firmware */
272 const char *name;
273 void __iomem *sba_hpa; /* base address */
274 spinlock_t sba_lock;
275 unsigned int flags; /* state/functionality enabled */
276 unsigned int hw_rev; /* HW revision of chip */
277
278 struct resource chip_resv; /* MMIO reserved for chip */
279 struct resource iommu_resv; /* MMIO reserved for iommu */
280
281 unsigned int num_ioc; /* number of on-board IOC's */
282 struct ioc ioc[MAX_IOC];
283};
284
285
286static struct sba_device *sba_list;
287
288static unsigned long ioc_needs_fdc = 0;
289
290/* global count of IOMMUs in the system */
291static unsigned int global_ioc_cnt = 0;
292
293/* PA8700 (Piranha 2.2) bug workaround */
294static unsigned long piranha_bad_128k = 0;
295
296/* Looks nice and keeps the compiler happy */
297#define SBA_DEV(d) ((struct sba_device *) (d))
298
Grant Grundler64908ad2005-10-21 22:37:20 -0400299#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700300static int reserve_sba_gart = 1;
301#endif
302
303#define ROUNDUP(x,y) ((x + ((y)-1)) & ~((y)-1))
304
305
306/************************************
307** SBA register read and write support
308**
309** BE WARNED: register writes are posted.
310** (ie follow writes which must reach HW with a read)
311**
312** Superdome (in particular, REO) allows only 64-bit CSR accesses.
313*/
314#define READ_REG32(addr) le32_to_cpu(__raw_readl(addr))
315#define READ_REG64(addr) le64_to_cpu(__raw_readq(addr))
316#define WRITE_REG32(val, addr) __raw_writel(cpu_to_le32(val), addr)
317#define WRITE_REG64(val, addr) __raw_writeq(cpu_to_le64(val), addr)
318
Grant Grundler64908ad2005-10-21 22:37:20 -0400319#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700320#define READ_REG(addr) READ_REG64(addr)
321#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
322#else
323#define READ_REG(addr) READ_REG32(addr)
324#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
325#endif
326
327#ifdef DEBUG_SBA_INIT
328
Grant Grundler64908ad2005-10-21 22:37:20 -0400329/* NOTE: When CONFIG_64BIT isn't defined, READ_REG64() is two 32-bit reads */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700330
331/**
332 * sba_dump_ranges - debugging only - print ranges assigned to this IOA
333 * @hpa: base address of the sba
334 *
335 * Print the MMIO and IO Port address ranges forwarded by an Astro/Ike/RIO
336 * IO Adapter (aka Bus Converter).
337 */
338static void
339sba_dump_ranges(void __iomem *hpa)
340{
341 DBG_INIT("SBA at 0x%p\n", hpa);
342 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
343 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
344 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
345 DBG_INIT("\n");
346 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
347 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
348 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
349}
350
351/**
352 * sba_dump_tlb - debugging only - print IOMMU operating parameters
353 * @hpa: base address of the IOMMU
354 *
355 * Print the size/location of the IO MMU PDIR.
356 */
357static void sba_dump_tlb(void __iomem *hpa)
358{
359 DBG_INIT("IO TLB at 0x%p\n", hpa);
360 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
361 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
362 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
363 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
364 DBG_INIT("\n");
365}
366#else
367#define sba_dump_ranges(x)
368#define sba_dump_tlb(x)
Grant Grundler64908ad2005-10-21 22:37:20 -0400369#endif /* DEBUG_SBA_INIT */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370
371
372#ifdef ASSERT_PDIR_SANITY
373
374/**
375 * sba_dump_pdir_entry - debugging only - print one IOMMU PDIR entry
376 * @ioc: IO MMU structure which owns the pdir we are interested in.
377 * @msg: text to print ont the output line.
378 * @pide: pdir index.
379 *
380 * Print one entry of the IO MMU PDIR in human readable form.
381 */
382static void
383sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
384{
385 /* start printing from lowest pde in rval */
386 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
387 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
388 uint rcnt;
389
390 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
391 msg,
392 rptr, pide & (BITS_PER_LONG - 1), *rptr);
393
394 rcnt = 0;
395 while (rcnt < BITS_PER_LONG) {
396 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
397 (rcnt == (pide & (BITS_PER_LONG - 1)))
398 ? " -->" : " ",
399 rcnt, ptr, *ptr );
400 rcnt++;
401 ptr++;
402 }
403 printk(KERN_DEBUG "%s", msg);
404}
405
406
407/**
408 * sba_check_pdir - debugging only - consistency checker
409 * @ioc: IO MMU structure which owns the pdir we are interested in.
410 * @msg: text to print ont the output line.
411 *
412 * Verify the resource map and pdir state is consistent
413 */
414static int
415sba_check_pdir(struct ioc *ioc, char *msg)
416{
417 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
418 u32 *rptr = (u32 *) ioc->res_map; /* resource map ptr */
419 u64 *pptr = ioc->pdir_base; /* pdir ptr */
420 uint pide = 0;
421
422 while (rptr < rptr_end) {
423 u32 rval = *rptr;
424 int rcnt = 32; /* number of bits we might check */
425
426 while (rcnt) {
427 /* Get last byte and highest bit from that */
428 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
429 if ((rval ^ pde) & 0x80000000)
430 {
431 /*
432 ** BUMMER! -- res_map != pdir --
433 ** Dump rval and matching pdir entries
434 */
435 sba_dump_pdir_entry(ioc, msg, pide);
436 return(1);
437 }
438 rcnt--;
439 rval <<= 1; /* try the next bit */
440 pptr++;
441 pide++;
442 }
443 rptr++; /* look at next word of res_map */
444 }
445 /* It'd be nice if we always got here :^) */
446 return 0;
447}
448
449
450/**
451 * sba_dump_sg - debugging only - print Scatter-Gather list
452 * @ioc: IO MMU structure which owns the pdir we are interested in.
453 * @startsg: head of the SG list
454 * @nents: number of entries in SG list
455 *
456 * print the SG list so we can verify it's correct by hand.
457 */
458static void
459sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
460{
461 while (nents-- > 0) {
462 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
463 nents,
464 (unsigned long) sg_dma_address(startsg),
465 sg_dma_len(startsg),
466 sg_virt_addr(startsg), startsg->length);
467 startsg++;
468 }
469}
470
471#endif /* ASSERT_PDIR_SANITY */
472
473
474
475
476/**************************************************************
477*
478* I/O Pdir Resource Management
479*
480* Bits set in the resource map are in use.
481* Each bit can represent a number of pages.
482* LSbs represent lower addresses (IOVA's).
483*
484***************************************************************/
485#define PAGES_PER_RANGE 1 /* could increase this to 4 or 8 if needed */
486
487/* Convert from IOVP to IOVA and vice versa. */
488
489#ifdef ZX1_SUPPORT
490/* Pluto (aka ZX1) boxes need to set or clear the ibase bits appropriately */
491#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
492#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
493#else
494/* only support Astro and ancestors. Saves a few cycles in key places */
495#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
496#define SBA_IOVP(ioc,iova) (iova)
497#endif
498
499#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
500
501#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
502#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
503
504
505/**
506 * sba_search_bitmap - find free space in IO PDIR resource bitmap
507 * @ioc: IO MMU structure which owns the pdir we are interested in.
508 * @bits_wanted: number of entries we need.
509 *
510 * Find consecutive free bits in resource bitmap.
511 * Each bit represents one entry in the IO Pdir.
512 * Cool perf optimization: search for log2(size) bits at a time.
513 */
514static SBA_INLINE unsigned long
515sba_search_bitmap(struct ioc *ioc, unsigned long bits_wanted)
516{
517 unsigned long *res_ptr = ioc->res_hint;
518 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
519 unsigned long pide = ~0UL;
520
521 if (bits_wanted > (BITS_PER_LONG/2)) {
522 /* Search word at a time - no mask needed */
523 for(; res_ptr < res_end; ++res_ptr) {
524 if (*res_ptr == 0) {
525 *res_ptr = RESMAP_MASK(bits_wanted);
526 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
527 pide <<= 3; /* convert to bit address */
528 break;
529 }
530 }
531 /* point to the next word on next pass */
532 res_ptr++;
533 ioc->res_bitshift = 0;
534 } else {
535 /*
536 ** Search the resource bit map on well-aligned values.
537 ** "o" is the alignment.
538 ** We need the alignment to invalidate I/O TLB using
539 ** SBA HW features in the unmap path.
540 */
541 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
542 uint bitshiftcnt = ROUNDUP(ioc->res_bitshift, o);
543 unsigned long mask;
544
545 if (bitshiftcnt >= BITS_PER_LONG) {
546 bitshiftcnt = 0;
547 res_ptr++;
548 }
549 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
550
551 DBG_RES("%s() o %ld %p", __FUNCTION__, o, res_ptr);
552 while(res_ptr < res_end)
553 {
554 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
555 WARN_ON(mask == 0);
556 if(((*res_ptr) & mask) == 0) {
557 *res_ptr |= mask; /* mark resources busy! */
558 pide = ((unsigned long)res_ptr - (unsigned long)ioc->res_map);
559 pide <<= 3; /* convert to bit address */
560 pide += bitshiftcnt;
561 break;
562 }
563 mask >>= o;
564 bitshiftcnt += o;
565 if (mask == 0) {
566 mask = RESMAP_MASK(bits_wanted);
567 bitshiftcnt=0;
568 res_ptr++;
569 }
570 }
571 /* look in the same word on the next pass */
572 ioc->res_bitshift = bitshiftcnt + bits_wanted;
573 }
574
575 /* wrapped ? */
576 if (res_end <= res_ptr) {
577 ioc->res_hint = (unsigned long *) ioc->res_map;
578 ioc->res_bitshift = 0;
579 } else {
580 ioc->res_hint = res_ptr;
581 }
582 return (pide);
583}
584
585
586/**
587 * sba_alloc_range - find free bits and mark them in IO PDIR resource bitmap
588 * @ioc: IO MMU structure which owns the pdir we are interested in.
589 * @size: number of bytes to create a mapping for
590 *
591 * Given a size, find consecutive unmarked and then mark those bits in the
592 * resource bit map.
593 */
594static int
595sba_alloc_range(struct ioc *ioc, size_t size)
596{
597 unsigned int pages_needed = size >> IOVP_SHIFT;
598#ifdef SBA_COLLECT_STATS
599 unsigned long cr_start = mfctl(16);
600#endif
601 unsigned long pide;
602
603 pide = sba_search_bitmap(ioc, pages_needed);
604 if (pide >= (ioc->res_size << 3)) {
605 pide = sba_search_bitmap(ioc, pages_needed);
606 if (pide >= (ioc->res_size << 3))
607 panic("%s: I/O MMU @ %p is out of mapping resources\n",
608 __FILE__, ioc->ioc_hpa);
609 }
610
611#ifdef ASSERT_PDIR_SANITY
612 /* verify the first enable bit is clear */
613 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
614 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
615 }
616#endif
617
618 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
619 __FUNCTION__, size, pages_needed, pide,
620 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
621 ioc->res_bitshift );
622
623#ifdef SBA_COLLECT_STATS
624 {
625 unsigned long cr_end = mfctl(16);
626 unsigned long tmp = cr_end - cr_start;
627 /* check for roll over */
628 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
629 }
630 ioc->avg_search[ioc->avg_idx++] = cr_start;
631 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
632
633 ioc->used_pages += pages_needed;
634#endif
635
636 return (pide);
637}
638
639
640/**
641 * sba_free_range - unmark bits in IO PDIR resource bitmap
642 * @ioc: IO MMU structure which owns the pdir we are interested in.
643 * @iova: IO virtual address which was previously allocated.
644 * @size: number of bytes to create a mapping for
645 *
646 * clear bits in the ioc's resource map
647 */
648static SBA_INLINE void
649sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
650{
651 unsigned long iovp = SBA_IOVP(ioc, iova);
652 unsigned int pide = PDIR_INDEX(iovp);
653 unsigned int ridx = pide >> 3; /* convert bit to byte address */
654 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
655
656 int bits_not_wanted = size >> IOVP_SHIFT;
657
658 /* 3-bits "bit" address plus 2 (or 3) bits for "byte" == bit in word */
659 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
660
661 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
662 __FUNCTION__, (uint) iova, size,
663 bits_not_wanted, m, pide, res_ptr, *res_ptr);
664
665#ifdef SBA_COLLECT_STATS
666 ioc->used_pages -= bits_not_wanted;
667#endif
668
669 *res_ptr &= ~m;
670}
671
672
673/**************************************************************
674*
675* "Dynamic DMA Mapping" support (aka "Coherent I/O")
676*
677***************************************************************/
678
Grant Grundler64908ad2005-10-21 22:37:20 -0400679#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -0700680#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
681#endif
682
683typedef unsigned long space_t;
684#define KERNEL_SPACE 0
685
686/**
687 * sba_io_pdir_entry - fill in one IO PDIR entry
688 * @pdir_ptr: pointer to IO PDIR entry
689 * @sid: process Space ID - currently only support KERNEL_SPACE
690 * @vba: Virtual CPU address of buffer to map
691 * @hint: DMA hint set to use for this mapping
692 *
693 * SBA Mapping Routine
694 *
695 * Given a virtual address (vba, arg2) and space id, (sid, arg1)
696 * sba_io_pdir_entry() loads the I/O PDIR entry pointed to by
697 * pdir_ptr (arg0).
698 * Using the bass-ackwards HP bit numbering, Each IO Pdir entry
699 * for Astro/Ike looks like:
700 *
701 *
702 * 0 19 51 55 63
703 * +-+---------------------+----------------------------------+----+--------+
704 * |V| U | PPN[43:12] | U | VI |
705 * +-+---------------------+----------------------------------+----+--------+
706 *
707 * Pluto is basically identical, supports fewer physical address bits:
708 *
709 * 0 23 51 55 63
710 * +-+------------------------+-------------------------------+----+--------+
711 * |V| U | PPN[39:12] | U | VI |
712 * +-+------------------------+-------------------------------+----+--------+
713 *
714 * V == Valid Bit (Most Significant Bit is bit 0)
715 * U == Unused
716 * PPN == Physical Page Number
717 * VI == Virtual Index (aka Coherent Index)
718 *
719 * LPA instruction output is put into PPN field.
720 * LCI (Load Coherence Index) instruction provides the "VI" bits.
721 *
722 * We pre-swap the bytes since PCX-W is Big Endian and the
723 * IOMMU uses little endian for the pdir.
724 */
725
726void SBA_INLINE
727sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
728 unsigned long hint)
729{
730 u64 pa; /* physical address */
731 register unsigned ci; /* coherent index */
732
733 pa = virt_to_phys(vba);
734 pa &= IOVP_MASK;
735
736 mtsp(sid,1);
737 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
738 pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
739
740 pa |= 0x8000000000000000ULL; /* set "valid" bit */
741 *pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
742
743 /*
744 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
745 * (bit #61, big endian), we have to flush and sync every time
746 * IO-PDIR is changed in Ike/Astro.
747 */
Grant Grundler64908ad2005-10-21 22:37:20 -0400748 if (ioc_needs_fdc)
749 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700750}
751
752
753/**
754 * sba_mark_invalid - invalidate one or more IO PDIR entries
755 * @ioc: IO MMU structure which owns the pdir we are interested in.
756 * @iova: IO Virtual Address mapped earlier
757 * @byte_cnt: number of bytes this mapping covers.
758 *
759 * Marking the IO PDIR entry(ies) as Invalid and invalidate
760 * corresponding IO TLB entry. The Ike PCOM (Purge Command Register)
761 * is to purge stale entries in the IO TLB when unmapping entries.
762 *
763 * The PCOM register supports purging of multiple pages, with a minium
764 * of 1 page and a maximum of 2GB. Hardware requires the address be
765 * aligned to the size of the range being purged. The size of the range
766 * must be a power of 2. The "Cool perf optimization" in the
767 * allocation routine helps keep that true.
768 */
769static SBA_INLINE void
770sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
771{
772 u32 iovp = (u32) SBA_IOVP(ioc,iova);
Grant Grundler64908ad2005-10-21 22:37:20 -0400773 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
Linus Torvalds1da177e2005-04-16 15:20:36 -0700774
775#ifdef ASSERT_PDIR_SANITY
Grant Grundler64908ad2005-10-21 22:37:20 -0400776 /* Assert first pdir entry is set.
777 **
778 ** Even though this is a big-endian machine, the entries
779 ** in the iopdir are little endian. That's why we look at
780 ** the byte at +7 instead of at +0.
781 */
782 if (0x80 != (((u8 *) pdir_ptr)[7])) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700783 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
784 }
785#endif
786
Grant Grundler64908ad2005-10-21 22:37:20 -0400787 if (byte_cnt > IOVP_SIZE)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700788 {
Grant Grundler64908ad2005-10-21 22:37:20 -0400789#if 0
790 unsigned long entries_per_cacheline = ioc_needs_fdc ?
791 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
792 - (unsigned long) pdir_ptr;
793 : 262144;
794#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -0700795
Grant Grundler64908ad2005-10-21 22:37:20 -0400796 /* set "size" field for PCOM */
797 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799 do {
800 /* clear I/O Pdir entry "valid" bit first */
Grant Grundler64908ad2005-10-21 22:37:20 -0400801 ((u8 *) pdir_ptr)[7] = 0;
802 if (ioc_needs_fdc) {
803 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
804#if 0
805 entries_per_cacheline = L1_CACHE_SHIFT - 3;
806#endif
807 }
808 pdir_ptr++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700809 byte_cnt -= IOVP_SIZE;
Grant Grundler64908ad2005-10-21 22:37:20 -0400810 } while (byte_cnt > IOVP_SIZE);
811 } else
812 iovp |= IOVP_SHIFT; /* set "size" field for PCOM */
813
814 /*
815 ** clear I/O PDIR entry "valid" bit.
816 ** We have to R/M/W the cacheline regardless how much of the
817 ** pdir entry that we clobber.
818 ** The rest of the entry would be useful for debugging if we
819 ** could dump core on HPMC.
820 */
821 ((u8 *) pdir_ptr)[7] = 0;
822 if (ioc_needs_fdc)
823 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700824
825 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
826}
827
828/**
829 * sba_dma_supported - PCI driver can query DMA support
830 * @dev: instance of PCI owned by the driver that's asking
831 * @mask: number of address bits this PCI device can handle
832 *
833 * See Documentation/DMA-mapping.txt
834 */
835static int sba_dma_supported( struct device *dev, u64 mask)
836{
837 struct ioc *ioc;
Grant Grundler64908ad2005-10-21 22:37:20 -0400838
Linus Torvalds1da177e2005-04-16 15:20:36 -0700839 if (dev == NULL) {
840 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
841 BUG();
842 return(0);
843 }
844
Grant Grundler64908ad2005-10-21 22:37:20 -0400845 /* Documentation/DMA-mapping.txt tells drivers to try 64-bit first,
846 * then fall back to 32-bit if that fails.
847 * We are just "encouraging" 32-bit DMA masks here since we can
848 * never allow IOMMU bypass unless we add special support for ZX1.
849 */
850 if (mask > ~0U)
851 return 0;
852
Linus Torvalds1da177e2005-04-16 15:20:36 -0700853 ioc = GET_IOC(dev);
854
Grant Grundler64908ad2005-10-21 22:37:20 -0400855 /*
856 * check if mask is >= than the current max IO Virt Address
857 * The max IO Virt address will *always* < 30 bits.
858 */
859 return((int)(mask >= (ioc->ibase - 1 +
860 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861}
862
863
864/**
865 * sba_map_single - map one buffer and return IOVA for DMA
866 * @dev: instance of PCI owned by the driver that's asking.
867 * @addr: driver buffer to map.
868 * @size: number of bytes to map in driver buffer.
869 * @direction: R/W or both.
870 *
871 * See Documentation/DMA-mapping.txt
872 */
873static dma_addr_t
874sba_map_single(struct device *dev, void *addr, size_t size,
875 enum dma_data_direction direction)
876{
877 struct ioc *ioc;
878 unsigned long flags;
879 dma_addr_t iovp;
880 dma_addr_t offset;
881 u64 *pdir_start;
882 int pide;
883
884 ioc = GET_IOC(dev);
885
886 /* save offset bits */
887 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
888
889 /* round up to nearest IOVP_SIZE */
890 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
891
892 spin_lock_irqsave(&ioc->res_lock, flags);
893#ifdef ASSERT_PDIR_SANITY
894 sba_check_pdir(ioc,"Check before sba_map_single()");
895#endif
896
897#ifdef SBA_COLLECT_STATS
898 ioc->msingle_calls++;
899 ioc->msingle_pages += size >> IOVP_SHIFT;
900#endif
901 pide = sba_alloc_range(ioc, size);
902 iovp = (dma_addr_t) pide << IOVP_SHIFT;
903
904 DBG_RUN("%s() 0x%p -> 0x%lx\n",
905 __FUNCTION__, addr, (long) iovp | offset);
906
907 pdir_start = &(ioc->pdir_base[pide]);
908
909 while (size > 0) {
910 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
911
912 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
913 pdir_start,
914 (u8) (((u8 *) pdir_start)[7]),
915 (u8) (((u8 *) pdir_start)[6]),
916 (u8) (((u8 *) pdir_start)[5]),
917 (u8) (((u8 *) pdir_start)[4]),
918 (u8) (((u8 *) pdir_start)[3]),
919 (u8) (((u8 *) pdir_start)[2]),
920 (u8) (((u8 *) pdir_start)[1]),
921 (u8) (((u8 *) pdir_start)[0])
922 );
923
924 addr += IOVP_SIZE;
925 size -= IOVP_SIZE;
926 pdir_start++;
927 }
Grant Grundler64908ad2005-10-21 22:37:20 -0400928
929 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
930 if (ioc_needs_fdc)
931 asm volatile("sync" : : );
932
Linus Torvalds1da177e2005-04-16 15:20:36 -0700933#ifdef ASSERT_PDIR_SANITY
934 sba_check_pdir(ioc,"Check after sba_map_single()");
935#endif
936 spin_unlock_irqrestore(&ioc->res_lock, flags);
Grant Grundler64908ad2005-10-21 22:37:20 -0400937
938 /* form complete address */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700939 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
940}
941
942
943/**
944 * sba_unmap_single - unmap one IOVA and free resources
945 * @dev: instance of PCI owned by the driver that's asking.
946 * @iova: IOVA of driver buffer previously mapped.
947 * @size: number of bytes mapped in driver buffer.
948 * @direction: R/W or both.
949 *
950 * See Documentation/DMA-mapping.txt
951 */
952static void
953sba_unmap_single(struct device *dev, dma_addr_t iova, size_t size,
954 enum dma_data_direction direction)
955{
956 struct ioc *ioc;
957#if DELAYED_RESOURCE_CNT > 0
958 struct sba_dma_pair *d;
959#endif
960 unsigned long flags;
961 dma_addr_t offset;
962
963 DBG_RUN("%s() iovp 0x%lx/%x\n", __FUNCTION__, (long) iova, size);
964
965 ioc = GET_IOC(dev);
966 offset = iova & ~IOVP_MASK;
967 iova ^= offset; /* clear offset bits */
968 size += offset;
969 size = ROUNDUP(size, IOVP_SIZE);
970
971 spin_lock_irqsave(&ioc->res_lock, flags);
972
973#ifdef SBA_COLLECT_STATS
974 ioc->usingle_calls++;
975 ioc->usingle_pages += size >> IOVP_SHIFT;
976#endif
977
978 sba_mark_invalid(ioc, iova, size);
979
980#if DELAYED_RESOURCE_CNT > 0
981 /* Delaying when we re-use a IO Pdir entry reduces the number
982 * of MMIO reads needed to flush writes to the PCOM register.
983 */
984 d = &(ioc->saved[ioc->saved_cnt]);
985 d->iova = iova;
986 d->size = size;
987 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
988 int cnt = ioc->saved_cnt;
989 while (cnt--) {
990 sba_free_range(ioc, d->iova, d->size);
991 d--;
992 }
993 ioc->saved_cnt = 0;
Grant Grundler64908ad2005-10-21 22:37:20 -0400994
Linus Torvalds1da177e2005-04-16 15:20:36 -0700995 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
996 }
997#else /* DELAYED_RESOURCE_CNT == 0 */
998 sba_free_range(ioc, iova, size);
Grant Grundler64908ad2005-10-21 22:37:20 -0400999
1000 /* If fdc's were issued, force fdc's to be visible now */
1001 if (ioc_needs_fdc)
1002 asm volatile("sync" : : );
1003
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004 READ_REG(ioc->ioc_hpa+IOC_PCOM); /* flush purges */
1005#endif /* DELAYED_RESOURCE_CNT == 0 */
Grant Grundler64908ad2005-10-21 22:37:20 -04001006
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007 spin_unlock_irqrestore(&ioc->res_lock, flags);
1008
1009 /* XXX REVISIT for 2.5 Linux - need syncdma for zero-copy support.
1010 ** For Astro based systems this isn't a big deal WRT performance.
1011 ** As long as 2.4 kernels copyin/copyout data from/to userspace,
1012 ** we don't need the syncdma. The issue here is I/O MMU cachelines
1013 ** are *not* coherent in all cases. May be hwrev dependent.
1014 ** Need to investigate more.
1015 asm volatile("syncdma");
1016 */
1017}
1018
1019
1020/**
1021 * sba_alloc_consistent - allocate/map shared mem for DMA
1022 * @hwdev: instance of PCI owned by the driver that's asking.
1023 * @size: number of bytes mapped in driver buffer.
1024 * @dma_handle: IOVA of new buffer.
1025 *
1026 * See Documentation/DMA-mapping.txt
1027 */
1028static void *sba_alloc_consistent(struct device *hwdev, size_t size,
Al Viro5c1fb412005-10-21 03:21:28 -04001029 dma_addr_t *dma_handle, gfp_t gfp)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030{
1031 void *ret;
1032
1033 if (!hwdev) {
1034 /* only support PCI */
1035 *dma_handle = 0;
1036 return 0;
1037 }
1038
1039 ret = (void *) __get_free_pages(gfp, get_order(size));
1040
1041 if (ret) {
1042 memset(ret, 0, size);
1043 *dma_handle = sba_map_single(hwdev, ret, size, 0);
1044 }
1045
1046 return ret;
1047}
1048
1049
1050/**
1051 * sba_free_consistent - free/unmap shared mem for DMA
1052 * @hwdev: instance of PCI owned by the driver that's asking.
1053 * @size: number of bytes mapped in driver buffer.
1054 * @vaddr: virtual address IOVA of "consistent" buffer.
1055 * @dma_handler: IO virtual address of "consistent" buffer.
1056 *
1057 * See Documentation/DMA-mapping.txt
1058 */
1059static void
1060sba_free_consistent(struct device *hwdev, size_t size, void *vaddr,
1061 dma_addr_t dma_handle)
1062{
1063 sba_unmap_single(hwdev, dma_handle, size, 0);
1064 free_pages((unsigned long) vaddr, get_order(size));
1065}
1066
1067
1068/*
1069** Since 0 is a valid pdir_base index value, can't use that
1070** to determine if a value is valid or not. Use a flag to indicate
1071** the SG list entry contains a valid pdir index.
1072*/
1073#define PIDE_FLAG 0x80000000UL
1074
1075#ifdef SBA_COLLECT_STATS
1076#define IOMMU_MAP_STATS
1077#endif
1078#include "iommu-helpers.h"
1079
1080#ifdef DEBUG_LARGE_SG_ENTRIES
1081int dump_run_sg = 0;
1082#endif
1083
1084
1085/**
1086 * sba_map_sg - map Scatter/Gather list
1087 * @dev: instance of PCI owned by the driver that's asking.
1088 * @sglist: array of buffer/length pairs
1089 * @nents: number of entries in list
1090 * @direction: R/W or both.
1091 *
1092 * See Documentation/DMA-mapping.txt
1093 */
1094static int
1095sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
1096 enum dma_data_direction direction)
1097{
1098 struct ioc *ioc;
1099 int coalesced, filled = 0;
1100 unsigned long flags;
1101
1102 DBG_RUN_SG("%s() START %d entries\n", __FUNCTION__, nents);
1103
1104 ioc = GET_IOC(dev);
1105
1106 /* Fast path single entry scatterlists. */
1107 if (nents == 1) {
1108 sg_dma_address(sglist) = sba_map_single(dev,
1109 (void *)sg_virt_addr(sglist),
1110 sglist->length, direction);
1111 sg_dma_len(sglist) = sglist->length;
1112 return 1;
1113 }
1114
1115 spin_lock_irqsave(&ioc->res_lock, flags);
1116
1117#ifdef ASSERT_PDIR_SANITY
1118 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
1119 {
1120 sba_dump_sg(ioc, sglist, nents);
1121 panic("Check before sba_map_sg()");
1122 }
1123#endif
1124
1125#ifdef SBA_COLLECT_STATS
1126 ioc->msg_calls++;
1127#endif
1128
1129 /*
1130 ** First coalesce the chunks and allocate I/O pdir space
1131 **
1132 ** If this is one DMA stream, we can properly map using the
1133 ** correct virtual address associated with each DMA page.
1134 ** w/o this association, we wouldn't have coherent DMA!
1135 ** Access to the virtual address is what forces a two pass algorithm.
1136 */
1137 coalesced = iommu_coalesce_chunks(ioc, sglist, nents, sba_alloc_range);
1138
1139 /*
1140 ** Program the I/O Pdir
1141 **
1142 ** map the virtual addresses to the I/O Pdir
1143 ** o dma_address will contain the pdir index
1144 ** o dma_len will contain the number of bytes to map
1145 ** o address contains the virtual address.
1146 */
1147 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
1148
Grant Grundler64908ad2005-10-21 22:37:20 -04001149 /* force FDC ops in io_pdir_entry() to be visible to IOMMU */
1150 if (ioc_needs_fdc)
1151 asm volatile("sync" : : );
1152
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153#ifdef ASSERT_PDIR_SANITY
1154 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1155 {
1156 sba_dump_sg(ioc, sglist, nents);
1157 panic("Check after sba_map_sg()\n");
1158 }
1159#endif
1160
1161 spin_unlock_irqrestore(&ioc->res_lock, flags);
1162
1163 DBG_RUN_SG("%s() DONE %d mappings\n", __FUNCTION__, filled);
1164
1165 return filled;
1166}
1167
1168
1169/**
1170 * sba_unmap_sg - unmap Scatter/Gather list
1171 * @dev: instance of PCI owned by the driver that's asking.
1172 * @sglist: array of buffer/length pairs
1173 * @nents: number of entries in list
1174 * @direction: R/W or both.
1175 *
1176 * See Documentation/DMA-mapping.txt
1177 */
1178static void
1179sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1180 enum dma_data_direction direction)
1181{
1182 struct ioc *ioc;
1183#ifdef ASSERT_PDIR_SANITY
1184 unsigned long flags;
1185#endif
1186
1187 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1188 __FUNCTION__, nents, sg_virt_addr(sglist), sglist->length);
1189
1190 ioc = GET_IOC(dev);
1191
1192#ifdef SBA_COLLECT_STATS
1193 ioc->usg_calls++;
1194#endif
1195
1196#ifdef ASSERT_PDIR_SANITY
1197 spin_lock_irqsave(&ioc->res_lock, flags);
1198 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1199 spin_unlock_irqrestore(&ioc->res_lock, flags);
1200#endif
1201
1202 while (sg_dma_len(sglist) && nents--) {
1203
1204 sba_unmap_single(dev, sg_dma_address(sglist), sg_dma_len(sglist), direction);
1205#ifdef SBA_COLLECT_STATS
1206 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1207 ioc->usingle_calls--; /* kluge since call is unmap_sg() */
1208#endif
1209 ++sglist;
1210 }
1211
1212 DBG_RUN_SG("%s() DONE (nents %d)\n", __FUNCTION__, nents);
1213
1214#ifdef ASSERT_PDIR_SANITY
1215 spin_lock_irqsave(&ioc->res_lock, flags);
1216 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1217 spin_unlock_irqrestore(&ioc->res_lock, flags);
1218#endif
1219
1220}
1221
1222static struct hppa_dma_ops sba_ops = {
1223 .dma_supported = sba_dma_supported,
1224 .alloc_consistent = sba_alloc_consistent,
1225 .alloc_noncoherent = sba_alloc_consistent,
1226 .free_consistent = sba_free_consistent,
1227 .map_single = sba_map_single,
1228 .unmap_single = sba_unmap_single,
1229 .map_sg = sba_map_sg,
1230 .unmap_sg = sba_unmap_sg,
1231 .dma_sync_single_for_cpu = NULL,
1232 .dma_sync_single_for_device = NULL,
1233 .dma_sync_sg_for_cpu = NULL,
1234 .dma_sync_sg_for_device = NULL,
1235};
1236
1237
1238/**************************************************************************
1239**
1240** SBA PAT PDC support
1241**
1242** o call pdc_pat_cell_module()
1243** o store ranges in PCI "resource" structures
1244**
1245**************************************************************************/
1246
1247static void
1248sba_get_pat_resources(struct sba_device *sba_dev)
1249{
1250#if 0
1251/*
1252** TODO/REVISIT/FIXME: support for directed ranges requires calls to
1253** PAT PDC to program the SBA/LBA directed range registers...this
1254** burden may fall on the LBA code since it directly supports the
1255** PCI subsystem. It's not clear yet. - ggg
1256*/
1257PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1258 FIXME : ???
1259PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1260 Tells where the dvi bits are located in the address.
1261PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1262 FIXME : ???
1263#endif
1264}
1265
1266
1267/**************************************************************
1268*
1269* Initialization and claim
1270*
1271***************************************************************/
1272#define PIRANHA_ADDR_MASK 0x00160000UL /* bit 17,18,20 */
1273#define PIRANHA_ADDR_VAL 0x00060000UL /* bit 17,18 on */
1274static void *
1275sba_alloc_pdir(unsigned int pdir_size)
1276{
1277 unsigned long pdir_base;
1278 unsigned long pdir_order = get_order(pdir_size);
1279
1280 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
Grant Grundler64908ad2005-10-21 22:37:20 -04001281 if (NULL == (void *) pdir_base) {
1282 panic("%s() could not allocate I/O Page Table\n",
1283 __FUNCTION__);
1284 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285
1286 /* If this is not PA8700 (PCX-W2)
1287 ** OR newer than ver 2.2
1288 ** OR in a system that doesn't need VINDEX bits from SBA,
1289 **
1290 ** then we aren't exposed to the HW bug.
1291 */
1292 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1293 || (boot_cpu_data.pdc.versions > 0x202)
1294 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1295 return (void *) pdir_base;
1296
1297 /*
1298 * PA8700 (PCX-W2, aka piranha) silent data corruption fix
1299 *
1300 * An interaction between PA8700 CPU (Ver 2.2 or older) and
1301 * Ike/Astro can cause silent data corruption. This is only
1302 * a problem if the I/O PDIR is located in memory such that
1303 * (little-endian) bits 17 and 18 are on and bit 20 is off.
1304 *
1305 * Since the max IO Pdir size is 2MB, by cleverly allocating the
1306 * right physical address, we can either avoid (IOPDIR <= 1MB)
1307 * or minimize (2MB IO Pdir) the problem if we restrict the
1308 * IO Pdir to a maximum size of 2MB-128K (1902K).
1309 *
1310 * Because we always allocate 2^N sized IO pdirs, either of the
1311 * "bad" regions will be the last 128K if at all. That's easy
1312 * to test for.
1313 *
1314 */
1315 if (pdir_order <= (19-12)) {
1316 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1317 /* allocate a new one on 512k alignment */
1318 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1319 /* release original */
1320 free_pages(pdir_base, pdir_order);
1321
1322 pdir_base = new_pdir;
1323
1324 /* release excess */
1325 while (pdir_order < (19-12)) {
1326 new_pdir += pdir_size;
1327 free_pages(new_pdir, pdir_order);
1328 pdir_order +=1;
1329 pdir_size <<=1;
1330 }
1331 }
1332 } else {
1333 /*
1334 ** 1MB or 2MB Pdir
1335 ** Needs to be aligned on an "odd" 1MB boundary.
1336 */
1337 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1); /* 2 or 4MB */
1338
1339 /* release original */
1340 free_pages( pdir_base, pdir_order);
1341
1342 /* release first 1MB */
1343 free_pages(new_pdir, 20-12);
1344
1345 pdir_base = new_pdir + 1024*1024;
1346
1347 if (pdir_order > (20-12)) {
1348 /*
1349 ** 2MB Pdir.
1350 **
1351 ** Flag tells init_bitmap() to mark bad 128k as used
1352 ** and to reduce the size by 128k.
1353 */
1354 piranha_bad_128k = 1;
1355
1356 new_pdir += 3*1024*1024;
1357 /* release last 1MB */
1358 free_pages(new_pdir, 20-12);
1359
1360 /* release unusable 128KB */
1361 free_pages(new_pdir - 128*1024 , 17-12);
1362
1363 pdir_size -= 128*1024;
1364 }
1365 }
1366
1367 memset((void *) pdir_base, 0, pdir_size);
1368 return (void *) pdir_base;
1369}
1370
Matthew Wilcox56583742005-10-21 22:33:38 -04001371static struct device *next_device(struct klist_iter *i)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001372{
Matthew Wilcox56583742005-10-21 22:33:38 -04001373 struct klist_node * n = klist_next(i);
1374 return n ? container_of(n, struct device, knode_parent) : NULL;
1375}
1376
1377/* setup Mercury or Elroy IBASE/IMASK registers. */
1378static void
1379setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1380{
1381 /* lba_set_iregs() is in drivers/parisc/lba_pci.c */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001382 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1383 struct device *dev;
Matthew Wilcox56583742005-10-21 22:33:38 -04001384 struct klist_iter i;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001385
Matthew Wilcox56583742005-10-21 22:33:38 -04001386 klist_iter_init(&sba->dev.klist_children, &i);
1387 while ((dev = next_device(&i))) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001388 struct parisc_device *lba = to_parisc_device(dev);
Matthew Wilcox56583742005-10-21 22:33:38 -04001389 int rope_num = (lba->hpa.start >> 13) & 0xf;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001390 if (rope_num >> 3 == ioc_num)
1391 lba_set_iregs(lba, ioc->ibase, ioc->imask);
1392 }
Matthew Wilcox56583742005-10-21 22:33:38 -04001393 klist_iter_exit(&i);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001394}
1395
1396static void
1397sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1398{
1399 u32 iova_space_mask;
1400 u32 iova_space_size;
1401 int iov_order, tcnfg;
Grant Grundler64908ad2005-10-21 22:37:20 -04001402#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403 int agp_found = 0;
1404#endif
1405 /*
1406 ** Firmware programs the base and size of a "safe IOVA space"
1407 ** (one that doesn't overlap memory or LMMIO space) in the
1408 ** IBASE and IMASK registers.
1409 */
1410 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1411 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1412
1413 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1414 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1415 iova_space_size /= 2;
1416 }
1417
1418 /*
1419 ** iov_order is always based on a 1GB IOVA space since we want to
1420 ** turn on the other half for AGP GART.
1421 */
1422 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1423 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1424
1425 DBG_INIT("%s() hpa 0x%lx IOV %dMB (%d bits)\n",
1426 __FUNCTION__, ioc->ioc_hpa, iova_space_size >> 20,
1427 iov_order + PAGE_SHIFT);
1428
1429 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1430 get_order(ioc->pdir_size));
1431 if (!ioc->pdir_base)
1432 panic("Couldn't allocate I/O Page Table\n");
1433
1434 memset(ioc->pdir_base, 0, ioc->pdir_size);
1435
1436 DBG_INIT("%s() pdir %p size %x\n",
1437 __FUNCTION__, ioc->pdir_base, ioc->pdir_size);
1438
Grant Grundler64908ad2005-10-21 22:37:20 -04001439#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1441 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1442
1443 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1444 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1445#endif
1446
1447 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1448 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1449
1450 /* build IMASK for IOC and Elroy */
1451 iova_space_mask = 0xffffffff;
1452 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1453 ioc->imask = iova_space_mask;
1454#ifdef ZX1_SUPPORT
1455 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1456#endif
1457 sba_dump_tlb(ioc->ioc_hpa);
1458
1459 setup_ibase_imask(sba, ioc, ioc_num);
1460
1461 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1462
Grant Grundler64908ad2005-10-21 22:37:20 -04001463#ifdef CONFIG_64BIT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001464 /*
1465 ** Setting the upper bits makes checking for bypass addresses
1466 ** a little faster later on.
1467 */
1468 ioc->imask |= 0xFFFFFFFF00000000UL;
1469#endif
1470
1471 /* Set I/O PDIR Page size to system page size */
1472 switch (PAGE_SHIFT) {
1473 case 12: tcnfg = 0; break; /* 4K */
1474 case 13: tcnfg = 1; break; /* 8K */
1475 case 14: tcnfg = 2; break; /* 16K */
1476 case 16: tcnfg = 3; break; /* 64K */
1477 default:
1478 panic(__FILE__ "Unsupported system page size %d",
1479 1 << PAGE_SHIFT);
1480 break;
1481 }
1482 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1483
1484 /*
1485 ** Program the IOC's ibase and enable IOVA translation
1486 ** Bit zero == enable bit.
1487 */
1488 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1489
1490 /*
1491 ** Clear I/O TLB of any possible entries.
1492 ** (Yes. This is a bit paranoid...but so what)
1493 */
1494 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1495
Grant Grundler64908ad2005-10-21 22:37:20 -04001496#ifdef SBA_AGP_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001497 /*
1498 ** If an AGP device is present, only use half of the IOV space
1499 ** for PCI DMA. Unfortunately we can't know ahead of time
1500 ** whether GART support will actually be used, for now we
1501 ** can just key on any AGP device found in the system.
1502 ** We program the next pdir index after we stop w/ a key for
1503 ** the GART code to handshake on.
1504 */
1505 device=NULL;
1506 for (lba = sba->child; lba; lba = lba->sibling) {
1507 if (IS_QUICKSILVER(lba))
1508 break;
1509 }
1510
1511 if (lba) {
1512 DBG_INIT("%s: Reserving half of IOVA space for AGP GART support\n", __FUNCTION__);
1513 ioc->pdir_size /= 2;
1514 ((u64 *)ioc->pdir_base)[PDIR_INDEX(iova_space_size/2)] = SBA_IOMMU_COOKIE;
1515 } else {
1516 DBG_INIT("%s: No GART needed - no AGP controller found\n", __FUNCTION__);
1517 }
1518#endif /* 0 */
1519
1520}
1521
1522static void
1523sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1524{
1525 u32 iova_space_size, iova_space_mask;
1526 unsigned int pdir_size, iov_order;
1527
1528 /*
1529 ** Determine IOVA Space size from memory size.
1530 **
1531 ** Ideally, PCI drivers would register the maximum number
1532 ** of DMA they can have outstanding for each device they
1533 ** own. Next best thing would be to guess how much DMA
1534 ** can be outstanding based on PCI Class/sub-class. Both
1535 ** methods still require some "extra" to support PCI
1536 ** Hot-Plug/Removal of PCI cards. (aka PCI OLARD).
1537 **
1538 ** While we have 32-bits "IOVA" space, top two 2 bits are used
1539 ** for DMA hints - ergo only 30 bits max.
1540 */
1541
1542 iova_space_size = (u32) (num_physpages/global_ioc_cnt);
1543
1544 /* limit IOVA space size to 1MB-1GB */
1545 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1546 iova_space_size = 1 << (20 - PAGE_SHIFT);
1547 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001548 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1549 iova_space_size = 1 << (30 - PAGE_SHIFT);
1550 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001551
1552 /*
1553 ** iova space must be log2() in size.
1554 ** thus, pdir/res_map will also be log2().
1555 ** PIRANHA BUG: Exception is when IO Pdir is 2MB (gets reduced)
1556 */
1557 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1558
1559 /* iova_space_size is now bytes, not pages */
1560 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1561
1562 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1563
1564 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1565 __FUNCTION__,
1566 ioc->ioc_hpa,
1567 (unsigned long) num_physpages >> (20 - PAGE_SHIFT),
1568 iova_space_size>>20,
1569 iov_order + PAGE_SHIFT);
1570
1571 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1572
1573 DBG_INIT("%s() pdir %p size %x\n",
1574 __FUNCTION__, ioc->pdir_base, pdir_size);
1575
Grant Grundler64908ad2005-10-21 22:37:20 -04001576#ifdef SBA_HINT_SUPPORT
Linus Torvalds1da177e2005-04-16 15:20:36 -07001577 /* FIXME : DMA HINTs not used */
1578 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1579 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1580
1581 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1582 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1583#endif
1584
1585 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1586
1587 /* build IMASK for IOC and Elroy */
1588 iova_space_mask = 0xffffffff;
1589 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1590
1591 /*
1592 ** On C3000 w/512MB mem, HP-UX 10.20 reports:
1593 ** ibase=0, imask=0xFE000000, size=0x2000000.
1594 */
1595 ioc->ibase = 0;
1596 ioc->imask = iova_space_mask; /* save it */
1597#ifdef ZX1_SUPPORT
1598 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1599#endif
1600
1601 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1602 __FUNCTION__, ioc->ibase, ioc->imask);
1603
1604 /*
1605 ** FIXME: Hint registers are programmed with default hint
1606 ** values during boot, so hints should be sane even if we
1607 ** can't reprogram them the way drivers want.
1608 */
1609
1610 setup_ibase_imask(sba, ioc, ioc_num);
1611
1612 /*
1613 ** Program the IOC's ibase and enable IOVA translation
1614 */
1615 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1616 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1617
1618 /* Set I/O PDIR Page size to 4K */
1619 WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
1620
1621 /*
1622 ** Clear I/O TLB of any possible entries.
1623 ** (Yes. This is a bit paranoid...but so what)
1624 */
1625 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1626
1627 ioc->ibase = 0; /* used by SBA_IOVA and related macros */
1628
1629 DBG_INIT("%s() DONE\n", __FUNCTION__);
1630}
1631
1632
1633
1634/**************************************************************************
1635**
1636** SBA initialization code (HW and SW)
1637**
1638** o identify SBA chip itself
1639** o initialize SBA chip modes (HardFail)
1640** o initialize SBA chip modes (HardFail)
1641** o FIXME: initialize DMA hints for reasonable defaults
1642**
1643**************************************************************************/
1644
Helge Deller5076c152006-03-27 12:52:15 -07001645static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001646{
Helge Deller5076c152006-03-27 12:52:15 -07001647 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648}
1649
1650static void sba_hw_init(struct sba_device *sba_dev)
1651{
1652 int i;
1653 int num_ioc;
1654 u64 ioc_ctl;
1655
1656 if (!is_pdc_pat()) {
1657 /* Shutdown the USB controller on Astro-based workstations.
1658 ** Once we reprogram the IOMMU, the next DMA performed by
1659 ** USB will HPMC the box. USB is only enabled if a
1660 ** keyboard is present and found.
1661 **
1662 ** With serial console, j6k v5.0 firmware says:
1663 ** mem_kbd hpa 0xfee003f8 sba 0x0 pad 0x0 cl_class 0x7
1664 **
1665 ** FIXME: Using GFX+USB console at power up but direct
1666 ** linux to serial console is still broken.
1667 ** USB could generate DMA so we must reset USB.
1668 ** The proper sequence would be:
1669 ** o block console output
1670 ** o reset USB device
1671 ** o reprogram serial port
1672 ** o unblock console output
1673 */
1674 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1675 pdc_io_reset_devices();
1676 }
1677
1678 }
1679
1680
1681#if 0
1682printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1683 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1684
1685 /*
1686 ** Need to deal with DMA from LAN.
1687 ** Maybe use page zero boot device as a handle to talk
1688 ** to PDC about which device to shutdown.
1689 **
1690 ** Netbooting, j6k v5.0 firmware says:
1691 ** mem_boot hpa 0xf4008000 sba 0x0 pad 0x0 cl_class 0x1002
1692 ** ARGH! invalid class.
1693 */
1694 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1695 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1696 pdc_io_reset();
1697 }
1698#endif
1699
1700 if (!IS_PLUTO(sba_dev->iodc)) {
1701 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1702 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1703 __FUNCTION__, sba_dev->sba_hpa, ioc_ctl);
1704 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1705 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1706 /* j6700 v1.6 firmware sets 0x294f */
1707 /* A500 firmware sets 0x4d */
1708
1709 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1710
1711#ifdef DEBUG_SBA_INIT
1712 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1713 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1714#endif
1715 } /* if !PLUTO */
1716
1717 if (IS_ASTRO(sba_dev->iodc)) {
1718 int err;
1719 /* PAT_PDC (L-class) also reports the same goofy base */
1720 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1721 num_ioc = 1;
1722
1723 sba_dev->chip_resv.name = "Astro Intr Ack";
1724 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1725 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1726 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
Eric Sesterhennb7494552006-03-24 18:52:10 +01001727 BUG_ON(err < 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001728
1729 } else if (IS_PLUTO(sba_dev->iodc)) {
1730 int err;
1731
1732 /* We use a negative value for IOC HPA so it gets
1733 * corrected when we add it with IKE's IOC offset.
1734 * Doesnt look clean, but fewer code.
1735 */
1736 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1737 num_ioc = 1;
1738
1739 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1740 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1741 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1742 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1743 WARN_ON(err < 0);
1744
1745 sba_dev->iommu_resv.name = "IOVA Space";
1746 sba_dev->iommu_resv.start = 0x40000000UL;
1747 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1748 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1749 WARN_ON(err < 0);
1750 } else {
1751 /* IS_IKE (ie N-class, L3000, L1500) */
1752 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1753 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1754 num_ioc = 2;
1755
1756 /* TODO - LOOKUP Ike/Stretch chipset mem map */
1757 }
1758 /* XXX: What about Reo? */
1759
1760 sba_dev->num_ioc = num_ioc;
1761 for (i = 0; i < num_ioc; i++) {
1762 /*
1763 ** Make sure the box crashes if we get any errors on a rope.
1764 */
1765 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE0_CTL);
1766 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE1_CTL);
1767 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE2_CTL);
1768 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE3_CTL);
1769 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE4_CTL);
1770 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE5_CTL);
1771 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE6_CTL);
1772 WRITE_REG(HF_ENABLE, sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1773
1774 /* flush out the writes */
1775 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1776
1777 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1778 i,
1779 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1780 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1781 );
1782 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1783 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1784 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1785 );
1786
1787 if (IS_PLUTO(sba_dev->iodc)) {
1788 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1789 } else {
1790 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1791 }
1792 }
1793}
1794
1795static void
1796sba_common_init(struct sba_device *sba_dev)
1797{
1798 int i;
1799
1800 /* add this one to the head of the list (order doesn't matter)
1801 ** This will be useful for debugging - especially if we get coredumps
1802 */
1803 sba_dev->next = sba_list;
1804 sba_list = sba_dev;
1805
1806 for(i=0; i< sba_dev->num_ioc; i++) {
1807 int res_size;
1808#ifdef DEBUG_DMB_TRAP
1809 extern void iterate_pages(unsigned long , unsigned long ,
1810 void (*)(pte_t * , unsigned long),
1811 unsigned long );
1812 void set_data_memory_break(pte_t * , unsigned long);
1813#endif
1814 /* resource map size dictated by pdir_size */
1815 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64); /* entries */
1816
1817 /* Second part of PIRANHA BUG */
1818 if (piranha_bad_128k) {
1819 res_size -= (128*1024)/sizeof(u64);
1820 }
1821
1822 res_size >>= 3; /* convert bit count to byte count */
1823 DBG_INIT("%s() res_size 0x%x\n",
1824 __FUNCTION__, res_size);
1825
1826 sba_dev->ioc[i].res_size = res_size;
1827 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1828
1829#ifdef DEBUG_DMB_TRAP
1830 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1831 set_data_memory_break, 0);
1832#endif
1833
1834 if (NULL == sba_dev->ioc[i].res_map)
1835 {
1836 panic("%s:%s() could not allocate resource map\n",
1837 __FILE__, __FUNCTION__ );
1838 }
1839
1840 memset(sba_dev->ioc[i].res_map, 0, res_size);
1841 /* next available IOVP - circular search */
1842 sba_dev->ioc[i].res_hint = (unsigned long *)
1843 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1844
1845#ifdef ASSERT_PDIR_SANITY
1846 /* Mark first bit busy - ie no IOVA 0 */
1847 sba_dev->ioc[i].res_map[0] = 0x80;
1848 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1849#endif
1850
1851 /* Third (and last) part of PIRANHA BUG */
1852 if (piranha_bad_128k) {
1853 /* region from +1408K to +1536 is un-usable. */
1854
1855 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1856 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1857 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1858 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1859
1860 /* mark that part of the io pdir busy */
1861 while (p_start < p_end)
1862 *p_start++ = -1;
1863
1864 }
1865
1866#ifdef DEBUG_DMB_TRAP
1867 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1868 set_data_memory_break, 0);
1869 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1870 set_data_memory_break, 0);
1871#endif
1872
1873 DBG_INIT("%s() %d res_map %x %p\n",
1874 __FUNCTION__, i, res_size, sba_dev->ioc[i].res_map);
1875 }
1876
1877 spin_lock_init(&sba_dev->sba_lock);
1878 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1879
1880#ifdef DEBUG_SBA_INIT
1881 /*
1882 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set
1883 * (bit #61, big endian), we have to flush and sync every time
1884 * IO-PDIR is changed in Ike/Astro.
1885 */
1886 if (boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC) {
1887 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1888 } else {
1889 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1890 }
1891#endif
1892}
1893
1894#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001895static int sba_proc_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896{
1897 struct sba_device *sba_dev = sba_list;
1898 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
1899 int total_pages = (int) (ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001900#ifdef SBA_COLLECT_STATS
1901 unsigned long avg = 0, min, max;
1902#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001903 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001904
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001905 len += seq_printf(m, "%s rev %d.%d\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001906 sba_dev->name,
1907 (sba_dev->hw_rev & 0x7) + 1,
1908 (sba_dev->hw_rev & 0x18) >> 3
1909 );
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001910 len += seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001911 (int) ((ioc->res_size << 3) * sizeof(u64)), /* 8 bits/byte */
1912 total_pages);
1913
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001914 len += seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1915 ioc->res_size, ioc->res_size << 3); /* 8 bits per byte */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001916
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001917 len += seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001918 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1919 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1920 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE)
1921 );
1922
1923 for (i=0; i<4; i++)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001924 len += seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n", i,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1926 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1927 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18)
1928 );
1929
1930#ifdef SBA_COLLECT_STATS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001931 len += seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001932 total_pages - ioc->used_pages, ioc->used_pages,
1933 (int) (ioc->used_pages * 100 / total_pages));
1934
1935 min = max = ioc->avg_search[0];
1936 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1937 avg += ioc->avg_search[i];
1938 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1939 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1940 }
1941 avg /= SBA_SEARCH_SAMPLE;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001942 len += seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1943 min, avg, max);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001944
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001945 len += seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1946 ioc->msingle_calls, ioc->msingle_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001947 (int) ((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1948
1949 /* KLUGE - unmap_sg calls unmap_single for each mapped page */
1950 min = ioc->usingle_calls;
1951 max = ioc->usingle_pages - ioc->usg_pages;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001952 len += seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1953 min, max, (int) ((max * 1000)/min));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001954
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001955 len += seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1956 ioc->msg_calls, ioc->msg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001957 (int) ((ioc->msg_pages * 1000)/ioc->msg_calls));
1958
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001959 len += seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1960 ioc->usg_calls, ioc->usg_pages,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001961 (int) ((ioc->usg_pages * 1000)/ioc->usg_calls));
1962#endif
1963
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001964 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001965}
1966
Linus Torvalds1da177e2005-04-16 15:20:36 -07001967static int
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001968sba_proc_open(struct inode *i, struct file *f)
1969{
1970 return single_open(f, &sba_proc_info, NULL);
1971}
1972
1973static struct file_operations sba_proc_fops = {
1974 .owner = THIS_MODULE,
1975 .open = sba_proc_open,
1976 .read = seq_read,
1977 .llseek = seq_lseek,
1978 .release = single_release,
1979};
1980
1981static int
1982sba_proc_bitmap_info(struct seq_file *m, void *p)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001983{
1984 struct sba_device *sba_dev = sba_list;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001985 struct ioc *ioc = &sba_dev->ioc[0]; /* FIXME: Multi-IOC support! */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001986 unsigned int *res_ptr = (unsigned int *)ioc->res_map;
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001987 int i, len = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001988
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001989 for (i = 0; i < (ioc->res_size/sizeof(unsigned int)); ++i, ++res_ptr) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001990 if ((i & 7) == 0)
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001991 len += seq_printf(m, "\n ");
1992 len += seq_printf(m, " %08x", *res_ptr);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001993 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001994 len += seq_printf(m, "\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001995
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001996 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001997}
Kyle McMartin7ec14e42006-02-06 10:10:15 -07001998
1999static int
2000sba_proc_bitmap_open(struct inode *i, struct file *f)
2001{
2002 return single_open(f, &sba_proc_bitmap_info, NULL);
2003}
2004
2005static struct file_operations sba_proc_bitmap_fops = {
2006 .owner = THIS_MODULE,
2007 .open = sba_proc_bitmap_open,
2008 .read = seq_read,
2009 .llseek = seq_lseek,
2010 .release = single_release,
2011};
Linus Torvalds1da177e2005-04-16 15:20:36 -07002012#endif /* CONFIG_PROC_FS */
2013
2014static struct parisc_device_id sba_tbl[] = {
2015 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
2016 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
2017 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
2018 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
2019 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
2020 { 0, }
2021};
2022
2023int sba_driver_callback(struct parisc_device *);
2024
2025static struct parisc_driver sba_driver = {
2026 .name = MODULE_NAME,
2027 .id_table = sba_tbl,
2028 .probe = sba_driver_callback,
2029};
2030
2031/*
2032** Determine if sba should claim this chip (return 0) or not (return 1).
2033** If so, initialize the chip and tell other partners in crime they
2034** have work to do.
2035*/
2036int
2037sba_driver_callback(struct parisc_device *dev)
2038{
2039 struct sba_device *sba_dev;
2040 u32 func_class;
2041 int i;
2042 char *version;
Helge Deller5076c152006-03-27 12:52:15 -07002043 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
Kyle McMartin7ec14e42006-02-06 10:10:15 -07002044 struct proc_dir_entry *info_entry, *bitmap_entry, *root;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002045
2046 sba_dump_ranges(sba_addr);
2047
2048 /* Read HW Rev First */
2049 func_class = READ_REG(sba_addr + SBA_FCLASS);
2050
2051 if (IS_ASTRO(&dev->id)) {
2052 unsigned long fclass;
2053 static char astro_rev[]="Astro ?.?";
2054
2055 /* Astro is broken...Read HW Rev First */
2056 fclass = READ_REG(sba_addr);
2057
2058 astro_rev[6] = '1' + (char) (fclass & 0x7);
2059 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
2060 version = astro_rev;
2061
2062 } else if (IS_IKE(&dev->id)) {
2063 static char ike_rev[] = "Ike rev ?";
2064 ike_rev[8] = '0' + (char) (func_class & 0xff);
2065 version = ike_rev;
2066 } else if (IS_PLUTO(&dev->id)) {
2067 static char pluto_rev[]="Pluto ?.?";
2068 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
2069 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
2070 version = pluto_rev;
2071 } else {
2072 static char reo_rev[] = "REO rev ?";
2073 reo_rev[8] = '0' + (char) (func_class & 0xff);
2074 version = reo_rev;
2075 }
2076
2077 if (!global_ioc_cnt) {
2078 global_ioc_cnt = count_parisc_driver(&sba_driver);
2079
2080 /* Astro and Pluto have one IOC per SBA */
2081 if ((!IS_ASTRO(&dev->id)) || (!IS_PLUTO(&dev->id)))
2082 global_ioc_cnt *= 2;
2083 }
2084
2085 printk(KERN_INFO "%s found %s at 0x%lx\n",
Matthew Wilcox53f01bb2005-10-21 22:36:40 -04002086 MODULE_NAME, version, dev->hpa.start);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002087
Helge Dellercb6fc182006-01-17 12:40:40 -07002088 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002089 if (!sba_dev) {
2090 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
2091 return -ENOMEM;
2092 }
2093
2094 parisc_set_drvdata(dev, sba_dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002095
2096 for(i=0; i<MAX_IOC; i++)
2097 spin_lock_init(&(sba_dev->ioc[i].res_lock));
2098
2099 sba_dev->dev = dev;
2100 sba_dev->hw_rev = func_class;
2101 sba_dev->iodc = &dev->id;
2102 sba_dev->name = dev->name;
2103 sba_dev->sba_hpa = sba_addr;
2104
2105 sba_get_pat_resources(sba_dev);
2106 sba_hw_init(sba_dev);
2107 sba_common_init(sba_dev);
2108
2109 hppa_dma_ops = &sba_ops;
2110
2111#ifdef CONFIG_PROC_FS
Kyle McMartin7ec14e42006-02-06 10:10:15 -07002112 switch (dev->id.hversion) {
2113 case PLUTO_MCKINLEY_PORT:
2114 root = proc_mckinley_root;
2115 break;
2116 case ASTRO_RUNWAY_PORT:
2117 case IKE_MERCED_PORT:
2118 default:
2119 root = proc_runway_root;
2120 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002121 }
Kyle McMartin7ec14e42006-02-06 10:10:15 -07002122
2123 info_entry = create_proc_entry("sba_iommu", 0, root);
2124 bitmap_entry = create_proc_entry("sba_iommu-bitmap", 0, root);
2125
2126 if (info_entry)
2127 info_entry->proc_fops = &sba_proc_fops;
2128
2129 if (bitmap_entry)
2130 bitmap_entry->proc_fops = &sba_proc_bitmap_fops;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002131#endif
Kyle McMartin7ec14e42006-02-06 10:10:15 -07002132
Linus Torvalds1da177e2005-04-16 15:20:36 -07002133 parisc_vmerge_boundary = IOVP_SIZE;
2134 parisc_vmerge_max_size = IOVP_SIZE * BITS_PER_LONG;
2135 parisc_has_iommu();
2136 return 0;
2137}
2138
2139/*
2140** One time initialization to let the world know the SBA was found.
2141** This is the only routine which is NOT static.
2142** Must be called exactly once before pci_init().
2143*/
2144void __init sba_init(void)
2145{
2146 register_parisc_driver(&sba_driver);
2147}
2148
2149
2150/**
2151 * sba_get_iommu - Assign the iommu pointer for the pci bus controller.
2152 * @dev: The parisc device.
2153 *
2154 * Returns the appropriate IOMMU data for the given parisc PCI controller.
2155 * This is cached and used later for PCI DMA Mapping.
2156 */
2157void * sba_get_iommu(struct parisc_device *pci_hba)
2158{
2159 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2160 struct sba_device *sba = sba_dev->dev.driver_data;
2161 char t = sba_dev->id.hw_type;
2162 int iocnum = (pci_hba->hw_path >> 3); /* rope # */
2163
2164 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2165
2166 return &(sba->ioc[iocnum]);
2167}
2168
2169
2170/**
2171 * sba_directed_lmmio - return first directed LMMIO range routed to rope
2172 * @pa_dev: The parisc device.
2173 * @r: resource PCI host controller wants start/end fields assigned.
2174 *
2175 * For the given parisc PCI controller, determine if any direct ranges
2176 * are routed down the corresponding rope.
2177 */
2178void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2179{
2180 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2181 struct sba_device *sba = sba_dev->dev.driver_data;
2182 char t = sba_dev->id.hw_type;
2183 int i;
2184 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2185
Eric Sesterhennb7494552006-03-24 18:52:10 +01002186 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002187
2188 r->start = r->end = 0;
2189
2190 /* Astro has 4 directed ranges. Not sure about Ike/Pluto/et al */
2191 for (i=0; i<4; i++) {
2192 int base, size;
2193 void __iomem *reg = sba->sba_hpa + i*0x18;
2194
2195 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2196 if ((base & 1) == 0)
2197 continue; /* not enabled */
2198
2199 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2200
2201 if ((size & (ROPES_PER_IOC-1)) != rope)
2202 continue; /* directed down different rope */
2203
2204 r->start = (base & ~1UL) | PCI_F_EXTEND;
2205 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2206 r->end = r->start + size;
2207 }
2208}
2209
2210
2211/**
2212 * sba_distributed_lmmio - return portion of distributed LMMIO range
2213 * @pa_dev: The parisc device.
2214 * @r: resource PCI host controller wants start/end fields assigned.
2215 *
2216 * For the given parisc PCI controller, return portion of distributed LMMIO
2217 * range. The distributed LMMIO is always present and it's just a question
2218 * of the base address and size of the range.
2219 */
2220void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2221{
2222 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2223 struct sba_device *sba = sba_dev->dev.driver_data;
2224 char t = sba_dev->id.hw_type;
2225 int base, size;
2226 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1)); /* rope # */
2227
Eric Sesterhennb7494552006-03-24 18:52:10 +01002228 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
Linus Torvalds1da177e2005-04-16 15:20:36 -07002229
2230 r->start = r->end = 0;
2231
2232 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2233 if ((base & 1) == 0) {
2234 BUG(); /* Gah! Distr Range wasn't enabled! */
2235 return;
2236 }
2237
2238 r->start = (base & ~1UL) | PCI_F_EXTEND;
2239
2240 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2241 r->start += rope * (size + 1); /* adjust base for this rope */
2242 r->end = r->start + size;
2243}