Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1 | /* |
Luis R. Rodriguez | b3950e6 | 2010-04-15 17:39:03 -0400 | [diff] [blame] | 2 | * Copyright (c) 2008-2010 Atheros Communications Inc. |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/io.h> |
| 18 | #include <asm/unaligned.h> |
| 19 | |
Luis R. Rodriguez | af03abe | 2009-09-09 02:33:11 -0700 | [diff] [blame] | 20 | #include "hw.h" |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 21 | #include "hw-ops.h" |
Luis R. Rodriguez | cfe8cba | 2009-09-13 23:39:31 -0700 | [diff] [blame] | 22 | #include "rc.h" |
Luis R. Rodriguez | b622a72 | 2010-04-15 17:39:28 -0400 | [diff] [blame] | 23 | #include "ar9003_mac.h" |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 24 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 25 | #define ATH9K_CLOCK_RATE_CCK 22 |
| 26 | #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40 |
| 27 | #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44 |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 28 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 29 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 30 | |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 31 | MODULE_AUTHOR("Atheros Communications"); |
| 32 | MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); |
| 33 | MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards"); |
| 34 | MODULE_LICENSE("Dual BSD/GPL"); |
| 35 | |
| 36 | static int __init ath9k_init(void) |
| 37 | { |
| 38 | return 0; |
| 39 | } |
| 40 | module_init(ath9k_init); |
| 41 | |
| 42 | static void __exit ath9k_exit(void) |
| 43 | { |
| 44 | return; |
| 45 | } |
| 46 | module_exit(ath9k_exit); |
| 47 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 48 | /* Private hardware callbacks */ |
| 49 | |
| 50 | static void ath9k_hw_init_cal_settings(struct ath_hw *ah) |
| 51 | { |
| 52 | ath9k_hw_private_ops(ah)->init_cal_settings(ah); |
| 53 | } |
| 54 | |
| 55 | static void ath9k_hw_init_mode_regs(struct ath_hw *ah) |
| 56 | { |
| 57 | ath9k_hw_private_ops(ah)->init_mode_regs(ah); |
| 58 | } |
| 59 | |
| 60 | static bool ath9k_hw_macversion_supported(struct ath_hw *ah) |
| 61 | { |
| 62 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); |
| 63 | |
| 64 | return priv_ops->macversion_supported(ah->hw_version.macVersion); |
| 65 | } |
| 66 | |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 67 | static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah, |
| 68 | struct ath9k_channel *chan) |
| 69 | { |
| 70 | return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan); |
| 71 | } |
| 72 | |
Luis R. Rodriguez | 991312d | 2010-04-15 17:39:05 -0400 | [diff] [blame] | 73 | static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah) |
| 74 | { |
| 75 | if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs) |
| 76 | return; |
| 77 | |
| 78 | ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah); |
| 79 | } |
| 80 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 81 | /********************/ |
| 82 | /* Helper Functions */ |
| 83 | /********************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 84 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 85 | static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 86 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 87 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 88 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 89 | if (!ah->curchan) /* should really check for CCK instead */ |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 90 | return usecs *ATH9K_CLOCK_RATE_CCK; |
| 91 | if (conf->channel->band == IEEE80211_BAND_2GHZ) |
| 92 | return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM; |
| 93 | return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 94 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 95 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 96 | static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 97 | { |
Luis R. Rodriguez | b002a4a | 2009-09-13 00:03:27 -0700 | [diff] [blame] | 98 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 99 | |
Luis R. Rodriguez | 4febf7b | 2008-12-23 15:58:48 -0800 | [diff] [blame] | 100 | if (conf_is_ht40(conf)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 101 | return ath9k_hw_mac_clks(ah, usecs) * 2; |
| 102 | else |
| 103 | return ath9k_hw_mac_clks(ah, usecs); |
| 104 | } |
| 105 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 106 | bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 107 | { |
| 108 | int i; |
| 109 | |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 110 | BUG_ON(timeout < AH_TIME_QUANTUM); |
| 111 | |
| 112 | for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 113 | if ((REG_READ(ah, reg) & mask) == val) |
| 114 | return true; |
| 115 | |
| 116 | udelay(AH_TIME_QUANTUM); |
| 117 | } |
Sujith | 04bd4638 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 118 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 119 | ath_print(ath9k_hw_common(ah), ATH_DBG_ANY, |
| 120 | "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", |
| 121 | timeout, reg, REG_READ(ah, reg), mask, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 122 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 123 | return false; |
| 124 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 125 | EXPORT_SYMBOL(ath9k_hw_wait); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 126 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 127 | u32 ath9k_hw_reverse_bits(u32 val, u32 n) |
| 128 | { |
| 129 | u32 retval; |
| 130 | int i; |
| 131 | |
| 132 | for (i = 0, retval = 0; i < n; i++) { |
| 133 | retval = (retval << 1) | (val & 1); |
| 134 | val >>= 1; |
| 135 | } |
| 136 | return retval; |
| 137 | } |
| 138 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 139 | bool ath9k_get_channel_edges(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 140 | u16 flags, u16 *low, |
| 141 | u16 *high) |
| 142 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 143 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 144 | |
| 145 | if (flags & CHANNEL_5GHZ) { |
| 146 | *low = pCap->low_5ghz_chan; |
| 147 | *high = pCap->high_5ghz_chan; |
| 148 | return true; |
| 149 | } |
| 150 | if ((flags & CHANNEL_2GHZ)) { |
| 151 | *low = pCap->low_2ghz_chan; |
| 152 | *high = pCap->high_2ghz_chan; |
| 153 | return true; |
| 154 | } |
| 155 | return false; |
| 156 | } |
| 157 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 158 | u16 ath9k_hw_computetxtime(struct ath_hw *ah, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 159 | u8 phy, int kbps, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 160 | u32 frameLen, u16 rateix, |
| 161 | bool shortPreamble) |
| 162 | { |
| 163 | u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 164 | |
| 165 | if (kbps == 0) |
| 166 | return 0; |
| 167 | |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 168 | switch (phy) { |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 169 | case WLAN_RC_PHY_CCK: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 170 | phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS; |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 171 | if (shortPreamble) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 172 | phyTime >>= 1; |
| 173 | numBits = frameLen << 3; |
| 174 | txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps); |
| 175 | break; |
Sujith | 46d14a5 | 2008-11-18 09:08:13 +0530 | [diff] [blame] | 176 | case WLAN_RC_PHY_OFDM: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 177 | if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 178 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000; |
| 179 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 180 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 181 | txTime = OFDM_SIFS_TIME_QUARTER |
| 182 | + OFDM_PREAMBLE_TIME_QUARTER |
| 183 | + (numSymbols * OFDM_SYMBOL_TIME_QUARTER); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 184 | } else if (ah->curchan && |
| 185 | IS_CHAN_HALF_RATE(ah->curchan)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 186 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000; |
| 187 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 188 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 189 | txTime = OFDM_SIFS_TIME_HALF + |
| 190 | OFDM_PREAMBLE_TIME_HALF |
| 191 | + (numSymbols * OFDM_SYMBOL_TIME_HALF); |
| 192 | } else { |
| 193 | bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000; |
| 194 | numBits = OFDM_PLCP_BITS + (frameLen << 3); |
| 195 | numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol); |
| 196 | txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME |
| 197 | + (numSymbols * OFDM_SYMBOL_TIME); |
| 198 | } |
| 199 | break; |
| 200 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 201 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
Felix Fietkau | 545750d | 2009-11-23 22:21:01 +0100 | [diff] [blame] | 202 | "Unknown phy %u (rate ix %u)\n", phy, rateix); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 203 | txTime = 0; |
| 204 | break; |
| 205 | } |
| 206 | |
| 207 | return txTime; |
| 208 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 209 | EXPORT_SYMBOL(ath9k_hw_computetxtime); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 210 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 211 | void ath9k_hw_get_channel_centers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 212 | struct ath9k_channel *chan, |
| 213 | struct chan_centers *centers) |
| 214 | { |
| 215 | int8_t extoff; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 216 | |
| 217 | if (!IS_CHAN_HT40(chan)) { |
| 218 | centers->ctl_center = centers->ext_center = |
| 219 | centers->synth_center = chan->channel; |
| 220 | return; |
| 221 | } |
| 222 | |
| 223 | if ((chan->chanmode == CHANNEL_A_HT40PLUS) || |
| 224 | (chan->chanmode == CHANNEL_G_HT40PLUS)) { |
| 225 | centers->synth_center = |
| 226 | chan->channel + HT40_CHANNEL_CENTER_SHIFT; |
| 227 | extoff = 1; |
| 228 | } else { |
| 229 | centers->synth_center = |
| 230 | chan->channel - HT40_CHANNEL_CENTER_SHIFT; |
| 231 | extoff = -1; |
| 232 | } |
| 233 | |
| 234 | centers->ctl_center = |
| 235 | centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 236 | /* 25 MHz spacing is supported by hw but not on upper layers */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 237 | centers->ext_center = |
Luis R. Rodriguez | 6420014 | 2009-09-13 22:05:04 -0700 | [diff] [blame] | 238 | centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 239 | } |
| 240 | |
| 241 | /******************/ |
| 242 | /* Chip Revisions */ |
| 243 | /******************/ |
| 244 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 245 | static void ath9k_hw_read_revisions(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 246 | { |
| 247 | u32 val; |
| 248 | |
| 249 | val = REG_READ(ah, AR_SREV) & AR_SREV_ID; |
| 250 | |
| 251 | if (val == 0xFF) { |
| 252 | val = REG_READ(ah, AR_SREV); |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 253 | ah->hw_version.macVersion = |
| 254 | (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; |
| 255 | ah->hw_version.macRev = MS(val, AR_SREV_REVISION2); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 256 | ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 257 | } else { |
| 258 | if (!AR_SREV_9100(ah)) |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 259 | ah->hw_version.macVersion = MS(val, AR_SREV_VERSION); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 260 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 261 | ah->hw_version.macRev = val & AR_SREV_REVISION; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 262 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 263 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 264 | ah->is_pciexpress = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 265 | } |
| 266 | } |
| 267 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 268 | /************************************/ |
| 269 | /* HW Attach, Detach, Init Routines */ |
| 270 | /************************************/ |
| 271 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 272 | static void ath9k_hw_disablepcie(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 273 | { |
Sujith | feed029 | 2009-01-29 11:37:35 +0530 | [diff] [blame] | 274 | if (AR_SREV_9100(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 275 | return; |
| 276 | |
| 277 | REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); |
| 278 | REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); |
| 279 | REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); |
| 280 | REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); |
| 281 | REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); |
| 282 | REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); |
| 283 | REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); |
| 284 | REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); |
| 285 | REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); |
| 286 | |
| 287 | REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); |
| 288 | } |
| 289 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 290 | /* This should work for all families including legacy */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 291 | static bool ath9k_hw_chip_test(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 292 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 293 | struct ath_common *common = ath9k_hw_common(ah); |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 294 | u32 regAddr[2] = { AR_STA_ID0 }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 295 | u32 regHold[2]; |
| 296 | u32 patternData[4] = { 0x55555555, |
| 297 | 0xaaaaaaaa, |
| 298 | 0x66666666, |
| 299 | 0x99999999 }; |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 300 | int i, j, loop_max; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 301 | |
Senthil Balasubramanian | 1f3f061 | 2010-04-15 17:38:29 -0400 | [diff] [blame] | 302 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 303 | loop_max = 2; |
| 304 | regAddr[1] = AR_PHY_BASE + (8 << 2); |
| 305 | } else |
| 306 | loop_max = 1; |
| 307 | |
| 308 | for (i = 0; i < loop_max; i++) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 309 | u32 addr = regAddr[i]; |
| 310 | u32 wrData, rdData; |
| 311 | |
| 312 | regHold[i] = REG_READ(ah, addr); |
| 313 | for (j = 0; j < 0x100; j++) { |
| 314 | wrData = (j << 16) | j; |
| 315 | REG_WRITE(ah, addr, wrData); |
| 316 | rdData = REG_READ(ah, addr); |
| 317 | if (rdData != wrData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 318 | ath_print(common, ATH_DBG_FATAL, |
| 319 | "address test failed " |
| 320 | "addr: 0x%08x - wr:0x%08x != " |
| 321 | "rd:0x%08x\n", |
| 322 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 323 | return false; |
| 324 | } |
| 325 | } |
| 326 | for (j = 0; j < 4; j++) { |
| 327 | wrData = patternData[j]; |
| 328 | REG_WRITE(ah, addr, wrData); |
| 329 | rdData = REG_READ(ah, addr); |
| 330 | if (wrData != rdData) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 331 | ath_print(common, ATH_DBG_FATAL, |
| 332 | "address test failed " |
| 333 | "addr: 0x%08x - wr:0x%08x != " |
| 334 | "rd:0x%08x\n", |
| 335 | addr, wrData, rdData); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 336 | return false; |
| 337 | } |
| 338 | } |
| 339 | REG_WRITE(ah, regAddr[i], regHold[i]); |
| 340 | } |
| 341 | udelay(100); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 342 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 343 | return true; |
| 344 | } |
| 345 | |
Luis R. Rodriguez | b8b0f37 | 2009-08-03 12:24:43 -0700 | [diff] [blame] | 346 | static void ath9k_hw_init_config(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 347 | { |
| 348 | int i; |
| 349 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 350 | ah->config.dma_beacon_response_time = 2; |
| 351 | ah->config.sw_beacon_response_time = 10; |
| 352 | ah->config.additional_swba_backoff = 0; |
| 353 | ah->config.ack_6mb = 0x0; |
| 354 | ah->config.cwm_ignore_extcca = 0; |
| 355 | ah->config.pcie_powersave_enable = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 356 | ah->config.pcie_clock_req = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 357 | ah->config.pcie_waen = 0; |
| 358 | ah->config.analog_shiftreg = 1; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 359 | ah->config.ofdm_trig_low = 200; |
| 360 | ah->config.ofdm_trig_high = 500; |
| 361 | ah->config.cck_trig_high = 200; |
| 362 | ah->config.cck_trig_low = 100; |
Luis R. Rodriguez | 31a0bd3 | 2010-04-15 17:38:22 -0400 | [diff] [blame] | 363 | |
| 364 | /* |
| 365 | * For now ANI is disabled for AR9003, it is still |
| 366 | * being tested. |
| 367 | */ |
| 368 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 369 | ah->config.enable_ani = 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 370 | |
| 371 | for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 372 | ah->config.spurchans[i][0] = AR_NO_SPUR; |
| 373 | ah->config.spurchans[i][1] = AR_NO_SPUR; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 374 | } |
| 375 | |
Luis R. Rodriguez | 5ffaf8a | 2010-02-02 11:58:33 -0500 | [diff] [blame] | 376 | if (ah->hw_version.devid != AR2427_DEVID_PCIE) |
| 377 | ah->config.ht_enable = 1; |
| 378 | else |
| 379 | ah->config.ht_enable = 0; |
| 380 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 381 | ah->config.rx_intr_mitigation = true; |
Luis R. Rodriguez | 6158425 | 2009-03-12 18:18:49 -0400 | [diff] [blame] | 382 | |
| 383 | /* |
| 384 | * We need this for PCI devices only (Cardbus, PCI, miniPCI) |
| 385 | * _and_ if on non-uniprocessor systems (Multiprocessor/HT). |
| 386 | * This means we use it for all AR5416 devices, and the few |
| 387 | * minor PCI AR9280 devices out there. |
| 388 | * |
| 389 | * Serialization is required because these devices do not handle |
| 390 | * well the case of two concurrent reads/writes due to the latency |
| 391 | * involved. During one read/write another read/write can be issued |
| 392 | * on another CPU while the previous read/write may still be working |
| 393 | * on our hardware, if we hit this case the hardware poops in a loop. |
| 394 | * We prevent this by serializing reads and writes. |
| 395 | * |
| 396 | * This issue is not present on PCI-Express devices or pre-AR5416 |
| 397 | * devices (legacy, 802.11abg). |
| 398 | */ |
| 399 | if (num_possible_cpus() > 1) |
David S. Miller | 2d6a5e9 | 2009-03-17 15:01:30 -0700 | [diff] [blame] | 400 | ah->config.serialize_regmode = SER_REG_MODE_AUTO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 401 | } |
| 402 | |
Luis R. Rodriguez | 50aca25 | 2009-08-03 12:24:42 -0700 | [diff] [blame] | 403 | static void ath9k_hw_init_defaults(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 404 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 405 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
| 406 | |
| 407 | regulatory->country_code = CTRY_DEFAULT; |
| 408 | regulatory->power_limit = MAX_RATE_POWER; |
| 409 | regulatory->tp_scale = ATH9K_TP_SCALE_MAX; |
| 410 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 411 | ah->hw_version.magic = AR5416_MAGIC; |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 412 | ah->hw_version.subvendorid = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 413 | |
| 414 | ah->ah_flags = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 415 | if (!AR_SREV_9100(ah)) |
| 416 | ah->ah_flags = AH_USE_EEPROM; |
| 417 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 418 | ah->atim_window = 0; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 419 | ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE; |
| 420 | ah->beacon_interval = 100; |
| 421 | ah->enable_32kHz_clock = DONT_USE_32KHZ; |
| 422 | ah->slottime = (u32) -1; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 423 | ah->globaltxtimeout = (u32) -1; |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 424 | ah->power_mode = ATH9K_PM_UNDEFINED; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 425 | } |
| 426 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 427 | static int ath9k_hw_init_macaddr(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 428 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 429 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 430 | u32 sum; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 431 | int i; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 432 | u16 eeval; |
Luis R. Rodriguez | 4910167 | 2010-04-15 17:39:13 -0400 | [diff] [blame] | 433 | u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW }; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 434 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 435 | sum = 0; |
| 436 | for (i = 0; i < 3; i++) { |
Luis R. Rodriguez | 4910167 | 2010-04-15 17:39:13 -0400 | [diff] [blame] | 437 | eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 438 | sum += eeval; |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 439 | common->macaddr[2 * i] = eeval >> 8; |
| 440 | common->macaddr[2 * i + 1] = eeval & 0xff; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 441 | } |
Sujith | d8baa93 | 2009-03-30 15:28:25 +0530 | [diff] [blame] | 442 | if (sum == 0 || sum == 0xffff * 3) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 443 | return -EADDRNOTAVAIL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 444 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 445 | return 0; |
| 446 | } |
| 447 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 448 | static int ath9k_hw_post_init(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 449 | { |
| 450 | int ecode; |
| 451 | |
Sujith | 527d485 | 2010-03-17 14:25:16 +0530 | [diff] [blame] | 452 | if (!AR_SREV_9271(ah)) { |
| 453 | if (!ath9k_hw_chip_test(ah)) |
| 454 | return -ENODEV; |
| 455 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 456 | |
Luis R. Rodriguez | ebd5a14 | 2010-04-15 17:39:18 -0400 | [diff] [blame] | 457 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 458 | ecode = ar9002_hw_rf_claim(ah); |
| 459 | if (ecode != 0) |
| 460 | return ecode; |
| 461 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 462 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 463 | ecode = ath9k_hw_eeprom_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 464 | if (ecode != 0) |
| 465 | return ecode; |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 466 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 467 | ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG, |
| 468 | "Eeprom VER: %d, REV: %d\n", |
| 469 | ah->eep_ops->get_eeprom_ver(ah), |
| 470 | ah->eep_ops->get_eeprom_rev(ah)); |
Sujith | 7d01b22 | 2009-03-13 08:55:55 +0530 | [diff] [blame] | 471 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 472 | ecode = ath9k_hw_rf_alloc_ext_banks(ah); |
| 473 | if (ecode) { |
| 474 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 475 | "Failed allocating banks for " |
| 476 | "external radio\n"); |
| 477 | return ecode; |
Luis R. Rodriguez | 574d6b1 | 2009-10-19 02:33:37 -0400 | [diff] [blame] | 478 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 479 | |
| 480 | if (!AR_SREV_9100(ah)) { |
| 481 | ath9k_hw_ani_setup(ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 482 | ath9k_hw_ani_init(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 483 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 484 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 485 | return 0; |
| 486 | } |
| 487 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 488 | static void ath9k_hw_attach_ops(struct ath_hw *ah) |
| 489 | { |
| 490 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 491 | ar9003_hw_attach_ops(ah); |
| 492 | else |
| 493 | ar9002_hw_attach_ops(ah); |
| 494 | } |
| 495 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 496 | /* Called for all hardware families */ |
| 497 | static int __ath9k_hw_init(struct ath_hw *ah) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 498 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 499 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 500 | int r = 0; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 501 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 502 | if (ah->hw_version.devid == AR5416_AR9100_DEVID) |
| 503 | ah->hw_version.macVersion = AR_SREV_VERSION_9100; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 504 | |
| 505 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 506 | ath_print(common, ATH_DBG_FATAL, |
| 507 | "Couldn't reset chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 508 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 509 | } |
| 510 | |
Luis R. Rodriguez | bab1f62 | 2010-04-15 17:38:20 -0400 | [diff] [blame] | 511 | ath9k_hw_init_defaults(ah); |
| 512 | ath9k_hw_init_config(ah); |
| 513 | |
Luis R. Rodriguez | 8525f28 | 2010-04-15 17:38:19 -0400 | [diff] [blame] | 514 | ath9k_hw_attach_ops(ah); |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 515 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 516 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 517 | ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 518 | return -EIO; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) { |
| 522 | if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI || |
| 523 | (AR_SREV_9280(ah) && !ah->is_pciexpress)) { |
| 524 | ah->config.serialize_regmode = |
| 525 | SER_REG_MODE_ON; |
| 526 | } else { |
| 527 | ah->config.serialize_regmode = |
| 528 | SER_REG_MODE_OFF; |
| 529 | } |
| 530 | } |
| 531 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 532 | ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n", |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 533 | ah->config.serialize_regmode); |
| 534 | |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 535 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 536 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1; |
| 537 | else |
| 538 | ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD; |
| 539 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 540 | if (!ath9k_hw_macversion_supported(ah)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 541 | ath_print(common, ATH_DBG_FATAL, |
| 542 | "Mac Chip Rev 0x%02x.%x is not supported by " |
| 543 | "this driver\n", ah->hw_version.macVersion, |
| 544 | ah->hw_version.macRev); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 545 | return -EOPNOTSUPP; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 546 | } |
| 547 | |
Luis R. Rodriguez | 0df13da | 2010-04-15 17:38:59 -0400 | [diff] [blame] | 548 | if (AR_SREV_9271(ah) || AR_SREV_9100(ah)) |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 549 | ah->is_pciexpress = false; |
| 550 | |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 551 | ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 552 | ath9k_hw_init_cal_settings(ah); |
| 553 | |
| 554 | ah->ani_function = ATH9K_ANI_ALL; |
Luis R. Rodriguez | 31a0bd3 | 2010-04-15 17:38:22 -0400 | [diff] [blame] | 555 | if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 556 | ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; |
| 557 | |
| 558 | ath9k_hw_init_mode_regs(ah); |
| 559 | |
| 560 | if (ah->is_pciexpress) |
Vivek Natarajan | 93b1b37 | 2009-09-17 09:24:58 +0530 | [diff] [blame] | 561 | ath9k_hw_configpcipowersave(ah, 0, 0); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 562 | else |
| 563 | ath9k_hw_disablepcie(ah); |
| 564 | |
Luis R. Rodriguez | d8f492b | 2010-04-15 17:39:04 -0400 | [diff] [blame] | 565 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 566 | ar9002_hw_cck_chan14_spread(ah); |
Sujith | 193cd45 | 2009-09-18 15:04:07 +0530 | [diff] [blame] | 567 | |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 568 | r = ath9k_hw_post_init(ah); |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 569 | if (r) |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 570 | return r; |
Luis R. Rodriguez | aa4058a | 2009-08-03 12:24:45 -0700 | [diff] [blame] | 571 | |
| 572 | ath9k_hw_init_mode_gain_regs(ah); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 573 | r = ath9k_hw_fill_cap_info(ah); |
| 574 | if (r) |
| 575 | return r; |
| 576 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 577 | r = ath9k_hw_init_macaddr(ah); |
| 578 | if (r) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 579 | ath_print(common, ATH_DBG_FATAL, |
| 580 | "Failed to initialize MAC address\n"); |
Luis R. Rodriguez | 95fafca | 2009-08-03 12:24:54 -0700 | [diff] [blame] | 581 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 582 | } |
| 583 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 584 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 585 | ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 586 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 587 | ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 588 | |
Felix Fietkau | 641d992 | 2010-04-15 17:38:49 -0400 | [diff] [blame] | 589 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 590 | ar9003_hw_set_nf_limits(ah); |
| 591 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 592 | ath9k_init_nfcal_hist_buffer(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 593 | |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 594 | common->state = ATH_HW_INITIALIZED; |
| 595 | |
Luis R. Rodriguez | 4f3acf8 | 2009-08-03 12:24:36 -0700 | [diff] [blame] | 596 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 597 | } |
| 598 | |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 599 | int ath9k_hw_init(struct ath_hw *ah) |
| 600 | { |
| 601 | int ret; |
| 602 | struct ath_common *common = ath9k_hw_common(ah); |
| 603 | |
| 604 | /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */ |
| 605 | switch (ah->hw_version.devid) { |
| 606 | case AR5416_DEVID_PCI: |
| 607 | case AR5416_DEVID_PCIE: |
| 608 | case AR5416_AR9100_DEVID: |
| 609 | case AR9160_DEVID_PCI: |
| 610 | case AR9280_DEVID_PCI: |
| 611 | case AR9280_DEVID_PCIE: |
| 612 | case AR9285_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 613 | case AR9287_DEVID_PCI: |
| 614 | case AR9287_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 615 | case AR2427_DEVID_PCIE: |
Senthil Balasubramanian | db3cc53 | 2010-04-15 17:38:18 -0400 | [diff] [blame] | 616 | case AR9300_DEVID_PCIE: |
Luis R. Rodriguez | d70357d | 2010-04-15 17:38:06 -0400 | [diff] [blame] | 617 | break; |
| 618 | default: |
| 619 | if (common->bus_ops->ath_bus_type == ATH_USB) |
| 620 | break; |
| 621 | ath_print(common, ATH_DBG_FATAL, |
| 622 | "Hardware device ID 0x%04x not supported\n", |
| 623 | ah->hw_version.devid); |
| 624 | return -EOPNOTSUPP; |
| 625 | } |
| 626 | |
| 627 | ret = __ath9k_hw_init(ah); |
| 628 | if (ret) { |
| 629 | ath_print(common, ATH_DBG_FATAL, |
| 630 | "Unable to initialize hardware; " |
| 631 | "initialization status: %d\n", ret); |
| 632 | return ret; |
| 633 | } |
| 634 | |
| 635 | return 0; |
| 636 | } |
| 637 | EXPORT_SYMBOL(ath9k_hw_init); |
| 638 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 639 | static void ath9k_hw_init_qos(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 640 | { |
| 641 | REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); |
| 642 | REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210); |
| 643 | |
| 644 | REG_WRITE(ah, AR_QOS_NO_ACK, |
| 645 | SM(2, AR_QOS_NO_ACK_TWO_BIT) | |
| 646 | SM(5, AR_QOS_NO_ACK_BIT_OFF) | |
| 647 | SM(0, AR_QOS_NO_ACK_BYTE_OFF)); |
| 648 | |
| 649 | REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); |
| 650 | REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); |
| 651 | REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); |
| 652 | REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); |
| 653 | REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); |
| 654 | } |
| 655 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 656 | static void ath9k_hw_init_pll(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 657 | struct ath9k_channel *chan) |
| 658 | { |
Luis R. Rodriguez | 6477396 | 2010-04-15 17:38:17 -0400 | [diff] [blame] | 659 | u32 pll = ath9k_hw_compute_pll_control(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 660 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 661 | REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 662 | |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 663 | /* Switch the core clock for ar9271 to 117Mhz */ |
| 664 | if (AR_SREV_9271(ah)) { |
Sujith | 25e2ab1 | 2010-03-17 14:25:22 +0530 | [diff] [blame] | 665 | udelay(500); |
| 666 | REG_WRITE(ah, 0x50040, 0x304); |
Luis R. Rodriguez | c75724d | 2009-10-19 02:33:34 -0400 | [diff] [blame] | 667 | } |
| 668 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 669 | udelay(RTC_PLL_SETTLE_DELAY); |
| 670 | |
| 671 | REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); |
| 672 | } |
| 673 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 674 | static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 675 | enum nl80211_iftype opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 676 | { |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 677 | u32 imr_reg = AR_IMR_TXERR | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 678 | AR_IMR_TXURN | |
| 679 | AR_IMR_RXERR | |
| 680 | AR_IMR_RXORN | |
| 681 | AR_IMR_BCNMISC; |
| 682 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 683 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 684 | imr_reg |= AR_IMR_RXOK_HP; |
| 685 | if (ah->config.rx_intr_mitigation) |
| 686 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 687 | else |
| 688 | imr_reg |= AR_IMR_RXOK_LP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 689 | |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 690 | } else { |
| 691 | if (ah->config.rx_intr_mitigation) |
| 692 | imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR; |
| 693 | else |
| 694 | imr_reg |= AR_IMR_RXOK; |
| 695 | } |
| 696 | |
| 697 | if (ah->config.tx_intr_mitigation) |
| 698 | imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR; |
| 699 | else |
| 700 | imr_reg |= AR_IMR_TXOK; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 701 | |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 702 | if (opmode == NL80211_IFTYPE_AP) |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 703 | imr_reg |= AR_IMR_MIB; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 704 | |
Pavel Roskin | 152d530 | 2010-03-31 18:05:37 -0400 | [diff] [blame] | 705 | REG_WRITE(ah, AR_IMR, imr_reg); |
Pavel Roskin | 74bad5c | 2010-02-23 18:15:27 -0500 | [diff] [blame] | 706 | ah->imrs2_reg |= AR_IMR_S2_GTT; |
| 707 | REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 708 | |
| 709 | if (!AR_SREV_9100(ah)) { |
| 710 | REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF); |
| 711 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT); |
| 712 | REG_WRITE(ah, AR_INTR_SYNC_MASK, 0); |
| 713 | } |
Vasanthakumar Thiagarajan | 6686024 | 2010-04-15 17:39:07 -0400 | [diff] [blame] | 714 | |
| 715 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 716 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0); |
| 717 | REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0); |
| 718 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0); |
| 719 | REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0); |
| 720 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 721 | } |
| 722 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 723 | static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 724 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 725 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 726 | val = min(val, (u32) 0xFFFF); |
| 727 | REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 728 | } |
| 729 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 730 | static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 731 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 732 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 733 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK)); |
| 734 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val); |
| 735 | } |
| 736 | |
| 737 | static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) |
| 738 | { |
| 739 | u32 val = ath9k_hw_mac_to_clks(ah, us); |
| 740 | val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS)); |
| 741 | REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 742 | } |
| 743 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 744 | static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 745 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 746 | if (tu > 0xFFFF) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 747 | ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT, |
| 748 | "bad global tx timeout %u\n", tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 749 | ah->globaltxtimeout = (u32) -1; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 750 | return false; |
| 751 | } else { |
| 752 | REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 753 | ah->globaltxtimeout = tu; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 754 | return true; |
| 755 | } |
| 756 | } |
| 757 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 758 | void ath9k_hw_init_global_settings(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 759 | { |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 760 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
| 761 | int acktimeout; |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 762 | int slottime; |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 763 | int sifstime; |
| 764 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 765 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n", |
| 766 | ah->misc_mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 767 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 768 | if (ah->misc_mode != 0) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 769 | REG_WRITE(ah, AR_PCU_MISC, |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 770 | REG_READ(ah, AR_PCU_MISC) | ah->misc_mode); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 771 | |
| 772 | if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ) |
| 773 | sifstime = 16; |
| 774 | else |
| 775 | sifstime = 10; |
| 776 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 777 | /* As defined by IEEE 802.11-2007 17.3.8.6 */ |
| 778 | slottime = ah->slottime + 3 * ah->coverage_class; |
| 779 | acktimeout = slottime + sifstime; |
Felix Fietkau | 42c4568 | 2010-02-11 18:07:19 +0100 | [diff] [blame] | 780 | |
| 781 | /* |
| 782 | * Workaround for early ACK timeouts, add an offset to match the |
| 783 | * initval's 64us ack timeout value. |
| 784 | * This was initially only meant to work around an issue with delayed |
| 785 | * BA frames in some implementations, but it has been found to fix ACK |
| 786 | * timeout issues in other cases as well. |
| 787 | */ |
| 788 | if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ) |
| 789 | acktimeout += 64 - sifstime - ah->slottime; |
| 790 | |
Felix Fietkau | e239d85 | 2010-01-15 02:34:58 +0100 | [diff] [blame] | 791 | ath9k_hw_setslottime(ah, slottime); |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 792 | ath9k_hw_set_ack_timeout(ah, acktimeout); |
| 793 | ath9k_hw_set_cts_timeout(ah, acktimeout); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 794 | if (ah->globaltxtimeout != (u32) -1) |
| 795 | ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 796 | } |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 797 | EXPORT_SYMBOL(ath9k_hw_init_global_settings); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 798 | |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 799 | void ath9k_hw_deinit(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 800 | { |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 801 | struct ath_common *common = ath9k_hw_common(ah); |
| 802 | |
Sujith | 736b3a2 | 2010-03-17 14:25:24 +0530 | [diff] [blame] | 803 | if (common->state < ATH_HW_INITIALIZED) |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 804 | goto free_hw; |
| 805 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 806 | if (!AR_SREV_9100(ah)) |
Luis R. Rodriguez | e70c0cf | 2009-08-03 12:24:51 -0700 | [diff] [blame] | 807 | ath9k_hw_ani_disable(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 808 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 809 | ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); |
Luis R. Rodriguez | 211f585 | 2009-10-06 21:19:07 -0400 | [diff] [blame] | 810 | |
| 811 | free_hw: |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 812 | ath9k_hw_rf_free_ext_banks(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 813 | } |
Sujith | 285f2dd | 2010-01-08 10:36:07 +0530 | [diff] [blame] | 814 | EXPORT_SYMBOL(ath9k_hw_deinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 815 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 816 | /*******/ |
| 817 | /* INI */ |
| 818 | /*******/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 819 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 820 | u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan) |
Bob Copeland | 3a702e4 | 2009-03-30 22:30:29 -0400 | [diff] [blame] | 821 | { |
| 822 | u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); |
| 823 | |
| 824 | if (IS_CHAN_B(chan)) |
| 825 | ctl |= CTL_11B; |
| 826 | else if (IS_CHAN_G(chan)) |
| 827 | ctl |= CTL_11G; |
| 828 | else |
| 829 | ctl |= CTL_11A; |
| 830 | |
| 831 | return ctl; |
| 832 | } |
| 833 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 834 | /****************************************/ |
| 835 | /* Reset and Channel Switching Routines */ |
| 836 | /****************************************/ |
| 837 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 838 | static inline void ath9k_hw_set_dma(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 839 | { |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 840 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 841 | u32 regval; |
| 842 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 843 | /* |
| 844 | * set AHB_MODE not to do cacheline prefetches |
| 845 | */ |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 846 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
| 847 | regval = REG_READ(ah, AR_AHB_MODE); |
| 848 | REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN); |
| 849 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 850 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 851 | /* |
| 852 | * let mac dma reads be in 128 byte chunks |
| 853 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 854 | regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK; |
| 855 | REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B); |
| 856 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 857 | /* |
| 858 | * Restore TX Trigger Level to its pre-reset value. |
| 859 | * The initial value depends on whether aggregation is enabled, and is |
| 860 | * adjusted whenever underruns are detected. |
| 861 | */ |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 862 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 863 | REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 864 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 865 | /* |
| 866 | * let mac dma writes be in 128 byte chunks |
| 867 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 868 | regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK; |
| 869 | REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B); |
| 870 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 871 | /* |
| 872 | * Setup receive FIFO threshold to hold off TX activities |
| 873 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 874 | REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); |
| 875 | |
Felix Fietkau | 57b3222 | 2010-04-15 17:39:22 -0400 | [diff] [blame] | 876 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 877 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1); |
| 878 | REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1); |
| 879 | |
| 880 | ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize - |
| 881 | ah->caps.rx_status_len); |
| 882 | } |
| 883 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 884 | /* |
| 885 | * reduce the number of usable entries in PCU TXBUF to avoid |
| 886 | * wrap around issues. |
| 887 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 888 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 889 | /* For AR9285 the number of Fifos are reduced to half. |
| 890 | * So set the usable tx buf size also to half to |
| 891 | * avoid data/delimiter underruns |
| 892 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 893 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 894 | AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 895 | } else if (!AR_SREV_9271(ah)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 896 | REG_WRITE(ah, AR_PCU_TXBUF_CTRL, |
| 897 | AR_PCU_TXBUF_CTRL_USABLE_SIZE); |
| 898 | } |
Vasanthakumar Thiagarajan | 744d402 | 2010-04-15 17:39:27 -0400 | [diff] [blame] | 899 | |
| 900 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 901 | ath9k_hw_reset_txstatus_ring(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 902 | } |
| 903 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 904 | static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 905 | { |
| 906 | u32 val; |
| 907 | |
| 908 | val = REG_READ(ah, AR_STA_ID1); |
| 909 | val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC); |
| 910 | switch (opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 911 | case NL80211_IFTYPE_AP: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 912 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP |
| 913 | | AR_STA_ID1_KSRCH_MODE); |
| 914 | REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 915 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 916 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 917 | case NL80211_IFTYPE_MESH_POINT: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 918 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC |
| 919 | | AR_STA_ID1_KSRCH_MODE); |
| 920 | REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); |
| 921 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 922 | case NL80211_IFTYPE_STATION: |
| 923 | case NL80211_IFTYPE_MONITOR: |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 924 | REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE); |
| 925 | break; |
| 926 | } |
| 927 | } |
| 928 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 929 | void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled, |
| 930 | u32 *coef_mantissa, u32 *coef_exponent) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 931 | { |
| 932 | u32 coef_exp, coef_man; |
| 933 | |
| 934 | for (coef_exp = 31; coef_exp > 0; coef_exp--) |
| 935 | if ((coef_scaled >> coef_exp) & 0x1) |
| 936 | break; |
| 937 | |
| 938 | coef_exp = 14 - (coef_exp - COEF_SCALE_S); |
| 939 | |
| 940 | coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); |
| 941 | |
| 942 | *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); |
| 943 | *coef_exponent = coef_exp - 16; |
| 944 | } |
| 945 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 946 | static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 947 | { |
| 948 | u32 rst_flags; |
| 949 | u32 tmpReg; |
| 950 | |
Sujith | 7076849 | 2009-02-16 13:23:12 +0530 | [diff] [blame] | 951 | if (AR_SREV_9100(ah)) { |
| 952 | u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 953 | val &= ~AR_RTC_DERIVED_CLK_PERIOD; |
| 954 | val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD); |
| 955 | REG_WRITE(ah, AR_RTC_DERIVED_CLK, val); |
| 956 | (void)REG_READ(ah, AR_RTC_DERIVED_CLK); |
| 957 | } |
| 958 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 959 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 960 | AR_RTC_FORCE_WAKE_ON_INT); |
| 961 | |
| 962 | if (AR_SREV_9100(ah)) { |
| 963 | rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD | |
| 964 | AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET; |
| 965 | } else { |
| 966 | tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); |
| 967 | if (tmpReg & |
| 968 | (AR_INTR_SYNC_LOCAL_TIMEOUT | |
| 969 | AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 970 | u32 val; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 971 | REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 972 | |
| 973 | val = AR_RC_HOSTIF; |
| 974 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 975 | val |= AR_RC_AHB; |
| 976 | REG_WRITE(ah, AR_RC, val); |
| 977 | |
| 978 | } else if (!AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 979 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 980 | |
| 981 | rst_flags = AR_RTC_RC_MAC_WARM; |
| 982 | if (type == ATH9K_RESET_COLD) |
| 983 | rst_flags |= AR_RTC_RC_MAC_COLD; |
| 984 | } |
| 985 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 986 | REG_WRITE(ah, AR_RTC_RC, rst_flags); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 987 | udelay(50); |
| 988 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 989 | REG_WRITE(ah, AR_RTC_RC, 0); |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 990 | if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 991 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 992 | "RTC stuck in MAC reset\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 993 | return false; |
| 994 | } |
| 995 | |
| 996 | if (!AR_SREV_9100(ah)) |
| 997 | REG_WRITE(ah, AR_RC, 0); |
| 998 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 999 | if (AR_SREV_9100(ah)) |
| 1000 | udelay(50); |
| 1001 | |
| 1002 | return true; |
| 1003 | } |
| 1004 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1005 | static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1006 | { |
| 1007 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN | |
| 1008 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1009 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1010 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1011 | REG_WRITE(ah, AR_RC, AR_RC_AHB); |
| 1012 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1013 | REG_WRITE(ah, AR_RTC_RESET, 0); |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1014 | |
Senthil Balasubramanian | 84e2169 | 2010-04-15 17:38:30 -0400 | [diff] [blame] | 1015 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1016 | udelay(2); |
| 1017 | |
| 1018 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Vasanthakumar Thiagarajan | 1c29ce6 | 2009-08-31 17:48:36 +0530 | [diff] [blame] | 1019 | REG_WRITE(ah, AR_RC, 0); |
| 1020 | |
Gabor Juhos | d03a66c | 2009-01-14 20:17:09 +0100 | [diff] [blame] | 1021 | REG_WRITE(ah, AR_RTC_RESET, 1); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1022 | |
| 1023 | if (!ath9k_hw_wait(ah, |
| 1024 | AR_RTC_STATUS, |
| 1025 | AR_RTC_STATUS_M, |
Sujith | 0caa7b1 | 2009-02-16 13:23:20 +0530 | [diff] [blame] | 1026 | AR_RTC_STATUS_ON, |
| 1027 | AH_WAIT_TIMEOUT)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1028 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 1029 | "RTC not waking up\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1030 | return false; |
| 1031 | } |
| 1032 | |
| 1033 | ath9k_hw_read_revisions(ah); |
| 1034 | |
| 1035 | return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM); |
| 1036 | } |
| 1037 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1038 | static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1039 | { |
| 1040 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1041 | AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); |
| 1042 | |
| 1043 | switch (type) { |
| 1044 | case ATH9K_RESET_POWER_ON: |
| 1045 | return ath9k_hw_set_reset_power_on(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1046 | case ATH9K_RESET_WARM: |
| 1047 | case ATH9K_RESET_COLD: |
| 1048 | return ath9k_hw_set_reset(ah, type); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1049 | default: |
| 1050 | return false; |
| 1051 | } |
| 1052 | } |
| 1053 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1054 | static bool ath9k_hw_chip_reset(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1055 | struct ath9k_channel *chan) |
| 1056 | { |
Vivek Natarajan | 42abfbe | 2009-09-17 09:27:59 +0530 | [diff] [blame] | 1057 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) { |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 1058 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) |
| 1059 | return false; |
| 1060 | } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1061 | return false; |
| 1062 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1063 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1064 | return false; |
| 1065 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1066 | ah->chip_fullsleep = false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1067 | ath9k_hw_init_pll(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1068 | ath9k_hw_set_rfmode(ah, chan); |
| 1069 | |
| 1070 | return true; |
| 1071 | } |
| 1072 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1073 | static bool ath9k_hw_channel_change(struct ath_hw *ah, |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1074 | struct ath9k_channel *chan) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1075 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1076 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1077 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 1078 | struct ieee80211_channel *channel = chan->chan; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1079 | u32 qnum; |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1080 | int r; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1081 | |
| 1082 | for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { |
| 1083 | if (ath9k_hw_numtxpending(ah, qnum)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1084 | ath_print(common, ATH_DBG_QUEUE, |
| 1085 | "Transmit frames pending on " |
| 1086 | "queue %d\n", qnum); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1087 | return false; |
| 1088 | } |
| 1089 | } |
| 1090 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1091 | if (!ath9k_hw_rfbus_req(ah)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1092 | ath_print(common, ATH_DBG_FATAL, |
| 1093 | "Could not kill baseband RX\n"); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1094 | return false; |
| 1095 | } |
| 1096 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1097 | ath9k_hw_set_channel_regs(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1098 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1099 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1100 | if (r) { |
| 1101 | ath_print(common, ATH_DBG_FATAL, |
| 1102 | "Failed to set channel\n"); |
| 1103 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1104 | } |
| 1105 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 1106 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1107 | ath9k_regd_get_ctl(regulatory, chan), |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1108 | channel->max_antenna_gain * 2, |
| 1109 | channel->max_power * 2, |
| 1110 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1111 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1112 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1113 | ath9k_hw_rfbus_done(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1114 | |
| 1115 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1116 | ath9k_hw_set_delta_slope(ah, chan); |
| 1117 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1118 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1119 | |
| 1120 | if (!chan->oneTimeCalsDone) |
| 1121 | chan->oneTimeCalsDone = true; |
| 1122 | |
| 1123 | return true; |
| 1124 | } |
| 1125 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1126 | int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1127 | bool bChannelChange) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1128 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1129 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1130 | u32 saveLedState; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1131 | struct ath9k_channel *curchan = ah->curchan; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1132 | u32 saveDefAntenna; |
| 1133 | u32 macStaId1; |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1134 | u64 tsf = 0; |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1135 | int i, r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1136 | |
Luis R. Rodriguez | 43c2761 | 2009-09-13 21:07:07 -0700 | [diff] [blame] | 1137 | ah->txchainmask = common->tx_chainmask; |
| 1138 | ah->rxchainmask = common->rx_chainmask; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1139 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1140 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1141 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1142 | |
Vasanthakumar Thiagarajan | 9ebef799 | 2009-09-17 09:26:44 +0530 | [diff] [blame] | 1143 | if (curchan && !ah->chip_fullsleep) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1144 | ath9k_hw_getnf(ah, curchan); |
| 1145 | |
| 1146 | if (bChannelChange && |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1147 | (ah->chip_fullsleep != true) && |
| 1148 | (ah->curchan != NULL) && |
| 1149 | (chan->channel != ah->curchan->channel) && |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1150 | ((chan->channelFlags & CHANNEL_ALL) == |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1151 | (ah->curchan->channelFlags & CHANNEL_ALL)) && |
Vasanthakumar Thiagarajan | 0a475cc | 2009-09-17 09:27:10 +0530 | [diff] [blame] | 1152 | !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) || |
| 1153 | IS_CHAN_A_5MHZ_SPACED(ah->curchan))) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1154 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1155 | if (ath9k_hw_channel_change(ah, chan)) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1156 | ath9k_hw_loadnf(ah, ah->curchan); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1157 | ath9k_hw_start_nfcal(ah); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1158 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1159 | } |
| 1160 | } |
| 1161 | |
| 1162 | saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); |
| 1163 | if (saveDefAntenna == 0) |
| 1164 | saveDefAntenna = 1; |
| 1165 | |
| 1166 | macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; |
| 1167 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1168 | /* For chips on which RTC reset is done, save TSF before it gets cleared */ |
| 1169 | if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 1170 | tsf = ath9k_hw_gettsf64(ah); |
| 1171 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1172 | saveLedState = REG_READ(ah, AR_CFG_LED) & |
| 1173 | (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL | |
| 1174 | AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW); |
| 1175 | |
| 1176 | ath9k_hw_mark_phy_inactive(ah); |
| 1177 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1178 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1179 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1180 | REG_WRITE(ah, |
| 1181 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1182 | AR9271_RADIO_RF_RST); |
| 1183 | udelay(50); |
| 1184 | } |
| 1185 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1186 | if (!ath9k_hw_chip_reset(ah, chan)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1187 | ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n"); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1188 | return -EINVAL; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1189 | } |
| 1190 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 1191 | /* Only required on the first reset */ |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1192 | if (AR_SREV_9271(ah) && ah->htc_reset_init) { |
| 1193 | ah->htc_reset_init = false; |
| 1194 | REG_WRITE(ah, |
| 1195 | AR9271_RESET_POWER_DOWN_CONTROL, |
| 1196 | AR9271_GATE_MAC_CTL); |
| 1197 | udelay(50); |
| 1198 | } |
| 1199 | |
Sujith | 46fe782 | 2009-09-17 09:25:25 +0530 | [diff] [blame] | 1200 | /* Restore TSF */ |
| 1201 | if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) |
| 1202 | ath9k_hw_settsf64(ah, tsf); |
| 1203 | |
Vasanthakumar Thiagarajan | 369391d | 2009-01-21 19:24:13 +0530 | [diff] [blame] | 1204 | if (AR_SREV_9280_10_OR_LATER(ah)) |
| 1205 | REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1206 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 1207 | r = ath9k_hw_process_ini(ah, chan); |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1208 | if (r) |
| 1209 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1210 | |
Jouni Malinen | 0ced0e1 | 2009-01-08 13:32:13 +0200 | [diff] [blame] | 1211 | /* Setup MFP options for CCMP */ |
| 1212 | if (AR_SREV_9280_20_OR_LATER(ah)) { |
| 1213 | /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt |
| 1214 | * frames when constructing CCMP AAD. */ |
| 1215 | REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT, |
| 1216 | 0xc7ff); |
| 1217 | ah->sw_mgmt_crypto = false; |
| 1218 | } else if (AR_SREV_9160_10_OR_LATER(ah)) { |
| 1219 | /* Disable hardware crypto for management frames */ |
| 1220 | REG_CLR_BIT(ah, AR_PCU_MISC_MODE2, |
| 1221 | AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE); |
| 1222 | REG_SET_BIT(ah, AR_PCU_MISC_MODE2, |
| 1223 | AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT); |
| 1224 | ah->sw_mgmt_crypto = true; |
| 1225 | } else |
| 1226 | ah->sw_mgmt_crypto = true; |
| 1227 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1228 | if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) |
| 1229 | ath9k_hw_set_delta_slope(ah, chan); |
| 1230 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1231 | ath9k_hw_spur_mitigate_freq(ah, chan); |
Sujith | d650915 | 2009-03-13 08:56:05 +0530 | [diff] [blame] | 1232 | ah->eep_ops->set_board_values(ah, chan); |
Luis R. Rodriguez | a776582 | 2009-10-19 02:33:45 -0400 | [diff] [blame] | 1233 | |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 1234 | REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); |
| 1235 | REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1236 | | macStaId1 |
| 1237 | | AR_STA_ID1_RTS_USE_DEF |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1238 | | (ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1239 | ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1240 | | ah->sta_id1_defaults); |
| 1241 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1242 | |
Luis R. Rodriguez | 13b8155 | 2009-09-10 17:52:45 -0700 | [diff] [blame] | 1243 | ath_hw_setbssidmask(common); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1244 | |
| 1245 | REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); |
| 1246 | |
Luis R. Rodriguez | 3453ad8 | 2009-09-10 08:57:00 -0700 | [diff] [blame] | 1247 | ath9k_hw_write_associd(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1248 | |
| 1249 | REG_WRITE(ah, AR_ISR, ~0); |
| 1250 | |
| 1251 | REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); |
| 1252 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1253 | r = ath9k_hw_rf_set_freq(ah, chan); |
Luis R. Rodriguez | 0a3b7ba | 2009-10-19 02:33:40 -0400 | [diff] [blame] | 1254 | if (r) |
| 1255 | return r; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1256 | |
| 1257 | for (i = 0; i < AR_NUM_DCU; i++) |
| 1258 | REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); |
| 1259 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1260 | ah->intr_txqs = 0; |
| 1261 | for (i = 0; i < ah->caps.total_queues; i++) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1262 | ath9k_hw_resettxqueue(ah, i); |
| 1263 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1264 | ath9k_hw_init_interrupt_masks(ah, ah->opmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1265 | ath9k_hw_init_qos(ah); |
| 1266 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1267 | if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT) |
Vasanthakumar Thiagarajan | 500c064 | 2008-09-10 18:50:17 +0530 | [diff] [blame] | 1268 | ath9k_enable_rfkill(ah); |
Johannes Berg | 3b319aa | 2009-06-13 14:50:26 +0530 | [diff] [blame] | 1269 | |
Felix Fietkau | 0005baf | 2010-01-15 02:33:40 +0100 | [diff] [blame] | 1270 | ath9k_hw_init_global_settings(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1271 | |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1272 | if (!AR_SREV_9300_20_OR_LATER(ah)) { |
Luis R. Rodriguez | 78ec267 | 2010-04-15 17:39:23 -0400 | [diff] [blame] | 1273 | ar9002_hw_enable_async_fifo(ah); |
Luis R. Rodriguez | 6c94fdc | 2010-04-15 17:39:24 -0400 | [diff] [blame] | 1274 | ar9002_hw_enable_wep_aggregation(ah); |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 1275 | } |
| 1276 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1277 | REG_WRITE(ah, AR_STA_ID1, |
| 1278 | REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); |
| 1279 | |
| 1280 | ath9k_hw_set_dma(ah); |
| 1281 | |
| 1282 | REG_WRITE(ah, AR_OBS, 8); |
| 1283 | |
Sujith | 0ce024c | 2009-12-14 14:57:00 +0530 | [diff] [blame] | 1284 | if (ah->config.rx_intr_mitigation) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1285 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); |
| 1286 | REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); |
| 1287 | } |
| 1288 | |
Vasanthakumar Thiagarajan | 7f62a13 | 2010-04-15 17:39:19 -0400 | [diff] [blame] | 1289 | if (ah->config.tx_intr_mitigation) { |
| 1290 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300); |
| 1291 | REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750); |
| 1292 | } |
| 1293 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1294 | ath9k_hw_init_bb(ah, chan); |
| 1295 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1296 | if (!ath9k_hw_init_cal(ah, chan)) |
Joe Perches | 6badaaf | 2009-06-28 09:26:32 -0700 | [diff] [blame] | 1297 | return -EIO; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1298 | |
Luis R. Rodriguez | 8fe6536 | 2010-04-15 17:38:14 -0400 | [diff] [blame] | 1299 | ath9k_hw_restore_chainmask(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1300 | REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); |
| 1301 | |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1302 | /* |
| 1303 | * For big endian systems turn on swapping for descriptors |
| 1304 | */ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1305 | if (AR_SREV_9100(ah)) { |
| 1306 | u32 mask; |
| 1307 | mask = REG_READ(ah, AR_CFG); |
| 1308 | if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1309 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd4638 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1310 | "CFG Byte Swap Set 0x%x\n", mask); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1311 | } else { |
| 1312 | mask = |
| 1313 | INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; |
| 1314 | REG_WRITE(ah, AR_CFG, mask); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1315 | ath_print(common, ATH_DBG_RESET, |
Sujith | 04bd4638 | 2008-11-28 22:18:05 +0530 | [diff] [blame] | 1316 | "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1317 | } |
| 1318 | } else { |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1319 | /* Configure AR9271 target WLAN */ |
| 1320 | if (AR_SREV_9271(ah)) |
| 1321 | REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1322 | #ifdef __BIG_ENDIAN |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1323 | else |
| 1324 | REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1325 | #endif |
| 1326 | } |
| 1327 | |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1328 | if (ah->btcoex_hw.enabled) |
Vasanthakumar Thiagarajan | 42cc41e | 2009-08-26 21:08:45 +0530 | [diff] [blame] | 1329 | ath9k_hw_btcoex_enable(ah); |
| 1330 | |
Vasanthakumar Thiagarajan | d8903a5 | 2010-04-15 17:39:25 -0400 | [diff] [blame] | 1331 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
| 1332 | ath9k_hw_loadnf(ah, curchan); |
| 1333 | ath9k_hw_start_nfcal(ah); |
| 1334 | } |
| 1335 | |
Luis R. Rodriguez | ae8d285 | 2008-12-23 15:58:40 -0800 | [diff] [blame] | 1336 | return 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1337 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1338 | EXPORT_SYMBOL(ath9k_hw_reset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1339 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1340 | /************************/ |
| 1341 | /* Key Cache Management */ |
| 1342 | /************************/ |
| 1343 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1344 | bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1345 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1346 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1347 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1348 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1349 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1350 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1351 | return false; |
| 1352 | } |
| 1353 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1354 | keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1355 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1356 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); |
| 1357 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); |
| 1358 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); |
| 1359 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); |
| 1360 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); |
| 1361 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); |
| 1362 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); |
| 1363 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); |
| 1364 | |
| 1365 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 1366 | u16 micentry = entry + 64; |
| 1367 | |
| 1368 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0); |
| 1369 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
| 1370 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0); |
| 1371 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
| 1372 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1373 | } |
| 1374 | |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1375 | return true; |
| 1376 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1377 | EXPORT_SYMBOL(ath9k_hw_keyreset); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1378 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1379 | bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1380 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1381 | u32 macHi, macLo; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1382 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1383 | if (entry >= ah->caps.keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1384 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1385 | "keychache entry %u out of range\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1386 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1387 | } |
| 1388 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1389 | if (mac != NULL) { |
| 1390 | macHi = (mac[5] << 8) | mac[4]; |
| 1391 | macLo = (mac[3] << 24) | |
| 1392 | (mac[2] << 16) | |
| 1393 | (mac[1] << 8) | |
| 1394 | mac[0]; |
| 1395 | macLo >>= 1; |
| 1396 | macLo |= (macHi & 1) << 31; |
| 1397 | macHi >>= 1; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1398 | } else { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1399 | macLo = macHi = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1400 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1401 | REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo); |
| 1402 | REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1403 | |
| 1404 | return true; |
| 1405 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1406 | EXPORT_SYMBOL(ath9k_hw_keysetmac); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1407 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1408 | bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1409 | const struct ath9k_keyval *k, |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 1410 | const u8 *mac) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1411 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1412 | const struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1413 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1414 | u32 key0, key1, key2, key3, key4; |
| 1415 | u32 keyType; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1416 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1417 | if (entry >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1418 | ath_print(common, ATH_DBG_FATAL, |
| 1419 | "keycache entry %u out of range\n", entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1420 | return false; |
| 1421 | } |
| 1422 | |
| 1423 | switch (k->kv_type) { |
| 1424 | case ATH9K_CIPHER_AES_OCB: |
| 1425 | keyType = AR_KEYTABLE_TYPE_AES; |
| 1426 | break; |
| 1427 | case ATH9K_CIPHER_AES_CCM: |
| 1428 | if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1429 | ath_print(common, ATH_DBG_ANY, |
| 1430 | "AES-CCM not supported by mac rev 0x%x\n", |
| 1431 | ah->hw_version.macRev); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1432 | return false; |
| 1433 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1434 | keyType = AR_KEYTABLE_TYPE_CCM; |
| 1435 | break; |
| 1436 | case ATH9K_CIPHER_TKIP: |
| 1437 | keyType = AR_KEYTABLE_TYPE_TKIP; |
| 1438 | if (ATH9K_IS_MIC_ENABLED(ah) |
| 1439 | && entry + 64 >= pCap->keycache_size) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1440 | ath_print(common, ATH_DBG_ANY, |
| 1441 | "entry %u inappropriate for TKIP\n", entry); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1442 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1443 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1444 | break; |
| 1445 | case ATH9K_CIPHER_WEP: |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1446 | if (k->kv_len < WLAN_KEY_LEN_WEP40) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1447 | ath_print(common, ATH_DBG_ANY, |
| 1448 | "WEP key length %u too small\n", k->kv_len); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1449 | return false; |
| 1450 | } |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1451 | if (k->kv_len <= WLAN_KEY_LEN_WEP40) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1452 | keyType = AR_KEYTABLE_TYPE_40; |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1453 | else if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1454 | keyType = AR_KEYTABLE_TYPE_104; |
| 1455 | else |
| 1456 | keyType = AR_KEYTABLE_TYPE_128; |
| 1457 | break; |
| 1458 | case ATH9K_CIPHER_CLR: |
| 1459 | keyType = AR_KEYTABLE_TYPE_CLR; |
| 1460 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1461 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1462 | ath_print(common, ATH_DBG_FATAL, |
| 1463 | "cipher %u not supported\n", k->kv_type); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1464 | return false; |
| 1465 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1466 | |
Jouni Malinen | e0caf9e | 2009-03-02 18:15:53 +0200 | [diff] [blame] | 1467 | key0 = get_unaligned_le32(k->kv_val + 0); |
| 1468 | key1 = get_unaligned_le16(k->kv_val + 4); |
| 1469 | key2 = get_unaligned_le32(k->kv_val + 6); |
| 1470 | key3 = get_unaligned_le16(k->kv_val + 10); |
| 1471 | key4 = get_unaligned_le32(k->kv_val + 12); |
Zhu Yi | e31a16d | 2009-05-21 21:47:03 +0800 | [diff] [blame] | 1472 | if (k->kv_len <= WLAN_KEY_LEN_WEP104) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1473 | key4 &= 0xff; |
| 1474 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1475 | /* |
| 1476 | * Note: Key cache registers access special memory area that requires |
| 1477 | * two 32-bit writes to actually update the values in the internal |
| 1478 | * memory. Consequently, the exact order and pairs used here must be |
| 1479 | * maintained. |
| 1480 | */ |
| 1481 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1482 | if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) { |
| 1483 | u16 micentry = entry + 64; |
| 1484 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1485 | /* |
| 1486 | * Write inverted key[47:0] first to avoid Michael MIC errors |
| 1487 | * on frames that could be sent or received at the same time. |
| 1488 | * The correct key will be written in the end once everything |
| 1489 | * else is ready. |
| 1490 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1491 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0); |
| 1492 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1493 | |
| 1494 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1495 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 1496 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1497 | |
| 1498 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1499 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 1500 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1501 | |
| 1502 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1503 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 1504 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1505 | if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1506 | /* |
| 1507 | * TKIP uses two key cache entries: |
| 1508 | * Michael MIC TX/RX keys in the same key cache entry |
| 1509 | * (idx = main index + 64): |
| 1510 | * key0 [31:0] = RX key [31:0] |
| 1511 | * key1 [15:0] = TX key [31:16] |
| 1512 | * key1 [31:16] = reserved |
| 1513 | * key2 [31:0] = RX key [63:32] |
| 1514 | * key3 [15:0] = TX key [15:0] |
| 1515 | * key3 [31:16] = reserved |
| 1516 | * key4 [31:0] = TX key [63:32] |
| 1517 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1518 | u32 mic0, mic1, mic2, mic3, mic4; |
| 1519 | |
| 1520 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 1521 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
| 1522 | mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff; |
| 1523 | mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff; |
| 1524 | mic4 = get_unaligned_le32(k->kv_txmic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1525 | |
| 1526 | /* Write RX[31:0] and TX[31:16] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1527 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 1528 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1529 | |
| 1530 | /* Write RX[63:32] and TX[15:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1531 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 1532 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1533 | |
| 1534 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1535 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4); |
| 1536 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 1537 | AR_KEYTABLE_TYPE_CLR); |
| 1538 | |
| 1539 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1540 | /* |
| 1541 | * TKIP uses four key cache entries (two for group |
| 1542 | * keys): |
| 1543 | * Michael MIC TX/RX keys are in different key cache |
| 1544 | * entries (idx = main index + 64 for TX and |
| 1545 | * main index + 32 + 96 for RX): |
| 1546 | * key0 [31:0] = TX/RX MIC key [31:0] |
| 1547 | * key1 [31:0] = reserved |
| 1548 | * key2 [31:0] = TX/RX MIC key [63:32] |
| 1549 | * key3 [31:0] = reserved |
| 1550 | * key4 [31:0] = reserved |
| 1551 | * |
| 1552 | * Upper layer code will call this function separately |
| 1553 | * for TX and RX keys when these registers offsets are |
| 1554 | * used. |
| 1555 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1556 | u32 mic0, mic2; |
| 1557 | |
| 1558 | mic0 = get_unaligned_le32(k->kv_mic + 0); |
| 1559 | mic2 = get_unaligned_le32(k->kv_mic + 4); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1560 | |
| 1561 | /* Write MIC key[31:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1562 | REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0); |
| 1563 | REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1564 | |
| 1565 | /* Write MIC key[63:32] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1566 | REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2); |
| 1567 | REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1568 | |
| 1569 | /* Write TX[63:32] and keyType(reserved) */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1570 | REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0); |
| 1571 | REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry), |
| 1572 | AR_KEYTABLE_TYPE_CLR); |
| 1573 | } |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1574 | |
| 1575 | /* MAC address registers are reserved for the MIC entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1576 | REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0); |
| 1577 | REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1578 | |
| 1579 | /* |
| 1580 | * Write the correct (un-inverted) key[47:0] last to enable |
| 1581 | * TKIP now that all other registers are set with correct |
| 1582 | * values. |
| 1583 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1584 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 1585 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
| 1586 | } else { |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1587 | /* Write key[47:0] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1588 | REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0); |
| 1589 | REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1590 | |
| 1591 | /* Write key[95:48] */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1592 | REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2); |
| 1593 | REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3); |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1594 | |
| 1595 | /* Write key[127:96] and key type */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1596 | REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4); |
| 1597 | REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType); |
| 1598 | |
Jouni Malinen | 672903b | 2009-03-02 15:06:31 +0200 | [diff] [blame] | 1599 | /* Write MAC address for the entry */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1600 | (void) ath9k_hw_keysetmac(ah, entry, mac); |
| 1601 | } |
| 1602 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1603 | return true; |
| 1604 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1605 | EXPORT_SYMBOL(ath9k_hw_set_keycache_entry); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1606 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1607 | bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1608 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1609 | if (entry < ah->caps.keycache_size) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1610 | u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry)); |
| 1611 | if (val & AR_KEYTABLE_VALID) |
| 1612 | return true; |
| 1613 | } |
| 1614 | return false; |
| 1615 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1616 | EXPORT_SYMBOL(ath9k_hw_keyisvalid); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1617 | |
| 1618 | /******************************/ |
| 1619 | /* Power Management (Chipset) */ |
| 1620 | /******************************/ |
| 1621 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1622 | /* |
| 1623 | * Notify Power Mgt is disabled in self-generated frames. |
| 1624 | * If requested, force chip to sleep. |
| 1625 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1626 | static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1627 | { |
| 1628 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1629 | if (setChip) { |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1630 | /* |
| 1631 | * Clear the RTC force wake bit to allow the |
| 1632 | * mac to go to sleep. |
| 1633 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1634 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1635 | AR_RTC_FORCE_WAKE_EN); |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1636 | if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1637 | REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF); |
| 1638 | |
Luis R. Rodriguez | 42d5bc3 | 2010-04-15 17:38:12 -0400 | [diff] [blame] | 1639 | /* Shutdown chip. Active low */ |
Sujith | 14b3af3 | 2010-03-17 14:25:18 +0530 | [diff] [blame] | 1640 | if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) |
Sujith | 4921be8 | 2009-09-18 15:04:27 +0530 | [diff] [blame] | 1641 | REG_CLR_BIT(ah, (AR_RTC_RESET), |
| 1642 | AR_RTC_RESET_EN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1643 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1644 | } |
| 1645 | |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1646 | /* |
| 1647 | * Notify Power Management is enabled in self-generating |
| 1648 | * frames. If request, set power mode of chip to |
| 1649 | * auto/normal. Duration in units of 128us (1/8 TU). |
| 1650 | */ |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1651 | static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1652 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1653 | REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1654 | if (setChip) { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1655 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1656 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1657 | if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1658 | /* Set WakeOnInterrupt bit; clear ForceWake bit */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1659 | REG_WRITE(ah, AR_RTC_FORCE_WAKE, |
| 1660 | AR_RTC_FORCE_WAKE_ON_INT); |
| 1661 | } else { |
Luis R. Rodriguez | bbd79af | 2010-04-15 17:38:16 -0400 | [diff] [blame] | 1662 | /* |
| 1663 | * Clear the RTC force wake bit to allow the |
| 1664 | * mac to go to sleep. |
| 1665 | */ |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1666 | REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1667 | AR_RTC_FORCE_WAKE_EN); |
| 1668 | } |
| 1669 | } |
| 1670 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1671 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1672 | static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1673 | { |
| 1674 | u32 val; |
| 1675 | int i; |
| 1676 | |
| 1677 | if (setChip) { |
| 1678 | if ((REG_READ(ah, AR_RTC_STATUS) & |
| 1679 | AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) { |
| 1680 | if (ath9k_hw_set_reset_reg(ah, |
| 1681 | ATH9K_RESET_POWER_ON) != true) { |
| 1682 | return false; |
| 1683 | } |
Luis R. Rodriguez | e041228 | 2010-04-15 17:38:15 -0400 | [diff] [blame] | 1684 | if (!AR_SREV_9300_20_OR_LATER(ah)) |
| 1685 | ath9k_hw_init_pll(ah, NULL); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1686 | } |
| 1687 | if (AR_SREV_9100(ah)) |
| 1688 | REG_SET_BIT(ah, AR_RTC_RESET, |
| 1689 | AR_RTC_RESET_EN); |
| 1690 | |
| 1691 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1692 | AR_RTC_FORCE_WAKE_EN); |
| 1693 | udelay(50); |
| 1694 | |
| 1695 | for (i = POWER_UP_TIME / 50; i > 0; i--) { |
| 1696 | val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; |
| 1697 | if (val == AR_RTC_STATUS_ON) |
| 1698 | break; |
| 1699 | udelay(50); |
| 1700 | REG_SET_BIT(ah, AR_RTC_FORCE_WAKE, |
| 1701 | AR_RTC_FORCE_WAKE_EN); |
| 1702 | } |
| 1703 | if (i == 0) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1704 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 1705 | "Failed to wakeup in %uus\n", |
| 1706 | POWER_UP_TIME / 20); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1707 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1708 | } |
| 1709 | } |
| 1710 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1711 | REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); |
| 1712 | |
| 1713 | return true; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1714 | } |
| 1715 | |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 1716 | bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1717 | { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1718 | struct ath_common *common = ath9k_hw_common(ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1719 | int status = true, setChip = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1720 | static const char *modes[] = { |
| 1721 | "AWAKE", |
| 1722 | "FULL-SLEEP", |
| 1723 | "NETWORK SLEEP", |
| 1724 | "UNDEFINED" |
| 1725 | }; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1726 | |
Gabor Juhos | cbdec97 | 2009-07-24 17:27:22 +0200 | [diff] [blame] | 1727 | if (ah->power_mode == mode) |
| 1728 | return status; |
| 1729 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1730 | ath_print(common, ATH_DBG_RESET, "%s -> %s\n", |
| 1731 | modes[ah->power_mode], modes[mode]); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1732 | |
| 1733 | switch (mode) { |
| 1734 | case ATH9K_PM_AWAKE: |
| 1735 | status = ath9k_hw_set_power_awake(ah, setChip); |
| 1736 | break; |
| 1737 | case ATH9K_PM_FULL_SLEEP: |
| 1738 | ath9k_set_power_sleep(ah, setChip); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1739 | ah->chip_fullsleep = true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1740 | break; |
| 1741 | case ATH9K_PM_NETWORK_SLEEP: |
| 1742 | ath9k_set_power_network_sleep(ah, setChip); |
| 1743 | break; |
| 1744 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1745 | ath_print(common, ATH_DBG_FATAL, |
| 1746 | "Unknown power mode %u\n", mode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1747 | return false; |
| 1748 | } |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1749 | ah->power_mode = mode; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1750 | |
| 1751 | return status; |
| 1752 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1753 | EXPORT_SYMBOL(ath9k_hw_setpower); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1754 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1755 | /*******************/ |
| 1756 | /* Beacon Handling */ |
| 1757 | /*******************/ |
| 1758 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1759 | void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1760 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1761 | int flags = 0; |
| 1762 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1763 | ah->beacon_interval = beacon_period; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1764 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1765 | switch (ah->opmode) { |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1766 | case NL80211_IFTYPE_STATION: |
| 1767 | case NL80211_IFTYPE_MONITOR: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1768 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 1769 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff); |
| 1770 | REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff); |
| 1771 | flags |= AR_TBTT_TIMER_EN; |
| 1772 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1773 | case NL80211_IFTYPE_ADHOC: |
Pat Erley | 9cb5412 | 2009-03-20 22:59:59 -0400 | [diff] [blame] | 1774 | case NL80211_IFTYPE_MESH_POINT: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1775 | REG_SET_BIT(ah, AR_TXCFG, |
| 1776 | AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY); |
| 1777 | REG_WRITE(ah, AR_NEXT_NDP_TIMER, |
| 1778 | TU_TO_USEC(next_beacon + |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1779 | (ah->atim_window ? ah-> |
| 1780 | atim_window : 1))); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1781 | flags |= AR_NDP_TIMER_EN; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1782 | case NL80211_IFTYPE_AP: |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1783 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon)); |
| 1784 | REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, |
| 1785 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1786 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1787 | dma_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1788 | REG_WRITE(ah, AR_NEXT_SWBA, |
| 1789 | TU_TO_USEC(next_beacon - |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1790 | ah->config. |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1791 | sw_beacon_response_time)); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1792 | flags |= |
| 1793 | AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; |
| 1794 | break; |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1795 | default: |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1796 | ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON, |
| 1797 | "%s: unsupported opmode: %d\n", |
| 1798 | __func__, ah->opmode); |
Colin McCabe | d97809d | 2008-12-01 13:38:55 -0800 | [diff] [blame] | 1799 | return; |
| 1800 | break; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1801 | } |
| 1802 | |
| 1803 | REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 1804 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period)); |
| 1805 | REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period)); |
| 1806 | REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period)); |
| 1807 | |
| 1808 | beacon_period &= ~ATH9K_BEACON_ENA; |
| 1809 | if (beacon_period & ATH9K_BEACON_RESET_TSF) { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1810 | ath9k_hw_reset_tsf(ah); |
| 1811 | } |
| 1812 | |
| 1813 | REG_SET_BIT(ah, AR_TIMER_MODE, flags); |
| 1814 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1815 | EXPORT_SYMBOL(ath9k_hw_beaconinit); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1816 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 1817 | void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1818 | const struct ath9k_beacon_state *bs) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1819 | { |
| 1820 | u32 nextTbtt, beaconintval, dtimperiod, beacontimeout; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1821 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1822 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1823 | |
| 1824 | REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt)); |
| 1825 | |
| 1826 | REG_WRITE(ah, AR_BEACON_PERIOD, |
| 1827 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1828 | REG_WRITE(ah, AR_DMA_BEACON_PERIOD, |
| 1829 | TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD)); |
| 1830 | |
| 1831 | REG_RMW_FIELD(ah, AR_RSSI_THR, |
| 1832 | AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold); |
| 1833 | |
| 1834 | beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD; |
| 1835 | |
| 1836 | if (bs->bs_sleepduration > beaconintval) |
| 1837 | beaconintval = bs->bs_sleepduration; |
| 1838 | |
| 1839 | dtimperiod = bs->bs_dtimperiod; |
| 1840 | if (bs->bs_sleepduration > dtimperiod) |
| 1841 | dtimperiod = bs->bs_sleepduration; |
| 1842 | |
| 1843 | if (beaconintval == dtimperiod) |
| 1844 | nextTbtt = bs->bs_nextdtim; |
| 1845 | else |
| 1846 | nextTbtt = bs->bs_nexttbtt; |
| 1847 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1848 | ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); |
| 1849 | ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); |
| 1850 | ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); |
| 1851 | ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1852 | |
| 1853 | REG_WRITE(ah, AR_NEXT_DTIM, |
| 1854 | TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); |
| 1855 | REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP)); |
| 1856 | |
| 1857 | REG_WRITE(ah, AR_SLEEP1, |
| 1858 | SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT) |
| 1859 | | AR_SLEEP1_ASSUME_DTIM); |
| 1860 | |
Sujith | 60b67f5 | 2008-08-07 10:52:38 +0530 | [diff] [blame] | 1861 | if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1862 | beacontimeout = (BEACON_TIMEOUT_VAL << 3); |
| 1863 | else |
| 1864 | beacontimeout = MIN_BEACON_TIMEOUT_VAL; |
| 1865 | |
| 1866 | REG_WRITE(ah, AR_SLEEP2, |
| 1867 | SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT)); |
| 1868 | |
| 1869 | REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval)); |
| 1870 | REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod)); |
| 1871 | |
| 1872 | REG_SET_BIT(ah, AR_TIMER_MODE, |
| 1873 | AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN | |
| 1874 | AR_DTIM_TIMER_EN); |
| 1875 | |
Sujith | 4af9cf4 | 2009-02-12 10:06:47 +0530 | [diff] [blame] | 1876 | /* TSF Out of Range Threshold */ |
| 1877 | REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1878 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 1879 | EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1880 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1881 | /*******************/ |
| 1882 | /* HW Capabilities */ |
| 1883 | /*******************/ |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1884 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1885 | int ath9k_hw_fill_cap_info(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1886 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1887 | struct ath9k_hw_capabilities *pCap = &ah->caps; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1888 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1889 | struct ath_common *common = ath9k_hw_common(ah); |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 1890 | struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1891 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1892 | u16 capField = 0, eeval; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1893 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1894 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0); |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1895 | regulatory->current_rd = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1896 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1897 | eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1); |
Sujith | fec0de1 | 2009-02-12 10:06:43 +0530 | [diff] [blame] | 1898 | if (AR_SREV_9285_10_OR_LATER(ah)) |
| 1899 | eeval |= AR9285_RDEXT_DEFAULT; |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1900 | regulatory->current_rd_ext = eeval; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1901 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1902 | capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1903 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1904 | if (ah->opmode != NL80211_IFTYPE_AP && |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 1905 | ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 1906 | if (regulatory->current_rd == 0x64 || |
| 1907 | regulatory->current_rd == 0x65) |
| 1908 | regulatory->current_rd += 5; |
| 1909 | else if (regulatory->current_rd == 0x41) |
| 1910 | regulatory->current_rd = 0x43; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 1911 | ath_print(common, ATH_DBG_REGULATORY, |
| 1912 | "regdomain mapped to 0x%x\n", regulatory->current_rd); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1913 | } |
Sujith | dc2222a | 2008-08-14 13:26:55 +0530 | [diff] [blame] | 1914 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1915 | eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE); |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 1916 | if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) { |
| 1917 | ath_print(common, ATH_DBG_FATAL, |
| 1918 | "no band has been marked as supported in EEPROM.\n"); |
| 1919 | return -EINVAL; |
| 1920 | } |
| 1921 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1922 | bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1923 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1924 | if (eeval & AR5416_OPFLAGS_11A) { |
| 1925 | set_bit(ATH9K_MODE_11A, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1926 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1927 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT20)) |
| 1928 | set_bit(ATH9K_MODE_11NA_HT20, |
| 1929 | pCap->wireless_modes); |
| 1930 | if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) { |
| 1931 | set_bit(ATH9K_MODE_11NA_HT40PLUS, |
| 1932 | pCap->wireless_modes); |
| 1933 | set_bit(ATH9K_MODE_11NA_HT40MINUS, |
| 1934 | pCap->wireless_modes); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1935 | } |
| 1936 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1937 | } |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 1938 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1939 | if (eeval & AR5416_OPFLAGS_11G) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1940 | set_bit(ATH9K_MODE_11G, pCap->wireless_modes); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1941 | if (ah->config.ht_enable) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1942 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT20)) |
| 1943 | set_bit(ATH9K_MODE_11NG_HT20, |
| 1944 | pCap->wireless_modes); |
| 1945 | if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) { |
| 1946 | set_bit(ATH9K_MODE_11NG_HT40PLUS, |
| 1947 | pCap->wireless_modes); |
| 1948 | set_bit(ATH9K_MODE_11NG_HT40MINUS, |
| 1949 | pCap->wireless_modes); |
| 1950 | } |
| 1951 | } |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 1952 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1953 | |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 1954 | pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK); |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1955 | /* |
| 1956 | * For AR9271 we will temporarilly uses the rx chainmax as read from |
| 1957 | * the EEPROM. |
| 1958 | */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1959 | if ((ah->hw_version.devid == AR5416_DEVID_PCI) && |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1960 | !(eeval & AR5416_OPFLAGS_11A) && |
| 1961 | !(AR_SREV_9271(ah))) |
| 1962 | /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1963 | pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7; |
| 1964 | else |
Luis R. Rodriguez | d7e7d22 | 2009-08-03 23:14:12 -0400 | [diff] [blame] | 1965 | /* Use rx_chainmask from EEPROM. */ |
Sujith | 8147f5d | 2009-02-20 15:13:23 +0530 | [diff] [blame] | 1966 | pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1967 | |
Sujith | d535a42 | 2009-02-09 13:27:06 +0530 | [diff] [blame] | 1968 | if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0))) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1969 | ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1970 | |
| 1971 | pCap->low_2ghz_chan = 2312; |
| 1972 | pCap->high_2ghz_chan = 2732; |
| 1973 | |
| 1974 | pCap->low_5ghz_chan = 4920; |
| 1975 | pCap->high_5ghz_chan = 6100; |
| 1976 | |
| 1977 | pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP; |
| 1978 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP; |
| 1979 | pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM; |
| 1980 | |
| 1981 | pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP; |
| 1982 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; |
| 1983 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; |
| 1984 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 1985 | if (ah->config.ht_enable) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 1986 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
| 1987 | else |
| 1988 | pCap->hw_caps &= ~ATH9K_HW_CAP_HT; |
| 1989 | |
| 1990 | pCap->hw_caps |= ATH9K_HW_CAP_GTT; |
| 1991 | pCap->hw_caps |= ATH9K_HW_CAP_VEOL; |
| 1992 | pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK; |
| 1993 | pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH; |
| 1994 | |
| 1995 | if (capField & AR_EEPROM_EEPCAP_MAXQCU) |
| 1996 | pCap->total_queues = |
| 1997 | MS(capField, AR_EEPROM_EEPCAP_MAXQCU); |
| 1998 | else |
| 1999 | pCap->total_queues = ATH9K_NUM_TX_QUEUES; |
| 2000 | |
| 2001 | if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES) |
| 2002 | pCap->keycache_size = |
| 2003 | 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES); |
| 2004 | else |
| 2005 | pCap->keycache_size = AR_KEYTABLE_SIZE; |
| 2006 | |
| 2007 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
Luis R. Rodriguez | f4709fd | 2009-11-24 21:37:57 -0500 | [diff] [blame] | 2008 | |
| 2009 | if (AR_SREV_9285(ah) || AR_SREV_9271(ah)) |
| 2010 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1; |
| 2011 | else |
| 2012 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2013 | |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2014 | if (AR_SREV_9271(ah)) |
| 2015 | pCap->num_gpio_pins = AR9271_NUM_GPIO; |
| 2016 | else if (AR_SREV_9285_10_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2017 | pCap->num_gpio_pins = AR9285_NUM_GPIO; |
| 2018 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2019 | pCap->num_gpio_pins = AR928X_NUM_GPIO; |
| 2020 | else |
| 2021 | pCap->num_gpio_pins = AR_NUM_GPIO; |
| 2022 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2023 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
| 2024 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
| 2025 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
| 2026 | } else { |
| 2027 | pCap->rts_aggr_limit = (8 * 1024); |
| 2028 | } |
| 2029 | |
| 2030 | pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM; |
| 2031 | |
Senthil Balasubramanian | e97275c | 2008-11-13 18:00:02 +0530 | [diff] [blame] | 2032 | #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2033 | ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT); |
| 2034 | if (ah->rfsilent & EEP_RFSILENT_ENABLED) { |
| 2035 | ah->rfkill_gpio = |
| 2036 | MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL); |
| 2037 | ah->rfkill_polarity = |
| 2038 | MS(ah->rfsilent, EEP_RFSILENT_POLARITY); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2039 | |
| 2040 | pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT; |
| 2041 | } |
| 2042 | #endif |
Vivek Natarajan | bde748a | 2010-04-05 14:48:05 +0530 | [diff] [blame] | 2043 | if (AR_SREV_9271(ah)) |
| 2044 | pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP; |
| 2045 | else |
| 2046 | pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2047 | |
Senthil Balasubramanian | e759407 | 2008-12-08 19:43:48 +0530 | [diff] [blame] | 2048 | if (AR_SREV_9280(ah) || AR_SREV_9285(ah)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2049 | pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 2050 | else |
| 2051 | pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS; |
| 2052 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2053 | if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2054 | pCap->reg_cap = |
| 2055 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 2056 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN | |
| 2057 | AR_EEPROM_EEREGCAP_EN_KK_U2 | |
| 2058 | AR_EEPROM_EEREGCAP_EN_KK_MIDBAND; |
| 2059 | } else { |
| 2060 | pCap->reg_cap = |
| 2061 | AR_EEPROM_EEREGCAP_EN_KK_NEW_11A | |
| 2062 | AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN; |
| 2063 | } |
| 2064 | |
Senthil Balasubramanian | ebb90cf | 2009-09-18 15:07:33 +0530 | [diff] [blame] | 2065 | /* Advertise midband for AR5416 with FCC midband set in eeprom */ |
| 2066 | if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) && |
| 2067 | AR_SREV_5416(ah)) |
| 2068 | pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2069 | |
| 2070 | pCap->num_antcfg_5ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2071 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2072 | pCap->num_antcfg_2ghz = |
Sujith | f74df6f | 2009-02-09 13:27:24 +0530 | [diff] [blame] | 2073 | ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2074 | |
Vasanthakumar Thiagarajan | fe12946 | 2009-09-09 15:25:50 +0530 | [diff] [blame] | 2075 | if (AR_SREV_9280_10_OR_LATER(ah) && |
Luis R. Rodriguez | a36cfbc | 2009-09-09 16:05:32 -0700 | [diff] [blame] | 2076 | ath9k_hw_btcoex_supported(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2077 | btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO; |
| 2078 | btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO; |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 2079 | |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2080 | if (AR_SREV_9285(ah)) { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2081 | btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE; |
| 2082 | btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2083 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2084 | btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE; |
Vasanthakumar Thiagarajan | 8c8f9ba | 2009-09-09 15:25:52 +0530 | [diff] [blame] | 2085 | } |
Vasanthakumar Thiagarajan | 22f25d0 | 2009-08-26 21:08:47 +0530 | [diff] [blame] | 2086 | } else { |
Luis R. Rodriguez | 766ec4a | 2009-09-09 14:52:02 -0700 | [diff] [blame] | 2087 | btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE; |
Vasanthakumar Thiagarajan | c97c92d | 2009-01-02 15:35:46 +0530 | [diff] [blame] | 2088 | } |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2089 | |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2090 | if (AR_SREV_9300_20_OR_LATER(ah)) { |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 2091 | pCap->hw_caps |= ATH9K_HW_CAP_EDMA; |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2092 | pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; |
| 2093 | pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; |
| 2094 | pCap->rx_status_len = sizeof(struct ar9003_rxs); |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 2095 | pCap->tx_desc_len = sizeof(struct ar9003_txc); |
Vasanthakumar Thiagarajan | 5088c2f | 2010-04-15 17:39:34 -0400 | [diff] [blame^] | 2096 | pCap->txs_len = sizeof(struct ar9003_txs); |
Vasanthakumar Thiagarajan | 162c3be | 2010-04-15 17:38:41 -0400 | [diff] [blame] | 2097 | } else { |
| 2098 | pCap->tx_desc_len = sizeof(struct ath_desc); |
Vasanthakumar Thiagarajan | ceb2644 | 2010-04-15 17:38:25 -0400 | [diff] [blame] | 2099 | } |
Vasanthakumar Thiagarajan | 1adf02f | 2010-04-15 17:38:24 -0400 | [diff] [blame] | 2100 | |
Vasanthakumar Thiagarajan | 6c84ce0 | 2010-04-15 17:39:16 -0400 | [diff] [blame] | 2101 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 2102 | pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; |
| 2103 | |
Gabor Juhos | a9a29ce | 2009-11-27 12:01:35 +0100 | [diff] [blame] | 2104 | return 0; |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2105 | } |
| 2106 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2107 | bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2108 | u32 capability, u32 *result) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2109 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2110 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2111 | switch (type) { |
| 2112 | case ATH9K_CAP_CIPHER: |
| 2113 | switch (capability) { |
| 2114 | case ATH9K_CIPHER_AES_CCM: |
| 2115 | case ATH9K_CIPHER_AES_OCB: |
| 2116 | case ATH9K_CIPHER_TKIP: |
| 2117 | case ATH9K_CIPHER_WEP: |
| 2118 | case ATH9K_CIPHER_MIC: |
| 2119 | case ATH9K_CIPHER_CLR: |
| 2120 | return true; |
| 2121 | default: |
| 2122 | return false; |
| 2123 | } |
| 2124 | case ATH9K_CAP_TKIP_MIC: |
| 2125 | switch (capability) { |
| 2126 | case 0: |
| 2127 | return true; |
| 2128 | case 1: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2129 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2130 | AR_STA_ID1_CRPT_MIC_ENABLE) ? true : |
| 2131 | false; |
| 2132 | } |
| 2133 | case ATH9K_CAP_TKIP_SPLIT: |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2134 | return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2135 | false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2136 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 2137 | switch (capability) { |
| 2138 | case 0: |
| 2139 | return true; |
| 2140 | case 1: |
| 2141 | if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { |
| 2142 | return false; |
| 2143 | } else { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2144 | return (ah->sta_id1_defaults & |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2145 | AR_STA_ID1_MCAST_KSRCH) ? true : |
| 2146 | false; |
| 2147 | } |
| 2148 | } |
| 2149 | return false; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2150 | case ATH9K_CAP_TXPOW: |
| 2151 | switch (capability) { |
| 2152 | case 0: |
| 2153 | return 0; |
| 2154 | case 1: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2155 | *result = regulatory->power_limit; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2156 | return 0; |
| 2157 | case 2: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2158 | *result = regulatory->max_power_level; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2159 | return 0; |
| 2160 | case 3: |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2161 | *result = regulatory->tp_scale; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2162 | return 0; |
| 2163 | } |
| 2164 | return false; |
Senthil Balasubramanian | 8bd1d07 | 2009-02-12 13:57:03 +0530 | [diff] [blame] | 2165 | case ATH9K_CAP_DS: |
| 2166 | return (AR_SREV_9280_20_OR_LATER(ah) && |
| 2167 | (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1)) |
| 2168 | ? false : true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2169 | default: |
| 2170 | return false; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2171 | } |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2172 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2173 | EXPORT_SYMBOL(ath9k_hw_getcapability); |
Luis R. Rodriguez | 6f25542 | 2008-10-03 15:45:27 -0700 | [diff] [blame] | 2174 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2175 | bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2176 | u32 capability, u32 setting, int *status) |
| 2177 | { |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2178 | switch (type) { |
| 2179 | case ATH9K_CAP_TKIP_MIC: |
| 2180 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2181 | ah->sta_id1_defaults |= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2182 | AR_STA_ID1_CRPT_MIC_ENABLE; |
| 2183 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2184 | ah->sta_id1_defaults &= |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2185 | ~AR_STA_ID1_CRPT_MIC_ENABLE; |
| 2186 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2187 | case ATH9K_CAP_MCAST_KEYSRCH: |
| 2188 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2189 | ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2190 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2191 | ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2192 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2193 | default: |
| 2194 | return false; |
| 2195 | } |
| 2196 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2197 | EXPORT_SYMBOL(ath9k_hw_setcapability); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2198 | |
| 2199 | /****************************/ |
| 2200 | /* GPIO / RFKILL / Antennae */ |
| 2201 | /****************************/ |
| 2202 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2203 | static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2204 | u32 gpio, u32 type) |
| 2205 | { |
| 2206 | int addr; |
| 2207 | u32 gpio_shift, tmp; |
| 2208 | |
| 2209 | if (gpio > 11) |
| 2210 | addr = AR_GPIO_OUTPUT_MUX3; |
| 2211 | else if (gpio > 5) |
| 2212 | addr = AR_GPIO_OUTPUT_MUX2; |
| 2213 | else |
| 2214 | addr = AR_GPIO_OUTPUT_MUX1; |
| 2215 | |
| 2216 | gpio_shift = (gpio % 6) * 5; |
| 2217 | |
| 2218 | if (AR_SREV_9280_20_OR_LATER(ah) |
| 2219 | || (addr != AR_GPIO_OUTPUT_MUX1)) { |
| 2220 | REG_RMW(ah, addr, (type << gpio_shift), |
| 2221 | (0x1f << gpio_shift)); |
| 2222 | } else { |
| 2223 | tmp = REG_READ(ah, addr); |
| 2224 | tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0); |
| 2225 | tmp &= ~(0x1f << gpio_shift); |
| 2226 | tmp |= (type << gpio_shift); |
| 2227 | REG_WRITE(ah, addr, tmp); |
| 2228 | } |
| 2229 | } |
| 2230 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2231 | void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2232 | { |
| 2233 | u32 gpio_shift; |
| 2234 | |
Luis R. Rodriguez | 9680e8a | 2009-09-13 23:28:00 -0700 | [diff] [blame] | 2235 | BUG_ON(gpio >= ah->caps.num_gpio_pins); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2236 | |
| 2237 | gpio_shift = gpio << 1; |
| 2238 | |
| 2239 | REG_RMW(ah, |
| 2240 | AR_GPIO_OE_OUT, |
| 2241 | (AR_GPIO_OE_OUT_DRV_NO << gpio_shift), |
| 2242 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2243 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2244 | EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2245 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2246 | u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2247 | { |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2248 | #define MS_REG_READ(x, y) \ |
| 2249 | (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) |
| 2250 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2251 | if (gpio >= ah->caps.num_gpio_pins) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2252 | return 0xffffffff; |
| 2253 | |
Felix Fietkau | 783dfca | 2010-04-15 17:38:11 -0400 | [diff] [blame] | 2254 | if (AR_SREV_9300_20_OR_LATER(ah)) |
| 2255 | return MS_REG_READ(AR9300, gpio) != 0; |
| 2256 | else if (AR_SREV_9271(ah)) |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2257 | return MS_REG_READ(AR9271, gpio) != 0; |
| 2258 | else if (AR_SREV_9287_10_OR_LATER(ah)) |
Vivek Natarajan | ac88b6e | 2009-07-23 10:59:57 +0530 | [diff] [blame] | 2259 | return MS_REG_READ(AR9287, gpio) != 0; |
| 2260 | else if (AR_SREV_9285_10_OR_LATER(ah)) |
Senthil Balasubramanian | cb33c41 | 2008-12-24 18:03:58 +0530 | [diff] [blame] | 2261 | return MS_REG_READ(AR9285, gpio) != 0; |
| 2262 | else if (AR_SREV_9280_10_OR_LATER(ah)) |
| 2263 | return MS_REG_READ(AR928X, gpio) != 0; |
| 2264 | else |
| 2265 | return MS_REG_READ(AR, gpio) != 0; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2266 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2267 | EXPORT_SYMBOL(ath9k_hw_gpio_get); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2268 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2269 | void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio, |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2270 | u32 ah_signal_type) |
| 2271 | { |
| 2272 | u32 gpio_shift; |
| 2273 | |
| 2274 | ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type); |
| 2275 | |
| 2276 | gpio_shift = 2 * gpio; |
| 2277 | |
| 2278 | REG_RMW(ah, |
| 2279 | AR_GPIO_OE_OUT, |
| 2280 | (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift), |
| 2281 | (AR_GPIO_OE_OUT_DRV << gpio_shift)); |
| 2282 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2283 | EXPORT_SYMBOL(ath9k_hw_cfg_output); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2284 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2285 | void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2286 | { |
Sujith | 5b5fa35 | 2010-03-17 14:25:15 +0530 | [diff] [blame] | 2287 | if (AR_SREV_9271(ah)) |
| 2288 | val = ~val; |
| 2289 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2290 | REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio), |
| 2291 | AR_GPIO_BIT(gpio)); |
| 2292 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2293 | EXPORT_SYMBOL(ath9k_hw_set_gpio); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2294 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2295 | u32 ath9k_hw_getdefantenna(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2296 | { |
| 2297 | return REG_READ(ah, AR_DEF_ANTENNA) & 0x7; |
| 2298 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2299 | EXPORT_SYMBOL(ath9k_hw_getdefantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2300 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2301 | void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2302 | { |
| 2303 | REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); |
| 2304 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2305 | EXPORT_SYMBOL(ath9k_hw_setantenna); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2306 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2307 | /*********************/ |
| 2308 | /* General Operation */ |
| 2309 | /*********************/ |
| 2310 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2311 | u32 ath9k_hw_getrxfilter(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2312 | { |
| 2313 | u32 bits = REG_READ(ah, AR_RX_FILTER); |
| 2314 | u32 phybits = REG_READ(ah, AR_PHY_ERR); |
| 2315 | |
| 2316 | if (phybits & AR_PHY_ERR_RADAR) |
| 2317 | bits |= ATH9K_RX_FILTER_PHYRADAR; |
| 2318 | if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING)) |
| 2319 | bits |= ATH9K_RX_FILTER_PHYERR; |
| 2320 | |
| 2321 | return bits; |
| 2322 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2323 | EXPORT_SYMBOL(ath9k_hw_getrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2324 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2325 | void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2326 | { |
| 2327 | u32 phybits; |
| 2328 | |
Sujith | 7ea310b | 2009-09-03 12:08:43 +0530 | [diff] [blame] | 2329 | REG_WRITE(ah, AR_RX_FILTER, bits); |
| 2330 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2331 | phybits = 0; |
| 2332 | if (bits & ATH9K_RX_FILTER_PHYRADAR) |
| 2333 | phybits |= AR_PHY_ERR_RADAR; |
| 2334 | if (bits & ATH9K_RX_FILTER_PHYERR) |
| 2335 | phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING; |
| 2336 | REG_WRITE(ah, AR_PHY_ERR, phybits); |
| 2337 | |
| 2338 | if (phybits) |
| 2339 | REG_WRITE(ah, AR_RXCFG, |
| 2340 | REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA); |
| 2341 | else |
| 2342 | REG_WRITE(ah, AR_RXCFG, |
| 2343 | REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA); |
| 2344 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2345 | EXPORT_SYMBOL(ath9k_hw_setrxfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2346 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2347 | bool ath9k_hw_phy_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2348 | { |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2349 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM)) |
| 2350 | return false; |
| 2351 | |
| 2352 | ath9k_hw_init_pll(ah, NULL); |
| 2353 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2354 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2355 | EXPORT_SYMBOL(ath9k_hw_phy_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2356 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2357 | bool ath9k_hw_disable(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2358 | { |
Luis R. Rodriguez | 9ecdef4 | 2009-09-09 21:10:09 -0700 | [diff] [blame] | 2359 | if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2360 | return false; |
| 2361 | |
Senthil Balasubramanian | 63a75b9 | 2009-09-18 15:07:03 +0530 | [diff] [blame] | 2362 | if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD)) |
| 2363 | return false; |
| 2364 | |
| 2365 | ath9k_hw_init_pll(ah, NULL); |
| 2366 | return true; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2367 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2368 | EXPORT_SYMBOL(ath9k_hw_disable); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2369 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2370 | void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2371 | { |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2372 | struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2373 | struct ath9k_channel *chan = ah->curchan; |
Luis R. Rodriguez | 5f8e077 | 2009-01-22 15:16:48 -0800 | [diff] [blame] | 2374 | struct ieee80211_channel *channel = chan->chan; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2375 | |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2376 | regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2377 | |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2378 | ah->eep_ops->set_txpower(ah, chan, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2379 | ath9k_regd_get_ctl(regulatory, chan), |
Vasanthakumar Thiagarajan | 8fbff4b | 2009-05-08 17:54:51 -0700 | [diff] [blame] | 2380 | channel->max_antenna_gain * 2, |
| 2381 | channel->max_power * 2, |
| 2382 | min((u32) MAX_RATE_POWER, |
Luis R. Rodriguez | 608b88c | 2009-08-17 18:07:23 -0700 | [diff] [blame] | 2383 | (u32) regulatory->power_limit)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2384 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2385 | EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2386 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2387 | void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2388 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 2389 | memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2390 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2391 | EXPORT_SYMBOL(ath9k_hw_setmac); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2392 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2393 | void ath9k_hw_setopmode(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2394 | { |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2395 | ath9k_hw_set_operating_mode(ah, ah->opmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2396 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2397 | EXPORT_SYMBOL(ath9k_hw_setopmode); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2398 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2399 | void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2400 | { |
| 2401 | REG_WRITE(ah, AR_MCAST_FIL0, filter0); |
| 2402 | REG_WRITE(ah, AR_MCAST_FIL1, filter1); |
| 2403 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2404 | EXPORT_SYMBOL(ath9k_hw_setmcastfilter); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2405 | |
Luis R. Rodriguez | f2b2143 | 2009-09-10 08:50:20 -0700 | [diff] [blame] | 2406 | void ath9k_hw_write_associd(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2407 | { |
Luis R. Rodriguez | 1510718 | 2009-09-10 09:22:37 -0700 | [diff] [blame] | 2408 | struct ath_common *common = ath9k_hw_common(ah); |
| 2409 | |
| 2410 | REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid)); |
| 2411 | REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) | |
| 2412 | ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S)); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2413 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2414 | EXPORT_SYMBOL(ath9k_hw_write_associd); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2415 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2416 | u64 ath9k_hw_gettsf64(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2417 | { |
| 2418 | u64 tsf; |
| 2419 | |
| 2420 | tsf = REG_READ(ah, AR_TSF_U32); |
| 2421 | tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32); |
| 2422 | |
| 2423 | return tsf; |
| 2424 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2425 | EXPORT_SYMBOL(ath9k_hw_gettsf64); |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2426 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2427 | void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64) |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2428 | { |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2429 | REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff); |
Alina Friedrichsen | b9a1619 | 2009-03-02 23:28:38 +0100 | [diff] [blame] | 2430 | REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2431 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2432 | EXPORT_SYMBOL(ath9k_hw_settsf64); |
Alina Friedrichsen | 27abe06 | 2009-01-23 05:44:21 +0100 | [diff] [blame] | 2433 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 2434 | void ath9k_hw_reset_tsf(struct ath_hw *ah) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2435 | { |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2436 | if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, |
| 2437 | AH_TSF_WRITE_TIMEOUT)) |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2438 | ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, |
| 2439 | "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); |
Gabor Juhos | f9b604f | 2009-06-21 00:02:15 +0200 | [diff] [blame] | 2440 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2441 | REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2442 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2443 | EXPORT_SYMBOL(ath9k_hw_reset_tsf); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2444 | |
Sujith | 54e4cec | 2009-08-07 09:45:09 +0530 | [diff] [blame] | 2445 | void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2446 | { |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2447 | if (setting) |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2448 | ah->misc_mode |= AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2449 | else |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 2450 | ah->misc_mode &= ~AR_PCU_TX_ADD_TSF; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2451 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2452 | EXPORT_SYMBOL(ath9k_hw_set_tsfadjust); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2453 | |
Luis R. Rodriguez | 30cbd42 | 2009-11-03 16:10:46 -0800 | [diff] [blame] | 2454 | /* |
| 2455 | * Extend 15-bit time stamp from rx descriptor to |
| 2456 | * a full 64-bit TSF using the current h/w TSF. |
| 2457 | */ |
| 2458 | u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp) |
| 2459 | { |
| 2460 | u64 tsf; |
| 2461 | |
| 2462 | tsf = ath9k_hw_gettsf64(ah); |
| 2463 | if ((tsf & 0x7fff) < rstamp) |
| 2464 | tsf -= 0x8000; |
| 2465 | return (tsf & ~0x7fff) | rstamp; |
| 2466 | } |
| 2467 | EXPORT_SYMBOL(ath9k_hw_extend_tsf); |
| 2468 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2469 | void ath9k_hw_set11nmac2040(struct ath_hw *ah) |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2470 | { |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2471 | struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf; |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2472 | u32 macmode; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2473 | |
Luis R. Rodriguez | 25c56ee | 2009-09-13 23:04:44 -0700 | [diff] [blame] | 2474 | if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca) |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2475 | macmode = AR_2040_JOINED_RX_CLEAR; |
| 2476 | else |
| 2477 | macmode = 0; |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2478 | |
Sujith | f1dc560 | 2008-10-29 10:16:30 +0530 | [diff] [blame] | 2479 | REG_WRITE(ah, AR_2040_MODE, macmode); |
Luis R. Rodriguez | f078f20 | 2008-08-04 00:16:41 -0700 | [diff] [blame] | 2480 | } |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2481 | |
| 2482 | /* HW Generic timers configuration */ |
| 2483 | |
| 2484 | static const struct ath_gen_timer_configuration gen_tmr_configuration[] = |
| 2485 | { |
| 2486 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2487 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2488 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2489 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2490 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2491 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2492 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2493 | {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080}, |
| 2494 | {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001}, |
| 2495 | {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4, |
| 2496 | AR_NDP2_TIMER_MODE, 0x0002}, |
| 2497 | {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4, |
| 2498 | AR_NDP2_TIMER_MODE, 0x0004}, |
| 2499 | {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4, |
| 2500 | AR_NDP2_TIMER_MODE, 0x0008}, |
| 2501 | {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4, |
| 2502 | AR_NDP2_TIMER_MODE, 0x0010}, |
| 2503 | {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4, |
| 2504 | AR_NDP2_TIMER_MODE, 0x0020}, |
| 2505 | {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4, |
| 2506 | AR_NDP2_TIMER_MODE, 0x0040}, |
| 2507 | {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4, |
| 2508 | AR_NDP2_TIMER_MODE, 0x0080} |
| 2509 | }; |
| 2510 | |
| 2511 | /* HW generic timer primitives */ |
| 2512 | |
| 2513 | /* compute and clear index of rightmost 1 */ |
| 2514 | static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask) |
| 2515 | { |
| 2516 | u32 b; |
| 2517 | |
| 2518 | b = *mask; |
| 2519 | b &= (0-b); |
| 2520 | *mask &= ~b; |
| 2521 | b *= debruijn32; |
| 2522 | b >>= 27; |
| 2523 | |
| 2524 | return timer_table->gen_timer_index[b]; |
| 2525 | } |
| 2526 | |
Vasanthakumar Thiagarajan | 1773912 | 2009-08-26 21:08:50 +0530 | [diff] [blame] | 2527 | u32 ath9k_hw_gettsf32(struct ath_hw *ah) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2528 | { |
| 2529 | return REG_READ(ah, AR_TSF_L32); |
| 2530 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2531 | EXPORT_SYMBOL(ath9k_hw_gettsf32); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2532 | |
| 2533 | struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah, |
| 2534 | void (*trigger)(void *), |
| 2535 | void (*overflow)(void *), |
| 2536 | void *arg, |
| 2537 | u8 timer_index) |
| 2538 | { |
| 2539 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2540 | struct ath_gen_timer *timer; |
| 2541 | |
| 2542 | timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL); |
| 2543 | |
| 2544 | if (timer == NULL) { |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2545 | ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, |
| 2546 | "Failed to allocate memory" |
| 2547 | "for hw timer[%d]\n", timer_index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2548 | return NULL; |
| 2549 | } |
| 2550 | |
| 2551 | /* allocate a hardware generic timer slot */ |
| 2552 | timer_table->timers[timer_index] = timer; |
| 2553 | timer->index = timer_index; |
| 2554 | timer->trigger = trigger; |
| 2555 | timer->overflow = overflow; |
| 2556 | timer->arg = arg; |
| 2557 | |
| 2558 | return timer; |
| 2559 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2560 | EXPORT_SYMBOL(ath_gen_timer_alloc); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2561 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2562 | void ath9k_hw_gen_timer_start(struct ath_hw *ah, |
| 2563 | struct ath_gen_timer *timer, |
| 2564 | u32 timer_next, |
| 2565 | u32 timer_period) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2566 | { |
| 2567 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2568 | u32 tsf; |
| 2569 | |
| 2570 | BUG_ON(!timer_period); |
| 2571 | |
| 2572 | set_bit(timer->index, &timer_table->timer_mask.timer_bits); |
| 2573 | |
| 2574 | tsf = ath9k_hw_gettsf32(ah); |
| 2575 | |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2576 | ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER, |
| 2577 | "curent tsf %x period %x" |
| 2578 | "timer_next %x\n", tsf, timer_period, timer_next); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2579 | |
| 2580 | /* |
| 2581 | * Pull timer_next forward if the current TSF already passed it |
| 2582 | * because of software latency |
| 2583 | */ |
| 2584 | if (timer_next < tsf) |
| 2585 | timer_next = tsf + timer_period; |
| 2586 | |
| 2587 | /* |
| 2588 | * Program generic timer registers |
| 2589 | */ |
| 2590 | REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr, |
| 2591 | timer_next); |
| 2592 | REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr, |
| 2593 | timer_period); |
| 2594 | REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2595 | gen_tmr_configuration[timer->index].mode_mask); |
| 2596 | |
| 2597 | /* Enable both trigger and thresh interrupt masks */ |
| 2598 | REG_SET_BIT(ah, AR_IMR_S5, |
| 2599 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2600 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2601 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2602 | EXPORT_SYMBOL(ath9k_hw_gen_timer_start); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2603 | |
Luis R. Rodriguez | cd9bf68 | 2009-09-13 02:08:34 -0700 | [diff] [blame] | 2604 | void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer) |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2605 | { |
| 2606 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2607 | |
| 2608 | if ((timer->index < AR_FIRST_NDP_TIMER) || |
| 2609 | (timer->index >= ATH_MAX_GEN_TIMER)) { |
| 2610 | return; |
| 2611 | } |
| 2612 | |
| 2613 | /* Clear generic timer enable bits. */ |
| 2614 | REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr, |
| 2615 | gen_tmr_configuration[timer->index].mode_mask); |
| 2616 | |
| 2617 | /* Disable both trigger and thresh interrupt masks */ |
| 2618 | REG_CLR_BIT(ah, AR_IMR_S5, |
| 2619 | (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) | |
| 2620 | SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG))); |
| 2621 | |
| 2622 | clear_bit(timer->index, &timer_table->timer_mask.timer_bits); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2623 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2624 | EXPORT_SYMBOL(ath9k_hw_gen_timer_stop); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2625 | |
| 2626 | void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer) |
| 2627 | { |
| 2628 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2629 | |
| 2630 | /* free the hardware generic timer slot */ |
| 2631 | timer_table->timers[timer->index] = NULL; |
| 2632 | kfree(timer); |
| 2633 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2634 | EXPORT_SYMBOL(ath_gen_timer_free); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2635 | |
| 2636 | /* |
| 2637 | * Generic Timer Interrupts handling |
| 2638 | */ |
| 2639 | void ath_gen_timer_isr(struct ath_hw *ah) |
| 2640 | { |
| 2641 | struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers; |
| 2642 | struct ath_gen_timer *timer; |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2643 | struct ath_common *common = ath9k_hw_common(ah); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2644 | u32 trigger_mask, thresh_mask, index; |
| 2645 | |
| 2646 | /* get hardware generic timer interrupt status */ |
| 2647 | trigger_mask = ah->intr_gen_timer_trigger; |
| 2648 | thresh_mask = ah->intr_gen_timer_thresh; |
| 2649 | trigger_mask &= timer_table->timer_mask.val; |
| 2650 | thresh_mask &= timer_table->timer_mask.val; |
| 2651 | |
| 2652 | trigger_mask &= ~thresh_mask; |
| 2653 | |
| 2654 | while (thresh_mask) { |
| 2655 | index = rightmost_index(timer_table, &thresh_mask); |
| 2656 | timer = timer_table->timers[index]; |
| 2657 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2658 | ath_print(common, ATH_DBG_HWTIMER, |
| 2659 | "TSF overflow for Gen timer %d\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2660 | timer->overflow(timer->arg); |
| 2661 | } |
| 2662 | |
| 2663 | while (trigger_mask) { |
| 2664 | index = rightmost_index(timer_table, &trigger_mask); |
| 2665 | timer = timer_table->timers[index]; |
| 2666 | BUG_ON(!timer); |
Luis R. Rodriguez | c46917b | 2009-09-13 02:42:02 -0700 | [diff] [blame] | 2667 | ath_print(common, ATH_DBG_HWTIMER, |
| 2668 | "Gen timer[%d] trigger\n", index); |
Vasanthakumar Thiagarajan | ff155a4 | 2009-08-26 21:08:49 +0530 | [diff] [blame] | 2669 | timer->trigger(timer->arg); |
| 2670 | } |
| 2671 | } |
Luis R. Rodriguez | 7322fd1 | 2009-09-23 23:07:00 -0400 | [diff] [blame] | 2672 | EXPORT_SYMBOL(ath_gen_timer_isr); |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2673 | |
Sujith | 05020d2 | 2010-03-17 14:25:23 +0530 | [diff] [blame] | 2674 | /********/ |
| 2675 | /* HTC */ |
| 2676 | /********/ |
| 2677 | |
| 2678 | void ath9k_hw_htc_resetinit(struct ath_hw *ah) |
| 2679 | { |
| 2680 | ah->htc_reset_init = true; |
| 2681 | } |
| 2682 | EXPORT_SYMBOL(ath9k_hw_htc_resetinit); |
| 2683 | |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2684 | static struct { |
| 2685 | u32 version; |
| 2686 | const char * name; |
| 2687 | } ath_mac_bb_names[] = { |
| 2688 | /* Devices with external radios */ |
| 2689 | { AR_SREV_VERSION_5416_PCI, "5416" }, |
| 2690 | { AR_SREV_VERSION_5416_PCIE, "5418" }, |
| 2691 | { AR_SREV_VERSION_9100, "9100" }, |
| 2692 | { AR_SREV_VERSION_9160, "9160" }, |
| 2693 | /* Single-chip solutions */ |
| 2694 | { AR_SREV_VERSION_9280, "9280" }, |
| 2695 | { AR_SREV_VERSION_9285, "9285" }, |
Luis R. Rodriguez | 1115847 | 2009-10-27 12:59:35 -0400 | [diff] [blame] | 2696 | { AR_SREV_VERSION_9287, "9287" }, |
| 2697 | { AR_SREV_VERSION_9271, "9271" }, |
Luis R. Rodriguez | ec83903 | 2010-04-15 17:39:20 -0400 | [diff] [blame] | 2698 | { AR_SREV_VERSION_9300, "9300" }, |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2699 | }; |
| 2700 | |
| 2701 | /* For devices with external radios */ |
| 2702 | static struct { |
| 2703 | u16 version; |
| 2704 | const char * name; |
| 2705 | } ath_rf_names[] = { |
| 2706 | { 0, "5133" }, |
| 2707 | { AR_RAD5133_SREV_MAJOR, "5133" }, |
| 2708 | { AR_RAD5122_SREV_MAJOR, "5122" }, |
| 2709 | { AR_RAD2133_SREV_MAJOR, "2133" }, |
| 2710 | { AR_RAD2122_SREV_MAJOR, "2122" } |
| 2711 | }; |
| 2712 | |
| 2713 | /* |
| 2714 | * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown. |
| 2715 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2716 | static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2717 | { |
| 2718 | int i; |
| 2719 | |
| 2720 | for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) { |
| 2721 | if (ath_mac_bb_names[i].version == mac_bb_version) { |
| 2722 | return ath_mac_bb_names[i].name; |
| 2723 | } |
| 2724 | } |
| 2725 | |
| 2726 | return "????"; |
| 2727 | } |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2728 | |
| 2729 | /* |
| 2730 | * Return the RF name. "????" is returned if the RF is unknown. |
| 2731 | * Used for devices with external radios. |
| 2732 | */ |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2733 | static const char *ath9k_hw_rf_name(u16 rf_version) |
Luis R. Rodriguez | 2da4f01 | 2009-10-27 12:59:33 -0400 | [diff] [blame] | 2734 | { |
| 2735 | int i; |
| 2736 | |
| 2737 | for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) { |
| 2738 | if (ath_rf_names[i].version == rf_version) { |
| 2739 | return ath_rf_names[i].name; |
| 2740 | } |
| 2741 | } |
| 2742 | |
| 2743 | return "????"; |
| 2744 | } |
Luis R. Rodriguez | f934c4d | 2009-10-27 12:59:34 -0400 | [diff] [blame] | 2745 | |
| 2746 | void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len) |
| 2747 | { |
| 2748 | int used; |
| 2749 | |
| 2750 | /* chipsets >= AR9280 are single-chip */ |
| 2751 | if (AR_SREV_9280_10_OR_LATER(ah)) { |
| 2752 | used = snprintf(hw_name, len, |
| 2753 | "Atheros AR%s Rev:%x", |
| 2754 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2755 | ah->hw_version.macRev); |
| 2756 | } |
| 2757 | else { |
| 2758 | used = snprintf(hw_name, len, |
| 2759 | "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x", |
| 2760 | ath9k_hw_mac_bb_name(ah->hw_version.macVersion), |
| 2761 | ah->hw_version.macRev, |
| 2762 | ath9k_hw_rf_name((ah->hw_version.analog5GhzRev & |
| 2763 | AR_RADIO_SREV_MAJOR)), |
| 2764 | ah->hw_version.phyRev); |
| 2765 | } |
| 2766 | |
| 2767 | hw_name[used] = '\0'; |
| 2768 | } |
| 2769 | EXPORT_SYMBOL(ath9k_hw_name); |