Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) ST Ericsson SA 2011 |
| 3 | * |
| 4 | * License Terms: GNU General Public License v2 |
| 5 | * |
| 6 | * STE Ux500 PRCMU API |
| 7 | */ |
| 8 | #ifndef __MACH_PRCMU_H |
| 9 | #define __MACH_PRCMU_H |
| 10 | |
| 11 | #include <linux/interrupt.h> |
| 12 | #include <linux/notifier.h> |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 13 | #include <linux/err.h> |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 14 | |
| 15 | /* PRCMU Wakeup defines */ |
| 16 | enum prcmu_wakeup_index { |
| 17 | PRCMU_WAKEUP_INDEX_RTC, |
| 18 | PRCMU_WAKEUP_INDEX_RTT0, |
| 19 | PRCMU_WAKEUP_INDEX_RTT1, |
| 20 | PRCMU_WAKEUP_INDEX_HSI0, |
| 21 | PRCMU_WAKEUP_INDEX_HSI1, |
| 22 | PRCMU_WAKEUP_INDEX_USB, |
| 23 | PRCMU_WAKEUP_INDEX_ABB, |
| 24 | PRCMU_WAKEUP_INDEX_ABB_FIFO, |
| 25 | PRCMU_WAKEUP_INDEX_ARM, |
| 26 | PRCMU_WAKEUP_INDEX_CD_IRQ, |
| 27 | NUM_PRCMU_WAKEUP_INDICES |
| 28 | }; |
| 29 | #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) |
| 30 | |
| 31 | /* EPOD (power domain) IDs */ |
| 32 | |
| 33 | /* |
| 34 | * DB8500 EPODs |
| 35 | * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP |
| 36 | * - EPOD_ID_SVAPIPE: power domain for SVA pipe |
| 37 | * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP |
| 38 | * - EPOD_ID_SIAPIPE: power domain for SIA pipe |
| 39 | * - EPOD_ID_SGA: power domain for SGA |
| 40 | * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE |
| 41 | * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 |
| 42 | * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 |
| 43 | * - NUM_EPOD_ID: number of power domains |
| 44 | * |
| 45 | * TODO: These should be prefixed. |
| 46 | */ |
| 47 | #define EPOD_ID_SVAMMDSP 0 |
| 48 | #define EPOD_ID_SVAPIPE 1 |
| 49 | #define EPOD_ID_SIAMMDSP 2 |
| 50 | #define EPOD_ID_SIAPIPE 3 |
| 51 | #define EPOD_ID_SGA 4 |
| 52 | #define EPOD_ID_B2R2_MCDE 5 |
| 53 | #define EPOD_ID_ESRAM12 6 |
| 54 | #define EPOD_ID_ESRAM34 7 |
| 55 | #define NUM_EPOD_ID 8 |
| 56 | |
| 57 | /* |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 58 | * state definition for EPOD (power domain) |
| 59 | * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged |
| 60 | * - EPOD_STATE_OFF: The EPOD is switched off |
| 61 | * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in |
| 62 | * retention |
| 63 | * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off |
| 64 | * - EPOD_STATE_ON: Same as above, but with clock enabled |
| 65 | */ |
| 66 | #define EPOD_STATE_NO_CHANGE 0x00 |
| 67 | #define EPOD_STATE_OFF 0x01 |
| 68 | #define EPOD_STATE_RAMRET 0x02 |
| 69 | #define EPOD_STATE_ON_CLK_OFF 0x03 |
| 70 | #define EPOD_STATE_ON 0x04 |
| 71 | |
| 72 | /* |
| 73 | * CLKOUT sources |
| 74 | */ |
| 75 | #define PRCMU_CLKSRC_CLK38M 0x00 |
| 76 | #define PRCMU_CLKSRC_ACLK 0x01 |
| 77 | #define PRCMU_CLKSRC_SYSCLK 0x02 |
| 78 | #define PRCMU_CLKSRC_LCDCLK 0x03 |
| 79 | #define PRCMU_CLKSRC_SDMMCCLK 0x04 |
| 80 | #define PRCMU_CLKSRC_TVCLK 0x05 |
| 81 | #define PRCMU_CLKSRC_TIMCLK 0x06 |
| 82 | #define PRCMU_CLKSRC_CLK009 0x07 |
| 83 | /* These are only valid for CLKOUT1: */ |
| 84 | #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 |
| 85 | #define PRCMU_CLKSRC_I2CCLK 0x41 |
| 86 | #define PRCMU_CLKSRC_MSP02CLK 0x42 |
| 87 | #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 |
| 88 | #define PRCMU_CLKSRC_HSIRXCLK 0x44 |
| 89 | #define PRCMU_CLKSRC_HSITXCLK 0x45 |
| 90 | #define PRCMU_CLKSRC_ARMCLKFIX 0x46 |
| 91 | #define PRCMU_CLKSRC_HDMICLK 0x47 |
| 92 | |
| 93 | /* |
| 94 | * Clock identifiers. |
| 95 | */ |
| 96 | enum prcmu_clock { |
| 97 | PRCMU_SGACLK, |
| 98 | PRCMU_UARTCLK, |
| 99 | PRCMU_MSP02CLK, |
| 100 | PRCMU_MSP1CLK, |
| 101 | PRCMU_I2CCLK, |
| 102 | PRCMU_SDMMCCLK, |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 103 | PRCMU_SPARE1CLK, |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 104 | PRCMU_SLIMCLK, |
| 105 | PRCMU_PER1CLK, |
| 106 | PRCMU_PER2CLK, |
| 107 | PRCMU_PER3CLK, |
| 108 | PRCMU_PER5CLK, |
| 109 | PRCMU_PER6CLK, |
| 110 | PRCMU_PER7CLK, |
| 111 | PRCMU_LCDCLK, |
| 112 | PRCMU_BMLCLK, |
| 113 | PRCMU_HSITXCLK, |
| 114 | PRCMU_HSIRXCLK, |
| 115 | PRCMU_HDMICLK, |
| 116 | PRCMU_APEATCLK, |
| 117 | PRCMU_APETRACECLK, |
| 118 | PRCMU_MCDECLK, |
| 119 | PRCMU_IPI2CCLK, |
| 120 | PRCMU_DSIALTCLK, |
| 121 | PRCMU_DMACLK, |
| 122 | PRCMU_B2R2CLK, |
| 123 | PRCMU_TVCLK, |
| 124 | PRCMU_SSPCLK, |
| 125 | PRCMU_RNGCLK, |
| 126 | PRCMU_UICCCLK, |
| 127 | PRCMU_PWMCLK, |
| 128 | PRCMU_IRDACLK, |
| 129 | PRCMU_IRRCCLK, |
| 130 | PRCMU_SIACLK, |
| 131 | PRCMU_SVACLK, |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 132 | PRCMU_ACLK, |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 133 | PRCMU_NUM_REG_CLOCKS, |
| 134 | PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 135 | PRCMU_CDCLK, |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 136 | PRCMU_TIMCLK, |
| 137 | PRCMU_PLLSOC0, |
| 138 | PRCMU_PLLSOC1, |
| 139 | PRCMU_PLLDDR, |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 140 | PRCMU_PLLDSI, |
| 141 | PRCMU_DSI0CLK, |
| 142 | PRCMU_DSI1CLK, |
| 143 | PRCMU_DSI0ESCCLK, |
| 144 | PRCMU_DSI1ESCCLK, |
| 145 | PRCMU_DSI2ESCCLK, |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 146 | }; |
| 147 | |
| 148 | /** |
| 149 | * enum ape_opp - APE OPP states definition |
| 150 | * @APE_OPP_INIT: |
| 151 | * @APE_NO_CHANGE: The APE operating point is unchanged |
| 152 | * @APE_100_OPP: The new APE operating point is ape100opp |
| 153 | * @APE_50_OPP: 50% |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 154 | * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 155 | */ |
| 156 | enum ape_opp { |
| 157 | APE_OPP_INIT = 0x00, |
| 158 | APE_NO_CHANGE = 0x01, |
| 159 | APE_100_OPP = 0x02, |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 160 | APE_50_OPP = 0x03, |
| 161 | APE_50_PARTLY_25_OPP = 0xFF, |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 162 | }; |
| 163 | |
| 164 | /** |
| 165 | * enum arm_opp - ARM OPP states definition |
| 166 | * @ARM_OPP_INIT: |
| 167 | * @ARM_NO_CHANGE: The ARM operating point is unchanged |
| 168 | * @ARM_100_OPP: The new ARM operating point is arm100opp |
| 169 | * @ARM_50_OPP: The new ARM operating point is arm50opp |
| 170 | * @ARM_MAX_OPP: Operating point is "max" (more than 100) |
| 171 | * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 |
| 172 | * @ARM_EXTCLK: The new ARM operating point is armExtClk |
| 173 | */ |
| 174 | enum arm_opp { |
| 175 | ARM_OPP_INIT = 0x00, |
| 176 | ARM_NO_CHANGE = 0x01, |
| 177 | ARM_100_OPP = 0x02, |
| 178 | ARM_50_OPP = 0x03, |
| 179 | ARM_MAX_OPP = 0x04, |
| 180 | ARM_MAX_FREQ100OPP = 0x05, |
| 181 | ARM_EXTCLK = 0x07 |
| 182 | }; |
| 183 | |
| 184 | /** |
| 185 | * enum ddr_opp - DDR OPP states definition |
| 186 | * @DDR_100_OPP: The new DDR operating point is ddr100opp |
| 187 | * @DDR_50_OPP: The new DDR operating point is ddr50opp |
| 188 | * @DDR_25_OPP: The new DDR operating point is ddr25opp |
| 189 | */ |
| 190 | enum ddr_opp { |
| 191 | DDR_100_OPP = 0x00, |
| 192 | DDR_50_OPP = 0x01, |
| 193 | DDR_25_OPP = 0x02, |
| 194 | }; |
| 195 | |
| 196 | /* |
| 197 | * Definitions for controlling ESRAM0 in deep sleep. |
| 198 | */ |
| 199 | #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 |
| 200 | #define ESRAM0_DEEP_SLEEP_STATE_RET 2 |
| 201 | |
| 202 | /** |
| 203 | * enum ddr_pwrst - DDR power states definition |
| 204 | * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged |
| 205 | * @DDR_PWR_STATE_ON: |
| 206 | * @DDR_PWR_STATE_OFFLOWLAT: |
| 207 | * @DDR_PWR_STATE_OFFHIGHLAT: |
| 208 | */ |
| 209 | enum ddr_pwrst { |
| 210 | DDR_PWR_STATE_UNCHANGED = 0x00, |
| 211 | DDR_PWR_STATE_ON = 0x01, |
| 212 | DDR_PWR_STATE_OFFLOWLAT = 0x02, |
| 213 | DDR_PWR_STATE_OFFHIGHLAT = 0x03 |
| 214 | }; |
| 215 | |
| 216 | #include <linux/mfd/db8500-prcmu.h> |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 217 | |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 218 | #if defined(CONFIG_UX500_SOC_DB8500) |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 219 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 220 | #include <mach/id.h> |
| 221 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 222 | static inline void __init prcmu_early_init(void) |
| 223 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 224 | return db8500_prcmu_early_init(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 225 | } |
| 226 | |
| 227 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, |
| 228 | bool keep_ap_pll) |
| 229 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 230 | return db8500_prcmu_set_power_state(state, keep_ulp_clk, |
| 231 | keep_ap_pll); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 232 | } |
| 233 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 234 | static inline u8 prcmu_get_power_state_result(void) |
| 235 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 236 | return db8500_prcmu_get_power_state_result(); |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 237 | } |
| 238 | |
Daniel Lezcano | 485540d | 2012-02-20 12:30:26 +0100 | [diff] [blame] | 239 | static inline int prcmu_gic_decouple(void) |
| 240 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 241 | return db8500_prcmu_gic_decouple(); |
Daniel Lezcano | 485540d | 2012-02-20 12:30:26 +0100 | [diff] [blame] | 242 | } |
| 243 | |
| 244 | static inline int prcmu_gic_recouple(void) |
| 245 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 246 | return db8500_prcmu_gic_recouple(); |
Daniel Lezcano | 485540d | 2012-02-20 12:30:26 +0100 | [diff] [blame] | 247 | } |
| 248 | |
Daniel Lezcano | cc9a0f6 | 2012-02-28 22:46:06 +0100 | [diff] [blame] | 249 | static inline bool prcmu_gic_pending_irq(void) |
| 250 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 251 | return db8500_prcmu_gic_pending_irq(); |
Daniel Lezcano | cc9a0f6 | 2012-02-28 22:46:06 +0100 | [diff] [blame] | 252 | } |
| 253 | |
Daniel Lezcano | 34fe6f1 | 2012-02-28 22:46:09 +0100 | [diff] [blame] | 254 | static inline bool prcmu_is_cpu_in_wfi(int cpu) |
| 255 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 256 | return db8500_prcmu_is_cpu_in_wfi(cpu); |
Daniel Lezcano | 34fe6f1 | 2012-02-28 22:46:09 +0100 | [diff] [blame] | 257 | } |
| 258 | |
Daniel Lezcano | 9f60d33 | 2012-02-28 22:46:07 +0100 | [diff] [blame] | 259 | static inline int prcmu_copy_gic_settings(void) |
| 260 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 261 | return db8500_prcmu_copy_gic_settings(); |
Daniel Lezcano | 9f60d33 | 2012-02-28 22:46:07 +0100 | [diff] [blame] | 262 | } |
| 263 | |
Daniel Lezcano | 9ab492e | 2012-02-28 22:46:08 +0100 | [diff] [blame] | 264 | static inline bool prcmu_pending_irq(void) |
| 265 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 266 | return db8500_prcmu_pending_irq(); |
Daniel Lezcano | 9ab492e | 2012-02-28 22:46:08 +0100 | [diff] [blame] | 267 | } |
| 268 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 269 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) |
| 270 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 271 | return db8500_prcmu_set_epod(epod_id, epod_state); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 272 | } |
| 273 | |
| 274 | static inline void prcmu_enable_wakeups(u32 wakeups) |
| 275 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 276 | db8500_prcmu_enable_wakeups(wakeups); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | static inline void prcmu_disable_wakeups(void) |
| 280 | { |
| 281 | prcmu_enable_wakeups(0); |
| 282 | } |
| 283 | |
| 284 | static inline void prcmu_config_abb_event_readout(u32 abb_events) |
| 285 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 286 | db8500_prcmu_config_abb_event_readout(abb_events); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) |
| 290 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 291 | db8500_prcmu_get_abb_event_buffer(buf); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 292 | } |
| 293 | |
| 294 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); |
| 295 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 296 | int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 297 | |
| 298 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div); |
| 299 | |
| 300 | static inline int prcmu_request_clock(u8 clock, bool enable) |
| 301 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 302 | return db8500_prcmu_request_clock(clock, enable); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 303 | } |
| 304 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 305 | unsigned long prcmu_clock_rate(u8 clock); |
| 306 | long prcmu_round_clock_rate(u8 clock, unsigned long rate); |
| 307 | int prcmu_set_clock_rate(u8 clock, unsigned long rate); |
| 308 | |
| 309 | static inline int prcmu_set_ddr_opp(u8 opp) |
| 310 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 311 | return db8500_prcmu_set_ddr_opp(opp); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 312 | } |
| 313 | static inline int prcmu_get_ddr_opp(void) |
| 314 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 315 | return db8500_prcmu_get_ddr_opp(); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 316 | } |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 317 | |
| 318 | static inline int prcmu_set_arm_opp(u8 opp) |
| 319 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 320 | return db8500_prcmu_set_arm_opp(opp); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | static inline int prcmu_get_arm_opp(void) |
| 324 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 325 | return db8500_prcmu_get_arm_opp(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 326 | } |
| 327 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 328 | static inline int prcmu_set_ape_opp(u8 opp) |
| 329 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 330 | return db8500_prcmu_set_ape_opp(opp); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | static inline int prcmu_get_ape_opp(void) |
| 334 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 335 | return db8500_prcmu_get_ape_opp(); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 336 | } |
| 337 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 338 | static inline void prcmu_system_reset(u16 reset_code) |
| 339 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 340 | return db8500_prcmu_system_reset(reset_code); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 341 | } |
| 342 | |
| 343 | static inline u16 prcmu_get_reset_code(void) |
| 344 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 345 | return db8500_prcmu_get_reset_code(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 346 | } |
| 347 | |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame^] | 348 | int prcmu_ac_wake_req(void); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 349 | void prcmu_ac_sleep_req(void); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 350 | static inline void prcmu_modem_reset(void) |
| 351 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 352 | return db8500_prcmu_modem_reset(); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 353 | } |
| 354 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 355 | static inline bool prcmu_is_ac_wake_requested(void) |
| 356 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 357 | return db8500_prcmu_is_ac_wake_requested(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 358 | } |
| 359 | |
| 360 | static inline int prcmu_set_display_clocks(void) |
| 361 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 362 | return db8500_prcmu_set_display_clocks(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 363 | } |
| 364 | |
| 365 | static inline int prcmu_disable_dsipll(void) |
| 366 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 367 | return db8500_prcmu_disable_dsipll(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | static inline int prcmu_enable_dsipll(void) |
| 371 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 372 | return db8500_prcmu_enable_dsipll(); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 373 | } |
| 374 | |
| 375 | static inline int prcmu_config_esram0_deep_sleep(u8 state) |
| 376 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 377 | return db8500_prcmu_config_esram0_deep_sleep(state); |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 378 | } |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 379 | |
| 380 | static inline int prcmu_config_hotdog(u8 threshold) |
| 381 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 382 | return db8500_prcmu_config_hotdog(threshold); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 383 | } |
| 384 | |
| 385 | static inline int prcmu_config_hotmon(u8 low, u8 high) |
| 386 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 387 | return db8500_prcmu_config_hotmon(low, high); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 388 | } |
| 389 | |
| 390 | static inline int prcmu_start_temp_sense(u16 cycles32k) |
| 391 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 392 | return db8500_prcmu_start_temp_sense(cycles32k); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 393 | } |
| 394 | |
| 395 | static inline int prcmu_stop_temp_sense(void) |
| 396 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 397 | return db8500_prcmu_stop_temp_sense(); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 398 | } |
| 399 | |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 400 | static inline u32 prcmu_read(unsigned int reg) |
| 401 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 402 | return db8500_prcmu_read(reg); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 403 | } |
| 404 | |
| 405 | static inline void prcmu_write(unsigned int reg, u32 value) |
| 406 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 407 | db8500_prcmu_write(reg, value); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) |
| 411 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 412 | db8500_prcmu_write_masked(reg, mask, value); |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 413 | } |
| 414 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 415 | static inline int prcmu_enable_a9wdog(u8 id) |
| 416 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 417 | return db8500_prcmu_enable_a9wdog(id); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 418 | } |
| 419 | |
| 420 | static inline int prcmu_disable_a9wdog(u8 id) |
| 421 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 422 | return db8500_prcmu_disable_a9wdog(id); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 423 | } |
| 424 | |
| 425 | static inline int prcmu_kick_a9wdog(u8 id) |
| 426 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 427 | return db8500_prcmu_kick_a9wdog(id); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 428 | } |
| 429 | |
| 430 | static inline int prcmu_load_a9wdog(u8 id, u32 timeout) |
| 431 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 432 | return db8500_prcmu_load_a9wdog(id, timeout); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 433 | } |
| 434 | |
| 435 | static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) |
| 436 | { |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 437 | return db8500_prcmu_config_a9wdog(num, sleep_auto_off); |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 438 | } |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 439 | #else |
| 440 | |
| 441 | static inline void __init prcmu_early_init(void) {} |
| 442 | |
| 443 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, |
| 444 | bool keep_ap_pll) |
| 445 | { |
| 446 | return 0; |
| 447 | } |
| 448 | |
| 449 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) |
| 450 | { |
| 451 | return 0; |
| 452 | } |
| 453 | |
| 454 | static inline void prcmu_enable_wakeups(u32 wakeups) {} |
| 455 | |
| 456 | static inline void prcmu_disable_wakeups(void) {} |
| 457 | |
| 458 | static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) |
| 459 | { |
| 460 | return -ENOSYS; |
| 461 | } |
| 462 | |
| 463 | static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) |
| 464 | { |
| 465 | return -ENOSYS; |
| 466 | } |
| 467 | |
Mattias Nilsson | 3c3e489 | 2012-03-08 14:02:05 +0100 | [diff] [blame] | 468 | static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, |
| 469 | u8 size) |
| 470 | { |
| 471 | return -ENOSYS; |
| 472 | } |
| 473 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 474 | static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) |
| 475 | { |
| 476 | return 0; |
| 477 | } |
| 478 | |
| 479 | static inline int prcmu_request_clock(u8 clock, bool enable) |
| 480 | { |
| 481 | return 0; |
| 482 | } |
| 483 | |
Mattias Nilsson | 6b6fae2 | 2012-01-13 16:20:28 +0100 | [diff] [blame] | 484 | static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) |
| 485 | { |
| 486 | return 0; |
| 487 | } |
| 488 | |
| 489 | static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) |
| 490 | { |
| 491 | return 0; |
| 492 | } |
| 493 | |
| 494 | static inline unsigned long prcmu_clock_rate(u8 clock) |
| 495 | { |
| 496 | return 0; |
| 497 | } |
| 498 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 499 | static inline int prcmu_set_ape_opp(u8 opp) |
| 500 | { |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | static inline int prcmu_get_ape_opp(void) |
| 505 | { |
| 506 | return APE_100_OPP; |
| 507 | } |
| 508 | |
| 509 | static inline int prcmu_set_arm_opp(u8 opp) |
| 510 | { |
| 511 | return 0; |
| 512 | } |
| 513 | |
| 514 | static inline int prcmu_get_arm_opp(void) |
| 515 | { |
| 516 | return ARM_100_OPP; |
| 517 | } |
| 518 | |
| 519 | static inline int prcmu_set_ddr_opp(u8 opp) |
| 520 | { |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | static inline int prcmu_get_ddr_opp(void) |
| 525 | { |
| 526 | return DDR_100_OPP; |
| 527 | } |
| 528 | |
| 529 | static inline void prcmu_system_reset(u16 reset_code) {} |
| 530 | |
| 531 | static inline u16 prcmu_get_reset_code(void) |
| 532 | { |
| 533 | return 0; |
| 534 | } |
| 535 | |
Arun Murthy | 5261e10 | 2012-05-21 14:28:21 +0530 | [diff] [blame^] | 536 | static inline int prcmu_ac_wake_req(void) |
| 537 | { |
| 538 | return 0; |
| 539 | } |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 540 | |
| 541 | static inline void prcmu_ac_sleep_req(void) {} |
| 542 | |
| 543 | static inline void prcmu_modem_reset(void) {} |
| 544 | |
| 545 | static inline bool prcmu_is_ac_wake_requested(void) |
| 546 | { |
| 547 | return false; |
| 548 | } |
| 549 | |
| 550 | static inline int prcmu_set_display_clocks(void) |
| 551 | { |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | static inline int prcmu_disable_dsipll(void) |
| 556 | { |
| 557 | return 0; |
| 558 | } |
| 559 | |
| 560 | static inline int prcmu_enable_dsipll(void) |
| 561 | { |
| 562 | return 0; |
| 563 | } |
| 564 | |
| 565 | static inline int prcmu_config_esram0_deep_sleep(u8 state) |
| 566 | { |
| 567 | return 0; |
| 568 | } |
| 569 | |
| 570 | static inline void prcmu_config_abb_event_readout(u32 abb_events) {} |
| 571 | |
| 572 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) |
| 573 | { |
| 574 | *buf = NULL; |
| 575 | } |
| 576 | |
Mattias Nilsson | 0508901 | 2012-01-13 16:20:20 +0100 | [diff] [blame] | 577 | static inline int prcmu_config_hotdog(u8 threshold) |
| 578 | { |
| 579 | return 0; |
| 580 | } |
| 581 | |
| 582 | static inline int prcmu_config_hotmon(u8 low, u8 high) |
| 583 | { |
| 584 | return 0; |
| 585 | } |
| 586 | |
| 587 | static inline int prcmu_start_temp_sense(u16 cycles32k) |
| 588 | { |
| 589 | return 0; |
| 590 | } |
| 591 | |
| 592 | static inline int prcmu_stop_temp_sense(void) |
| 593 | { |
| 594 | return 0; |
| 595 | } |
| 596 | |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 597 | static inline u32 prcmu_read(unsigned int reg) |
| 598 | { |
| 599 | return 0; |
| 600 | } |
| 601 | |
| 602 | static inline void prcmu_write(unsigned int reg, u32 value) {} |
| 603 | |
| 604 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} |
| 605 | |
| 606 | #endif |
| 607 | |
| 608 | static inline void prcmu_set(unsigned int reg, u32 bits) |
| 609 | { |
| 610 | prcmu_write_masked(reg, bits, bits); |
| 611 | } |
| 612 | |
| 613 | static inline void prcmu_clear(unsigned int reg, u32 bits) |
| 614 | { |
| 615 | prcmu_write_masked(reg, bits, 0); |
| 616 | } |
| 617 | |
Linus Walleij | dece370 | 2012-04-13 14:01:39 +0200 | [diff] [blame] | 618 | #if defined(CONFIG_UX500_SOC_DB8500) |
Mattias Nilsson | b4a6dbd | 2012-01-13 16:21:00 +0100 | [diff] [blame] | 619 | |
| 620 | /** |
| 621 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. |
| 622 | */ |
| 623 | static inline void prcmu_enable_spi2(void) |
| 624 | { |
| 625 | if (cpu_is_u8500()) |
| 626 | prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); |
| 627 | } |
| 628 | |
| 629 | /** |
| 630 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. |
| 631 | */ |
| 632 | static inline void prcmu_disable_spi2(void) |
| 633 | { |
| 634 | if (cpu_is_u8500()) |
| 635 | prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); |
| 636 | } |
| 637 | |
| 638 | /** |
| 639 | * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD |
| 640 | * and UARTMOD on OtherAlternateC3. |
| 641 | */ |
| 642 | static inline void prcmu_enable_stm_mod_uart(void) |
| 643 | { |
| 644 | if (cpu_is_u8500()) { |
| 645 | prcmu_set(DB8500_PRCM_GPIOCR, |
| 646 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | |
| 647 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | /** |
| 652 | * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD |
| 653 | * and UARTMOD on OtherAlternateC3. |
| 654 | */ |
| 655 | static inline void prcmu_disable_stm_mod_uart(void) |
| 656 | { |
| 657 | if (cpu_is_u8500()) { |
| 658 | prcmu_clear(DB8500_PRCM_GPIOCR, |
| 659 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | |
| 660 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); |
| 661 | } |
| 662 | } |
| 663 | |
| 664 | /** |
| 665 | * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1. |
| 666 | */ |
| 667 | static inline void prcmu_enable_stm_ape(void) |
| 668 | { |
| 669 | if (cpu_is_u8500()) { |
| 670 | prcmu_set(DB8500_PRCM_GPIOCR, |
| 671 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); |
| 672 | } |
| 673 | } |
| 674 | |
| 675 | /** |
| 676 | * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1. |
| 677 | */ |
| 678 | static inline void prcmu_disable_stm_ape(void) |
| 679 | { |
| 680 | if (cpu_is_u8500()) { |
| 681 | prcmu_clear(DB8500_PRCM_GPIOCR, |
| 682 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); |
| 683 | } |
| 684 | } |
| 685 | |
| 686 | #else |
| 687 | |
| 688 | static inline void prcmu_enable_spi2(void) {} |
| 689 | static inline void prcmu_disable_spi2(void) {} |
| 690 | static inline void prcmu_enable_stm_mod_uart(void) {} |
| 691 | static inline void prcmu_disable_stm_mod_uart(void) {} |
| 692 | static inline void prcmu_enable_stm_ape(void) {} |
| 693 | static inline void prcmu_disable_stm_ape(void) {} |
| 694 | |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 695 | #endif |
| 696 | |
| 697 | /* PRCMU QoS APE OPP class */ |
| 698 | #define PRCMU_QOS_APE_OPP 1 |
| 699 | #define PRCMU_QOS_DDR_OPP 2 |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 700 | #define PRCMU_QOS_ARM_OPP 3 |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 701 | #define PRCMU_QOS_DEFAULT_VALUE -1 |
| 702 | |
Mattias Nilsson | 4d64d2e | 2012-01-13 16:20:43 +0100 | [diff] [blame] | 703 | #ifdef CONFIG_DBX500_PRCMU_QOS_POWER |
Mattias Nilsson | fea799e | 2011-08-12 10:28:02 +0200 | [diff] [blame] | 704 | |
| 705 | unsigned long prcmu_qos_get_cpufreq_opp_delay(void); |
| 706 | void prcmu_qos_set_cpufreq_opp_delay(unsigned long); |
| 707 | void prcmu_qos_force_opp(int, s32); |
| 708 | int prcmu_qos_requirement(int pm_qos_class); |
| 709 | int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); |
| 710 | int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); |
| 711 | void prcmu_qos_remove_requirement(int pm_qos_class, char *name); |
| 712 | int prcmu_qos_add_notifier(int prcmu_qos_class, |
| 713 | struct notifier_block *notifier); |
| 714 | int prcmu_qos_remove_notifier(int prcmu_qos_class, |
| 715 | struct notifier_block *notifier); |
| 716 | |
| 717 | #else |
| 718 | |
| 719 | static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) |
| 720 | { |
| 721 | return 0; |
| 722 | } |
| 723 | |
| 724 | static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} |
| 725 | |
| 726 | static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} |
| 727 | |
| 728 | static inline int prcmu_qos_requirement(int prcmu_qos_class) |
| 729 | { |
| 730 | return 0; |
| 731 | } |
| 732 | |
| 733 | static inline int prcmu_qos_add_requirement(int prcmu_qos_class, |
| 734 | char *name, s32 value) |
| 735 | { |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static inline int prcmu_qos_update_requirement(int prcmu_qos_class, |
| 740 | char *name, s32 new_value) |
| 741 | { |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) |
| 746 | { |
| 747 | } |
| 748 | |
| 749 | static inline int prcmu_qos_add_notifier(int prcmu_qos_class, |
| 750 | struct notifier_block *notifier) |
| 751 | { |
| 752 | return 0; |
| 753 | } |
| 754 | static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, |
| 755 | struct notifier_block *notifier) |
| 756 | { |
| 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | #endif |
| 761 | |
| 762 | #endif /* __MACH_PRCMU_H */ |