Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1 | /* |
| 2 | * IOMMU API for ARM architected SMMU implementations. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License |
| 14 | * along with this program; if not, write to the Free Software |
| 15 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 16 | * |
| 17 | * Copyright (C) 2013 ARM Limited |
| 18 | * |
| 19 | * Author: Will Deacon <will.deacon@arm.com> |
| 20 | * |
| 21 | * This driver currently supports: |
| 22 | * - SMMUv1 and v2 implementations |
| 23 | * - Stream-matching and stream-indexing |
| 24 | * - v7/v8 long-descriptor format |
| 25 | * - Non-secure access to the SMMU |
| 26 | * - 4k and 64k pages, with contiguous pte hints. |
| 27 | * - Up to 39-bit addressing |
| 28 | * - Context fault reporting |
| 29 | */ |
| 30 | |
| 31 | #define pr_fmt(fmt) "arm-smmu: " fmt |
| 32 | |
| 33 | #include <linux/delay.h> |
| 34 | #include <linux/dma-mapping.h> |
| 35 | #include <linux/err.h> |
| 36 | #include <linux/interrupt.h> |
| 37 | #include <linux/io.h> |
| 38 | #include <linux/iommu.h> |
| 39 | #include <linux/mm.h> |
| 40 | #include <linux/module.h> |
| 41 | #include <linux/of.h> |
| 42 | #include <linux/platform_device.h> |
| 43 | #include <linux/slab.h> |
| 44 | #include <linux/spinlock.h> |
| 45 | |
| 46 | #include <linux/amba/bus.h> |
| 47 | |
| 48 | #include <asm/pgalloc.h> |
| 49 | |
| 50 | /* Maximum number of stream IDs assigned to a single device */ |
| 51 | #define MAX_MASTER_STREAMIDS 8 |
| 52 | |
| 53 | /* Maximum number of context banks per SMMU */ |
| 54 | #define ARM_SMMU_MAX_CBS 128 |
| 55 | |
| 56 | /* Maximum number of mapping groups per SMMU */ |
| 57 | #define ARM_SMMU_MAX_SMRS 128 |
| 58 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 59 | /* SMMU global address space */ |
| 60 | #define ARM_SMMU_GR0(smmu) ((smmu)->base) |
| 61 | #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize) |
| 62 | |
| 63 | /* Page table bits */ |
| 64 | #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0) |
| 65 | #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52) |
| 66 | #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10) |
| 67 | #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8) |
| 68 | #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8) |
| 69 | #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8) |
| 70 | |
| 71 | #if PAGE_SIZE == SZ_4K |
| 72 | #define ARM_SMMU_PTE_CONT_ENTRIES 16 |
| 73 | #elif PAGE_SIZE == SZ_64K |
| 74 | #define ARM_SMMU_PTE_CONT_ENTRIES 32 |
| 75 | #else |
| 76 | #define ARM_SMMU_PTE_CONT_ENTRIES 1 |
| 77 | #endif |
| 78 | |
| 79 | #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES) |
| 80 | #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1)) |
| 81 | #define ARM_SMMU_PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(pte_t)) |
| 82 | |
| 83 | /* Stage-1 PTE */ |
| 84 | #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6) |
| 85 | #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6) |
| 86 | #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2 |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 87 | #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 88 | |
| 89 | /* Stage-2 PTE */ |
| 90 | #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6) |
| 91 | #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6) |
| 92 | #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6) |
| 93 | #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2) |
| 94 | #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2) |
| 95 | #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2) |
| 96 | |
| 97 | /* Configuration registers */ |
| 98 | #define ARM_SMMU_GR0_sCR0 0x0 |
| 99 | #define sCR0_CLIENTPD (1 << 0) |
| 100 | #define sCR0_GFRE (1 << 1) |
| 101 | #define sCR0_GFIE (1 << 2) |
| 102 | #define sCR0_GCFGFRE (1 << 4) |
| 103 | #define sCR0_GCFGFIE (1 << 5) |
| 104 | #define sCR0_USFCFG (1 << 10) |
| 105 | #define sCR0_VMIDPNE (1 << 11) |
| 106 | #define sCR0_PTM (1 << 12) |
| 107 | #define sCR0_FB (1 << 13) |
| 108 | #define sCR0_BSU_SHIFT 14 |
| 109 | #define sCR0_BSU_MASK 0x3 |
| 110 | |
| 111 | /* Identification registers */ |
| 112 | #define ARM_SMMU_GR0_ID0 0x20 |
| 113 | #define ARM_SMMU_GR0_ID1 0x24 |
| 114 | #define ARM_SMMU_GR0_ID2 0x28 |
| 115 | #define ARM_SMMU_GR0_ID3 0x2c |
| 116 | #define ARM_SMMU_GR0_ID4 0x30 |
| 117 | #define ARM_SMMU_GR0_ID5 0x34 |
| 118 | #define ARM_SMMU_GR0_ID6 0x38 |
| 119 | #define ARM_SMMU_GR0_ID7 0x3c |
| 120 | #define ARM_SMMU_GR0_sGFSR 0x48 |
| 121 | #define ARM_SMMU_GR0_sGFSYNR0 0x50 |
| 122 | #define ARM_SMMU_GR0_sGFSYNR1 0x54 |
| 123 | #define ARM_SMMU_GR0_sGFSYNR2 0x58 |
| 124 | #define ARM_SMMU_GR0_PIDR0 0xfe0 |
| 125 | #define ARM_SMMU_GR0_PIDR1 0xfe4 |
| 126 | #define ARM_SMMU_GR0_PIDR2 0xfe8 |
| 127 | |
| 128 | #define ID0_S1TS (1 << 30) |
| 129 | #define ID0_S2TS (1 << 29) |
| 130 | #define ID0_NTS (1 << 28) |
| 131 | #define ID0_SMS (1 << 27) |
| 132 | #define ID0_PTFS_SHIFT 24 |
| 133 | #define ID0_PTFS_MASK 0x2 |
| 134 | #define ID0_PTFS_V8_ONLY 0x2 |
| 135 | #define ID0_CTTW (1 << 14) |
| 136 | #define ID0_NUMIRPT_SHIFT 16 |
| 137 | #define ID0_NUMIRPT_MASK 0xff |
| 138 | #define ID0_NUMSMRG_SHIFT 0 |
| 139 | #define ID0_NUMSMRG_MASK 0xff |
| 140 | |
| 141 | #define ID1_PAGESIZE (1 << 31) |
| 142 | #define ID1_NUMPAGENDXB_SHIFT 28 |
| 143 | #define ID1_NUMPAGENDXB_MASK 7 |
| 144 | #define ID1_NUMS2CB_SHIFT 16 |
| 145 | #define ID1_NUMS2CB_MASK 0xff |
| 146 | #define ID1_NUMCB_SHIFT 0 |
| 147 | #define ID1_NUMCB_MASK 0xff |
| 148 | |
| 149 | #define ID2_OAS_SHIFT 4 |
| 150 | #define ID2_OAS_MASK 0xf |
| 151 | #define ID2_IAS_SHIFT 0 |
| 152 | #define ID2_IAS_MASK 0xf |
| 153 | #define ID2_UBS_SHIFT 8 |
| 154 | #define ID2_UBS_MASK 0xf |
| 155 | #define ID2_PTFS_4K (1 << 12) |
| 156 | #define ID2_PTFS_16K (1 << 13) |
| 157 | #define ID2_PTFS_64K (1 << 14) |
| 158 | |
| 159 | #define PIDR2_ARCH_SHIFT 4 |
| 160 | #define PIDR2_ARCH_MASK 0xf |
| 161 | |
| 162 | /* Global TLB invalidation */ |
| 163 | #define ARM_SMMU_GR0_STLBIALL 0x60 |
| 164 | #define ARM_SMMU_GR0_TLBIVMID 0x64 |
| 165 | #define ARM_SMMU_GR0_TLBIALLNSNH 0x68 |
| 166 | #define ARM_SMMU_GR0_TLBIALLH 0x6c |
| 167 | #define ARM_SMMU_GR0_sTLBGSYNC 0x70 |
| 168 | #define ARM_SMMU_GR0_sTLBGSTATUS 0x74 |
| 169 | #define sTLBGSTATUS_GSACTIVE (1 << 0) |
| 170 | #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */ |
| 171 | |
| 172 | /* Stream mapping registers */ |
| 173 | #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2)) |
| 174 | #define SMR_VALID (1 << 31) |
| 175 | #define SMR_MASK_SHIFT 16 |
| 176 | #define SMR_MASK_MASK 0x7fff |
| 177 | #define SMR_ID_SHIFT 0 |
| 178 | #define SMR_ID_MASK 0x7fff |
| 179 | |
| 180 | #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2)) |
| 181 | #define S2CR_CBNDX_SHIFT 0 |
| 182 | #define S2CR_CBNDX_MASK 0xff |
| 183 | #define S2CR_TYPE_SHIFT 16 |
| 184 | #define S2CR_TYPE_MASK 0x3 |
| 185 | #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT) |
| 186 | #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT) |
| 187 | #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT) |
| 188 | |
| 189 | /* Context bank attribute registers */ |
| 190 | #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2)) |
| 191 | #define CBAR_VMID_SHIFT 0 |
| 192 | #define CBAR_VMID_MASK 0xff |
| 193 | #define CBAR_S1_MEMATTR_SHIFT 12 |
| 194 | #define CBAR_S1_MEMATTR_MASK 0xf |
| 195 | #define CBAR_S1_MEMATTR_WB 0xf |
| 196 | #define CBAR_TYPE_SHIFT 16 |
| 197 | #define CBAR_TYPE_MASK 0x3 |
| 198 | #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT) |
| 199 | #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT) |
| 200 | #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT) |
| 201 | #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT) |
| 202 | #define CBAR_IRPTNDX_SHIFT 24 |
| 203 | #define CBAR_IRPTNDX_MASK 0xff |
| 204 | |
| 205 | #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2)) |
| 206 | #define CBA2R_RW64_32BIT (0 << 0) |
| 207 | #define CBA2R_RW64_64BIT (1 << 0) |
| 208 | |
| 209 | /* Translation context bank */ |
| 210 | #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1)) |
| 211 | #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize) |
| 212 | |
| 213 | #define ARM_SMMU_CB_SCTLR 0x0 |
| 214 | #define ARM_SMMU_CB_RESUME 0x8 |
| 215 | #define ARM_SMMU_CB_TTBCR2 0x10 |
| 216 | #define ARM_SMMU_CB_TTBR0_LO 0x20 |
| 217 | #define ARM_SMMU_CB_TTBR0_HI 0x24 |
| 218 | #define ARM_SMMU_CB_TTBCR 0x30 |
| 219 | #define ARM_SMMU_CB_S1_MAIR0 0x38 |
| 220 | #define ARM_SMMU_CB_FSR 0x58 |
| 221 | #define ARM_SMMU_CB_FAR_LO 0x60 |
| 222 | #define ARM_SMMU_CB_FAR_HI 0x64 |
| 223 | #define ARM_SMMU_CB_FSYNR0 0x68 |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 224 | #define ARM_SMMU_CB_S1_TLBIASID 0x610 |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 225 | |
| 226 | #define SCTLR_S1_ASIDPNE (1 << 12) |
| 227 | #define SCTLR_CFCFG (1 << 7) |
| 228 | #define SCTLR_CFIE (1 << 6) |
| 229 | #define SCTLR_CFRE (1 << 5) |
| 230 | #define SCTLR_E (1 << 4) |
| 231 | #define SCTLR_AFE (1 << 2) |
| 232 | #define SCTLR_TRE (1 << 1) |
| 233 | #define SCTLR_M (1 << 0) |
| 234 | #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE) |
| 235 | |
| 236 | #define RESUME_RETRY (0 << 0) |
| 237 | #define RESUME_TERMINATE (1 << 0) |
| 238 | |
| 239 | #define TTBCR_EAE (1 << 31) |
| 240 | |
| 241 | #define TTBCR_PASIZE_SHIFT 16 |
| 242 | #define TTBCR_PASIZE_MASK 0x7 |
| 243 | |
| 244 | #define TTBCR_TG0_4K (0 << 14) |
| 245 | #define TTBCR_TG0_64K (1 << 14) |
| 246 | |
| 247 | #define TTBCR_SH0_SHIFT 12 |
| 248 | #define TTBCR_SH0_MASK 0x3 |
| 249 | #define TTBCR_SH_NS 0 |
| 250 | #define TTBCR_SH_OS 2 |
| 251 | #define TTBCR_SH_IS 3 |
| 252 | |
| 253 | #define TTBCR_ORGN0_SHIFT 10 |
| 254 | #define TTBCR_IRGN0_SHIFT 8 |
| 255 | #define TTBCR_RGN_MASK 0x3 |
| 256 | #define TTBCR_RGN_NC 0 |
| 257 | #define TTBCR_RGN_WBWA 1 |
| 258 | #define TTBCR_RGN_WT 2 |
| 259 | #define TTBCR_RGN_WB 3 |
| 260 | |
| 261 | #define TTBCR_SL0_SHIFT 6 |
| 262 | #define TTBCR_SL0_MASK 0x3 |
| 263 | #define TTBCR_SL0_LVL_2 0 |
| 264 | #define TTBCR_SL0_LVL_1 1 |
| 265 | |
| 266 | #define TTBCR_T1SZ_SHIFT 16 |
| 267 | #define TTBCR_T0SZ_SHIFT 0 |
| 268 | #define TTBCR_SZ_MASK 0xf |
| 269 | |
| 270 | #define TTBCR2_SEP_SHIFT 15 |
| 271 | #define TTBCR2_SEP_MASK 0x7 |
| 272 | |
| 273 | #define TTBCR2_PASIZE_SHIFT 0 |
| 274 | #define TTBCR2_PASIZE_MASK 0x7 |
| 275 | |
| 276 | /* Common definitions for PASize and SEP fields */ |
| 277 | #define TTBCR2_ADDR_32 0 |
| 278 | #define TTBCR2_ADDR_36 1 |
| 279 | #define TTBCR2_ADDR_40 2 |
| 280 | #define TTBCR2_ADDR_42 3 |
| 281 | #define TTBCR2_ADDR_44 4 |
| 282 | #define TTBCR2_ADDR_48 5 |
| 283 | |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 284 | #define TTBRn_HI_ASID_SHIFT 16 |
| 285 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 286 | #define MAIR_ATTR_SHIFT(n) ((n) << 3) |
| 287 | #define MAIR_ATTR_MASK 0xff |
| 288 | #define MAIR_ATTR_DEVICE 0x04 |
| 289 | #define MAIR_ATTR_NC 0x44 |
| 290 | #define MAIR_ATTR_WBRWA 0xff |
| 291 | #define MAIR_ATTR_IDX_NC 0 |
| 292 | #define MAIR_ATTR_IDX_CACHE 1 |
| 293 | #define MAIR_ATTR_IDX_DEV 2 |
| 294 | |
| 295 | #define FSR_MULTI (1 << 31) |
| 296 | #define FSR_SS (1 << 30) |
| 297 | #define FSR_UUT (1 << 8) |
| 298 | #define FSR_ASF (1 << 7) |
| 299 | #define FSR_TLBLKF (1 << 6) |
| 300 | #define FSR_TLBMCF (1 << 5) |
| 301 | #define FSR_EF (1 << 4) |
| 302 | #define FSR_PF (1 << 3) |
| 303 | #define FSR_AFF (1 << 2) |
| 304 | #define FSR_TF (1 << 1) |
| 305 | |
| 306 | #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \ |
| 307 | FSR_TLBLKF) |
| 308 | #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \ |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 309 | FSR_EF | FSR_PF | FSR_TF | FSR_IGN) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 310 | |
| 311 | #define FSYNR0_WNR (1 << 4) |
| 312 | |
| 313 | struct arm_smmu_smr { |
| 314 | u8 idx; |
| 315 | u16 mask; |
| 316 | u16 id; |
| 317 | }; |
| 318 | |
| 319 | struct arm_smmu_master { |
| 320 | struct device_node *of_node; |
| 321 | |
| 322 | /* |
| 323 | * The following is specific to the master's position in the |
| 324 | * SMMU chain. |
| 325 | */ |
| 326 | struct rb_node node; |
| 327 | int num_streamids; |
| 328 | u16 streamids[MAX_MASTER_STREAMIDS]; |
| 329 | |
| 330 | /* |
| 331 | * We only need to allocate these on the root SMMU, as we |
| 332 | * configure unmatched streams to bypass translation. |
| 333 | */ |
| 334 | struct arm_smmu_smr *smrs; |
| 335 | }; |
| 336 | |
| 337 | struct arm_smmu_device { |
| 338 | struct device *dev; |
| 339 | struct device_node *parent_of_node; |
| 340 | |
| 341 | void __iomem *base; |
| 342 | unsigned long size; |
| 343 | unsigned long pagesize; |
| 344 | |
| 345 | #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0) |
| 346 | #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1) |
| 347 | #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2) |
| 348 | #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3) |
| 349 | #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4) |
| 350 | u32 features; |
| 351 | int version; |
| 352 | |
| 353 | u32 num_context_banks; |
| 354 | u32 num_s2_context_banks; |
| 355 | DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS); |
| 356 | atomic_t irptndx; |
| 357 | |
| 358 | u32 num_mapping_groups; |
| 359 | DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS); |
| 360 | |
| 361 | unsigned long input_size; |
| 362 | unsigned long s1_output_size; |
| 363 | unsigned long s2_output_size; |
| 364 | |
| 365 | u32 num_global_irqs; |
| 366 | u32 num_context_irqs; |
| 367 | unsigned int *irqs; |
| 368 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 369 | struct list_head list; |
| 370 | struct rb_root masters; |
| 371 | }; |
| 372 | |
| 373 | struct arm_smmu_cfg { |
| 374 | struct arm_smmu_device *smmu; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 375 | u8 cbndx; |
| 376 | u8 irptndx; |
| 377 | u32 cbar; |
| 378 | pgd_t *pgd; |
| 379 | }; |
Dan Carpenter | faea13b7 | 2013-08-21 09:33:30 +0100 | [diff] [blame] | 380 | #define INVALID_IRPTNDX 0xff |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 381 | |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 382 | #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx) |
| 383 | #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1) |
| 384 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 385 | struct arm_smmu_domain { |
| 386 | /* |
| 387 | * A domain can span across multiple, chained SMMUs and requires |
| 388 | * all devices within the domain to follow the same translation |
| 389 | * path. |
| 390 | */ |
| 391 | struct arm_smmu_device *leaf_smmu; |
| 392 | struct arm_smmu_cfg root_cfg; |
| 393 | phys_addr_t output_mask; |
| 394 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 395 | struct mutex lock; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 396 | }; |
| 397 | |
| 398 | static DEFINE_SPINLOCK(arm_smmu_devices_lock); |
| 399 | static LIST_HEAD(arm_smmu_devices); |
| 400 | |
| 401 | static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu, |
| 402 | struct device_node *dev_node) |
| 403 | { |
| 404 | struct rb_node *node = smmu->masters.rb_node; |
| 405 | |
| 406 | while (node) { |
| 407 | struct arm_smmu_master *master; |
| 408 | master = container_of(node, struct arm_smmu_master, node); |
| 409 | |
| 410 | if (dev_node < master->of_node) |
| 411 | node = node->rb_left; |
| 412 | else if (dev_node > master->of_node) |
| 413 | node = node->rb_right; |
| 414 | else |
| 415 | return master; |
| 416 | } |
| 417 | |
| 418 | return NULL; |
| 419 | } |
| 420 | |
| 421 | static int insert_smmu_master(struct arm_smmu_device *smmu, |
| 422 | struct arm_smmu_master *master) |
| 423 | { |
| 424 | struct rb_node **new, *parent; |
| 425 | |
| 426 | new = &smmu->masters.rb_node; |
| 427 | parent = NULL; |
| 428 | while (*new) { |
| 429 | struct arm_smmu_master *this; |
| 430 | this = container_of(*new, struct arm_smmu_master, node); |
| 431 | |
| 432 | parent = *new; |
| 433 | if (master->of_node < this->of_node) |
| 434 | new = &((*new)->rb_left); |
| 435 | else if (master->of_node > this->of_node) |
| 436 | new = &((*new)->rb_right); |
| 437 | else |
| 438 | return -EEXIST; |
| 439 | } |
| 440 | |
| 441 | rb_link_node(&master->node, parent, new); |
| 442 | rb_insert_color(&master->node, &smmu->masters); |
| 443 | return 0; |
| 444 | } |
| 445 | |
| 446 | static int register_smmu_master(struct arm_smmu_device *smmu, |
| 447 | struct device *dev, |
| 448 | struct of_phandle_args *masterspec) |
| 449 | { |
| 450 | int i; |
| 451 | struct arm_smmu_master *master; |
| 452 | |
| 453 | master = find_smmu_master(smmu, masterspec->np); |
| 454 | if (master) { |
| 455 | dev_err(dev, |
| 456 | "rejecting multiple registrations for master device %s\n", |
| 457 | masterspec->np->name); |
| 458 | return -EBUSY; |
| 459 | } |
| 460 | |
| 461 | if (masterspec->args_count > MAX_MASTER_STREAMIDS) { |
| 462 | dev_err(dev, |
| 463 | "reached maximum number (%d) of stream IDs for master device %s\n", |
| 464 | MAX_MASTER_STREAMIDS, masterspec->np->name); |
| 465 | return -ENOSPC; |
| 466 | } |
| 467 | |
| 468 | master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL); |
| 469 | if (!master) |
| 470 | return -ENOMEM; |
| 471 | |
| 472 | master->of_node = masterspec->np; |
| 473 | master->num_streamids = masterspec->args_count; |
| 474 | |
| 475 | for (i = 0; i < master->num_streamids; ++i) |
| 476 | master->streamids[i] = masterspec->args[i]; |
| 477 | |
| 478 | return insert_smmu_master(smmu, master); |
| 479 | } |
| 480 | |
| 481 | static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu) |
| 482 | { |
| 483 | struct arm_smmu_device *parent; |
| 484 | |
| 485 | if (!smmu->parent_of_node) |
| 486 | return NULL; |
| 487 | |
| 488 | spin_lock(&arm_smmu_devices_lock); |
| 489 | list_for_each_entry(parent, &arm_smmu_devices, list) |
| 490 | if (parent->dev->of_node == smmu->parent_of_node) |
| 491 | goto out_unlock; |
| 492 | |
| 493 | parent = NULL; |
| 494 | dev_warn(smmu->dev, |
| 495 | "Failed to find SMMU parent despite parent in DT\n"); |
| 496 | out_unlock: |
| 497 | spin_unlock(&arm_smmu_devices_lock); |
| 498 | return parent; |
| 499 | } |
| 500 | |
| 501 | static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end) |
| 502 | { |
| 503 | int idx; |
| 504 | |
| 505 | do { |
| 506 | idx = find_next_zero_bit(map, end, start); |
| 507 | if (idx == end) |
| 508 | return -ENOSPC; |
| 509 | } while (test_and_set_bit(idx, map)); |
| 510 | |
| 511 | return idx; |
| 512 | } |
| 513 | |
| 514 | static void __arm_smmu_free_bitmap(unsigned long *map, int idx) |
| 515 | { |
| 516 | clear_bit(idx, map); |
| 517 | } |
| 518 | |
| 519 | /* Wait for any pending TLB invalidations to complete */ |
| 520 | static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu) |
| 521 | { |
| 522 | int count = 0; |
| 523 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 524 | |
| 525 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC); |
| 526 | while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS) |
| 527 | & sTLBGSTATUS_GSACTIVE) { |
| 528 | cpu_relax(); |
| 529 | if (++count == TLB_LOOP_TIMEOUT) { |
| 530 | dev_err_ratelimited(smmu->dev, |
| 531 | "TLB sync timed out -- SMMU may be deadlocked\n"); |
| 532 | return; |
| 533 | } |
| 534 | udelay(1); |
| 535 | } |
| 536 | } |
| 537 | |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 538 | static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg) |
| 539 | { |
| 540 | struct arm_smmu_device *smmu = cfg->smmu; |
| 541 | void __iomem *base = ARM_SMMU_GR0(smmu); |
| 542 | bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 543 | |
| 544 | if (stage1) { |
| 545 | base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx); |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 546 | writel_relaxed(ARM_SMMU_CB_ASID(cfg), |
| 547 | base + ARM_SMMU_CB_S1_TLBIASID); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 548 | } else { |
| 549 | base = ARM_SMMU_GR0(smmu); |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 550 | writel_relaxed(ARM_SMMU_CB_VMID(cfg), |
| 551 | base + ARM_SMMU_GR0_TLBIVMID); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 552 | } |
| 553 | |
| 554 | arm_smmu_tlb_sync(smmu); |
| 555 | } |
| 556 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 557 | static irqreturn_t arm_smmu_context_fault(int irq, void *dev) |
| 558 | { |
| 559 | int flags, ret; |
| 560 | u32 fsr, far, fsynr, resume; |
| 561 | unsigned long iova; |
| 562 | struct iommu_domain *domain = dev; |
| 563 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 564 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 565 | struct arm_smmu_device *smmu = root_cfg->smmu; |
| 566 | void __iomem *cb_base; |
| 567 | |
| 568 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); |
| 569 | fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR); |
| 570 | |
| 571 | if (!(fsr & FSR_FAULT)) |
| 572 | return IRQ_NONE; |
| 573 | |
| 574 | if (fsr & FSR_IGN) |
| 575 | dev_err_ratelimited(smmu->dev, |
| 576 | "Unexpected context fault (fsr 0x%u)\n", |
| 577 | fsr); |
| 578 | |
| 579 | fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0); |
| 580 | flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ; |
| 581 | |
| 582 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO); |
| 583 | iova = far; |
| 584 | #ifdef CONFIG_64BIT |
| 585 | far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI); |
| 586 | iova |= ((unsigned long)far << 32); |
| 587 | #endif |
| 588 | |
| 589 | if (!report_iommu_fault(domain, smmu->dev, iova, flags)) { |
| 590 | ret = IRQ_HANDLED; |
| 591 | resume = RESUME_RETRY; |
| 592 | } else { |
Andreas Herrmann | 2ef0f03 | 2013-10-01 13:39:08 +0100 | [diff] [blame] | 593 | dev_err_ratelimited(smmu->dev, |
| 594 | "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n", |
| 595 | iova, fsynr, root_cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 596 | ret = IRQ_NONE; |
| 597 | resume = RESUME_TERMINATE; |
| 598 | } |
| 599 | |
| 600 | /* Clear the faulting FSR */ |
| 601 | writel(fsr, cb_base + ARM_SMMU_CB_FSR); |
| 602 | |
| 603 | /* Retry or terminate any stalled transactions */ |
| 604 | if (fsr & FSR_SS) |
| 605 | writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME); |
| 606 | |
| 607 | return ret; |
| 608 | } |
| 609 | |
| 610 | static irqreturn_t arm_smmu_global_fault(int irq, void *dev) |
| 611 | { |
| 612 | u32 gfsr, gfsynr0, gfsynr1, gfsynr2; |
| 613 | struct arm_smmu_device *smmu = dev; |
| 614 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 615 | |
| 616 | gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 617 | if (!gfsr) |
| 618 | return IRQ_NONE; |
| 619 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 620 | gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0); |
| 621 | gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1); |
| 622 | gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2); |
| 623 | |
| 624 | dev_err_ratelimited(smmu->dev, |
| 625 | "Unexpected global fault, this could be serious\n"); |
| 626 | dev_err_ratelimited(smmu->dev, |
| 627 | "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n", |
| 628 | gfsr, gfsynr0, gfsynr1, gfsynr2); |
| 629 | |
| 630 | writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR); |
Will Deacon | adaba32 | 2013-07-31 19:21:26 +0100 | [diff] [blame] | 631 | return IRQ_HANDLED; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 632 | } |
| 633 | |
| 634 | static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) |
| 635 | { |
| 636 | u32 reg; |
| 637 | bool stage1; |
| 638 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 639 | struct arm_smmu_device *smmu = root_cfg->smmu; |
| 640 | void __iomem *cb_base, *gr0_base, *gr1_base; |
| 641 | |
| 642 | gr0_base = ARM_SMMU_GR0(smmu); |
| 643 | gr1_base = ARM_SMMU_GR1(smmu); |
| 644 | stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS; |
| 645 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); |
| 646 | |
| 647 | /* CBAR */ |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 648 | reg = root_cfg->cbar; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 649 | if (smmu->version == 1) |
| 650 | reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT; |
| 651 | |
| 652 | /* Use the weakest memory type, so it is overridden by the pte */ |
| 653 | if (stage1) |
| 654 | reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 655 | else |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 656 | reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 657 | writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx)); |
| 658 | |
| 659 | if (smmu->version > 1) { |
| 660 | /* CBA2R */ |
| 661 | #ifdef CONFIG_64BIT |
| 662 | reg = CBA2R_RW64_64BIT; |
| 663 | #else |
| 664 | reg = CBA2R_RW64_32BIT; |
| 665 | #endif |
| 666 | writel_relaxed(reg, |
| 667 | gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx)); |
| 668 | |
| 669 | /* TTBCR2 */ |
| 670 | switch (smmu->input_size) { |
| 671 | case 32: |
| 672 | reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT); |
| 673 | break; |
| 674 | case 36: |
| 675 | reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT); |
| 676 | break; |
| 677 | case 39: |
| 678 | reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT); |
| 679 | break; |
| 680 | case 42: |
| 681 | reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT); |
| 682 | break; |
| 683 | case 44: |
| 684 | reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT); |
| 685 | break; |
| 686 | case 48: |
| 687 | reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT); |
| 688 | break; |
| 689 | } |
| 690 | |
| 691 | switch (smmu->s1_output_size) { |
| 692 | case 32: |
| 693 | reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT); |
| 694 | break; |
| 695 | case 36: |
| 696 | reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT); |
| 697 | break; |
| 698 | case 39: |
| 699 | reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT); |
| 700 | break; |
| 701 | case 42: |
| 702 | reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT); |
| 703 | break; |
| 704 | case 44: |
| 705 | reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT); |
| 706 | break; |
| 707 | case 48: |
| 708 | reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT); |
| 709 | break; |
| 710 | } |
| 711 | |
| 712 | if (stage1) |
| 713 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2); |
| 714 | } |
| 715 | |
| 716 | /* TTBR0 */ |
| 717 | reg = __pa(root_cfg->pgd); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 718 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); |
| 719 | reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 720 | if (stage1) |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 721 | reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 722 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 723 | |
| 724 | /* |
| 725 | * TTBCR |
| 726 | * We use long descriptor, with inner-shareable WBWA tables in TTBR0. |
| 727 | */ |
| 728 | if (smmu->version > 1) { |
| 729 | if (PAGE_SIZE == SZ_4K) |
| 730 | reg = TTBCR_TG0_4K; |
| 731 | else |
| 732 | reg = TTBCR_TG0_64K; |
| 733 | |
| 734 | if (!stage1) { |
| 735 | switch (smmu->s2_output_size) { |
| 736 | case 32: |
| 737 | reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT); |
| 738 | break; |
| 739 | case 36: |
| 740 | reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT); |
| 741 | break; |
| 742 | case 40: |
| 743 | reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT); |
| 744 | break; |
| 745 | case 42: |
| 746 | reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT); |
| 747 | break; |
| 748 | case 44: |
| 749 | reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT); |
| 750 | break; |
| 751 | case 48: |
| 752 | reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT); |
| 753 | break; |
| 754 | } |
| 755 | } else { |
| 756 | reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT; |
| 757 | } |
| 758 | } else { |
| 759 | reg = 0; |
| 760 | } |
| 761 | |
| 762 | reg |= TTBCR_EAE | |
| 763 | (TTBCR_SH_IS << TTBCR_SH0_SHIFT) | |
| 764 | (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) | |
| 765 | (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) | |
| 766 | (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT); |
| 767 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR); |
| 768 | |
| 769 | /* MAIR0 (stage-1 only) */ |
| 770 | if (stage1) { |
| 771 | reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) | |
| 772 | (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) | |
| 773 | (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV)); |
| 774 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0); |
| 775 | } |
| 776 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 777 | /* SCTLR */ |
| 778 | reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP; |
| 779 | if (stage1) |
| 780 | reg |= SCTLR_S1_ASIDPNE; |
| 781 | #ifdef __BIG_ENDIAN |
| 782 | reg |= SCTLR_E; |
| 783 | #endif |
Will Deacon | 2572484 | 2013-08-21 13:49:53 +0100 | [diff] [blame] | 784 | writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | static int arm_smmu_init_domain_context(struct iommu_domain *domain, |
| 788 | struct device *dev) |
| 789 | { |
| 790 | int irq, ret, start; |
| 791 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 792 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 793 | struct arm_smmu_device *smmu, *parent; |
| 794 | |
| 795 | /* |
| 796 | * Walk the SMMU chain to find the root device for this chain. |
| 797 | * We assume that no masters have translations which terminate |
| 798 | * early, and therefore check that the root SMMU does indeed have |
| 799 | * a StreamID for the master in question. |
| 800 | */ |
| 801 | parent = dev->archdata.iommu; |
| 802 | smmu_domain->output_mask = -1; |
| 803 | do { |
| 804 | smmu = parent; |
| 805 | smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1; |
| 806 | } while ((parent = find_parent_smmu(smmu))); |
| 807 | |
| 808 | if (!find_smmu_master(smmu, dev->of_node)) { |
| 809 | dev_err(dev, "unable to find root SMMU for device\n"); |
| 810 | return -ENODEV; |
| 811 | } |
| 812 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 813 | if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) { |
| 814 | /* |
| 815 | * We will likely want to change this if/when KVM gets |
| 816 | * involved. |
| 817 | */ |
| 818 | root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
| 819 | start = smmu->num_s2_context_banks; |
| 820 | } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) { |
| 821 | root_cfg->cbar = CBAR_TYPE_S2_TRANS; |
| 822 | start = 0; |
| 823 | } else { |
| 824 | root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS; |
| 825 | start = smmu->num_s2_context_banks; |
| 826 | } |
| 827 | |
| 828 | ret = __arm_smmu_alloc_bitmap(smmu->context_map, start, |
| 829 | smmu->num_context_banks); |
| 830 | if (IS_ERR_VALUE(ret)) |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 831 | return ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 832 | |
| 833 | root_cfg->cbndx = ret; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 834 | if (smmu->version == 1) { |
| 835 | root_cfg->irptndx = atomic_inc_return(&smmu->irptndx); |
| 836 | root_cfg->irptndx %= smmu->num_context_irqs; |
| 837 | } else { |
| 838 | root_cfg->irptndx = root_cfg->cbndx; |
| 839 | } |
| 840 | |
| 841 | irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; |
| 842 | ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED, |
| 843 | "arm-smmu-context-fault", domain); |
| 844 | if (IS_ERR_VALUE(ret)) { |
| 845 | dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", |
| 846 | root_cfg->irptndx, irq); |
Dan Carpenter | faea13b7 | 2013-08-21 09:33:30 +0100 | [diff] [blame] | 847 | root_cfg->irptndx = INVALID_IRPTNDX; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 848 | goto out_free_context; |
| 849 | } |
| 850 | |
| 851 | root_cfg->smmu = smmu; |
| 852 | arm_smmu_init_context_bank(smmu_domain); |
| 853 | return ret; |
| 854 | |
| 855 | out_free_context: |
| 856 | __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 857 | return ret; |
| 858 | } |
| 859 | |
| 860 | static void arm_smmu_destroy_domain_context(struct iommu_domain *domain) |
| 861 | { |
| 862 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 863 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 864 | struct arm_smmu_device *smmu = root_cfg->smmu; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 865 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 866 | int irq; |
| 867 | |
| 868 | if (!smmu) |
| 869 | return; |
| 870 | |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 871 | /* Disable the context bank and nuke the TLB before freeing it. */ |
| 872 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx); |
| 873 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
| 874 | arm_smmu_tlb_inv_context(root_cfg); |
| 875 | |
Dan Carpenter | faea13b7 | 2013-08-21 09:33:30 +0100 | [diff] [blame] | 876 | if (root_cfg->irptndx != INVALID_IRPTNDX) { |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 877 | irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx]; |
| 878 | free_irq(irq, domain); |
| 879 | } |
| 880 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 881 | __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx); |
| 882 | } |
| 883 | |
| 884 | static int arm_smmu_domain_init(struct iommu_domain *domain) |
| 885 | { |
| 886 | struct arm_smmu_domain *smmu_domain; |
| 887 | pgd_t *pgd; |
| 888 | |
| 889 | /* |
| 890 | * Allocate the domain and initialise some of its data structures. |
| 891 | * We can't really do anything meaningful until we've added a |
| 892 | * master. |
| 893 | */ |
| 894 | smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL); |
| 895 | if (!smmu_domain) |
| 896 | return -ENOMEM; |
| 897 | |
| 898 | pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL); |
| 899 | if (!pgd) |
| 900 | goto out_free_domain; |
| 901 | smmu_domain->root_cfg.pgd = pgd; |
| 902 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 903 | mutex_init(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 904 | domain->priv = smmu_domain; |
| 905 | return 0; |
| 906 | |
| 907 | out_free_domain: |
| 908 | kfree(smmu_domain); |
| 909 | return -ENOMEM; |
| 910 | } |
| 911 | |
| 912 | static void arm_smmu_free_ptes(pmd_t *pmd) |
| 913 | { |
| 914 | pgtable_t table = pmd_pgtable(*pmd); |
| 915 | pgtable_page_dtor(table); |
| 916 | __free_page(table); |
| 917 | } |
| 918 | |
| 919 | static void arm_smmu_free_pmds(pud_t *pud) |
| 920 | { |
| 921 | int i; |
| 922 | pmd_t *pmd, *pmd_base = pmd_offset(pud, 0); |
| 923 | |
| 924 | pmd = pmd_base; |
| 925 | for (i = 0; i < PTRS_PER_PMD; ++i) { |
| 926 | if (pmd_none(*pmd)) |
| 927 | continue; |
| 928 | |
| 929 | arm_smmu_free_ptes(pmd); |
| 930 | pmd++; |
| 931 | } |
| 932 | |
| 933 | pmd_free(NULL, pmd_base); |
| 934 | } |
| 935 | |
| 936 | static void arm_smmu_free_puds(pgd_t *pgd) |
| 937 | { |
| 938 | int i; |
| 939 | pud_t *pud, *pud_base = pud_offset(pgd, 0); |
| 940 | |
| 941 | pud = pud_base; |
| 942 | for (i = 0; i < PTRS_PER_PUD; ++i) { |
| 943 | if (pud_none(*pud)) |
| 944 | continue; |
| 945 | |
| 946 | arm_smmu_free_pmds(pud); |
| 947 | pud++; |
| 948 | } |
| 949 | |
| 950 | pud_free(NULL, pud_base); |
| 951 | } |
| 952 | |
| 953 | static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain) |
| 954 | { |
| 955 | int i; |
| 956 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 957 | pgd_t *pgd, *pgd_base = root_cfg->pgd; |
| 958 | |
| 959 | /* |
| 960 | * Recursively free the page tables for this domain. We don't |
| 961 | * care about speculative TLB filling, because the TLB will be |
| 962 | * nuked next time this context bank is re-allocated and no devices |
| 963 | * currently map to these tables. |
| 964 | */ |
| 965 | pgd = pgd_base; |
| 966 | for (i = 0; i < PTRS_PER_PGD; ++i) { |
| 967 | if (pgd_none(*pgd)) |
| 968 | continue; |
| 969 | arm_smmu_free_puds(pgd); |
| 970 | pgd++; |
| 971 | } |
| 972 | |
| 973 | kfree(pgd_base); |
| 974 | } |
| 975 | |
| 976 | static void arm_smmu_domain_destroy(struct iommu_domain *domain) |
| 977 | { |
| 978 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 979 | |
| 980 | /* |
| 981 | * Free the domain resources. We assume that all devices have |
| 982 | * already been detached. |
| 983 | */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 984 | arm_smmu_destroy_domain_context(domain); |
| 985 | arm_smmu_free_pgtables(smmu_domain); |
| 986 | kfree(smmu_domain); |
| 987 | } |
| 988 | |
| 989 | static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu, |
| 990 | struct arm_smmu_master *master) |
| 991 | { |
| 992 | int i; |
| 993 | struct arm_smmu_smr *smrs; |
| 994 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 995 | |
| 996 | if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)) |
| 997 | return 0; |
| 998 | |
| 999 | if (master->smrs) |
| 1000 | return -EEXIST; |
| 1001 | |
| 1002 | smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL); |
| 1003 | if (!smrs) { |
| 1004 | dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n", |
| 1005 | master->num_streamids, master->of_node->name); |
| 1006 | return -ENOMEM; |
| 1007 | } |
| 1008 | |
| 1009 | /* Allocate the SMRs on the root SMMU */ |
| 1010 | for (i = 0; i < master->num_streamids; ++i) { |
| 1011 | int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0, |
| 1012 | smmu->num_mapping_groups); |
| 1013 | if (IS_ERR_VALUE(idx)) { |
| 1014 | dev_err(smmu->dev, "failed to allocate free SMR\n"); |
| 1015 | goto err_free_smrs; |
| 1016 | } |
| 1017 | |
| 1018 | smrs[i] = (struct arm_smmu_smr) { |
| 1019 | .idx = idx, |
| 1020 | .mask = 0, /* We don't currently share SMRs */ |
| 1021 | .id = master->streamids[i], |
| 1022 | }; |
| 1023 | } |
| 1024 | |
| 1025 | /* It worked! Now, poke the actual hardware */ |
| 1026 | for (i = 0; i < master->num_streamids; ++i) { |
| 1027 | u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT | |
| 1028 | smrs[i].mask << SMR_MASK_SHIFT; |
| 1029 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx)); |
| 1030 | } |
| 1031 | |
| 1032 | master->smrs = smrs; |
| 1033 | return 0; |
| 1034 | |
| 1035 | err_free_smrs: |
| 1036 | while (--i >= 0) |
| 1037 | __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx); |
| 1038 | kfree(smrs); |
| 1039 | return -ENOSPC; |
| 1040 | } |
| 1041 | |
| 1042 | static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu, |
| 1043 | struct arm_smmu_master *master) |
| 1044 | { |
| 1045 | int i; |
| 1046 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1047 | struct arm_smmu_smr *smrs = master->smrs; |
| 1048 | |
| 1049 | /* Invalidate the SMRs before freeing back to the allocator */ |
| 1050 | for (i = 0; i < master->num_streamids; ++i) { |
| 1051 | u8 idx = smrs[i].idx; |
| 1052 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx)); |
| 1053 | __arm_smmu_free_bitmap(smmu->smr_map, idx); |
| 1054 | } |
| 1055 | |
| 1056 | master->smrs = NULL; |
| 1057 | kfree(smrs); |
| 1058 | } |
| 1059 | |
| 1060 | static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu, |
| 1061 | struct arm_smmu_master *master) |
| 1062 | { |
| 1063 | int i; |
| 1064 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1065 | |
| 1066 | for (i = 0; i < master->num_streamids; ++i) { |
| 1067 | u16 sid = master->streamids[i]; |
| 1068 | writel_relaxed(S2CR_TYPE_BYPASS, |
| 1069 | gr0_base + ARM_SMMU_GR0_S2CR(sid)); |
| 1070 | } |
| 1071 | } |
| 1072 | |
| 1073 | static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain, |
| 1074 | struct arm_smmu_master *master) |
| 1075 | { |
| 1076 | int i, ret; |
| 1077 | struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu; |
| 1078 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1079 | |
| 1080 | ret = arm_smmu_master_configure_smrs(smmu, master); |
| 1081 | if (ret) |
| 1082 | return ret; |
| 1083 | |
| 1084 | /* Bypass the leaves */ |
| 1085 | smmu = smmu_domain->leaf_smmu; |
| 1086 | while ((parent = find_parent_smmu(smmu))) { |
| 1087 | /* |
| 1088 | * We won't have a StreamID match for anything but the root |
| 1089 | * smmu, so we only need to worry about StreamID indexing, |
| 1090 | * where we must install bypass entries in the S2CRs. |
| 1091 | */ |
| 1092 | if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) |
| 1093 | continue; |
| 1094 | |
| 1095 | arm_smmu_bypass_stream_mapping(smmu, master); |
| 1096 | smmu = parent; |
| 1097 | } |
| 1098 | |
| 1099 | /* Now we're at the root, time to point at our context bank */ |
| 1100 | for (i = 0; i < master->num_streamids; ++i) { |
| 1101 | u32 idx, s2cr; |
| 1102 | idx = master->smrs ? master->smrs[i].idx : master->streamids[i]; |
| 1103 | s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) | |
| 1104 | (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT); |
| 1105 | writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx)); |
| 1106 | } |
| 1107 | |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
| 1111 | static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain, |
| 1112 | struct arm_smmu_master *master) |
| 1113 | { |
| 1114 | struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu; |
| 1115 | |
| 1116 | /* |
| 1117 | * We *must* clear the S2CR first, because freeing the SMR means |
| 1118 | * that it can be re-allocated immediately. |
| 1119 | */ |
| 1120 | arm_smmu_bypass_stream_mapping(smmu, master); |
| 1121 | arm_smmu_master_free_smrs(smmu, master); |
| 1122 | } |
| 1123 | |
| 1124 | static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) |
| 1125 | { |
| 1126 | int ret = -EINVAL; |
| 1127 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1128 | struct arm_smmu_device *device_smmu = dev->archdata.iommu; |
| 1129 | struct arm_smmu_master *master; |
| 1130 | |
| 1131 | if (!device_smmu) { |
| 1132 | dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n"); |
| 1133 | return -ENXIO; |
| 1134 | } |
| 1135 | |
| 1136 | /* |
| 1137 | * Sanity check the domain. We don't currently support domains |
| 1138 | * that cross between different SMMU chains. |
| 1139 | */ |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1140 | mutex_lock(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1141 | if (!smmu_domain->leaf_smmu) { |
| 1142 | /* Now that we have a master, we can finalise the domain */ |
| 1143 | ret = arm_smmu_init_domain_context(domain, dev); |
| 1144 | if (IS_ERR_VALUE(ret)) |
| 1145 | goto err_unlock; |
| 1146 | |
| 1147 | smmu_domain->leaf_smmu = device_smmu; |
| 1148 | } else if (smmu_domain->leaf_smmu != device_smmu) { |
| 1149 | dev_err(dev, |
| 1150 | "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n", |
| 1151 | dev_name(smmu_domain->leaf_smmu->dev), |
| 1152 | dev_name(device_smmu->dev)); |
| 1153 | goto err_unlock; |
| 1154 | } |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1155 | mutex_unlock(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1156 | |
| 1157 | /* Looks ok, so add the device to the domain */ |
| 1158 | master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); |
| 1159 | if (!master) |
| 1160 | return -ENODEV; |
| 1161 | |
| 1162 | return arm_smmu_domain_add_master(smmu_domain, master); |
| 1163 | |
| 1164 | err_unlock: |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1165 | mutex_unlock(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1166 | return ret; |
| 1167 | } |
| 1168 | |
| 1169 | static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev) |
| 1170 | { |
| 1171 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1172 | struct arm_smmu_master *master; |
| 1173 | |
| 1174 | master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node); |
| 1175 | if (master) |
| 1176 | arm_smmu_domain_remove_master(smmu_domain, master); |
| 1177 | } |
| 1178 | |
| 1179 | static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, |
| 1180 | size_t size) |
| 1181 | { |
| 1182 | unsigned long offset = (unsigned long)addr & ~PAGE_MASK; |
| 1183 | |
| 1184 | /* |
| 1185 | * If the SMMU can't walk tables in the CPU caches, treat them |
| 1186 | * like non-coherent DMA since we need to flush the new entries |
| 1187 | * all the way out to memory. There's no possibility of recursion |
| 1188 | * here as the SMMU table walker will not be wired through another |
| 1189 | * SMMU. |
| 1190 | */ |
| 1191 | if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)) |
| 1192 | dma_map_page(smmu->dev, virt_to_page(addr), offset, size, |
| 1193 | DMA_TO_DEVICE); |
| 1194 | } |
| 1195 | |
| 1196 | static bool arm_smmu_pte_is_contiguous_range(unsigned long addr, |
| 1197 | unsigned long end) |
| 1198 | { |
| 1199 | return !(addr & ~ARM_SMMU_PTE_CONT_MASK) && |
| 1200 | (addr + ARM_SMMU_PTE_CONT_SIZE <= end); |
| 1201 | } |
| 1202 | |
| 1203 | static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd, |
| 1204 | unsigned long addr, unsigned long end, |
| 1205 | unsigned long pfn, int flags, int stage) |
| 1206 | { |
| 1207 | pte_t *pte, *start; |
| 1208 | pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF; |
| 1209 | |
| 1210 | if (pmd_none(*pmd)) { |
| 1211 | /* Allocate a new set of tables */ |
| 1212 | pgtable_t table = alloc_page(PGALLOC_GFP); |
| 1213 | if (!table) |
| 1214 | return -ENOMEM; |
| 1215 | |
| 1216 | arm_smmu_flush_pgtable(smmu, page_address(table), |
| 1217 | ARM_SMMU_PTE_HWTABLE_SIZE); |
Kirill A. Shutemov | 01058e7 | 2013-11-14 14:31:49 -0800 | [diff] [blame] | 1218 | if (!pgtable_page_ctor(table)) { |
| 1219 | __free_page(table); |
| 1220 | return -ENOMEM; |
| 1221 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1222 | pmd_populate(NULL, pmd, table); |
| 1223 | arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd)); |
| 1224 | } |
| 1225 | |
| 1226 | if (stage == 1) { |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1227 | pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1228 | if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ)) |
| 1229 | pteval |= ARM_SMMU_PTE_AP_RDONLY; |
| 1230 | |
| 1231 | if (flags & IOMMU_CACHE) |
| 1232 | pteval |= (MAIR_ATTR_IDX_CACHE << |
| 1233 | ARM_SMMU_PTE_ATTRINDX_SHIFT); |
| 1234 | } else { |
| 1235 | pteval |= ARM_SMMU_PTE_HAP_FAULT; |
| 1236 | if (flags & IOMMU_READ) |
| 1237 | pteval |= ARM_SMMU_PTE_HAP_READ; |
| 1238 | if (flags & IOMMU_WRITE) |
| 1239 | pteval |= ARM_SMMU_PTE_HAP_WRITE; |
| 1240 | if (flags & IOMMU_CACHE) |
| 1241 | pteval |= ARM_SMMU_PTE_MEMATTR_OIWB; |
| 1242 | else |
| 1243 | pteval |= ARM_SMMU_PTE_MEMATTR_NC; |
| 1244 | } |
| 1245 | |
| 1246 | /* If no access, create a faulting entry to avoid TLB fills */ |
| 1247 | if (!(flags & (IOMMU_READ | IOMMU_WRITE))) |
| 1248 | pteval &= ~ARM_SMMU_PTE_PAGE; |
| 1249 | |
| 1250 | pteval |= ARM_SMMU_PTE_SH_IS; |
| 1251 | start = pmd_page_vaddr(*pmd) + pte_index(addr); |
| 1252 | pte = start; |
| 1253 | |
| 1254 | /* |
| 1255 | * Install the page table entries. This is fairly complicated |
| 1256 | * since we attempt to make use of the contiguous hint in the |
| 1257 | * ptes where possible. The contiguous hint indicates a series |
| 1258 | * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically |
| 1259 | * contiguous region with the following constraints: |
| 1260 | * |
| 1261 | * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE |
| 1262 | * - Each pte in the region has the contiguous hint bit set |
| 1263 | * |
| 1264 | * This complicates unmapping (also handled by this code, when |
| 1265 | * neither IOMMU_READ or IOMMU_WRITE are set) because it is |
| 1266 | * possible, yet highly unlikely, that a client may unmap only |
| 1267 | * part of a contiguous range. This requires clearing of the |
| 1268 | * contiguous hint bits in the range before installing the new |
| 1269 | * faulting entries. |
| 1270 | * |
| 1271 | * Note that re-mapping an address range without first unmapping |
| 1272 | * it is not supported, so TLB invalidation is not required here |
| 1273 | * and is instead performed at unmap and domain-init time. |
| 1274 | */ |
| 1275 | do { |
| 1276 | int i = 1; |
| 1277 | pteval &= ~ARM_SMMU_PTE_CONT; |
| 1278 | |
| 1279 | if (arm_smmu_pte_is_contiguous_range(addr, end)) { |
| 1280 | i = ARM_SMMU_PTE_CONT_ENTRIES; |
| 1281 | pteval |= ARM_SMMU_PTE_CONT; |
| 1282 | } else if (pte_val(*pte) & |
| 1283 | (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) { |
| 1284 | int j; |
| 1285 | pte_t *cont_start; |
| 1286 | unsigned long idx = pte_index(addr); |
| 1287 | |
| 1288 | idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1); |
| 1289 | cont_start = pmd_page_vaddr(*pmd) + idx; |
| 1290 | for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j) |
| 1291 | pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT; |
| 1292 | |
| 1293 | arm_smmu_flush_pgtable(smmu, cont_start, |
| 1294 | sizeof(*pte) * |
| 1295 | ARM_SMMU_PTE_CONT_ENTRIES); |
| 1296 | } |
| 1297 | |
| 1298 | do { |
| 1299 | *pte = pfn_pte(pfn, __pgprot(pteval)); |
| 1300 | } while (pte++, pfn++, addr += PAGE_SIZE, --i); |
| 1301 | } while (addr != end); |
| 1302 | |
| 1303 | arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start)); |
| 1304 | return 0; |
| 1305 | } |
| 1306 | |
| 1307 | static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud, |
| 1308 | unsigned long addr, unsigned long end, |
| 1309 | phys_addr_t phys, int flags, int stage) |
| 1310 | { |
| 1311 | int ret; |
| 1312 | pmd_t *pmd; |
| 1313 | unsigned long next, pfn = __phys_to_pfn(phys); |
| 1314 | |
| 1315 | #ifndef __PAGETABLE_PMD_FOLDED |
| 1316 | if (pud_none(*pud)) { |
| 1317 | pmd = pmd_alloc_one(NULL, addr); |
| 1318 | if (!pmd) |
| 1319 | return -ENOMEM; |
| 1320 | } else |
| 1321 | #endif |
| 1322 | pmd = pmd_offset(pud, addr); |
| 1323 | |
| 1324 | do { |
| 1325 | next = pmd_addr_end(addr, end); |
| 1326 | ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn, |
| 1327 | flags, stage); |
| 1328 | pud_populate(NULL, pud, pmd); |
| 1329 | arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud)); |
| 1330 | phys += next - addr; |
| 1331 | } while (pmd++, addr = next, addr < end); |
| 1332 | |
| 1333 | return ret; |
| 1334 | } |
| 1335 | |
| 1336 | static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd, |
| 1337 | unsigned long addr, unsigned long end, |
| 1338 | phys_addr_t phys, int flags, int stage) |
| 1339 | { |
| 1340 | int ret = 0; |
| 1341 | pud_t *pud; |
| 1342 | unsigned long next; |
| 1343 | |
| 1344 | #ifndef __PAGETABLE_PUD_FOLDED |
| 1345 | if (pgd_none(*pgd)) { |
| 1346 | pud = pud_alloc_one(NULL, addr); |
| 1347 | if (!pud) |
| 1348 | return -ENOMEM; |
| 1349 | } else |
| 1350 | #endif |
| 1351 | pud = pud_offset(pgd, addr); |
| 1352 | |
| 1353 | do { |
| 1354 | next = pud_addr_end(addr, end); |
| 1355 | ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys, |
| 1356 | flags, stage); |
| 1357 | pgd_populate(NULL, pud, pgd); |
| 1358 | arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd)); |
| 1359 | phys += next - addr; |
| 1360 | } while (pud++, addr = next, addr < end); |
| 1361 | |
| 1362 | return ret; |
| 1363 | } |
| 1364 | |
| 1365 | static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain, |
| 1366 | unsigned long iova, phys_addr_t paddr, |
| 1367 | size_t size, int flags) |
| 1368 | { |
| 1369 | int ret, stage; |
| 1370 | unsigned long end; |
| 1371 | phys_addr_t input_mask, output_mask; |
| 1372 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
| 1373 | pgd_t *pgd = root_cfg->pgd; |
| 1374 | struct arm_smmu_device *smmu = root_cfg->smmu; |
| 1375 | |
| 1376 | if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) { |
| 1377 | stage = 2; |
| 1378 | output_mask = (1ULL << smmu->s2_output_size) - 1; |
| 1379 | } else { |
| 1380 | stage = 1; |
| 1381 | output_mask = (1ULL << smmu->s1_output_size) - 1; |
| 1382 | } |
| 1383 | |
| 1384 | if (!pgd) |
| 1385 | return -EINVAL; |
| 1386 | |
| 1387 | if (size & ~PAGE_MASK) |
| 1388 | return -EINVAL; |
| 1389 | |
| 1390 | input_mask = (1ULL << smmu->input_size) - 1; |
| 1391 | if ((phys_addr_t)iova & ~input_mask) |
| 1392 | return -ERANGE; |
| 1393 | |
| 1394 | if (paddr & ~output_mask) |
| 1395 | return -ERANGE; |
| 1396 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1397 | mutex_lock(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1398 | pgd += pgd_index(iova); |
| 1399 | end = iova + size; |
| 1400 | do { |
| 1401 | unsigned long next = pgd_addr_end(iova, end); |
| 1402 | |
| 1403 | ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr, |
| 1404 | flags, stage); |
| 1405 | if (ret) |
| 1406 | goto out_unlock; |
| 1407 | |
| 1408 | paddr += next - iova; |
| 1409 | iova = next; |
| 1410 | } while (pgd++, iova != end); |
| 1411 | |
| 1412 | out_unlock: |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1413 | mutex_unlock(&smmu_domain->lock); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1414 | |
| 1415 | /* Ensure new page tables are visible to the hardware walker */ |
| 1416 | if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) |
| 1417 | dsb(); |
| 1418 | |
| 1419 | return ret; |
| 1420 | } |
| 1421 | |
| 1422 | static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova, |
| 1423 | phys_addr_t paddr, size_t size, int flags) |
| 1424 | { |
| 1425 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1426 | |
Will Deacon | 5552ecd | 2013-11-08 15:08:06 +0000 | [diff] [blame] | 1427 | if (!smmu_domain) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1428 | return -ENODEV; |
| 1429 | |
| 1430 | /* Check for silent address truncation up the SMMU chain. */ |
| 1431 | if ((phys_addr_t)iova & ~smmu_domain->output_mask) |
| 1432 | return -ERANGE; |
| 1433 | |
| 1434 | return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags); |
| 1435 | } |
| 1436 | |
| 1437 | static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova, |
| 1438 | size_t size) |
| 1439 | { |
| 1440 | int ret; |
| 1441 | struct arm_smmu_domain *smmu_domain = domain->priv; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1442 | |
| 1443 | ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0); |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1444 | arm_smmu_tlb_inv_context(&smmu_domain->root_cfg); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1445 | return ret ? ret : size; |
| 1446 | } |
| 1447 | |
| 1448 | static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, |
| 1449 | dma_addr_t iova) |
| 1450 | { |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1451 | pgd_t *pgdp, pgd; |
| 1452 | pud_t pud; |
| 1453 | pmd_t pmd; |
| 1454 | pte_t pte; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1455 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1456 | struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1457 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1458 | pgdp = root_cfg->pgd; |
| 1459 | if (!pgdp) |
| 1460 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1461 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1462 | pgd = *(pgdp + pgd_index(iova)); |
| 1463 | if (pgd_none(pgd)) |
| 1464 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1465 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1466 | pud = *pud_offset(&pgd, iova); |
| 1467 | if (pud_none(pud)) |
| 1468 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1469 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1470 | pmd = *pmd_offset(&pud, iova); |
| 1471 | if (pmd_none(pmd)) |
| 1472 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1473 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1474 | pte = *(pmd_page_vaddr(pmd) + pte_index(iova)); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1475 | if (pte_none(pte)) |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1476 | return 0; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1477 | |
Will Deacon | a44a979 | 2013-11-07 18:47:50 +0000 | [diff] [blame] | 1478 | return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1479 | } |
| 1480 | |
| 1481 | static int arm_smmu_domain_has_cap(struct iommu_domain *domain, |
| 1482 | unsigned long cap) |
| 1483 | { |
| 1484 | unsigned long caps = 0; |
| 1485 | struct arm_smmu_domain *smmu_domain = domain->priv; |
| 1486 | |
| 1487 | if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) |
| 1488 | caps |= IOMMU_CAP_CACHE_COHERENCY; |
| 1489 | |
| 1490 | return !!(cap & caps); |
| 1491 | } |
| 1492 | |
| 1493 | static int arm_smmu_add_device(struct device *dev) |
| 1494 | { |
| 1495 | struct arm_smmu_device *child, *parent, *smmu; |
| 1496 | struct arm_smmu_master *master = NULL; |
| 1497 | |
| 1498 | spin_lock(&arm_smmu_devices_lock); |
| 1499 | list_for_each_entry(parent, &arm_smmu_devices, list) { |
| 1500 | smmu = parent; |
| 1501 | |
| 1502 | /* Try to find a child of the current SMMU. */ |
| 1503 | list_for_each_entry(child, &arm_smmu_devices, list) { |
| 1504 | if (child->parent_of_node == parent->dev->of_node) { |
| 1505 | /* Does the child sit above our master? */ |
| 1506 | master = find_smmu_master(child, dev->of_node); |
| 1507 | if (master) { |
| 1508 | smmu = NULL; |
| 1509 | break; |
| 1510 | } |
| 1511 | } |
| 1512 | } |
| 1513 | |
| 1514 | /* We found some children, so keep searching. */ |
| 1515 | if (!smmu) { |
| 1516 | master = NULL; |
| 1517 | continue; |
| 1518 | } |
| 1519 | |
| 1520 | master = find_smmu_master(smmu, dev->of_node); |
| 1521 | if (master) |
| 1522 | break; |
| 1523 | } |
| 1524 | spin_unlock(&arm_smmu_devices_lock); |
| 1525 | |
| 1526 | if (!master) |
| 1527 | return -ENODEV; |
| 1528 | |
| 1529 | dev->archdata.iommu = smmu; |
| 1530 | return 0; |
| 1531 | } |
| 1532 | |
| 1533 | static void arm_smmu_remove_device(struct device *dev) |
| 1534 | { |
| 1535 | dev->archdata.iommu = NULL; |
| 1536 | } |
| 1537 | |
| 1538 | static struct iommu_ops arm_smmu_ops = { |
| 1539 | .domain_init = arm_smmu_domain_init, |
| 1540 | .domain_destroy = arm_smmu_domain_destroy, |
| 1541 | .attach_dev = arm_smmu_attach_dev, |
| 1542 | .detach_dev = arm_smmu_detach_dev, |
| 1543 | .map = arm_smmu_map, |
| 1544 | .unmap = arm_smmu_unmap, |
| 1545 | .iova_to_phys = arm_smmu_iova_to_phys, |
| 1546 | .domain_has_cap = arm_smmu_domain_has_cap, |
| 1547 | .add_device = arm_smmu_add_device, |
| 1548 | .remove_device = arm_smmu_remove_device, |
| 1549 | .pgsize_bitmap = (SECTION_SIZE | |
| 1550 | ARM_SMMU_PTE_CONT_SIZE | |
| 1551 | PAGE_SIZE), |
| 1552 | }; |
| 1553 | |
| 1554 | static void arm_smmu_device_reset(struct arm_smmu_device *smmu) |
| 1555 | { |
| 1556 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1557 | void __iomem *cb_base; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1558 | int i = 0; |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1559 | u32 reg; |
| 1560 | |
| 1561 | /* Clear Global FSR */ |
| 1562 | reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR); |
| 1563 | writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1564 | |
| 1565 | /* Mark all SMRn as invalid and all S2CRn as bypass */ |
| 1566 | for (i = 0; i < smmu->num_mapping_groups; ++i) { |
| 1567 | writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i)); |
| 1568 | writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i)); |
| 1569 | } |
| 1570 | |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1571 | /* Make sure all context banks are disabled and clear CB_FSR */ |
| 1572 | for (i = 0; i < smmu->num_context_banks; ++i) { |
| 1573 | cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i); |
| 1574 | writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR); |
| 1575 | writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR); |
| 1576 | } |
Will Deacon | 1463fe4 | 2013-07-31 19:21:27 +0100 | [diff] [blame] | 1577 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1578 | /* Invalidate the TLB, just in case */ |
| 1579 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL); |
| 1580 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH); |
| 1581 | writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH); |
| 1582 | |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1583 | reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0); |
| 1584 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1585 | /* Enable fault reporting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1586 | reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1587 | |
| 1588 | /* Disable TLB broadcasting. */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1589 | reg |= (sCR0_VMIDPNE | sCR0_PTM); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1590 | |
| 1591 | /* Enable client access, but bypass when no mapping is found */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1592 | reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1593 | |
| 1594 | /* Disable forced broadcasting */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1595 | reg &= ~sCR0_FB; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1596 | |
| 1597 | /* Don't upgrade barriers */ |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1598 | reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1599 | |
| 1600 | /* Push the button */ |
| 1601 | arm_smmu_tlb_sync(smmu); |
Andreas Herrmann | 659db6f | 2013-10-01 13:39:09 +0100 | [diff] [blame] | 1602 | writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1603 | } |
| 1604 | |
| 1605 | static int arm_smmu_id_size_to_bits(int size) |
| 1606 | { |
| 1607 | switch (size) { |
| 1608 | case 0: |
| 1609 | return 32; |
| 1610 | case 1: |
| 1611 | return 36; |
| 1612 | case 2: |
| 1613 | return 40; |
| 1614 | case 3: |
| 1615 | return 42; |
| 1616 | case 4: |
| 1617 | return 44; |
| 1618 | case 5: |
| 1619 | default: |
| 1620 | return 48; |
| 1621 | } |
| 1622 | } |
| 1623 | |
| 1624 | static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) |
| 1625 | { |
| 1626 | unsigned long size; |
| 1627 | void __iomem *gr0_base = ARM_SMMU_GR0(smmu); |
| 1628 | u32 id; |
| 1629 | |
| 1630 | dev_notice(smmu->dev, "probing hardware configuration...\n"); |
| 1631 | |
| 1632 | /* Primecell ID */ |
| 1633 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2); |
| 1634 | smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1; |
| 1635 | dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version); |
| 1636 | |
| 1637 | /* ID0 */ |
| 1638 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0); |
| 1639 | #ifndef CONFIG_64BIT |
| 1640 | if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) { |
| 1641 | dev_err(smmu->dev, "\tno v7 descriptor support!\n"); |
| 1642 | return -ENODEV; |
| 1643 | } |
| 1644 | #endif |
| 1645 | if (id & ID0_S1TS) { |
| 1646 | smmu->features |= ARM_SMMU_FEAT_TRANS_S1; |
| 1647 | dev_notice(smmu->dev, "\tstage 1 translation\n"); |
| 1648 | } |
| 1649 | |
| 1650 | if (id & ID0_S2TS) { |
| 1651 | smmu->features |= ARM_SMMU_FEAT_TRANS_S2; |
| 1652 | dev_notice(smmu->dev, "\tstage 2 translation\n"); |
| 1653 | } |
| 1654 | |
| 1655 | if (id & ID0_NTS) { |
| 1656 | smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; |
| 1657 | dev_notice(smmu->dev, "\tnested translation\n"); |
| 1658 | } |
| 1659 | |
| 1660 | if (!(smmu->features & |
| 1661 | (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 | |
| 1662 | ARM_SMMU_FEAT_TRANS_NESTED))) { |
| 1663 | dev_err(smmu->dev, "\tno translation support!\n"); |
| 1664 | return -ENODEV; |
| 1665 | } |
| 1666 | |
| 1667 | if (id & ID0_CTTW) { |
| 1668 | smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; |
| 1669 | dev_notice(smmu->dev, "\tcoherent table walk\n"); |
| 1670 | } |
| 1671 | |
| 1672 | if (id & ID0_SMS) { |
| 1673 | u32 smr, sid, mask; |
| 1674 | |
| 1675 | smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; |
| 1676 | smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) & |
| 1677 | ID0_NUMSMRG_MASK; |
| 1678 | if (smmu->num_mapping_groups == 0) { |
| 1679 | dev_err(smmu->dev, |
| 1680 | "stream-matching supported, but no SMRs present!\n"); |
| 1681 | return -ENODEV; |
| 1682 | } |
| 1683 | |
| 1684 | smr = SMR_MASK_MASK << SMR_MASK_SHIFT; |
| 1685 | smr |= (SMR_ID_MASK << SMR_ID_SHIFT); |
| 1686 | writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0)); |
| 1687 | smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0)); |
| 1688 | |
| 1689 | mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK; |
| 1690 | sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK; |
| 1691 | if ((mask & sid) != sid) { |
| 1692 | dev_err(smmu->dev, |
| 1693 | "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n", |
| 1694 | mask, sid); |
| 1695 | return -ENODEV; |
| 1696 | } |
| 1697 | |
| 1698 | dev_notice(smmu->dev, |
| 1699 | "\tstream matching with %u register groups, mask 0x%x", |
| 1700 | smmu->num_mapping_groups, mask); |
| 1701 | } |
| 1702 | |
| 1703 | /* ID1 */ |
| 1704 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1); |
| 1705 | smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K; |
| 1706 | |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 1707 | /* Check for size mismatch of SMMU address space from mapped region */ |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1708 | size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1); |
| 1709 | size *= (smmu->pagesize << 1); |
Andreas Herrmann | c55af7f | 2013-10-01 13:39:06 +0100 | [diff] [blame] | 1710 | if (smmu->size != size) |
| 1711 | dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs " |
| 1712 | "from mapped region size (0x%lx)!\n", size, smmu->size); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1713 | |
| 1714 | smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & |
| 1715 | ID1_NUMS2CB_MASK; |
| 1716 | smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK; |
| 1717 | if (smmu->num_s2_context_banks > smmu->num_context_banks) { |
| 1718 | dev_err(smmu->dev, "impossible number of S2 context banks!\n"); |
| 1719 | return -ENODEV; |
| 1720 | } |
| 1721 | dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", |
| 1722 | smmu->num_context_banks, smmu->num_s2_context_banks); |
| 1723 | |
| 1724 | /* ID2 */ |
| 1725 | id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2); |
| 1726 | size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK); |
| 1727 | |
| 1728 | /* |
| 1729 | * Stage-1 output limited by stage-2 input size due to pgd |
| 1730 | * allocation (PTRS_PER_PGD). |
| 1731 | */ |
| 1732 | #ifdef CONFIG_64BIT |
| 1733 | /* Current maximum output size of 39 bits */ |
| 1734 | smmu->s1_output_size = min(39UL, size); |
| 1735 | #else |
| 1736 | smmu->s1_output_size = min(32UL, size); |
| 1737 | #endif |
| 1738 | |
| 1739 | /* The stage-2 output mask is also applied for bypass */ |
| 1740 | size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK); |
| 1741 | smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size); |
| 1742 | |
| 1743 | if (smmu->version == 1) { |
| 1744 | smmu->input_size = 32; |
| 1745 | } else { |
| 1746 | #ifdef CONFIG_64BIT |
| 1747 | size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK; |
| 1748 | size = min(39, arm_smmu_id_size_to_bits(size)); |
| 1749 | #else |
| 1750 | size = 32; |
| 1751 | #endif |
| 1752 | smmu->input_size = size; |
| 1753 | |
| 1754 | if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) || |
| 1755 | (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) || |
| 1756 | (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) { |
| 1757 | dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n", |
| 1758 | PAGE_SIZE); |
| 1759 | return -ENODEV; |
| 1760 | } |
| 1761 | } |
| 1762 | |
| 1763 | dev_notice(smmu->dev, |
| 1764 | "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n", |
| 1765 | smmu->input_size, smmu->s1_output_size, smmu->s2_output_size); |
| 1766 | return 0; |
| 1767 | } |
| 1768 | |
| 1769 | static int arm_smmu_device_dt_probe(struct platform_device *pdev) |
| 1770 | { |
| 1771 | struct resource *res; |
| 1772 | struct arm_smmu_device *smmu; |
| 1773 | struct device_node *dev_node; |
| 1774 | struct device *dev = &pdev->dev; |
| 1775 | struct rb_node *node; |
| 1776 | struct of_phandle_args masterspec; |
| 1777 | int num_irqs, i, err; |
| 1778 | |
| 1779 | smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); |
| 1780 | if (!smmu) { |
| 1781 | dev_err(dev, "failed to allocate arm_smmu_device\n"); |
| 1782 | return -ENOMEM; |
| 1783 | } |
| 1784 | smmu->dev = dev; |
| 1785 | |
| 1786 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Julia Lawall | 8a7f431 | 2013-08-19 12:20:37 +0100 | [diff] [blame] | 1787 | smmu->base = devm_ioremap_resource(dev, res); |
| 1788 | if (IS_ERR(smmu->base)) |
| 1789 | return PTR_ERR(smmu->base); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1790 | smmu->size = resource_size(res); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1791 | |
| 1792 | if (of_property_read_u32(dev->of_node, "#global-interrupts", |
| 1793 | &smmu->num_global_irqs)) { |
| 1794 | dev_err(dev, "missing #global-interrupts property\n"); |
| 1795 | return -ENODEV; |
| 1796 | } |
| 1797 | |
| 1798 | num_irqs = 0; |
| 1799 | while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) { |
| 1800 | num_irqs++; |
| 1801 | if (num_irqs > smmu->num_global_irqs) |
| 1802 | smmu->num_context_irqs++; |
| 1803 | } |
| 1804 | |
Andreas Herrmann | 44a08de | 2013-10-01 13:39:07 +0100 | [diff] [blame] | 1805 | if (!smmu->num_context_irqs) { |
| 1806 | dev_err(dev, "found %d interrupts but expected at least %d\n", |
| 1807 | num_irqs, smmu->num_global_irqs + 1); |
| 1808 | return -ENODEV; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1809 | } |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1810 | |
| 1811 | smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs, |
| 1812 | GFP_KERNEL); |
| 1813 | if (!smmu->irqs) { |
| 1814 | dev_err(dev, "failed to allocate %d irqs\n", num_irqs); |
| 1815 | return -ENOMEM; |
| 1816 | } |
| 1817 | |
| 1818 | for (i = 0; i < num_irqs; ++i) { |
| 1819 | int irq = platform_get_irq(pdev, i); |
| 1820 | if (irq < 0) { |
| 1821 | dev_err(dev, "failed to get irq index %d\n", i); |
| 1822 | return -ENODEV; |
| 1823 | } |
| 1824 | smmu->irqs[i] = irq; |
| 1825 | } |
| 1826 | |
| 1827 | i = 0; |
| 1828 | smmu->masters = RB_ROOT; |
| 1829 | while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters", |
| 1830 | "#stream-id-cells", i, |
| 1831 | &masterspec)) { |
| 1832 | err = register_smmu_master(smmu, dev, &masterspec); |
| 1833 | if (err) { |
| 1834 | dev_err(dev, "failed to add master %s\n", |
| 1835 | masterspec.np->name); |
| 1836 | goto out_put_masters; |
| 1837 | } |
| 1838 | |
| 1839 | i++; |
| 1840 | } |
| 1841 | dev_notice(dev, "registered %d master devices\n", i); |
| 1842 | |
| 1843 | if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0))) |
| 1844 | smmu->parent_of_node = dev_node; |
| 1845 | |
| 1846 | err = arm_smmu_device_cfg_probe(smmu); |
| 1847 | if (err) |
| 1848 | goto out_put_parent; |
| 1849 | |
| 1850 | if (smmu->version > 1 && |
| 1851 | smmu->num_context_banks != smmu->num_context_irqs) { |
| 1852 | dev_err(dev, |
| 1853 | "found only %d context interrupt(s) but %d required\n", |
| 1854 | smmu->num_context_irqs, smmu->num_context_banks); |
Wei Yongjun | 89a23cd | 2013-11-15 09:42:30 +0000 | [diff] [blame] | 1855 | err = -ENODEV; |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1856 | goto out_put_parent; |
| 1857 | } |
| 1858 | |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1859 | for (i = 0; i < smmu->num_global_irqs; ++i) { |
| 1860 | err = request_irq(smmu->irqs[i], |
| 1861 | arm_smmu_global_fault, |
| 1862 | IRQF_SHARED, |
| 1863 | "arm-smmu global fault", |
| 1864 | smmu); |
| 1865 | if (err) { |
| 1866 | dev_err(dev, "failed to request global IRQ %d (%u)\n", |
| 1867 | i, smmu->irqs[i]); |
| 1868 | goto out_free_irqs; |
| 1869 | } |
| 1870 | } |
| 1871 | |
| 1872 | INIT_LIST_HEAD(&smmu->list); |
| 1873 | spin_lock(&arm_smmu_devices_lock); |
| 1874 | list_add(&smmu->list, &arm_smmu_devices); |
| 1875 | spin_unlock(&arm_smmu_devices_lock); |
Will Deacon | fd90cec | 2013-08-21 13:56:34 +0100 | [diff] [blame] | 1876 | |
| 1877 | arm_smmu_device_reset(smmu); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1878 | return 0; |
| 1879 | |
| 1880 | out_free_irqs: |
| 1881 | while (i--) |
| 1882 | free_irq(smmu->irqs[i], smmu); |
| 1883 | |
| 1884 | out_put_parent: |
| 1885 | if (smmu->parent_of_node) |
| 1886 | of_node_put(smmu->parent_of_node); |
| 1887 | |
| 1888 | out_put_masters: |
| 1889 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
| 1890 | struct arm_smmu_master *master; |
| 1891 | master = container_of(node, struct arm_smmu_master, node); |
| 1892 | of_node_put(master->of_node); |
| 1893 | } |
| 1894 | |
| 1895 | return err; |
| 1896 | } |
| 1897 | |
| 1898 | static int arm_smmu_device_remove(struct platform_device *pdev) |
| 1899 | { |
| 1900 | int i; |
| 1901 | struct device *dev = &pdev->dev; |
| 1902 | struct arm_smmu_device *curr, *smmu = NULL; |
| 1903 | struct rb_node *node; |
| 1904 | |
| 1905 | spin_lock(&arm_smmu_devices_lock); |
| 1906 | list_for_each_entry(curr, &arm_smmu_devices, list) { |
| 1907 | if (curr->dev == dev) { |
| 1908 | smmu = curr; |
| 1909 | list_del(&smmu->list); |
| 1910 | break; |
| 1911 | } |
| 1912 | } |
| 1913 | spin_unlock(&arm_smmu_devices_lock); |
| 1914 | |
| 1915 | if (!smmu) |
| 1916 | return -ENODEV; |
| 1917 | |
| 1918 | if (smmu->parent_of_node) |
| 1919 | of_node_put(smmu->parent_of_node); |
| 1920 | |
| 1921 | for (node = rb_first(&smmu->masters); node; node = rb_next(node)) { |
| 1922 | struct arm_smmu_master *master; |
| 1923 | master = container_of(node, struct arm_smmu_master, node); |
| 1924 | of_node_put(master->of_node); |
| 1925 | } |
| 1926 | |
Will Deacon | ecfadb6 | 2013-07-31 19:21:28 +0100 | [diff] [blame] | 1927 | if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1928 | dev_err(dev, "removing device with active domains!\n"); |
| 1929 | |
| 1930 | for (i = 0; i < smmu->num_global_irqs; ++i) |
| 1931 | free_irq(smmu->irqs[i], smmu); |
| 1932 | |
| 1933 | /* Turn the thing off */ |
Will Deacon | 2572484 | 2013-08-21 13:49:53 +0100 | [diff] [blame] | 1934 | writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1935 | return 0; |
| 1936 | } |
| 1937 | |
| 1938 | #ifdef CONFIG_OF |
| 1939 | static struct of_device_id arm_smmu_of_match[] = { |
| 1940 | { .compatible = "arm,smmu-v1", }, |
| 1941 | { .compatible = "arm,smmu-v2", }, |
| 1942 | { .compatible = "arm,mmu-400", }, |
| 1943 | { .compatible = "arm,mmu-500", }, |
| 1944 | { }, |
| 1945 | }; |
| 1946 | MODULE_DEVICE_TABLE(of, arm_smmu_of_match); |
| 1947 | #endif |
| 1948 | |
| 1949 | static struct platform_driver arm_smmu_driver = { |
| 1950 | .driver = { |
| 1951 | .owner = THIS_MODULE, |
| 1952 | .name = "arm-smmu", |
| 1953 | .of_match_table = of_match_ptr(arm_smmu_of_match), |
| 1954 | }, |
| 1955 | .probe = arm_smmu_device_dt_probe, |
| 1956 | .remove = arm_smmu_device_remove, |
| 1957 | }; |
| 1958 | |
| 1959 | static int __init arm_smmu_init(void) |
| 1960 | { |
| 1961 | int ret; |
| 1962 | |
| 1963 | ret = platform_driver_register(&arm_smmu_driver); |
| 1964 | if (ret) |
| 1965 | return ret; |
| 1966 | |
| 1967 | /* Oh, for a proper bus abstraction */ |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 1968 | if (!iommu_present(&platform_bus_type)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1969 | bus_set_iommu(&platform_bus_type, &arm_smmu_ops); |
| 1970 | |
Dan Carpenter | 6614ee7 | 2013-08-21 09:34:20 +0100 | [diff] [blame] | 1971 | if (!iommu_present(&amba_bustype)) |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1972 | bus_set_iommu(&amba_bustype, &arm_smmu_ops); |
| 1973 | |
| 1974 | return 0; |
| 1975 | } |
| 1976 | |
| 1977 | static void __exit arm_smmu_exit(void) |
| 1978 | { |
| 1979 | return platform_driver_unregister(&arm_smmu_driver); |
| 1980 | } |
| 1981 | |
Andreas Herrmann | b1950b2 | 2013-10-01 13:39:05 +0100 | [diff] [blame] | 1982 | subsys_initcall(arm_smmu_init); |
Will Deacon | 45ae7cf | 2013-06-24 18:31:25 +0100 | [diff] [blame] | 1983 | module_exit(arm_smmu_exit); |
| 1984 | |
| 1985 | MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations"); |
| 1986 | MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>"); |
| 1987 | MODULE_LICENSE("GPL v2"); |