Max Filippov | 6840cc2 | 2014-03-12 21:55:24 +0400 | [diff] [blame] | 1 | /* |
| 2 | * Xtensa xtfpga SPI controller driver |
| 3 | * |
| 4 | * Copyright (c) 2014 Cadence Design Systems Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/delay.h> |
| 12 | #include <linux/io.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/of.h> |
| 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/spi/spi.h> |
| 17 | #include <linux/spi/spi_bitbang.h> |
| 18 | |
| 19 | #define XTFPGA_SPI_NAME "xtfpga_spi" |
| 20 | |
| 21 | #define XTFPGA_SPI_START 0x0 |
| 22 | #define XTFPGA_SPI_BUSY 0x4 |
| 23 | #define XTFPGA_SPI_DATA 0x8 |
| 24 | |
| 25 | #define BUSY_WAIT_US 100 |
| 26 | |
| 27 | struct xtfpga_spi { |
| 28 | struct spi_bitbang bitbang; |
| 29 | void __iomem *regs; |
| 30 | u32 data; |
| 31 | unsigned data_sz; |
| 32 | }; |
| 33 | |
| 34 | static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi, |
| 35 | unsigned addr, u32 val) |
| 36 | { |
Max Filippov | b0b4855 | 2015-09-22 14:32:03 +0300 | [diff] [blame] | 37 | __raw_writel(val, spi->regs + addr); |
Max Filippov | 6840cc2 | 2014-03-12 21:55:24 +0400 | [diff] [blame] | 38 | } |
| 39 | |
| 40 | static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi, |
| 41 | unsigned addr) |
| 42 | { |
Max Filippov | b0b4855 | 2015-09-22 14:32:03 +0300 | [diff] [blame] | 43 | return __raw_readl(spi->regs + addr); |
Max Filippov | 6840cc2 | 2014-03-12 21:55:24 +0400 | [diff] [blame] | 44 | } |
| 45 | |
| 46 | static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi) |
| 47 | { |
| 48 | unsigned i; |
Jingoo Han | cdc67fa | 2014-09-02 11:54:37 +0900 | [diff] [blame] | 49 | |
Max Filippov | 6840cc2 | 2014-03-12 21:55:24 +0400 | [diff] [blame] | 50 | for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) && |
| 51 | i < BUSY_WAIT_US; ++i) |
| 52 | udelay(1); |
| 53 | WARN_ON_ONCE(i == BUSY_WAIT_US); |
| 54 | } |
| 55 | |
| 56 | static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs, |
| 57 | u32 v, u8 bits) |
| 58 | { |
| 59 | struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master); |
| 60 | |
| 61 | xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0)); |
| 62 | xspi->data_sz += bits; |
| 63 | if (xspi->data_sz >= 16) { |
| 64 | xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA, |
| 65 | xspi->data >> (xspi->data_sz - 16)); |
| 66 | xspi->data_sz -= 16; |
| 67 | xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1); |
| 68 | xtfpga_spi_wait_busy(xspi); |
| 69 | xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0); |
| 70 | } |
| 71 | |
| 72 | return 0; |
| 73 | } |
| 74 | |
| 75 | static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on) |
| 76 | { |
| 77 | struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master); |
| 78 | |
| 79 | WARN_ON(xspi->data_sz != 0); |
| 80 | xspi->data_sz = 0; |
| 81 | } |
| 82 | |
| 83 | static int xtfpga_spi_probe(struct platform_device *pdev) |
| 84 | { |
| 85 | struct xtfpga_spi *xspi; |
| 86 | struct resource *mem; |
| 87 | int ret; |
| 88 | struct spi_master *master; |
| 89 | |
| 90 | master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi)); |
| 91 | if (!master) |
| 92 | return -ENOMEM; |
| 93 | |
| 94 | master->flags = SPI_MASTER_NO_RX; |
| 95 | master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16); |
| 96 | master->bus_num = pdev->dev.id; |
| 97 | master->dev.of_node = pdev->dev.of_node; |
| 98 | |
| 99 | xspi = spi_master_get_devdata(master); |
| 100 | xspi->bitbang.master = master; |
| 101 | xspi->bitbang.chipselect = xtfpga_spi_chipselect; |
| 102 | xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word; |
| 103 | |
| 104 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 105 | if (!mem) { |
| 106 | dev_err(&pdev->dev, "No memory resource\n"); |
| 107 | ret = -ENODEV; |
| 108 | goto err; |
| 109 | } |
| 110 | xspi->regs = devm_ioremap_resource(&pdev->dev, mem); |
| 111 | if (IS_ERR(xspi->regs)) { |
| 112 | ret = PTR_ERR(xspi->regs); |
| 113 | goto err; |
| 114 | } |
| 115 | |
| 116 | xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0); |
| 117 | usleep_range(1000, 2000); |
| 118 | if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) { |
| 119 | dev_err(&pdev->dev, "Device stuck in busy state\n"); |
| 120 | ret = -EBUSY; |
| 121 | goto err; |
| 122 | } |
| 123 | |
| 124 | ret = spi_bitbang_start(&xspi->bitbang); |
| 125 | if (ret < 0) { |
| 126 | dev_err(&pdev->dev, "spi_bitbang_start failed\n"); |
| 127 | goto err; |
| 128 | } |
| 129 | |
| 130 | platform_set_drvdata(pdev, master); |
| 131 | return 0; |
| 132 | err: |
| 133 | spi_master_put(master); |
| 134 | return ret; |
| 135 | } |
| 136 | |
| 137 | static int xtfpga_spi_remove(struct platform_device *pdev) |
| 138 | { |
| 139 | struct spi_master *master = platform_get_drvdata(pdev); |
| 140 | struct xtfpga_spi *xspi = spi_master_get_devdata(master); |
| 141 | |
| 142 | spi_bitbang_stop(&xspi->bitbang); |
| 143 | spi_master_put(master); |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | MODULE_ALIAS("platform:" XTFPGA_SPI_NAME); |
| 149 | |
| 150 | #ifdef CONFIG_OF |
| 151 | static const struct of_device_id xtfpga_spi_of_match[] = { |
| 152 | { .compatible = "cdns,xtfpga-spi", }, |
| 153 | {} |
| 154 | }; |
| 155 | MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match); |
| 156 | #endif |
| 157 | |
| 158 | static struct platform_driver xtfpga_spi_driver = { |
| 159 | .probe = xtfpga_spi_probe, |
| 160 | .remove = xtfpga_spi_remove, |
| 161 | .driver = { |
| 162 | .name = XTFPGA_SPI_NAME, |
Max Filippov | 6840cc2 | 2014-03-12 21:55:24 +0400 | [diff] [blame] | 163 | .of_match_table = of_match_ptr(xtfpga_spi_of_match), |
| 164 | }, |
| 165 | }; |
| 166 | module_platform_driver(xtfpga_spi_driver); |
| 167 | |
| 168 | MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>"); |
| 169 | MODULE_DESCRIPTION("xtensa xtfpga SPI driver"); |
| 170 | MODULE_LICENSE("GPL"); |