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gerrit-public.fairphone.software / kernel / msm-4.19 / 5612ac83b9d7a32a7f2967d9f6f97e7f3428dfd2 / . / arch / arm / boot / dts / imx6q-evi.dts
blob: fd2220aa49e278f6dac12a553a306e62ea296e66 [file] [log] [blame]
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]1/*
2 * Copyright 2016 United Western Technologies.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 *
42 */
43
44/dts-v1/;
45#include "imx6q.dtsi"
46#include <dt-bindings/gpio/gpio.h>
47#include <dt-bindings/interrupt-controller/irq.h>
48
49/ {
50 model = "Uniwest Evi";
51 compatible = "uniwest,imx6q-evi", "fsl,imx6q";
52
53 memory {
54 reg = <0x10000000 0x40000000>;
55 };
56
57 reg_usbh1_vbus: regulator-usbhubreset {
58 compatible = "regulator-fixed";
59 regulator-name = "usbh1_vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 enable-active-high;
63 startup-delay-us = <2>;
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_usbh1_hubreset>;
66 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
67 };
68
69 reg_usb_otg_vbus: regulator-usbotgvbus {
70 compatible = "regulator-fixed";
71 regulator-name = "usb_otg_vbus";
72 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_usbotgvbus>;
76 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 regulator-always-on;
79 };
80
81 panel {
82 compatible = "sharp,lq101k1ly04";
83
84 port {
85 panel_in: endpoint {
86 remote-endpoint = <&lvds0_out>;
87 };
88 };
89 };
90};
91
92&ecspi1 {
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]93 cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
96 status = "okay";
97};
98
99&ecspi3 {
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]100 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
101 <&gpio4 25 GPIO_ACTIVE_LOW>,
102 <&gpio4 26 GPIO_ACTIVE_LOW>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3cs>;
105 status = "okay";
106};
107
108&ecspi5 {
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]109 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
110 <&gpio1 13 GPIO_ACTIVE_LOW>,
111 <&gpio1 12 GPIO_ACTIVE_LOW>,
112 <&gpio2 9 GPIO_ACTIVE_HIGH>;
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_ecspi5 &pinctrl_ecspi5cs>;
115 status = "okay";
116
117 eeprom: m95m02@1 {
118 compatible = "st,m95m02", "atmel,at25";
119 size = <262144>;
120 pagesize = <256>;
121 address-width = <24>;
122 spi-max-frequency = <5000000>;
123 reg = <1>;
124 };
125
126 pb_rtc: rtc@3 {
127 compatible = "nxp,rtc-pcf2123";
128 spi-max-frequency = <2450000>;
129 spi-cs-high;
130 reg = <3>;
131 };
132};
133
134&fec {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_enet>;
137 phy-mode = "rgmii";
138 phy-reset-gpios = <&gpio1 25 0>;
Joshua Claytone7d0dbf2016-08-15 22:29:45 +0800[diff] [blame]139 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
140 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
141 fsl,err006687-workaround-present;
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]142 status = "okay";
143};
144
145&gpmi {
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_gpminand>;
148 status = "okay";
149};
150
151&i2c2 {
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c2>;
154 clock-frequency = <100000>;
155 status = "okay";
156};
157
158&i2c3 {
159 pinctrl-names = "default", "gpio";
160 pinctrl-0 = <&pinctrl_i2c3>;
161 pinctrl-1 = <&pinctrl_i2c3_gpio>;
162 clock-frequency = <100000>;
163 scl-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
164 sda-gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
165 status = "okay";
166
167 battery: sbs-battery@b {
168 compatible = "sbs,sbs-battery";
169 reg = <0x0b>;
170 sbs,poll-retry-count = <100>;
171 sbs,i2c-retry-count = <100>;
172 };
173};
174
175&ldb {
176 status = "okay";
177
178 lvds0: lvds-channel@0 {
179 status = "okay";
180
181 port@4 {
182 reg = <4>;
183 lvds0_out: endpoint {
184 remote-endpoint = <&panel_in>;
185 };
186 };
187 };
188};
189
190&ssi1 {
191 status = "okay";
192};
193
194&uart1 {
195 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_uart1>;
197 status = "okay";
198};
199
200&uart2 {
201 pinctrl-names = "default";
202 pinctrl-0 = <&pinctrl_uart2>;
203 status = "okay";
204};
205
206&usbh1 {
207 vbus-supply = <&reg_usbh1_vbus>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_usbh1>;
210 dr_mode = "host";
211 disable-over-current;
212 status = "okay";
213};
214
215&usbotg {
216 vbus-supply = <&reg_usb_otg_vbus>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_usbotg>;
219 disable-over-current;
220 dr_mode = "otg";
221 status = "okay";
222};
223
224&usdhc1 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_usdhc1>;
227 non-removable;
228 status = "okay";
229};
230
231&weim {
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]232 ranges = <0 0 0x08000000 0x08000000>;
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_weimfpga &pinctrl_weimcs>;
235 status = "okay";
236};
237
238&iomuxc {
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_hog>;
241
242 pinctrl_hog: hoggrp {
243 fsl,pins = <
244 /* pwr mcu alert irq */
245 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
246 /* remainder ???? */
247 MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
248 >;
249 };
250
251 pinctrl_ecspi1: ecspi1grp {
252 fsl,pins = <
253 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
254 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
255 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
256 >;
257 };
258
259 pinctrl_ecspi1cs: ecspi1csgrp {
260 fsl,pins = <
261 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
262 >;
263 };
264
265 pinctrl_ecspi3: ecspi3grp {
266 fsl,pins = <
267 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x10068
268 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x10068
269 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x1f068
270 >;
271 };
272
273 pinctrl_ecspi3cs: ecspi3csgrp {
274 fsl,pins = <
275 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b0
276 MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b0
277 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
278 MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b0
279 >;
280 };
281
282 pinctrl_ecspi5: ecspi5grp {
283 fsl,pins = <
284 MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x100b1
285 MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x100b1
286 MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x100b1
287 >;
288 };
289
290 pinctrl_ecspi5cs: ecspi5csgrp {
291 fsl,pins = <
292 MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
293 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x1b0b0
294 MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0
295 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
296 >;
297 };
298
299 pinctrl_enet: enetgrp {
300 fsl,pins = <
301 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
302 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200[diff] [blame]303 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
304 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
305 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
306 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
307 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
308 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]309 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
Uwe Kleine-Königc007b3a2016-07-08 23:22:54 +0200[diff] [blame]310 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
311 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
312 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
313 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
314 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
315 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]316 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
317 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
Joshua Claytone7d0dbf2016-08-15 22:29:45 +0800[diff] [blame]318 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
Joshua Claytonbdd91352016-02-03 09:37:45 -0800[diff] [blame]319 >;
320 };
321
322 pinctrl_gpminand: gpminandgrp {
323 fsl,pins = <
324 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
325 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
326 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
327 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
328 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
329 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
330 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
331 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
332 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
333 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
334 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
335 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
336 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
337 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
338 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
339 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
340 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
341 >;
342 };
343
344 pinctrl_i2c2: i2c2grp {
345 fsl,pins = <
346 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
347 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
348 >;
349 };
350
351 pinctrl_i2c3: i2c3grp {
352 fsl,pins = <
353 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
354 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
355 >;
356 };
357
358 pinctrl_i2c3_gpio: i2c3gpiogrp {
359 fsl,pins = <
360 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x4001b8b1
361 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001b8b1
362 >;
363 };
364
365 pinctrl_weimcs: weimcsgrp {
366 fsl,pins = <
367 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
368 MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1
369 >;
370 };
371
372 pinctrl_weimfpga: weimfpgagrp {
373 fsl,pins = <
374 /* weim misc */
375 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
376 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
377 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
378 MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0xb0b1
379 MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0xb0b1
380 MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0xb0b1
381 MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0xb0b1
382 MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0xb0b1
383 MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0xb0b1
384 /* weim data */
385 MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
386 MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
387 MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
388 MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
389 MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
390 MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
391 MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
392 MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
393 MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
394 MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
395 MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
396 MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
397 MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
398 MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
399 MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
400 MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
401 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
402 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
403 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
404 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
405 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
406 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
407 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
408 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
409 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
410 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
411 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
412 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
413 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
414 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
415 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
416 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
417 /* weim address */
418 MX6QDL_PAD_EIM_A25__EIM_ADDR25 0xb0b1
419 MX6QDL_PAD_EIM_A24__EIM_ADDR24 0xb0b1
420 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
421 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
422 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
423 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
424 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
425 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
426 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
427 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
428 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
429 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
430 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
431 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
432 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
433 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
434 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
435 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
436 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
437 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
438 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
439 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
440 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
441 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
442 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
443 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
444 >;
445 };
446
447 pinctrl_uart1: uart1grp {
448 fsl,pins = <
449 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
450 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
451 >;
452 };
453
454 pinctrl_uart2: uart2grp {
455 fsl,pins = <
456 MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
457 MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
458 MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x1b0b1
459 MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x1b0b1
460 >;
461 };
462
463 pinctrl_usbh1: usbh1grp {
464 fsl,pins = <
465 MX6QDL_PAD_GPIO_3__USB_H1_OC 0x1b0b0
466 /* usbh1_b OC */
467 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
468 >;
469 };
470
471 pinctrl_usbh1_hubreset: usbh1hubresetgrp {
472 fsl,pins = <
473 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
474 >;
475 };
476
477 pinctrl_usbotg: usbotggrp {
478 fsl,pins = <
479 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
480 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
481 >;
482 };
483
484 pinctrl_usbotgvbus: usbotgvbusgrp {
485 fsl,pins = <
486 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0
487 >;
488 };
489
490 pinctrl_usdhc1: usdhc1grp {
491 fsl,pins = <
492 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
493 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
494 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
495 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
496 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
497 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
498 >;
499 };
500};