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Shawn Guo117ccd552013-05-03 11:28:42 +08001/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include "imx6sl.dtsi"
12
13/ {
14 model = "Freescale i.MX6 SoloLite EVK Board";
15 compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
16
17 memory {
18 reg = <0x80000000 0x40000000>;
19 };
Peter Chen60222322013-09-10 10:23:16 +080020
21 regulators {
22 compatible = "simple-bus";
23
24 reg_usb_otg1_vbus: usb_otg1_vbus {
25 compatible = "regulator-fixed";
26 regulator-name = "usb_otg1_vbus";
27 regulator-min-microvolt = <5000000>;
28 regulator-max-microvolt = <5000000>;
29 gpio = <&gpio4 0 0>;
30 enable-active-high;
31 };
32
33 reg_usb_otg2_vbus: usb_otg2_vbus {
34 compatible = "regulator-fixed";
35 regulator-name = "usb_otg2_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 gpio = <&gpio4 2 0>;
39 enable-active-high;
40 };
41 };
Shawn Guo117ccd552013-05-03 11:28:42 +080042};
43
Huang Shijied1b53972013-10-18 10:32:53 +080044&ecspi1 {
45 fsl,spi-num-chipselects = <1>;
46 cs-gpios = <&gpio4 11 0>;
47 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080048 pinctrl-0 = <&pinctrl_ecspi1>;
Huang Shijied1b53972013-10-18 10:32:53 +080049 status = "okay";
50
51 flash: m25p80@0 {
52 #address-cells = <1>;
53 #size-cells = <1>;
54 compatible = "st,m25p32";
55 spi-max-frequency = <20000000>;
56 reg = <0>;
57 };
58};
59
Shawn Guo117ccd552013-05-03 11:28:42 +080060&fec {
61 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +080062 pinctrl-0 = <&pinctrl_fec>;
Shawn Guo117ccd552013-05-03 11:28:42 +080063 phy-mode = "rmii";
64 status = "okay";
65};
66
67&iomuxc {
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_hog>;
70
Shawn Guofffaa652013-11-04 10:49:04 +080071 imx6sl-evk {
Shawn Guo117ccd552013-05-03 11:28:42 +080072 pinctrl_hog: hoggrp {
73 fsl,pins = <
74 MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
75 MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
76 MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
77 MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
78 MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
Peter Chen60222322013-09-10 10:23:16 +080079 MX6SL_PAD_KEY_COL4__GPIO4_IO00 0x80000000
80 MX6SL_PAD_KEY_COL5__GPIO4_IO02 0x80000000
Shawn Guo117ccd552013-05-03 11:28:42 +080081 >;
82 };
Shawn Guofffaa652013-11-04 10:49:04 +080083
84 pinctrl_ecspi1: ecspi1grp {
85 fsl,pins = <
86 MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
87 MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
88 MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
89 >;
90 };
91
92 pinctrl_fec: fecgrp {
93 fsl,pins = <
94 MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
95 MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
96 MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
97 MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
98 MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
99 MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
100 MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
101 MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
102 MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
103 >;
104 };
105
106 pinctrl_uart1: uart1grp {
107 fsl,pins = <
108 MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
109 MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
110 >;
111 };
112
113 pinctrl_usbotg1: usbotg1grp {
114 fsl,pins = <
115 MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
116 >;
117 };
118
119 pinctrl_usdhc1: usdhc1grp {
120 fsl,pins = <
121 MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
122 MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
123 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
124 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
125 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
126 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
127 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
128 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
129 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
130 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
131 >;
132 };
133
134 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
135 fsl,pins = <
136 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
137 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
138 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
139 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
140 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
141 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
142 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
143 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
144 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
145 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
146 >;
147 };
148
149 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
150 fsl,pins = <
151 MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
152 MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
153 MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
154 MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
155 MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
156 MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
157 MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
158 MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
159 MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
160 MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
161 >;
162 };
163
164 pinctrl_usdhc2: usdhc2grp {
165 fsl,pins = <
166 MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
167 MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
168 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
169 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
170 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
171 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
172 >;
173 };
174
175 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
176 fsl,pins = <
177 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
178 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
179 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
180 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
181 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
182 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
183 >;
184 };
185
186 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
187 fsl,pins = <
188 MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
189 MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
190 MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
191 MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
192 MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
193 MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
194 >;
195 };
196
197 pinctrl_usdhc3: usdhc3grp {
198 fsl,pins = <
199 MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
200 MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
201 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
202 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
203 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
204 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
205 >;
206 };
207
208 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
209 fsl,pins = <
210 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
211 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
212 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
213 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
214 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
215 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
216 >;
217 };
218
219 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
220 fsl,pins = <
221 MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
222 MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
223 MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
224 MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
225 MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
226 MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
227 >;
228 };
Shawn Guo117ccd552013-05-03 11:28:42 +0800229 };
230};
231
232&uart1 {
233 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800234 pinctrl-0 = <&pinctrl_uart1>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800235 status = "okay";
236};
237
Peter Chen60222322013-09-10 10:23:16 +0800238&usbotg1 {
239 vbus-supply = <&reg_usb_otg1_vbus>;
240 pinctrl-names = "default";
Shawn Guofffaa652013-11-04 10:49:04 +0800241 pinctrl-0 = <&pinctrl_usbotg1>;
Peter Chen60222322013-09-10 10:23:16 +0800242 disable-over-current;
243 status = "okay";
244};
245
246&usbotg2 {
247 vbus-supply = <&reg_usb_otg2_vbus>;
248 dr_mode = "host";
249 disable-over-current;
250 status = "okay";
251};
252
Shawn Guo117ccd552013-05-03 11:28:42 +0800253&usdhc1 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800254 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800255 pinctrl-0 = <&pinctrl_usdhc1>;
256 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
257 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800258 bus-width = <8>;
259 cd-gpios = <&gpio4 7 0>;
260 wp-gpios = <&gpio4 6 0>;
261 status = "okay";
262};
263
264&usdhc2 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800265 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800266 pinctrl-0 = <&pinctrl_usdhc2>;
267 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
268 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800269 cd-gpios = <&gpio5 0 0>;
270 wp-gpios = <&gpio4 29 0>;
271 status = "okay";
272};
273
274&usdhc3 {
Dong Aishengfa87dfd2013-10-09 19:20:07 +0800275 pinctrl-names = "default", "state_100mhz", "state_200mhz";
Shawn Guofffaa652013-11-04 10:49:04 +0800276 pinctrl-0 = <&pinctrl_usdhc3>;
277 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
278 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
Shawn Guo117ccd552013-05-03 11:28:42 +0800279 cd-gpios = <&gpio3 22 0>;
280 status = "okay";
281};