blob: 7235ffb58a18b65731a645361aea1d399a0a6cd1 [file] [log] [blame]
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Keith Packard <keithp@keithp.com>
25 *
26 */
27
28#include <linux/i2c.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090029#include <linux/slab.h>
Paul Gortmaker2d1a8a42011-08-30 18:16:33 -040030#include <linux/export.h>
David Howells760285e2012-10-02 18:01:07 +010031#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_edid.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070035#include "intel_drv.h"
David Howells760285e2012-10-02 18:01:07 +010036#include <drm/i915_drm.h>
Keith Packarda4fc5ed2009-04-07 16:16:42 -070037#include "i915_drv.h"
Keith Packarda4fc5ed2009-04-07 16:16:42 -070038
Keith Packarda4fc5ed2009-04-07 16:16:42 -070039#define DP_LINK_CHECK_TIMEOUT (10 * 1000)
40
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +080041struct dp_link_dpll {
42 int link_bw;
43 struct dpll dpll;
44};
45
46static const struct dp_link_dpll gen4_dpll[] = {
47 { DP_LINK_BW_1_62,
48 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
49 { DP_LINK_BW_2_7,
50 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
51};
52
53static const struct dp_link_dpll pch_dpll[] = {
54 { DP_LINK_BW_1_62,
55 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
56 { DP_LINK_BW_2_7,
57 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
58};
59
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080060static const struct dp_link_dpll vlv_dpll[] = {
61 { DP_LINK_BW_1_62,
Chon Ming Lee58f6e632013-09-25 15:47:51 +080062 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +080063 { DP_LINK_BW_2_7,
64 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
65};
66
Chon Ming Leeef9348c2014-04-09 13:28:18 +030067/*
68 * CHV supports eDP 1.4 that have more link rates.
69 * Below only provides the fixed rate but exclude variable rate.
70 */
71static const struct dp_link_dpll chv_dpll[] = {
72 /*
73 * CHV requires to program fractional division for m2.
74 * m2 is stored in fixed point format using formula below
75 * (m2_int << 22) | m2_fraction
76 */
77 { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */
78 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
79 { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */
80 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
81 { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */
82 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
83};
84
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070085/**
86 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
87 * @intel_dp: DP struct
88 *
89 * If a CPU or PCH DP output is attached to an eDP panel, this function
90 * will return true, and false otherwise.
91 */
92static bool is_edp(struct intel_dp *intel_dp)
93{
Paulo Zanonida63a9f2012-10-26 19:05:46 -020094 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
95
96 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -070097}
98
Imre Deak68b4d822013-05-08 13:14:06 +030099static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700100{
Imre Deak68b4d822013-05-08 13:14:06 +0300101 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
102
103 return intel_dig_port->base.base.dev;
Jesse Barnescfcb0fc2010-10-07 16:01:06 -0700104}
105
Chris Wilsondf0e9242010-09-09 16:20:55 +0100106static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
107{
Paulo Zanonifa90ece2012-10-26 19:05:44 -0200108 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
Chris Wilsondf0e9242010-09-09 16:20:55 +0100109}
110
Chris Wilsonea5b2132010-08-04 13:50:23 +0100111static void intel_dp_link_down(struct intel_dp *intel_dp);
Jani Nikulaadddaaf2014-03-14 16:51:13 +0200112static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +0100113static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700114
115static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100116intel_dp_max_link_bw(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700117{
Jesse Barnes7183dc22011-07-07 11:10:58 -0700118 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
Todd Previte06ea66b2014-01-20 10:19:39 -0700119 struct drm_device *dev = intel_dp->attached_connector->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700120
121 switch (max_link_bw) {
122 case DP_LINK_BW_1_62:
123 case DP_LINK_BW_2_7:
124 break;
Imre Deakd4eead52013-07-09 17:05:26 +0300125 case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
Todd Previte06ea66b2014-01-20 10:19:39 -0700126 if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
127 intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
128 max_link_bw = DP_LINK_BW_5_4;
129 else
130 max_link_bw = DP_LINK_BW_2_7;
Imre Deakd4eead52013-07-09 17:05:26 +0300131 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700132 default:
Imre Deakd4eead52013-07-09 17:05:26 +0300133 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
134 max_link_bw);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700135 max_link_bw = DP_LINK_BW_1_62;
136 break;
137 }
138 return max_link_bw;
139}
140
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400141/*
142 * The units on the numbers in the next two are... bizarre. Examples will
143 * make it clearer; this one parallels an example in the eDP spec.
144 *
145 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
146 *
147 * 270000 * 1 * 8 / 10 == 216000
148 *
149 * The actual data capacity of that configuration is 2.16Gbit/s, so the
150 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
151 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
152 * 119000. At 18bpp that's 2142000 kilobits per second.
153 *
154 * Thus the strange-looking division by 10 in intel_dp_link_required, to
155 * get the result in decakilobits instead of kilobits.
156 */
157
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700158static int
Keith Packardc8982612012-01-25 08:16:25 -0800159intel_dp_link_required(int pixel_clock, int bpp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700160{
Adam Jacksoncd9dde42011-10-14 12:43:49 -0400161 return (pixel_clock * bpp + 9) / 10;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700162}
163
164static int
Dave Airliefe27d532010-06-30 11:46:17 +1000165intel_dp_max_data_rate(int max_link_clock, int max_lanes)
166{
167 return (max_link_clock * max_lanes * 8) / 10;
168}
169
Damien Lespiauc19de8e2013-11-28 15:29:18 +0000170static enum drm_mode_status
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700171intel_dp_mode_valid(struct drm_connector *connector,
172 struct drm_display_mode *mode)
173{
Chris Wilsondf0e9242010-09-09 16:20:55 +0100174 struct intel_dp *intel_dp = intel_attached_dp(connector);
Jani Nikuladd06f902012-10-19 14:51:50 +0300175 struct intel_connector *intel_connector = to_intel_connector(connector);
176 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
Daniel Vetter36008362013-03-27 00:44:59 +0100177 int target_clock = mode->clock;
178 int max_rate, mode_rate, max_lanes, max_link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700179
Jani Nikuladd06f902012-10-19 14:51:50 +0300180 if (is_edp(intel_dp) && fixed_mode) {
181 if (mode->hdisplay > fixed_mode->hdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100182 return MODE_PANEL;
183
Jani Nikuladd06f902012-10-19 14:51:50 +0300184 if (mode->vdisplay > fixed_mode->vdisplay)
Zhao Yakui7de56f42010-07-19 09:43:14 +0100185 return MODE_PANEL;
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200186
187 target_clock = fixed_mode->clock;
Zhao Yakui7de56f42010-07-19 09:43:14 +0100188 }
189
Daniel Vetter36008362013-03-27 00:44:59 +0100190 max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
191 max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
192
193 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
194 mode_rate = intel_dp_link_required(target_clock, 18);
195
196 if (mode_rate > max_rate)
Daniel Vetterc4867932012-04-10 10:42:36 +0200197 return MODE_CLOCK_HIGH;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700198
199 if (mode->clock < 10000)
200 return MODE_CLOCK_LOW;
201
Daniel Vetter0af78a22012-05-23 11:30:55 +0200202 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
203 return MODE_H_ILLEGAL;
204
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700205 return MODE_OK;
206}
207
208static uint32_t
209pack_aux(uint8_t *src, int src_bytes)
210{
211 int i;
212 uint32_t v = 0;
213
214 if (src_bytes > 4)
215 src_bytes = 4;
216 for (i = 0; i < src_bytes; i++)
217 v |= ((uint32_t) src[i]) << ((3-i) * 8);
218 return v;
219}
220
221static void
222unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
223{
224 int i;
225 if (dst_bytes > 4)
226 dst_bytes = 4;
227 for (i = 0; i < dst_bytes; i++)
228 dst[i] = src >> ((3-i) * 8);
229}
230
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700231/* hrawclock is 1/4 the FSB frequency */
232static int
233intel_hrawclk(struct drm_device *dev)
234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 uint32_t clkcfg;
237
Vijay Purushothaman9473c8f2012-09-27 19:13:01 +0530238 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
239 if (IS_VALLEYVIEW(dev))
240 return 200;
241
Keith Packardfb0f8fb2009-06-11 22:31:31 -0700242 clkcfg = I915_READ(CLKCFG);
243 switch (clkcfg & CLKCFG_FSB_MASK) {
244 case CLKCFG_FSB_400:
245 return 100;
246 case CLKCFG_FSB_533:
247 return 133;
248 case CLKCFG_FSB_667:
249 return 166;
250 case CLKCFG_FSB_800:
251 return 200;
252 case CLKCFG_FSB_1067:
253 return 266;
254 case CLKCFG_FSB_1333:
255 return 333;
256 /* these two are just a guess; one of them might be right */
257 case CLKCFG_FSB_1600:
258 case CLKCFG_FSB_1600_ALT:
259 return 400;
260 default:
261 return 133;
262 }
263}
264
Jani Nikulabf13e812013-09-06 07:40:05 +0300265static void
266intel_dp_init_panel_power_sequencer(struct drm_device *dev,
267 struct intel_dp *intel_dp,
268 struct edp_power_seq *out);
269static void
270intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
271 struct intel_dp *intel_dp,
272 struct edp_power_seq *out);
273
274static enum pipe
275vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
276{
277 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
278 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
279 struct drm_device *dev = intel_dig_port->base.base.dev;
280 struct drm_i915_private *dev_priv = dev->dev_private;
281 enum port port = intel_dig_port->port;
282 enum pipe pipe;
283
284 /* modeset should have pipe */
285 if (crtc)
286 return to_intel_crtc(crtc)->pipe;
287
288 /* init time, try to find a pipe with this port selected */
289 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
290 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
291 PANEL_PORT_SELECT_MASK;
292 if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
293 return pipe;
294 if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
295 return pipe;
296 }
297
298 /* shrug */
299 return PIPE_A;
300}
301
302static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
303{
304 struct drm_device *dev = intel_dp_to_dev(intel_dp);
305
306 if (HAS_PCH_SPLIT(dev))
307 return PCH_PP_CONTROL;
308 else
309 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
310}
311
312static u32 _pp_stat_reg(struct intel_dp *intel_dp)
313{
314 struct drm_device *dev = intel_dp_to_dev(intel_dp);
315
316 if (HAS_PCH_SPLIT(dev))
317 return PCH_PP_STATUS;
318 else
319 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
320}
321
Daniel Vetter4be73782014-01-17 14:39:48 +0100322static bool edp_have_panel_power(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700323{
Paulo Zanoni30add222012-10-26 19:05:45 -0200324 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700325 struct drm_i915_private *dev_priv = dev->dev_private;
326
Jani Nikulabf13e812013-09-06 07:40:05 +0300327 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700328}
329
Daniel Vetter4be73782014-01-17 14:39:48 +0100330static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
Keith Packardebf33b12011-09-29 15:53:27 -0700331{
Paulo Zanoni30add222012-10-26 19:05:45 -0200332 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardebf33b12011-09-29 15:53:27 -0700333 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deakbb4932c2014-04-14 20:24:33 +0300334 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
335 struct intel_encoder *intel_encoder = &intel_dig_port->base;
336 enum intel_display_power_domain power_domain;
Keith Packardebf33b12011-09-29 15:53:27 -0700337
Imre Deakbb4932c2014-04-14 20:24:33 +0300338 power_domain = intel_display_port_power_domain(intel_encoder);
339 return intel_display_power_enabled(dev_priv, power_domain) &&
Paulo Zanoniefbc20a2014-04-01 14:55:09 -0300340 (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
Keith Packardebf33b12011-09-29 15:53:27 -0700341}
342
Keith Packard9b984da2011-09-19 13:54:47 -0700343static void
344intel_dp_check_edp(struct intel_dp *intel_dp)
345{
Paulo Zanoni30add222012-10-26 19:05:45 -0200346 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard9b984da2011-09-19 13:54:47 -0700347 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packardebf33b12011-09-29 15:53:27 -0700348
Keith Packard9b984da2011-09-19 13:54:47 -0700349 if (!is_edp(intel_dp))
350 return;
Jesse Barnes453c5422013-03-28 09:55:41 -0700351
Daniel Vetter4be73782014-01-17 14:39:48 +0100352 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
Keith Packard9b984da2011-09-19 13:54:47 -0700353 WARN(1, "eDP powered off while attempting aux channel communication.\n");
354 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
Jani Nikulabf13e812013-09-06 07:40:05 +0300355 I915_READ(_pp_stat_reg(intel_dp)),
356 I915_READ(_pp_ctrl_reg(intel_dp)));
Keith Packard9b984da2011-09-19 13:54:47 -0700357 }
358}
359
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100360static uint32_t
361intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
362{
363 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
364 struct drm_device *dev = intel_dig_port->base.base.dev;
365 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300366 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100367 uint32_t status;
368 bool done;
369
Daniel Vetteref04f002012-12-01 21:03:59 +0100370#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100371 if (has_aux_irq)
Paulo Zanonib18ac462013-02-18 19:00:24 -0300372 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
Imre Deak35987062013-05-21 20:03:20 +0300373 msecs_to_jiffies_timeout(10));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100374 else
375 done = wait_for_atomic(C, 10) == 0;
376 if (!done)
377 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
378 has_aux_irq);
379#undef C
380
381 return status;
382}
383
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000384static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
385{
386 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
387 struct drm_device *dev = intel_dig_port->base.base.dev;
388
389 /*
390 * The clock divider is based off the hrawclk, and would like to run at
391 * 2MHz. So, take the hrawclk value and divide by 2 and use that
392 */
393 return index ? 0 : intel_hrawclk(dev) / 2;
394}
395
396static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
397{
398 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
399 struct drm_device *dev = intel_dig_port->base.base.dev;
400
401 if (index)
402 return 0;
403
404 if (intel_dig_port->port == PORT_A) {
405 if (IS_GEN6(dev) || IS_GEN7(dev))
406 return 200; /* SNB & IVB eDP input clock at 400Mhz */
407 else
408 return 225; /* eDP input clock at 450Mhz */
409 } else {
410 return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411 }
412}
413
414static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300415{
416 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
417 struct drm_device *dev = intel_dig_port->base.base.dev;
418 struct drm_i915_private *dev_priv = dev->dev_private;
419
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000420 if (intel_dig_port->port == PORT_A) {
Chris Wilsonbc866252013-07-21 16:00:03 +0100421 if (index)
422 return 0;
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000423 return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300424 } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
425 /* Workaround for non-ULT HSW */
Chris Wilsonbc866252013-07-21 16:00:03 +0100426 switch (index) {
427 case 0: return 63;
428 case 1: return 72;
429 default: return 0;
430 }
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000431 } else {
Chris Wilsonbc866252013-07-21 16:00:03 +0100432 return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
Rodrigo Vivib84a1cf2013-07-11 18:44:57 -0300433 }
434}
435
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000436static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
437{
438 return index ? 0 : 100;
439}
440
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000441static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
442 bool has_aux_irq,
443 int send_bytes,
444 uint32_t aux_clock_divider)
445{
446 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
447 struct drm_device *dev = intel_dig_port->base.base.dev;
448 uint32_t precharge, timeout;
449
450 if (IS_GEN6(dev))
451 precharge = 3;
452 else
453 precharge = 5;
454
455 if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
456 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
457 else
458 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
459
460 return DP_AUX_CH_CTL_SEND_BUSY |
Damien Lespiau788d4432014-01-20 15:52:31 +0000461 DP_AUX_CH_CTL_DONE |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000462 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000463 DP_AUX_CH_CTL_TIME_OUT_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000464 timeout |
Damien Lespiau788d4432014-01-20 15:52:31 +0000465 DP_AUX_CH_CTL_RECEIVE_ERROR |
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000466 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
467 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
Damien Lespiau788d4432014-01-20 15:52:31 +0000468 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000469}
470
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700471static int
Chris Wilsonea5b2132010-08-04 13:50:23 +0100472intel_dp_aux_ch(struct intel_dp *intel_dp,
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700473 uint8_t *send, int send_bytes,
474 uint8_t *recv, int recv_size)
475{
Paulo Zanoni174edf12012-10-26 19:05:50 -0200476 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
477 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700478 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni9ed35ab2013-02-18 19:00:25 -0300479 uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700480 uint32_t ch_data = ch_ctl + 4;
Chris Wilsonbc866252013-07-21 16:00:03 +0100481 uint32_t aux_clock_divider;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100482 int i, ret, recv_bytes;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700483 uint32_t status;
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000484 int try, clock = 0;
Daniel Vetter4e6b7882014-02-07 16:33:20 +0100485 bool has_aux_irq = HAS_AUX_IRQ(dev);
Jani Nikula884f19e2014-03-14 16:51:14 +0200486 bool vdd;
487
488 vdd = _edp_panel_vdd_on(intel_dp);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100489
490 /* dp aux is extremely sensitive to irq latency, hence request the
491 * lowest possible wakeup latency and so prevent the cpu from going into
492 * deep sleep states.
493 */
494 pm_qos_update_request(&dev_priv->pm_qos, 0);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700495
Keith Packard9b984da2011-09-19 13:54:47 -0700496 intel_dp_check_edp(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +0800497
Paulo Zanonic67a4702013-08-19 13:18:09 -0300498 intel_aux_display_runtime_get(dev_priv);
499
Jesse Barnes11bee432011-08-01 15:02:20 -0700500 /* Try to wait for any previous AUX channel activity */
501 for (try = 0; try < 3; try++) {
Daniel Vetteref04f002012-12-01 21:03:59 +0100502 status = I915_READ_NOTRACE(ch_ctl);
Jesse Barnes11bee432011-08-01 15:02:20 -0700503 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
504 break;
505 msleep(1);
506 }
507
508 if (try == 3) {
509 WARN(1, "dp_aux_ch not started status 0x%08x\n",
510 I915_READ(ch_ctl));
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100511 ret = -EBUSY;
512 goto out;
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100513 }
514
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300515 /* Only 5 data registers! */
516 if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
517 ret = -E2BIG;
518 goto out;
519 }
520
Damien Lespiauec5b01d2014-01-21 13:35:39 +0000521 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
Damien Lespiau153b1102014-01-21 13:37:15 +0000522 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
523 has_aux_irq,
524 send_bytes,
525 aux_clock_divider);
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000526
Chris Wilsonbc866252013-07-21 16:00:03 +0100527 /* Must try at least 3 times according to DP spec */
528 for (try = 0; try < 5; try++) {
529 /* Load the send data into the aux channel data registers */
530 for (i = 0; i < send_bytes; i += 4)
531 I915_WRITE(ch_data + i,
532 pack_aux(send + i, send_bytes - i));
Akshay Joshi0206e352011-08-16 15:34:10 -0400533
Chris Wilsonbc866252013-07-21 16:00:03 +0100534 /* Send the command and wait for it to complete */
Damien Lespiau5ed12a12014-01-20 15:52:30 +0000535 I915_WRITE(ch_ctl, send_ctl);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100536
Chris Wilsonbc866252013-07-21 16:00:03 +0100537 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
Akshay Joshi0206e352011-08-16 15:34:10 -0400538
Chris Wilsonbc866252013-07-21 16:00:03 +0100539 /* Clear done status and any errors */
540 I915_WRITE(ch_ctl,
541 status |
542 DP_AUX_CH_CTL_DONE |
543 DP_AUX_CH_CTL_TIME_OUT_ERROR |
544 DP_AUX_CH_CTL_RECEIVE_ERROR);
Adam Jacksond7e96fe2011-07-26 15:39:46 -0400545
Chris Wilsonbc866252013-07-21 16:00:03 +0100546 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
547 DP_AUX_CH_CTL_RECEIVE_ERROR))
548 continue;
549 if (status & DP_AUX_CH_CTL_DONE)
550 break;
551 }
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100552 if (status & DP_AUX_CH_CTL_DONE)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700553 break;
554 }
555
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700556 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700557 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100558 ret = -EBUSY;
559 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700560 }
561
562 /* Check for timeout or receive error.
563 * Timeouts occur when the sink is not connected
564 */
Keith Packarda5b3da52009-06-11 22:30:32 -0700565 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700566 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100567 ret = -EIO;
568 goto out;
Keith Packarda5b3da52009-06-11 22:30:32 -0700569 }
Keith Packard1ae8c0a2009-06-28 15:42:17 -0700570
571 /* Timeouts occur when the device isn't connected, so they're
572 * "normal" -- don't fill the kernel log with these */
Keith Packarda5b3da52009-06-11 22:30:32 -0700573 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
Zhao Yakui28c97732009-10-09 11:39:41 +0800574 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100575 ret = -ETIMEDOUT;
576 goto out;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700577 }
578
579 /* Unload any bytes sent back from the other side */
580 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
581 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700582 if (recv_bytes > recv_size)
583 recv_bytes = recv_size;
Akshay Joshi0206e352011-08-16 15:34:10 -0400584
Chris Wilson4f7f7b72010-08-18 18:12:56 +0100585 for (i = 0; i < recv_bytes; i += 4)
586 unpack_aux(I915_READ(ch_data + i),
587 recv + i, recv_bytes - i);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700588
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100589 ret = recv_bytes;
590out:
591 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
Paulo Zanonic67a4702013-08-19 13:18:09 -0300592 intel_aux_display_runtime_put(dev_priv);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100593
Jani Nikula884f19e2014-03-14 16:51:14 +0200594 if (vdd)
595 edp_panel_vdd_off(intel_dp, false);
596
Daniel Vetter9ee32fea2012-12-01 13:53:48 +0100597 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700598}
599
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300600#define BARE_ADDRESS_SIZE 3
601#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
Jani Nikula9d1a1032014-03-14 16:51:15 +0200602static ssize_t
603intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700604{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200605 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
606 uint8_t txbuf[20], rxbuf[20];
607 size_t txsize, rxsize;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700608 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700609
Jani Nikula9d1a1032014-03-14 16:51:15 +0200610 txbuf[0] = msg->request << 4;
611 txbuf[1] = msg->address >> 8;
612 txbuf[2] = msg->address & 0xff;
613 txbuf[3] = msg->size - 1;
Paulo Zanoni46a5ae92013-09-17 11:14:10 -0300614
Jani Nikula9d1a1032014-03-14 16:51:15 +0200615 switch (msg->request & ~DP_AUX_I2C_MOT) {
616 case DP_AUX_NATIVE_WRITE:
617 case DP_AUX_I2C_WRITE:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300618 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200619 rxsize = 1;
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200620
Jani Nikula9d1a1032014-03-14 16:51:15 +0200621 if (WARN_ON(txsize > 20))
622 return -E2BIG;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700623
Jani Nikula9d1a1032014-03-14 16:51:15 +0200624 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700625
Jani Nikula9d1a1032014-03-14 16:51:15 +0200626 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
627 if (ret > 0) {
628 msg->reply = rxbuf[0] >> 4;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700629
Jani Nikula9d1a1032014-03-14 16:51:15 +0200630 /* Return payload size. */
631 ret = msg->size;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700632 }
Jani Nikula9d1a1032014-03-14 16:51:15 +0200633 break;
634
635 case DP_AUX_NATIVE_READ:
636 case DP_AUX_I2C_READ:
Jani Nikulaa6c8aff02014-04-07 12:37:25 +0300637 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200638 rxsize = msg->size + 1;
639
640 if (WARN_ON(rxsize > 20))
641 return -E2BIG;
642
643 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
644 if (ret > 0) {
645 msg->reply = rxbuf[0] >> 4;
646 /*
647 * Assume happy day, and copy the data. The caller is
648 * expected to check msg->reply before touching it.
649 *
650 * Return payload size.
651 */
652 ret--;
653 memcpy(msg->buffer, rxbuf + 1, ret);
654 }
655 break;
656
657 default:
658 ret = -EINVAL;
659 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700660 }
Jani Nikulaf51a44b2014-02-11 11:52:05 +0200661
Jani Nikula9d1a1032014-03-14 16:51:15 +0200662 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700663}
664
Jani Nikula9d1a1032014-03-14 16:51:15 +0200665static void
666intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700667{
Jani Nikula9d1a1032014-03-14 16:51:15 +0200668 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jani Nikula33ad6622014-03-14 16:51:16 +0200669 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
670 enum port port = intel_dig_port->port;
Jani Nikula0b998362014-03-14 16:51:17 +0200671 const char *name = NULL;
Dave Airlieab2c0672009-12-04 10:55:24 +1000672 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700673
Jani Nikula33ad6622014-03-14 16:51:16 +0200674 switch (port) {
675 case PORT_A:
676 intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200677 name = "DPDDC-A";
Dave Airlieab2c0672009-12-04 10:55:24 +1000678 break;
Jani Nikula33ad6622014-03-14 16:51:16 +0200679 case PORT_B:
680 intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200681 name = "DPDDC-B";
Jani Nikula33ad6622014-03-14 16:51:16 +0200682 break;
683 case PORT_C:
684 intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200685 name = "DPDDC-C";
Jani Nikula33ad6622014-03-14 16:51:16 +0200686 break;
687 case PORT_D:
688 intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
Jani Nikula0b998362014-03-14 16:51:17 +0200689 name = "DPDDC-D";
Dave Airlieab2c0672009-12-04 10:55:24 +1000690 break;
691 default:
Jani Nikula33ad6622014-03-14 16:51:16 +0200692 BUG();
Dave Airlieab2c0672009-12-04 10:55:24 +1000693 }
694
Jani Nikula33ad6622014-03-14 16:51:16 +0200695 if (!HAS_DDI(dev))
696 intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
David Flynn8316f332010-12-08 16:10:21 +0000697
Jani Nikula0b998362014-03-14 16:51:17 +0200698 intel_dp->aux.name = name;
Jani Nikula9d1a1032014-03-14 16:51:15 +0200699 intel_dp->aux.dev = dev->dev;
700 intel_dp->aux.transfer = intel_dp_aux_transfer;
David Flynn8316f332010-12-08 16:10:21 +0000701
Jani Nikula0b998362014-03-14 16:51:17 +0200702 DRM_DEBUG_KMS("registering %s bus for %s\n", name,
703 connector->base.kdev->kobj.name);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700704
Jani Nikula0b998362014-03-14 16:51:17 +0200705 ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
706 if (ret < 0) {
707 DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
708 name, ret);
709 return;
Dave Airlieab2c0672009-12-04 10:55:24 +1000710 }
David Flynn8316f332010-12-08 16:10:21 +0000711
Jani Nikula0b998362014-03-14 16:51:17 +0200712 ret = sysfs_create_link(&connector->base.kdev->kobj,
713 &intel_dp->aux.ddc.dev.kobj,
714 intel_dp->aux.ddc.dev.kobj.name);
715 if (ret < 0) {
716 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
717 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700718 }
719}
720
Imre Deak80f65de2014-02-11 17:12:49 +0200721static void
722intel_dp_connector_unregister(struct intel_connector *intel_connector)
723{
724 struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
725
726 sysfs_remove_link(&intel_connector->base.kdev->kobj,
Jani Nikula0b998362014-03-14 16:51:17 +0200727 intel_dp->aux.ddc.dev.kobj.name);
Imre Deak80f65de2014-02-11 17:12:49 +0200728 intel_connector_unregister(intel_connector);
729}
730
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200731static void
732intel_dp_set_clock(struct intel_encoder *encoder,
733 struct intel_crtc_config *pipe_config, int link_bw)
734{
735 struct drm_device *dev = encoder->base.dev;
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800736 const struct dp_link_dpll *divisor = NULL;
737 int i, count = 0;
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200738
739 if (IS_G4X(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800740 divisor = gen4_dpll;
741 count = ARRAY_SIZE(gen4_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200742 } else if (IS_HASWELL(dev)) {
743 /* Haswell has special-purpose DP DDI clocks. */
744 } else if (HAS_PCH_SPLIT(dev)) {
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800745 divisor = pch_dpll;
746 count = ARRAY_SIZE(pch_dpll);
Chon Ming Leeef9348c2014-04-09 13:28:18 +0300747 } else if (IS_CHERRYVIEW(dev)) {
748 divisor = chv_dpll;
749 count = ARRAY_SIZE(chv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200750 } else if (IS_VALLEYVIEW(dev)) {
Chon Ming Lee65ce4bf2013-09-04 01:30:38 +0800751 divisor = vlv_dpll;
752 count = ARRAY_SIZE(vlv_dpll);
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200753 }
Chon Ming Lee9dd4ffd2013-09-04 01:30:37 +0800754
755 if (divisor && count) {
756 for (i = 0; i < count; i++) {
757 if (link_bw == divisor[i].link_bw) {
758 pipe_config->dpll = divisor[i].dpll;
759 pipe_config->clock_set = true;
760 break;
761 }
762 }
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200763 }
764}
765
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530766static void
767intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
768{
769 struct drm_device *dev = crtc->base.dev;
770 struct drm_i915_private *dev_priv = dev->dev_private;
771 enum transcoder transcoder = crtc->config.cpu_transcoder;
772
773 I915_WRITE(PIPE_DATA_M2(transcoder),
774 TU_SIZE(m_n->tu) | m_n->gmch_m);
775 I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
776 I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
777 I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
778}
779
Paulo Zanoni00c09d72012-10-26 19:05:52 -0200780bool
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100781intel_dp_compute_config(struct intel_encoder *encoder,
782 struct intel_crtc_config *pipe_config)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700783{
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100784 struct drm_device *dev = encoder->base.dev;
Daniel Vetter36008362013-03-27 00:44:59 +0100785 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100786 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100787 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300788 enum port port = dp_to_dig_port(intel_dp)->port;
Jesse Barnes2dd24552013-04-25 12:55:01 -0700789 struct intel_crtc *intel_crtc = encoder->new_crtc;
Jani Nikuladd06f902012-10-19 14:51:50 +0300790 struct intel_connector *intel_connector = intel_dp->attached_connector;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700791 int lane_count, clock;
Daniel Vetter397fe152012-10-22 22:56:43 +0200792 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
Todd Previte06ea66b2014-01-20 10:19:39 -0700793 /* Conveniently, the link BW constants become indices with a shift...*/
794 int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
Daniel Vetter083f9562012-04-20 20:23:49 +0200795 int bpp, mode_rate;
Todd Previte06ea66b2014-01-20 10:19:39 -0700796 static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
Daniel Vetterff9a6752013-06-01 17:16:21 +0200797 int link_avail, link_clock;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700798
Imre Deakbc7d38a2013-05-16 14:40:36 +0300799 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +0100800 pipe_config->has_pch_encoder = true;
801
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200802 pipe_config->has_dp_encoder = true;
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200803 pipe_config->has_audio = intel_dp->has_audio;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700804
Jani Nikuladd06f902012-10-19 14:51:50 +0300805 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
806 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
807 adjusted_mode);
Jesse Barnes2dd24552013-04-25 12:55:01 -0700808 if (!HAS_PCH_SPLIT(dev))
809 intel_gmch_panel_fitting(intel_crtc, pipe_config,
810 intel_connector->panel.fitting_mode);
811 else
Jesse Barnesb074cec2013-04-25 12:55:02 -0700812 intel_pch_panel_fitting(intel_crtc, pipe_config,
813 intel_connector->panel.fitting_mode);
Zhao Yakui0d3a1be2010-07-19 09:43:13 +0100814 }
815
Daniel Vettercb1793c2012-06-04 18:39:21 +0200816 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
Daniel Vetter0af78a22012-05-23 11:30:55 +0200817 return false;
818
Daniel Vetter083f9562012-04-20 20:23:49 +0200819 DRM_DEBUG_KMS("DP link computation with max lane count %i "
820 "max bw %02x pixel clock %iKHz\n",
Damien Lespiau241bfc32013-09-25 16:45:37 +0100821 max_lane_count, bws[max_clock],
822 adjusted_mode->crtc_clock);
Daniel Vetter083f9562012-04-20 20:23:49 +0200823
Daniel Vetter36008362013-03-27 00:44:59 +0100824 /* Walk through all bpp values. Luckily they're all nicely spaced with 2
825 * bpc in between. */
Daniel Vetter3e7ca982013-06-01 19:45:56 +0200826 bpp = pipe_config->pipe_bpp;
Jani Nikula6da7f102013-10-16 17:06:17 +0300827 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
828 dev_priv->vbt.edp_bpp < bpp) {
Imre Deak79842112013-07-18 17:44:13 +0300829 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
830 dev_priv->vbt.edp_bpp);
Jani Nikula6da7f102013-10-16 17:06:17 +0300831 bpp = dev_priv->vbt.edp_bpp;
Imre Deak79842112013-07-18 17:44:13 +0300832 }
Daniel Vetter657445f2013-05-04 10:09:18 +0200833
Daniel Vetter36008362013-03-27 00:44:59 +0100834 for (; bpp >= 6*3; bpp -= 2*3) {
Damien Lespiau241bfc32013-09-25 16:45:37 +0100835 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
836 bpp);
Daniel Vetterc4867932012-04-10 10:42:36 +0200837
Daniel Vetter38aecea2014-03-03 11:18:10 +0100838 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
839 for (clock = 0; clock <= max_clock; clock++) {
Daniel Vetter36008362013-03-27 00:44:59 +0100840 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
841 link_avail = intel_dp_max_data_rate(link_clock,
842 lane_count);
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200843
Daniel Vetter36008362013-03-27 00:44:59 +0100844 if (mode_rate <= link_avail) {
845 goto found;
846 }
847 }
848 }
849 }
850
851 return false;
852
853found:
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200854 if (intel_dp->color_range_auto) {
855 /*
856 * See:
857 * CEA-861-E - 5.1 Default Encoding Parameters
858 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
859 */
Thierry Reding18316c82012-12-20 15:41:44 +0100860 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
Ville Syrjälä55bc60d2013-01-17 16:31:29 +0200861 intel_dp->color_range = DP_COLOR_RANGE_16_235;
862 else
863 intel_dp->color_range = 0;
864 }
865
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200866 if (intel_dp->color_range)
Daniel Vetter50f3b012013-03-27 00:44:56 +0100867 pipe_config->limited_color_range = true;
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200868
Daniel Vetter36008362013-03-27 00:44:59 +0100869 intel_dp->link_bw = bws[clock];
870 intel_dp->lane_count = lane_count;
Daniel Vetter657445f2013-05-04 10:09:18 +0200871 pipe_config->pipe_bpp = bpp;
Daniel Vetterff9a6752013-06-01 17:16:21 +0200872 pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
Daniel Vetterc4867932012-04-10 10:42:36 +0200873
Daniel Vetter36008362013-03-27 00:44:59 +0100874 DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
875 intel_dp->link_bw, intel_dp->lane_count,
Daniel Vetterff9a6752013-06-01 17:16:21 +0200876 pipe_config->port_clock, bpp);
Daniel Vetter36008362013-03-27 00:44:59 +0100877 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
878 mode_rate, link_avail);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700879
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200880 intel_link_compute_m_n(bpp, lane_count,
Damien Lespiau241bfc32013-09-25 16:45:37 +0100881 adjusted_mode->crtc_clock,
882 pipe_config->port_clock,
Daniel Vetter03afc4a2013-04-02 23:42:31 +0200883 &pipe_config->dp_m_n);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700884
Pradeep Bhat439d7ac2014-04-05 12:13:28 +0530885 if (intel_connector->panel.downclock_mode != NULL &&
886 intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
887 intel_link_compute_m_n(bpp, lane_count,
888 intel_connector->panel.downclock_mode->clock,
889 pipe_config->port_clock,
890 &pipe_config->dp_m2_n2);
891 }
892
Daniel Vetterc6bb3532013-04-19 11:14:33 +0200893 intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
894
Daniel Vetter36008362013-03-27 00:44:59 +0100895 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700896}
897
Daniel Vetter7c62a162013-06-01 17:16:20 +0200898static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
Daniel Vetterea9b6002012-11-29 15:59:31 +0100899{
Daniel Vetter7c62a162013-06-01 17:16:20 +0200900 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
901 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
902 struct drm_device *dev = crtc->base.dev;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100903 struct drm_i915_private *dev_priv = dev->dev_private;
904 u32 dpa_ctl;
905
Daniel Vetterff9a6752013-06-01 17:16:21 +0200906 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
Daniel Vetterea9b6002012-11-29 15:59:31 +0100907 dpa_ctl = I915_READ(DP_A);
908 dpa_ctl &= ~DP_PLL_FREQ_MASK;
909
Daniel Vetterff9a6752013-06-01 17:16:21 +0200910 if (crtc->config.port_clock == 162000) {
Daniel Vetter1ce17032012-11-29 15:59:32 +0100911 /* For a long time we've carried around a ILK-DevA w/a for the
912 * 160MHz clock. If we're really unlucky, it's still required.
913 */
914 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
Daniel Vetterea9b6002012-11-29 15:59:31 +0100915 dpa_ctl |= DP_PLL_FREQ_160MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200916 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100917 } else {
918 dpa_ctl |= DP_PLL_FREQ_270MHZ;
Daniel Vetter7c62a162013-06-01 17:16:20 +0200919 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
Daniel Vetterea9b6002012-11-29 15:59:31 +0100920 }
Daniel Vetter1ce17032012-11-29 15:59:32 +0100921
Daniel Vetterea9b6002012-11-29 15:59:31 +0100922 I915_WRITE(DP_A, dpa_ctl);
923
924 POSTING_READ(DP_A);
925 udelay(500);
926}
927
Daniel Vetter8ac33ed2014-04-24 23:54:54 +0200928static void intel_dp_prepare(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700929{
Daniel Vetterb934223d2013-07-21 21:37:05 +0200930 struct drm_device *dev = encoder->base.dev;
Keith Packard417e8222011-11-01 19:54:11 -0700931 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200932 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +0300933 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200934 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
935 struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700936
Keith Packard417e8222011-11-01 19:54:11 -0700937 /*
Keith Packard1a2eb462011-11-16 16:26:07 -0800938 * There are four kinds of DP registers:
Keith Packard417e8222011-11-01 19:54:11 -0700939 *
940 * IBX PCH
Keith Packard1a2eb462011-11-16 16:26:07 -0800941 * SNB CPU
942 * IVB CPU
Keith Packard417e8222011-11-01 19:54:11 -0700943 * CPT PCH
944 *
945 * IBX PCH and CPU are the same for almost everything,
946 * except that the CPU DP PLL is configured in this
947 * register
948 *
949 * CPT PCH is quite different, having many bits moved
950 * to the TRANS_DP_CTL register instead. That
951 * configuration happens (oddly) in ironlake_pch_enable
952 */
Adam Jackson9c9e7922010-04-05 17:57:59 -0400953
Keith Packard417e8222011-11-01 19:54:11 -0700954 /* Preserve the BIOS-computed detected bit. This is
955 * supposed to be read-only.
956 */
957 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700958
Keith Packard417e8222011-11-01 19:54:11 -0700959 /* Handle DP bits in common between all three register formats */
Keith Packard417e8222011-11-01 19:54:11 -0700960 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
Daniel Vetter17aa6be2013-04-30 14:01:40 +0200961 intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
Keith Packarda4fc5ed2009-04-07 16:16:42 -0700962
Daniel Vetter9ed109a2014-04-24 23:54:52 +0200963 if (crtc->config.has_audio) {
Wu Fengguange0dac652011-09-05 14:25:34 +0800964 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
Daniel Vetter7c62a162013-06-01 17:16:20 +0200965 pipe_name(crtc->pipe));
Chris Wilsonea5b2132010-08-04 13:50:23 +0100966 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
Daniel Vetterb934223d2013-07-21 21:37:05 +0200967 intel_write_eld(&encoder->base, adjusted_mode);
Wu Fengguange0dac652011-09-05 14:25:34 +0800968 }
Paulo Zanoni247d89f2012-10-15 15:51:33 -0300969
Keith Packard417e8222011-11-01 19:54:11 -0700970 /* Split out the IBX/CPU vs CPT settings */
Zhenyu Wang32f9d652009-07-24 01:00:32 +0800971
Imre Deakbc7d38a2013-05-16 14:40:36 +0300972 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Keith Packard1a2eb462011-11-16 16:26:07 -0800973 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
974 intel_dp->DP |= DP_SYNC_HS_HIGH;
975 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
976 intel_dp->DP |= DP_SYNC_VS_HIGH;
977 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
978
Jani Nikula6aba5b62013-10-04 15:08:10 +0300979 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard1a2eb462011-11-16 16:26:07 -0800980 intel_dp->DP |= DP_ENHANCED_FRAMING;
981
Daniel Vetter7c62a162013-06-01 17:16:20 +0200982 intel_dp->DP |= crtc->pipe << 29;
Imre Deakbc7d38a2013-05-16 14:40:36 +0300983 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Jesse Barnesb2634012013-03-28 09:55:40 -0700984 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
Ville Syrjälä3685a8f2013-01-17 16:31:28 +0200985 intel_dp->DP |= intel_dp->color_range;
Keith Packard417e8222011-11-01 19:54:11 -0700986
987 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
988 intel_dp->DP |= DP_SYNC_HS_HIGH;
989 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
990 intel_dp->DP |= DP_SYNC_VS_HIGH;
991 intel_dp->DP |= DP_LINK_TRAIN_OFF;
992
Jani Nikula6aba5b62013-10-04 15:08:10 +0300993 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
Keith Packard417e8222011-11-01 19:54:11 -0700994 intel_dp->DP |= DP_ENHANCED_FRAMING;
995
Chon Ming Lee44f37d12014-04-09 13:28:21 +0300996 if (!IS_CHERRYVIEW(dev)) {
997 if (crtc->pipe == 1)
998 intel_dp->DP |= DP_PIPEB_SELECT;
999 } else {
1000 intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1001 }
Keith Packard417e8222011-11-01 19:54:11 -07001002 } else {
1003 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001004 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001005}
1006
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001007#define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1008#define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001009
Paulo Zanoni1a5ef5b2013-12-19 14:29:43 -02001010#define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0)
1011#define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0)
Keith Packard99ea7122011-11-01 19:57:50 -07001012
Paulo Zanoniffd6749d2013-12-19 14:29:42 -02001013#define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1014#define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
Keith Packard99ea7122011-11-01 19:57:50 -07001015
Daniel Vetter4be73782014-01-17 14:39:48 +01001016static void wait_panel_status(struct intel_dp *intel_dp,
Keith Packard99ea7122011-11-01 19:57:50 -07001017 u32 mask,
1018 u32 value)
1019{
Paulo Zanoni30add222012-10-26 19:05:45 -02001020 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001021 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07001022 u32 pp_stat_reg, pp_ctrl_reg;
1023
Jani Nikulabf13e812013-09-06 07:40:05 +03001024 pp_stat_reg = _pp_stat_reg(intel_dp);
1025 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001026
1027 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001028 mask, value,
1029 I915_READ(pp_stat_reg),
1030 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001031
Jesse Barnes453c5422013-03-28 09:55:41 -07001032 if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001033 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07001034 I915_READ(pp_stat_reg),
1035 I915_READ(pp_ctrl_reg));
Keith Packard99ea7122011-11-01 19:57:50 -07001036 }
Chris Wilson54c136d2013-12-02 09:57:16 +00001037
1038 DRM_DEBUG_KMS("Wait complete\n");
Keith Packard99ea7122011-11-01 19:57:50 -07001039}
1040
Daniel Vetter4be73782014-01-17 14:39:48 +01001041static void wait_panel_on(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001042{
1043 DRM_DEBUG_KMS("Wait for panel power on\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001044 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001045}
1046
Daniel Vetter4be73782014-01-17 14:39:48 +01001047static void wait_panel_off(struct intel_dp *intel_dp)
Keith Packardbd943152011-09-18 23:09:52 -07001048{
Keith Packardbd943152011-09-18 23:09:52 -07001049 DRM_DEBUG_KMS("Wait for panel power off time\n");
Daniel Vetter4be73782014-01-17 14:39:48 +01001050 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
Keith Packardbd943152011-09-18 23:09:52 -07001051}
Keith Packardbd943152011-09-18 23:09:52 -07001052
Daniel Vetter4be73782014-01-17 14:39:48 +01001053static void wait_panel_power_cycle(struct intel_dp *intel_dp)
Keith Packard99ea7122011-11-01 19:57:50 -07001054{
1055 DRM_DEBUG_KMS("Wait for panel power cycle\n");
Paulo Zanonidce56b32013-12-19 14:29:40 -02001056
1057 /* When we disable the VDD override bit last we have to do the manual
1058 * wait. */
1059 wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1060 intel_dp->panel_power_cycle_delay);
1061
Daniel Vetter4be73782014-01-17 14:39:48 +01001062 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
Keith Packard99ea7122011-11-01 19:57:50 -07001063}
Keith Packardbd943152011-09-18 23:09:52 -07001064
Daniel Vetter4be73782014-01-17 14:39:48 +01001065static void wait_backlight_on(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001066{
1067 wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1068 intel_dp->backlight_on_delay);
1069}
1070
Daniel Vetter4be73782014-01-17 14:39:48 +01001071static void edp_wait_backlight_off(struct intel_dp *intel_dp)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001072{
1073 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1074 intel_dp->backlight_off_delay);
1075}
Keith Packard99ea7122011-11-01 19:57:50 -07001076
Keith Packard832dd3c2011-11-01 19:34:06 -07001077/* Read the current pp_control value, unlocking the register if it
1078 * is locked
1079 */
1080
Jesse Barnes453c5422013-03-28 09:55:41 -07001081static u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
Keith Packard832dd3c2011-11-01 19:34:06 -07001082{
Jesse Barnes453c5422013-03-28 09:55:41 -07001083 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1084 struct drm_i915_private *dev_priv = dev->dev_private;
1085 u32 control;
Jesse Barnes453c5422013-03-28 09:55:41 -07001086
Jani Nikulabf13e812013-09-06 07:40:05 +03001087 control = I915_READ(_pp_ctrl_reg(intel_dp));
Keith Packard832dd3c2011-11-01 19:34:06 -07001088 control &= ~PANEL_UNLOCK_MASK;
1089 control |= PANEL_UNLOCK_REGS;
1090 return control;
Keith Packardbd943152011-09-18 23:09:52 -07001091}
1092
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001093static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001094{
Paulo Zanoni30add222012-10-26 19:05:45 -02001095 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deak4e6e1a52014-03-27 17:45:11 +02001096 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1097 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jesse Barnes5d613502011-01-24 17:10:54 -08001098 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001099 enum intel_display_power_domain power_domain;
Jesse Barnes5d613502011-01-24 17:10:54 -08001100 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001101 u32 pp_stat_reg, pp_ctrl_reg;
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001102 bool need_to_disable = !intel_dp->want_panel_vdd;
Jesse Barnes5d613502011-01-24 17:10:54 -08001103
Keith Packard97af61f572011-09-28 16:23:51 -07001104 if (!is_edp(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001105 return false;
Keith Packardbd943152011-09-18 23:09:52 -07001106
1107 intel_dp->want_panel_vdd = true;
Keith Packard99ea7122011-11-01 19:57:50 -07001108
Daniel Vetter4be73782014-01-17 14:39:48 +01001109 if (edp_have_panel_vdd(intel_dp))
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001110 return need_to_disable;
Paulo Zanonib0665d52013-10-30 19:50:27 -02001111
Imre Deak4e6e1a52014-03-27 17:45:11 +02001112 power_domain = intel_display_port_power_domain(intel_encoder);
1113 intel_display_power_get(dev_priv, power_domain);
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001114
Paulo Zanonib0665d52013-10-30 19:50:27 -02001115 DRM_DEBUG_KMS("Turning eDP VDD on\n");
Keith Packardbd943152011-09-18 23:09:52 -07001116
Daniel Vetter4be73782014-01-17 14:39:48 +01001117 if (!edp_have_panel_power(intel_dp))
1118 wait_panel_power_cycle(intel_dp);
Keith Packard99ea7122011-11-01 19:57:50 -07001119
Jesse Barnes453c5422013-03-28 09:55:41 -07001120 pp = ironlake_get_pp_control(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001121 pp |= EDP_FORCE_VDD;
Keith Packardebf33b12011-09-29 15:53:27 -07001122
Jani Nikulabf13e812013-09-06 07:40:05 +03001123 pp_stat_reg = _pp_stat_reg(intel_dp);
1124 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001125
1126 I915_WRITE(pp_ctrl_reg, pp);
1127 POSTING_READ(pp_ctrl_reg);
1128 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1129 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Keith Packardebf33b12011-09-29 15:53:27 -07001130 /*
1131 * If the panel wasn't on, delay before accessing aux channel
1132 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001133 if (!edp_have_panel_power(intel_dp)) {
Keith Packardbd943152011-09-18 23:09:52 -07001134 DRM_DEBUG_KMS("eDP was not running\n");
Keith Packardf01eca22011-09-28 16:48:10 -07001135 msleep(intel_dp->panel_power_up_delay);
Keith Packardf01eca22011-09-28 16:48:10 -07001136 }
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001137
1138 return need_to_disable;
1139}
1140
Daniel Vetterb80d6c72014-03-19 15:54:37 +01001141void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
Jani Nikulaadddaaf2014-03-14 16:51:13 +02001142{
1143 if (is_edp(intel_dp)) {
1144 bool vdd = _edp_panel_vdd_on(intel_dp);
1145
1146 WARN(!vdd, "eDP VDD already requested on\n");
1147 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001148}
1149
Daniel Vetter4be73782014-01-17 14:39:48 +01001150static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
Jesse Barnes5d613502011-01-24 17:10:54 -08001151{
Paulo Zanoni30add222012-10-26 19:05:45 -02001152 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes5d613502011-01-24 17:10:54 -08001153 struct drm_i915_private *dev_priv = dev->dev_private;
1154 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001155 u32 pp_stat_reg, pp_ctrl_reg;
Jesse Barnes5d613502011-01-24 17:10:54 -08001156
Daniel Vettera0e99e62012-12-02 01:05:46 +01001157 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1158
Daniel Vetter4be73782014-01-17 14:39:48 +01001159 if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
Imre Deak4e6e1a52014-03-27 17:45:11 +02001160 struct intel_digital_port *intel_dig_port =
1161 dp_to_dig_port(intel_dp);
1162 struct intel_encoder *intel_encoder = &intel_dig_port->base;
1163 enum intel_display_power_domain power_domain;
1164
Paulo Zanonib0665d52013-10-30 19:50:27 -02001165 DRM_DEBUG_KMS("Turning eDP VDD off\n");
1166
Jesse Barnes453c5422013-03-28 09:55:41 -07001167 pp = ironlake_get_pp_control(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001168 pp &= ~EDP_FORCE_VDD;
Jesse Barnes453c5422013-03-28 09:55:41 -07001169
Paulo Zanoni9f08ef52013-10-31 12:44:21 -02001170 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1171 pp_stat_reg = _pp_stat_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001172
1173 I915_WRITE(pp_ctrl_reg, pp);
1174 POSTING_READ(pp_ctrl_reg);
Jesse Barnes5d613502011-01-24 17:10:54 -08001175
Keith Packardbd943152011-09-18 23:09:52 -07001176 /* Make sure sequencer is idle before allowing subsequent activity */
Jesse Barnes453c5422013-03-28 09:55:41 -07001177 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1178 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
Paulo Zanoni90791a52013-12-06 17:32:42 -02001179
1180 if ((pp & POWER_TARGET_ON) == 0)
Paulo Zanonidce56b32013-12-19 14:29:40 -02001181 intel_dp->last_power_cycle = jiffies;
Paulo Zanonie9cb81a2013-11-21 13:47:23 -02001182
Imre Deak4e6e1a52014-03-27 17:45:11 +02001183 power_domain = intel_display_port_power_domain(intel_encoder);
1184 intel_display_power_put(dev_priv, power_domain);
Keith Packardbd943152011-09-18 23:09:52 -07001185 }
1186}
1187
Daniel Vetter4be73782014-01-17 14:39:48 +01001188static void edp_panel_vdd_work(struct work_struct *__work)
Keith Packardbd943152011-09-18 23:09:52 -07001189{
1190 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1191 struct intel_dp, panel_vdd_work);
Paulo Zanoni30add222012-10-26 19:05:45 -02001192 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001193
Keith Packard627f7672011-10-31 11:30:10 -07001194 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01001195 edp_panel_vdd_off_sync(intel_dp);
Keith Packard627f7672011-10-31 11:30:10 -07001196 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07001197}
1198
Daniel Vetter4be73782014-01-17 14:39:48 +01001199static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
Keith Packardbd943152011-09-18 23:09:52 -07001200{
Keith Packard97af61f572011-09-28 16:23:51 -07001201 if (!is_edp(intel_dp))
1202 return;
Jesse Barnes5d613502011-01-24 17:10:54 -08001203
Keith Packardbd943152011-09-18 23:09:52 -07001204 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
Keith Packardf2e8b182011-11-01 20:01:35 -07001205
Keith Packardbd943152011-09-18 23:09:52 -07001206 intel_dp->want_panel_vdd = false;
1207
1208 if (sync) {
Daniel Vetter4be73782014-01-17 14:39:48 +01001209 edp_panel_vdd_off_sync(intel_dp);
Keith Packardbd943152011-09-18 23:09:52 -07001210 } else {
1211 /*
1212 * Queue the timer to fire a long
1213 * time from now (relative to the power down delay)
1214 * to keep the panel power up across a sequence of operations
1215 */
1216 schedule_delayed_work(&intel_dp->panel_vdd_work,
1217 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1218 }
Jesse Barnes5d613502011-01-24 17:10:54 -08001219}
1220
Daniel Vetter4be73782014-01-17 14:39:48 +01001221void intel_edp_panel_on(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001222{
Paulo Zanoni30add222012-10-26 19:05:45 -02001223 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001224 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packard99ea7122011-11-01 19:57:50 -07001225 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001226 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001227
Keith Packard97af61f572011-09-28 16:23:51 -07001228 if (!is_edp(intel_dp))
Keith Packardbd943152011-09-18 23:09:52 -07001229 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001230
1231 DRM_DEBUG_KMS("Turn eDP power on\n");
1232
Daniel Vetter4be73782014-01-17 14:39:48 +01001233 if (edp_have_panel_power(intel_dp)) {
Keith Packard99ea7122011-11-01 19:57:50 -07001234 DRM_DEBUG_KMS("eDP power already on\n");
Keith Packard7d639f32011-09-29 16:05:34 -07001235 return;
Keith Packard99ea7122011-11-01 19:57:50 -07001236 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001237
Daniel Vetter4be73782014-01-17 14:39:48 +01001238 wait_panel_power_cycle(intel_dp);
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001239
Jani Nikulabf13e812013-09-06 07:40:05 +03001240 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001241 pp = ironlake_get_pp_control(intel_dp);
Keith Packard05ce1a42011-09-29 16:33:01 -07001242 if (IS_GEN5(dev)) {
1243 /* ILK workaround: disable reset around power sequence */
1244 pp &= ~PANEL_POWER_RESET;
Jani Nikulabf13e812013-09-06 07:40:05 +03001245 I915_WRITE(pp_ctrl_reg, pp);
1246 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001247 }
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001248
Keith Packard1c0ae802011-09-19 13:59:29 -07001249 pp |= POWER_TARGET_ON;
Keith Packard99ea7122011-11-01 19:57:50 -07001250 if (!IS_GEN5(dev))
1251 pp |= PANEL_POWER_RESET;
1252
Jesse Barnes453c5422013-03-28 09:55:41 -07001253 I915_WRITE(pp_ctrl_reg, pp);
1254 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001255
Daniel Vetter4be73782014-01-17 14:39:48 +01001256 wait_panel_on(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001257 intel_dp->last_power_on = jiffies;
Jesse Barnes9934c132010-07-22 13:18:19 -07001258
Keith Packard05ce1a42011-09-29 16:33:01 -07001259 if (IS_GEN5(dev)) {
1260 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
Jani Nikulabf13e812013-09-06 07:40:05 +03001261 I915_WRITE(pp_ctrl_reg, pp);
1262 POSTING_READ(pp_ctrl_reg);
Keith Packard05ce1a42011-09-29 16:33:01 -07001263 }
Jesse Barnes9934c132010-07-22 13:18:19 -07001264}
1265
Daniel Vetter4be73782014-01-17 14:39:48 +01001266void intel_edp_panel_off(struct intel_dp *intel_dp)
Jesse Barnes9934c132010-07-22 13:18:19 -07001267{
Imre Deak4e6e1a52014-03-27 17:45:11 +02001268 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1269 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanoni30add222012-10-26 19:05:45 -02001270 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Jesse Barnes9934c132010-07-22 13:18:19 -07001271 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak4e6e1a52014-03-27 17:45:11 +02001272 enum intel_display_power_domain power_domain;
Keith Packard99ea7122011-11-01 19:57:50 -07001273 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001274 u32 pp_ctrl_reg;
Jesse Barnes9934c132010-07-22 13:18:19 -07001275
Keith Packard97af61f572011-09-28 16:23:51 -07001276 if (!is_edp(intel_dp))
1277 return;
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001278
Keith Packard99ea7122011-11-01 19:57:50 -07001279 DRM_DEBUG_KMS("Turn eDP power off\n");
Jesse Barnes37c6c9b2010-08-11 10:04:43 -07001280
Daniel Vetter4be73782014-01-17 14:39:48 +01001281 edp_wait_backlight_off(intel_dp);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001282
Jani Nikula24f3e092014-03-17 16:43:36 +02001283 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1284
Jesse Barnes453c5422013-03-28 09:55:41 -07001285 pp = ironlake_get_pp_control(intel_dp);
Daniel Vetter35a38552012-08-12 22:17:14 +02001286 /* We need to switch off panel power _and_ force vdd, for otherwise some
1287 * panels get very unhappy and cease to work. */
Patrik Jakobssonb3064152014-03-04 00:42:44 +01001288 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
1289 EDP_BLC_ENABLE);
Jesse Barnes453c5422013-03-28 09:55:41 -07001290
Jani Nikulabf13e812013-09-06 07:40:05 +03001291 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001292
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001293 intel_dp->want_panel_vdd = false;
1294
Jesse Barnes453c5422013-03-28 09:55:41 -07001295 I915_WRITE(pp_ctrl_reg, pp);
1296 POSTING_READ(pp_ctrl_reg);
Jesse Barnes9934c132010-07-22 13:18:19 -07001297
Paulo Zanonidce56b32013-12-19 14:29:40 -02001298 intel_dp->last_power_cycle = jiffies;
Daniel Vetter4be73782014-01-17 14:39:48 +01001299 wait_panel_off(intel_dp);
Paulo Zanoni849e39f2014-03-07 20:05:20 -03001300
1301 /* We got a reference when we enabled the VDD. */
Imre Deak4e6e1a52014-03-27 17:45:11 +02001302 power_domain = intel_display_port_power_domain(intel_encoder);
1303 intel_display_power_put(dev_priv, power_domain);
Jesse Barnes9934c132010-07-22 13:18:19 -07001304}
1305
Daniel Vetter4be73782014-01-17 14:39:48 +01001306void intel_edp_backlight_on(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001307{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001308 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1309 struct drm_device *dev = intel_dig_port->base.base.dev;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001310 struct drm_i915_private *dev_priv = dev->dev_private;
1311 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001312 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001313
Keith Packardf01eca22011-09-28 16:48:10 -07001314 if (!is_edp(intel_dp))
1315 return;
1316
Zhao Yakui28c97732009-10-09 11:39:41 +08001317 DRM_DEBUG_KMS("\n");
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07001318 /*
1319 * If we enable the backlight right away following a panel power
1320 * on, we may see slight flicker as the panel syncs with the eDP
1321 * link. So delay a bit to make sure the image is solid before
1322 * allowing it to appear.
1323 */
Daniel Vetter4be73782014-01-17 14:39:48 +01001324 wait_backlight_on(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001325 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001326 pp |= EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001327
Jani Nikulabf13e812013-09-06 07:40:05 +03001328 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001329
1330 I915_WRITE(pp_ctrl_reg, pp);
1331 POSTING_READ(pp_ctrl_reg);
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001332
Jesse Barnes752aa882013-10-31 18:55:49 +02001333 intel_panel_enable_backlight(intel_dp->attached_connector);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001334}
1335
Daniel Vetter4be73782014-01-17 14:39:48 +01001336void intel_edp_backlight_off(struct intel_dp *intel_dp)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001337{
Paulo Zanoni30add222012-10-26 19:05:45 -02001338 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001339 struct drm_i915_private *dev_priv = dev->dev_private;
1340 u32 pp;
Jesse Barnes453c5422013-03-28 09:55:41 -07001341 u32 pp_ctrl_reg;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001342
Keith Packardf01eca22011-09-28 16:48:10 -07001343 if (!is_edp(intel_dp))
1344 return;
1345
Jesse Barnes752aa882013-10-31 18:55:49 +02001346 intel_panel_disable_backlight(intel_dp->attached_connector);
Daniel Vetter035aa3d2012-10-20 20:57:42 +02001347
Zhao Yakui28c97732009-10-09 11:39:41 +08001348 DRM_DEBUG_KMS("\n");
Jesse Barnes453c5422013-03-28 09:55:41 -07001349 pp = ironlake_get_pp_control(intel_dp);
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001350 pp &= ~EDP_BLC_ENABLE;
Jesse Barnes453c5422013-03-28 09:55:41 -07001351
Jani Nikulabf13e812013-09-06 07:40:05 +03001352 pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
Jesse Barnes453c5422013-03-28 09:55:41 -07001353
1354 I915_WRITE(pp_ctrl_reg, pp);
1355 POSTING_READ(pp_ctrl_reg);
Paulo Zanonidce56b32013-12-19 14:29:40 -02001356 intel_dp->last_backlight_off = jiffies;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08001357}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001358
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001359static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001360{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001361 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1362 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1363 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001364 struct drm_i915_private *dev_priv = dev->dev_private;
1365 u32 dpa_ctl;
1366
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001367 assert_pipe_disabled(dev_priv,
1368 to_intel_crtc(crtc)->pipe);
1369
Jesse Barnesd240f202010-08-13 15:43:26 -07001370 DRM_DEBUG_KMS("\n");
1371 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001372 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1373 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1374
1375 /* We don't adjust intel_dp->DP while tearing down the link, to
1376 * facilitate link retraining (e.g. after hotplug). Hence clear all
1377 * enable bits here to ensure that we don't enable too much. */
1378 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1379 intel_dp->DP |= DP_PLL_ENABLE;
1380 I915_WRITE(DP_A, intel_dp->DP);
Jesse Barnes298b0b32010-10-07 16:01:24 -07001381 POSTING_READ(DP_A);
1382 udelay(200);
Jesse Barnesd240f202010-08-13 15:43:26 -07001383}
1384
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001385static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
Jesse Barnesd240f202010-08-13 15:43:26 -07001386{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02001387 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1388 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1389 struct drm_device *dev = crtc->dev;
Jesse Barnesd240f202010-08-13 15:43:26 -07001390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 u32 dpa_ctl;
1392
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001393 assert_pipe_disabled(dev_priv,
1394 to_intel_crtc(crtc)->pipe);
1395
Jesse Barnesd240f202010-08-13 15:43:26 -07001396 dpa_ctl = I915_READ(DP_A);
Daniel Vetter07679352012-09-06 22:15:42 +02001397 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1398 "dp pll off, should be on\n");
1399 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1400
1401 /* We can't rely on the value tracked for the DP register in
1402 * intel_dp->DP because link_down must not change that (otherwise link
1403 * re-training will fail. */
Jesse Barnes298b0b32010-10-07 16:01:24 -07001404 dpa_ctl &= ~DP_PLL_ENABLE;
Jesse Barnesd240f202010-08-13 15:43:26 -07001405 I915_WRITE(DP_A, dpa_ctl);
Chris Wilson1af5fa12010-09-08 21:07:28 +01001406 POSTING_READ(DP_A);
Jesse Barnesd240f202010-08-13 15:43:26 -07001407 udelay(200);
1408}
1409
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001410/* If the sink supports it, try to set the power state appropriately */
Paulo Zanonic19b0662012-10-15 15:51:41 -03001411void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001412{
1413 int ret, i;
1414
1415 /* Should have a valid DPCD by this point */
1416 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1417 return;
1418
1419 if (mode != DRM_MODE_DPMS_ON) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001420 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1421 DP_SET_POWER_D3);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001422 if (ret != 1)
1423 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1424 } else {
1425 /*
1426 * When turning on, we need to retry for 1ms to give the sink
1427 * time to wake up.
1428 */
1429 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02001430 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
1431 DP_SET_POWER_D0);
Jesse Barnesc7ad3812011-07-07 11:11:03 -07001432 if (ret == 1)
1433 break;
1434 msleep(1);
1435 }
1436 }
1437}
1438
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001439static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1440 enum pipe *pipe)
Jesse Barnesd240f202010-08-13 15:43:26 -07001441{
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001443 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001444 struct drm_device *dev = encoder->base.dev;
1445 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak6d129be2014-03-05 16:20:54 +02001446 enum intel_display_power_domain power_domain;
1447 u32 tmp;
1448
1449 power_domain = intel_display_port_power_domain(encoder);
1450 if (!intel_display_power_enabled(dev_priv, power_domain))
1451 return false;
1452
1453 tmp = I915_READ(intel_dp->output_reg);
Jesse Barnesd240f202010-08-13 15:43:26 -07001454
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001455 if (!(tmp & DP_PORT_EN))
1456 return false;
1457
Imre Deakbc7d38a2013-05-16 14:40:36 +03001458 if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001459 *pipe = PORT_TO_PIPE_CPT(tmp);
Ville Syrjälä71485e02014-04-09 13:28:55 +03001460 } else if (IS_CHERRYVIEW(dev)) {
1461 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001462 } else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001463 *pipe = PORT_TO_PIPE(tmp);
1464 } else {
1465 u32 trans_sel;
1466 u32 trans_dp;
1467 int i;
1468
1469 switch (intel_dp->output_reg) {
1470 case PCH_DP_B:
1471 trans_sel = TRANS_DP_PORT_SEL_B;
1472 break;
1473 case PCH_DP_C:
1474 trans_sel = TRANS_DP_PORT_SEL_C;
1475 break;
1476 case PCH_DP_D:
1477 trans_sel = TRANS_DP_PORT_SEL_D;
1478 break;
1479 default:
1480 return true;
1481 }
1482
1483 for_each_pipe(i) {
1484 trans_dp = I915_READ(TRANS_DP_CTL(i));
1485 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1486 *pipe = i;
1487 return true;
1488 }
1489 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001490
Daniel Vetter4a0833e2012-10-26 10:58:11 +02001491 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1492 intel_dp->output_reg);
1493 }
Daniel Vetter19d8fe12012-07-02 13:26:27 +02001494
1495 return true;
1496}
1497
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001498static void intel_dp_get_config(struct intel_encoder *encoder,
1499 struct intel_crtc_config *pipe_config)
1500{
1501 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001502 u32 tmp, flags = 0;
Xiong Zhang63000ef2013-06-28 12:59:06 +08001503 struct drm_device *dev = encoder->base.dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 enum port port = dp_to_dig_port(intel_dp)->port;
1506 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
Ville Syrjälä18442d02013-09-13 16:00:08 +03001507 int dotclock;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001508
Daniel Vetter9ed109a2014-04-24 23:54:52 +02001509 tmp = I915_READ(intel_dp->output_reg);
1510 if (tmp & DP_AUDIO_OUTPUT_ENABLE)
1511 pipe_config->has_audio = true;
1512
Xiong Zhang63000ef2013-06-28 12:59:06 +08001513 if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
Xiong Zhang63000ef2013-06-28 12:59:06 +08001514 if (tmp & DP_SYNC_HS_HIGH)
1515 flags |= DRM_MODE_FLAG_PHSYNC;
1516 else
1517 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001518
Xiong Zhang63000ef2013-06-28 12:59:06 +08001519 if (tmp & DP_SYNC_VS_HIGH)
1520 flags |= DRM_MODE_FLAG_PVSYNC;
1521 else
1522 flags |= DRM_MODE_FLAG_NVSYNC;
1523 } else {
1524 tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1525 if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
1526 flags |= DRM_MODE_FLAG_PHSYNC;
1527 else
1528 flags |= DRM_MODE_FLAG_NHSYNC;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001529
Xiong Zhang63000ef2013-06-28 12:59:06 +08001530 if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
1531 flags |= DRM_MODE_FLAG_PVSYNC;
1532 else
1533 flags |= DRM_MODE_FLAG_NVSYNC;
1534 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001535
1536 pipe_config->adjusted_mode.flags |= flags;
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001537
Ville Syrjäläeb14cb72013-09-10 17:02:54 +03001538 pipe_config->has_dp_encoder = true;
1539
1540 intel_dp_get_m_n(crtc, pipe_config);
1541
Ville Syrjälä18442d02013-09-13 16:00:08 +03001542 if (port == PORT_A) {
Jesse Barnesf1f644d2013-06-27 00:39:25 +03001543 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
1544 pipe_config->port_clock = 162000;
1545 else
1546 pipe_config->port_clock = 270000;
1547 }
Ville Syrjälä18442d02013-09-13 16:00:08 +03001548
1549 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1550 &pipe_config->dp_m_n);
1551
1552 if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
1553 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1554
Damien Lespiau241bfc32013-09-25 16:45:37 +01001555 pipe_config->adjusted_mode.crtc_clock = dotclock;
Daniel Vetter7f16e5c2013-11-04 16:28:47 +01001556
Jani Nikulac6cd2ee2013-10-21 10:52:07 +03001557 if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
1558 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
1559 /*
1560 * This is a big fat ugly hack.
1561 *
1562 * Some machines in UEFI boot mode provide us a VBT that has 18
1563 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
1564 * unknown we fail to light up. Yet the same BIOS boots up with
1565 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
1566 * max, not what it tells us to use.
1567 *
1568 * Note: This will still be broken if the eDP panel is not lit
1569 * up by the BIOS, and thus we can't get the mode at module
1570 * load.
1571 */
1572 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
1573 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
1574 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
1575 }
Jesse Barnes045ac3b2013-05-14 17:08:26 -07001576}
1577
Rodrigo Vivia031d702013-10-03 16:15:06 -03001578static bool is_edp_psr(struct drm_device *dev)
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001579{
Rodrigo Vivia031d702013-10-03 16:15:06 -03001580 struct drm_i915_private *dev_priv = dev->dev_private;
1581
1582 return dev_priv->psr.sink_support;
Shobhit Kumar2293bb52013-07-11 18:44:56 -03001583}
1584
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001585static bool intel_edp_is_psr_enabled(struct drm_device *dev)
1586{
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588
Ben Widawsky18b59922013-09-20 09:35:30 -07001589 if (!HAS_PSR(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001590 return false;
1591
Ben Widawsky18b59922013-09-20 09:35:30 -07001592 return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001593}
1594
1595static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
1596 struct edp_vsc_psr *vsc_psr)
1597{
1598 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1599 struct drm_device *dev = dig_port->base.base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
1602 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
1603 u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
1604 uint32_t *data = (uint32_t *) vsc_psr;
1605 unsigned int i;
1606
1607 /* As per BSPec (Pipe Video Data Island Packet), we need to disable
1608 the video DIP being updated before program video DIP data buffer
1609 registers for DIP being updated. */
1610 I915_WRITE(ctl_reg, 0);
1611 POSTING_READ(ctl_reg);
1612
1613 for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
1614 if (i < sizeof(struct edp_vsc_psr))
1615 I915_WRITE(data_reg + i, *data++);
1616 else
1617 I915_WRITE(data_reg + i, 0);
1618 }
1619
1620 I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
1621 POSTING_READ(ctl_reg);
1622}
1623
1624static void intel_edp_psr_setup(struct intel_dp *intel_dp)
1625{
1626 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1627 struct drm_i915_private *dev_priv = dev->dev_private;
1628 struct edp_vsc_psr psr_vsc;
1629
1630 if (intel_dp->psr_setup_done)
1631 return;
1632
1633 /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
1634 memset(&psr_vsc, 0, sizeof(psr_vsc));
1635 psr_vsc.sdp_header.HB0 = 0;
1636 psr_vsc.sdp_header.HB1 = 0x7;
1637 psr_vsc.sdp_header.HB2 = 0x2;
1638 psr_vsc.sdp_header.HB3 = 0x8;
1639 intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
1640
1641 /* Avoid continuous PSR exit by masking memup and hpd */
Ben Widawsky18b59922013-09-20 09:35:30 -07001642 I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
Rodrigo Vivi0cc4b692013-10-03 13:31:26 -03001643 EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001644
1645 intel_dp->psr_setup_done = true;
1646}
1647
1648static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
1649{
1650 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1651 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001652 uint32_t aux_clock_divider;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001653 int precharge = 0x3;
1654 int msg_size = 5; /* Header(4) + Message(1) */
1655
Damien Lespiauec5b01d2014-01-21 13:35:39 +00001656 aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
1657
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001658 /* Enable PSR in sink */
1659 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
Jani Nikula9d1a1032014-03-14 16:51:15 +02001660 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1661 DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001662 else
Jani Nikula9d1a1032014-03-14 16:51:15 +02001663 drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
1664 DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001665
1666 /* Setup AUX registers */
Ben Widawsky18b59922013-09-20 09:35:30 -07001667 I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
1668 I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
1669 I915_WRITE(EDP_PSR_AUX_CTL(dev),
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001670 DP_AUX_CH_CTL_TIME_OUT_400us |
1671 (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1672 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1673 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
1674}
1675
1676static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
1677{
1678 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 uint32_t max_sleep_time = 0x1f;
1681 uint32_t idle_frames = 1;
1682 uint32_t val = 0x0;
Ben Widawskyed8546a2013-11-04 22:45:05 -08001683 const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001684
1685 if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
1686 val |= EDP_PSR_LINK_STANDBY;
1687 val |= EDP_PSR_TP2_TP3_TIME_0us;
1688 val |= EDP_PSR_TP1_TIME_0us;
1689 val |= EDP_PSR_SKIP_AUX_EXIT;
1690 } else
1691 val |= EDP_PSR_LINK_DISABLE;
1692
Ben Widawsky18b59922013-09-20 09:35:30 -07001693 I915_WRITE(EDP_PSR_CTL(dev), val |
Ben Widawsky24bd9bf2014-03-04 22:38:10 -08001694 (IS_BROADWELL(dev) ? 0 : link_entry_time) |
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001695 max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
1696 idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
1697 EDP_PSR_ENABLE);
1698}
1699
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001700static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
1701{
1702 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1703 struct drm_device *dev = dig_port->base.base.dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705 struct drm_crtc *crtc = dig_port->base.base.crtc;
1706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Matt Roperf4510a22014-04-01 15:22:40 -07001707 struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001708 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
1709
Rodrigo Vivia031d702013-10-03 16:15:06 -03001710 dev_priv->psr.source_ok = false;
1711
Ben Widawsky18b59922013-09-20 09:35:30 -07001712 if (!HAS_PSR(dev)) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001713 DRM_DEBUG_KMS("PSR not supported on this platform\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001714 return false;
1715 }
1716
1717 if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
1718 (dig_port->port != PORT_A)) {
1719 DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001720 return false;
1721 }
1722
Jani Nikulad330a952014-01-21 11:24:25 +02001723 if (!i915.enable_psr) {
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001724 DRM_DEBUG_KMS("PSR disable by flag\n");
Rodrigo Vivi105b7c12013-07-11 18:45:02 -03001725 return false;
1726 }
1727
Chris Wilsoncd234b02013-08-02 20:39:49 +01001728 crtc = dig_port->base.base.crtc;
1729 if (crtc == NULL) {
1730 DRM_DEBUG_KMS("crtc not active for PSR\n");
Chris Wilsoncd234b02013-08-02 20:39:49 +01001731 return false;
1732 }
1733
1734 intel_crtc = to_intel_crtc(crtc);
Ville Syrjälä20ddf662013-09-04 18:25:25 +03001735 if (!intel_crtc_active(crtc)) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001736 DRM_DEBUG_KMS("crtc not active for PSR\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001737 return false;
1738 }
1739
Matt Roperf4510a22014-04-01 15:22:40 -07001740 obj = to_intel_framebuffer(crtc->primary->fb)->obj;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001741 if (obj->tiling_mode != I915_TILING_X ||
1742 obj->fence_reg == I915_FENCE_REG_NONE) {
1743 DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001744 return false;
1745 }
1746
1747 if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
1748 DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001749 return false;
1750 }
1751
1752 if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
1753 S3D_ENABLE) {
1754 DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001755 return false;
1756 }
1757
Ville Syrjäläca73b4f2013-09-04 18:25:24 +03001758 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001759 DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001760 return false;
1761 }
1762
Rodrigo Vivia031d702013-10-03 16:15:06 -03001763 dev_priv->psr.source_ok = true;
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001764 return true;
1765}
1766
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001767static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001768{
1769 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1770
Rodrigo Vivi3f51e472013-07-11 18:45:00 -03001771 if (!intel_edp_psr_match_conditions(intel_dp) ||
1772 intel_edp_is_psr_enabled(dev))
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001773 return;
1774
1775 /* Setup PSR once */
1776 intel_edp_psr_setup(intel_dp);
1777
1778 /* Enable PSR on the panel */
1779 intel_edp_psr_enable_sink(intel_dp);
1780
1781 /* Enable PSR on the host */
1782 intel_edp_psr_enable_source(intel_dp);
1783}
1784
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001785void intel_edp_psr_enable(struct intel_dp *intel_dp)
1786{
1787 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1788
1789 if (intel_edp_psr_match_conditions(intel_dp) &&
1790 !intel_edp_is_psr_enabled(dev))
1791 intel_edp_psr_do_enable(intel_dp);
1792}
1793
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001794void intel_edp_psr_disable(struct intel_dp *intel_dp)
1795{
1796 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798
1799 if (!intel_edp_is_psr_enabled(dev))
1800 return;
1801
Ben Widawsky18b59922013-09-20 09:35:30 -07001802 I915_WRITE(EDP_PSR_CTL(dev),
1803 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001804
1805 /* Wait till PSR is idle */
Ben Widawsky18b59922013-09-20 09:35:30 -07001806 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03001807 EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
1808 DRM_ERROR("Timed out waiting for PSR Idle State\n");
1809}
1810
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001811void intel_edp_psr_update(struct drm_device *dev)
1812{
1813 struct intel_encoder *encoder;
1814 struct intel_dp *intel_dp = NULL;
1815
1816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
1817 if (encoder->type == INTEL_OUTPUT_EDP) {
1818 intel_dp = enc_to_intel_dp(&encoder->base);
1819
Rodrigo Vivia031d702013-10-03 16:15:06 -03001820 if (!is_edp_psr(dev))
Rodrigo Vivi3d739d92013-07-11 18:45:01 -03001821 return;
1822
1823 if (!intel_edp_psr_match_conditions(intel_dp))
1824 intel_edp_psr_disable(intel_dp);
1825 else
1826 if (!intel_edp_is_psr_enabled(dev))
1827 intel_edp_psr_do_enable(intel_dp);
1828 }
1829}
1830
Daniel Vettere8cb4552012-07-01 13:05:48 +02001831static void intel_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001832{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001833 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001834 enum port port = dp_to_dig_port(intel_dp)->port;
1835 struct drm_device *dev = encoder->base.dev;
Daniel Vetter6cb49832012-05-20 17:14:50 +02001836
1837 /* Make sure the panel is off before trying to change the mode. But also
1838 * ensure that we have vdd while we switch off the panel. */
Jani Nikula24f3e092014-03-17 16:43:36 +02001839 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001840 intel_edp_backlight_off(intel_dp);
Jani Nikulafdbc3b12013-11-12 17:10:13 +02001841 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
Daniel Vetter4be73782014-01-17 14:39:48 +01001842 intel_edp_panel_off(intel_dp);
Daniel Vetter37398502012-09-06 22:15:44 +02001843
1844 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
Imre Deak982a3862013-05-23 19:39:40 +03001845 if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
Daniel Vetter37398502012-09-06 22:15:44 +02001846 intel_dp_link_down(intel_dp);
Jesse Barnesd240f202010-08-13 15:43:26 -07001847}
1848
Ville Syrjälä49277c32014-03-31 18:21:26 +03001849static void g4x_post_disable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001850{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001851 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deak982a3862013-05-23 19:39:40 +03001852 enum port port = dp_to_dig_port(intel_dp)->port;
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001853
Ville Syrjälä49277c32014-03-31 18:21:26 +03001854 if (port != PORT_A)
1855 return;
1856
1857 intel_dp_link_down(intel_dp);
1858 ironlake_edp_pll_off(intel_dp);
1859}
1860
1861static void vlv_post_disable_dp(struct intel_encoder *encoder)
1862{
1863 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1864
1865 intel_dp_link_down(intel_dp);
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001866}
1867
Ville Syrjälä580d3812014-04-09 13:29:00 +03001868static void chv_post_disable_dp(struct intel_encoder *encoder)
1869{
1870 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872 struct drm_device *dev = encoder->base.dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc =
1875 to_intel_crtc(encoder->base.crtc);
1876 enum dpio_channel ch = vlv_dport_to_channel(dport);
1877 enum pipe pipe = intel_crtc->pipe;
1878 u32 val;
1879
1880 intel_dp_link_down(intel_dp);
1881
1882 mutex_lock(&dev_priv->dpio_lock);
1883
1884 /* Propagate soft reset to data lane reset */
1885 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
1886 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1887 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
1888
1889 mutex_unlock(&dev_priv->dpio_lock);
1890}
1891
Daniel Vettere8cb4552012-07-01 13:05:48 +02001892static void intel_enable_dp(struct intel_encoder *encoder)
Jesse Barnesd240f202010-08-13 15:43:26 -07001893{
Daniel Vettere8cb4552012-07-01 13:05:48 +02001894 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1895 struct drm_device *dev = encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001896 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonea5b2132010-08-04 13:50:23 +01001897 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001898
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02001899 if (WARN_ON(dp_reg & DP_PORT_EN))
1900 return;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001901
Jani Nikula24f3e092014-03-17 16:43:36 +02001902 intel_edp_panel_vdd_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001903 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1904 intel_dp_start_link_train(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01001905 intel_edp_panel_on(intel_dp);
1906 edp_panel_vdd_off(intel_dp, true);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001907 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03001908 intel_dp_stop_link_train(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001909}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001910
Jani Nikulaecff4f32013-09-06 07:38:29 +03001911static void g4x_enable_dp(struct intel_encoder *encoder)
1912{
Jani Nikula828f5c62013-09-05 16:44:45 +03001913 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1914
Jani Nikulaecff4f32013-09-06 07:38:29 +03001915 intel_enable_dp(encoder);
Daniel Vetter4be73782014-01-17 14:39:48 +01001916 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001917}
Jesse Barnes89b667f2013-04-18 14:51:36 -07001918
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001919static void vlv_enable_dp(struct intel_encoder *encoder)
1920{
Jani Nikula828f5c62013-09-05 16:44:45 +03001921 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1922
Daniel Vetter4be73782014-01-17 14:39:48 +01001923 intel_edp_backlight_on(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001924}
1925
Jani Nikulaecff4f32013-09-06 07:38:29 +03001926static void g4x_pre_enable_dp(struct intel_encoder *encoder)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001927{
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02001928 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
Imre Deakbc7d38a2013-05-16 14:40:36 +03001929 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001930
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02001931 intel_dp_prepare(encoder);
1932
Daniel Vetterd41f1ef2014-04-24 23:54:53 +02001933 /* Only ilk+ has port A */
1934 if (dport->port == PORT_A) {
1935 ironlake_set_pll_cpu_edp(intel_dp);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001936 ironlake_edp_pll_on(intel_dp);
Daniel Vetterd41f1ef2014-04-24 23:54:53 +02001937 }
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001938}
1939
1940static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1941{
1942 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1943 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Jesse Barnesb2634012013-03-28 09:55:40 -07001944 struct drm_device *dev = encoder->base.dev;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001945 struct drm_i915_private *dev_priv = dev->dev_private;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001946 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001947 enum dpio_channel port = vlv_dport_to_channel(dport);
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001948 int pipe = intel_crtc->pipe;
Jani Nikulabf13e812013-09-06 07:40:05 +03001949 struct edp_power_seq power_seq;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001950 u32 val;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07001951
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001952 mutex_lock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001953
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001954 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001955 val = 0;
1956 if (pipe)
1957 val |= (1<<21);
1958 else
1959 val &= ~(1<<21);
1960 val |= 0x001000c4;
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001961 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1962 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1963 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001964
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001965 mutex_unlock(&dev_priv->dpio_lock);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001966
Imre Deak2cac6132014-01-30 16:50:42 +02001967 if (is_edp(intel_dp)) {
1968 /* init power sequencer on this pipe and port */
1969 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
1970 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
1971 &power_seq);
1972 }
Jani Nikulabf13e812013-09-06 07:40:05 +03001973
Jani Nikulaab1f90f2013-07-30 12:20:30 +03001974 intel_enable_dp(encoder);
1975
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001976 vlv_wait_port_ready(dev_priv, dport);
Jesse Barnes89b667f2013-04-18 14:51:36 -07001977}
1978
Jani Nikulaecff4f32013-09-06 07:38:29 +03001979static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
Jesse Barnes89b667f2013-04-18 14:51:36 -07001980{
1981 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1982 struct drm_device *dev = encoder->base.dev;
1983 struct drm_i915_private *dev_priv = dev->dev_private;
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001984 struct intel_crtc *intel_crtc =
1985 to_intel_crtc(encoder->base.crtc);
Chon Ming Leee4607fc2013-11-06 14:36:35 +08001986 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08001987 int pipe = intel_crtc->pipe;
Jesse Barnes89b667f2013-04-18 14:51:36 -07001988
Daniel Vetter8ac33ed2014-04-24 23:54:54 +02001989 intel_dp_prepare(encoder);
1990
Jesse Barnes89b667f2013-04-18 14:51:36 -07001991 /* Program Tx lane resets to default */
Chris Wilson0980a602013-07-26 19:57:35 +01001992 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001993 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001994 DPIO_PCS_TX_LANE2_RESET |
1995 DPIO_PCS_TX_LANE1_RESET);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08001996 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
Jesse Barnes89b667f2013-04-18 14:51:36 -07001997 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1998 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1999 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2000 DPIO_PCS_CLK_SOFT_RESET);
2001
2002 /* Fix up inter-pair skew failure */
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002003 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2004 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2005 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
Chris Wilson0980a602013-07-26 19:57:35 +01002006 mutex_unlock(&dev_priv->dpio_lock);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002007}
2008
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002009static void chv_pre_enable_dp(struct intel_encoder *encoder)
2010{
2011 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2012 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2013 struct drm_device *dev = encoder->base.dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 struct edp_power_seq power_seq;
2016 struct intel_crtc *intel_crtc =
2017 to_intel_crtc(encoder->base.crtc);
2018 enum dpio_channel ch = vlv_dport_to_channel(dport);
2019 int pipe = intel_crtc->pipe;
2020 int data, i;
Ville Syrjälä949c1d42014-04-09 13:28:58 +03002021 u32 val;
2022
2023 mutex_lock(&dev_priv->dpio_lock);
2024
2025 /* Deassert soft data lane reset*/
2026 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch));
2027 val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2028 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val);
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002029
2030 /* Program Tx lane latency optimal setting*/
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002031 for (i = 0; i < 4; i++) {
2032 /* Set the latency optimal bit */
2033 data = (i == 1) ? 0x0 : 0x6;
2034 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
2035 data << DPIO_FRC_LATENCY_SHFIT);
2036
2037 /* Set the upar bit */
2038 data = (i == 1) ? 0x0 : 0x1;
2039 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
2040 data << DPIO_UPAR_SHIFT);
2041 }
2042
2043 /* Data lane stagger programming */
2044 /* FIXME: Fix up value only after power analysis */
2045
2046 mutex_unlock(&dev_priv->dpio_lock);
2047
2048 if (is_edp(intel_dp)) {
2049 /* init power sequencer on this pipe and port */
2050 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2051 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2052 &power_seq);
2053 }
2054
2055 intel_enable_dp(encoder);
2056
2057 vlv_wait_port_ready(dev_priv, dport);
2058}
2059
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002060/*
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002061 * Native read with retry for link status and receiver capability reads for
2062 * cases where the sink may still be asleep.
Jani Nikula9d1a1032014-03-14 16:51:15 +02002063 *
2064 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
2065 * supposed to retry 3 times per the spec.
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002066 */
Jani Nikula9d1a1032014-03-14 16:51:15 +02002067static ssize_t
2068intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
2069 void *buffer, size_t size)
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002070{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002071 ssize_t ret;
2072 int i;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002073
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002074 for (i = 0; i < 3; i++) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02002075 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
2076 if (ret == size)
2077 return ret;
Jesse Barnesdf0c2372011-07-07 11:11:02 -07002078 msleep(1);
2079 }
2080
Jani Nikula9d1a1032014-03-14 16:51:15 +02002081 return ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002082}
2083
2084/*
2085 * Fetch AUX CH registers 0x202 - 0x207 which contain
2086 * link status information
2087 */
2088static bool
Keith Packard93f62da2011-11-01 19:45:03 -07002089intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002090{
Jani Nikula9d1a1032014-03-14 16:51:15 +02002091 return intel_dp_dpcd_read_wake(&intel_dp->aux,
2092 DP_LANE0_1_STATUS,
2093 link_status,
2094 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002095}
2096
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002097/*
2098 * These are source-specific values; current Intel hardware supports
2099 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
2100 */
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002101
2102static uint8_t
Keith Packard1a2eb462011-11-16 16:26:07 -08002103intel_dp_voltage_max(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002104{
Paulo Zanoni30add222012-10-26 19:05:45 -02002105 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002106 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002107
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002108 if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002109 return DP_TRAIN_VOLTAGE_SWING_1200;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002110 else if (IS_GEN7(dev) && port == PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08002111 return DP_TRAIN_VOLTAGE_SWING_800;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002112 else if (HAS_PCH_CPT(dev) && port != PORT_A)
Keith Packard1a2eb462011-11-16 16:26:07 -08002113 return DP_TRAIN_VOLTAGE_SWING_1200;
2114 else
2115 return DP_TRAIN_VOLTAGE_SWING_800;
2116}
2117
2118static uint8_t
2119intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
2120{
Paulo Zanoni30add222012-10-26 19:05:45 -02002121 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002122 enum port port = dp_to_dig_port(intel_dp)->port;
Keith Packard1a2eb462011-11-16 16:26:07 -08002123
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002124 if (IS_BROADWELL(dev)) {
2125 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2126 case DP_TRAIN_VOLTAGE_SWING_400:
2127 case DP_TRAIN_VOLTAGE_SWING_600:
2128 return DP_TRAIN_PRE_EMPHASIS_6;
2129 case DP_TRAIN_VOLTAGE_SWING_800:
2130 return DP_TRAIN_PRE_EMPHASIS_3_5;
2131 case DP_TRAIN_VOLTAGE_SWING_1200:
2132 default:
2133 return DP_TRAIN_PRE_EMPHASIS_0;
2134 }
2135 } else if (IS_HASWELL(dev)) {
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002136 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2137 case DP_TRAIN_VOLTAGE_SWING_400:
2138 return DP_TRAIN_PRE_EMPHASIS_9_5;
2139 case DP_TRAIN_VOLTAGE_SWING_600:
2140 return DP_TRAIN_PRE_EMPHASIS_6;
2141 case DP_TRAIN_VOLTAGE_SWING_800:
2142 return DP_TRAIN_PRE_EMPHASIS_3_5;
2143 case DP_TRAIN_VOLTAGE_SWING_1200:
2144 default:
2145 return DP_TRAIN_PRE_EMPHASIS_0;
2146 }
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002147 } else if (IS_VALLEYVIEW(dev)) {
2148 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2149 case DP_TRAIN_VOLTAGE_SWING_400:
2150 return DP_TRAIN_PRE_EMPHASIS_9_5;
2151 case DP_TRAIN_VOLTAGE_SWING_600:
2152 return DP_TRAIN_PRE_EMPHASIS_6;
2153 case DP_TRAIN_VOLTAGE_SWING_800:
2154 return DP_TRAIN_PRE_EMPHASIS_3_5;
2155 case DP_TRAIN_VOLTAGE_SWING_1200:
2156 default:
2157 return DP_TRAIN_PRE_EMPHASIS_0;
2158 }
Imre Deakbc7d38a2013-05-16 14:40:36 +03002159 } else if (IS_GEN7(dev) && port == PORT_A) {
Keith Packard1a2eb462011-11-16 16:26:07 -08002160 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2161 case DP_TRAIN_VOLTAGE_SWING_400:
2162 return DP_TRAIN_PRE_EMPHASIS_6;
2163 case DP_TRAIN_VOLTAGE_SWING_600:
2164 case DP_TRAIN_VOLTAGE_SWING_800:
2165 return DP_TRAIN_PRE_EMPHASIS_3_5;
2166 default:
2167 return DP_TRAIN_PRE_EMPHASIS_0;
2168 }
2169 } else {
2170 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
2171 case DP_TRAIN_VOLTAGE_SWING_400:
2172 return DP_TRAIN_PRE_EMPHASIS_6;
2173 case DP_TRAIN_VOLTAGE_SWING_600:
2174 return DP_TRAIN_PRE_EMPHASIS_6;
2175 case DP_TRAIN_VOLTAGE_SWING_800:
2176 return DP_TRAIN_PRE_EMPHASIS_3_5;
2177 case DP_TRAIN_VOLTAGE_SWING_1200:
2178 default:
2179 return DP_TRAIN_PRE_EMPHASIS_0;
2180 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002181 }
2182}
2183
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002184static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2185{
2186 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2187 struct drm_i915_private *dev_priv = dev->dev_private;
2188 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002189 struct intel_crtc *intel_crtc =
2190 to_intel_crtc(dport->base.base.crtc);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002191 unsigned long demph_reg_value, preemph_reg_value,
2192 uniqtranscale_reg_value;
2193 uint8_t train_set = intel_dp->train_set[0];
Chon Ming Leee4607fc2013-11-06 14:36:35 +08002194 enum dpio_channel port = vlv_dport_to_channel(dport);
Chon Ming Lee5e69f972013-09-05 20:41:49 +08002195 int pipe = intel_crtc->pipe;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002196
2197 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2198 case DP_TRAIN_PRE_EMPHASIS_0:
2199 preemph_reg_value = 0x0004000;
2200 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2201 case DP_TRAIN_VOLTAGE_SWING_400:
2202 demph_reg_value = 0x2B405555;
2203 uniqtranscale_reg_value = 0x552AB83A;
2204 break;
2205 case DP_TRAIN_VOLTAGE_SWING_600:
2206 demph_reg_value = 0x2B404040;
2207 uniqtranscale_reg_value = 0x5548B83A;
2208 break;
2209 case DP_TRAIN_VOLTAGE_SWING_800:
2210 demph_reg_value = 0x2B245555;
2211 uniqtranscale_reg_value = 0x5560B83A;
2212 break;
2213 case DP_TRAIN_VOLTAGE_SWING_1200:
2214 demph_reg_value = 0x2B405555;
2215 uniqtranscale_reg_value = 0x5598DA3A;
2216 break;
2217 default:
2218 return 0;
2219 }
2220 break;
2221 case DP_TRAIN_PRE_EMPHASIS_3_5:
2222 preemph_reg_value = 0x0002000;
2223 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2224 case DP_TRAIN_VOLTAGE_SWING_400:
2225 demph_reg_value = 0x2B404040;
2226 uniqtranscale_reg_value = 0x5552B83A;
2227 break;
2228 case DP_TRAIN_VOLTAGE_SWING_600:
2229 demph_reg_value = 0x2B404848;
2230 uniqtranscale_reg_value = 0x5580B83A;
2231 break;
2232 case DP_TRAIN_VOLTAGE_SWING_800:
2233 demph_reg_value = 0x2B404040;
2234 uniqtranscale_reg_value = 0x55ADDA3A;
2235 break;
2236 default:
2237 return 0;
2238 }
2239 break;
2240 case DP_TRAIN_PRE_EMPHASIS_6:
2241 preemph_reg_value = 0x0000000;
2242 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2243 case DP_TRAIN_VOLTAGE_SWING_400:
2244 demph_reg_value = 0x2B305555;
2245 uniqtranscale_reg_value = 0x5570B83A;
2246 break;
2247 case DP_TRAIN_VOLTAGE_SWING_600:
2248 demph_reg_value = 0x2B2B4040;
2249 uniqtranscale_reg_value = 0x55ADDA3A;
2250 break;
2251 default:
2252 return 0;
2253 }
2254 break;
2255 case DP_TRAIN_PRE_EMPHASIS_9_5:
2256 preemph_reg_value = 0x0006000;
2257 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2258 case DP_TRAIN_VOLTAGE_SWING_400:
2259 demph_reg_value = 0x1B405555;
2260 uniqtranscale_reg_value = 0x55ADDA3A;
2261 break;
2262 default:
2263 return 0;
2264 }
2265 break;
2266 default:
2267 return 0;
2268 }
2269
Chris Wilson0980a602013-07-26 19:57:35 +01002270 mutex_lock(&dev_priv->dpio_lock);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002271 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2272 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2273 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002274 uniqtranscale_reg_value);
Chon Ming Leeab3c7592013-11-07 10:43:30 +08002275 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2276 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2277 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2278 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
Chris Wilson0980a602013-07-26 19:57:35 +01002279 mutex_unlock(&dev_priv->dpio_lock);
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002280
2281 return 0;
2282}
2283
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002284static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
2285{
2286 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2287 struct drm_i915_private *dev_priv = dev->dev_private;
2288 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2289 struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2290 u32 deemph_reg_value, margin_reg_value, val, tx_dw2;
2291 uint8_t train_set = intel_dp->train_set[0];
2292 enum dpio_channel ch = vlv_dport_to_channel(dport);
2293 int pipe = intel_crtc->pipe;
2294
2295 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2296 case DP_TRAIN_PRE_EMPHASIS_0:
2297 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2298 case DP_TRAIN_VOLTAGE_SWING_400:
2299 deemph_reg_value = 128;
2300 margin_reg_value = 52;
2301 break;
2302 case DP_TRAIN_VOLTAGE_SWING_600:
2303 deemph_reg_value = 128;
2304 margin_reg_value = 77;
2305 break;
2306 case DP_TRAIN_VOLTAGE_SWING_800:
2307 deemph_reg_value = 128;
2308 margin_reg_value = 102;
2309 break;
2310 case DP_TRAIN_VOLTAGE_SWING_1200:
2311 deemph_reg_value = 128;
2312 margin_reg_value = 154;
2313 /* FIXME extra to set for 1200 */
2314 break;
2315 default:
2316 return 0;
2317 }
2318 break;
2319 case DP_TRAIN_PRE_EMPHASIS_3_5:
2320 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2321 case DP_TRAIN_VOLTAGE_SWING_400:
2322 deemph_reg_value = 85;
2323 margin_reg_value = 78;
2324 break;
2325 case DP_TRAIN_VOLTAGE_SWING_600:
2326 deemph_reg_value = 85;
2327 margin_reg_value = 116;
2328 break;
2329 case DP_TRAIN_VOLTAGE_SWING_800:
2330 deemph_reg_value = 85;
2331 margin_reg_value = 154;
2332 break;
2333 default:
2334 return 0;
2335 }
2336 break;
2337 case DP_TRAIN_PRE_EMPHASIS_6:
2338 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2339 case DP_TRAIN_VOLTAGE_SWING_400:
2340 deemph_reg_value = 64;
2341 margin_reg_value = 104;
2342 break;
2343 case DP_TRAIN_VOLTAGE_SWING_600:
2344 deemph_reg_value = 64;
2345 margin_reg_value = 154;
2346 break;
2347 default:
2348 return 0;
2349 }
2350 break;
2351 case DP_TRAIN_PRE_EMPHASIS_9_5:
2352 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2353 case DP_TRAIN_VOLTAGE_SWING_400:
2354 deemph_reg_value = 43;
2355 margin_reg_value = 154;
2356 break;
2357 default:
2358 return 0;
2359 }
2360 break;
2361 default:
2362 return 0;
2363 }
2364
2365 mutex_lock(&dev_priv->dpio_lock);
2366
2367 /* Clear calc init */
2368 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0);
2369
2370 /* Program swing deemph */
2371 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch));
2372 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
2373 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
2374 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val);
2375
2376 /* Program swing margin */
2377 tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch));
2378 tx_dw2 &= ~DPIO_SWING_MARGIN_MASK;
2379 tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
2380 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2381
2382 /* Disable unique transition scale */
2383 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2384 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
2385 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2386
2387 if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
2388 == DP_TRAIN_PRE_EMPHASIS_0) &&
2389 ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
2390 == DP_TRAIN_VOLTAGE_SWING_1200)) {
2391
2392 /*
2393 * The document said it needs to set bit 27 for ch0 and bit 26
2394 * for ch1. Might be a typo in the doc.
2395 * For now, for this unique transition scale selection, set bit
2396 * 27 for ch0 and ch1.
2397 */
2398 val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
2399 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
2400 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);
2401
2402 tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
2403 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2);
2404 }
2405
2406 /* Start swing calculation */
2407 vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch),
2408 (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3));
2409
2410 /* LRC Bypass */
2411 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
2412 val |= DPIO_LRC_BYPASS;
2413 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);
2414
2415 mutex_unlock(&dev_priv->dpio_lock);
2416
2417 return 0;
2418}
2419
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002420static void
Jani Nikula0301b3a2013-10-15 09:36:08 +03002421intel_get_adjust_train(struct intel_dp *intel_dp,
2422 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002423{
2424 uint8_t v = 0;
2425 uint8_t p = 0;
2426 int lane;
Keith Packard1a2eb462011-11-16 16:26:07 -08002427 uint8_t voltage_max;
2428 uint8_t preemph_max;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002429
Jesse Barnes33a34e42010-09-08 12:42:02 -07002430 for (lane = 0; lane < intel_dp->lane_count; lane++) {
Daniel Vetter0f037bd2012-10-18 10:15:27 +02002431 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
2432 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002433
2434 if (this_v > v)
2435 v = this_v;
2436 if (this_p > p)
2437 p = this_p;
2438 }
2439
Keith Packard1a2eb462011-11-16 16:26:07 -08002440 voltage_max = intel_dp_voltage_max(intel_dp);
Keith Packard417e8222011-11-01 19:54:11 -07002441 if (v >= voltage_max)
2442 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002443
Keith Packard1a2eb462011-11-16 16:26:07 -08002444 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
2445 if (p >= preemph_max)
2446 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002447
2448 for (lane = 0; lane < 4; lane++)
Jesse Barnes33a34e42010-09-08 12:42:02 -07002449 intel_dp->train_set[lane] = v | p;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002450}
2451
2452static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002453intel_gen4_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002454{
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002455 uint32_t signal_levels = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002456
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002457 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002458 case DP_TRAIN_VOLTAGE_SWING_400:
2459 default:
2460 signal_levels |= DP_VOLTAGE_0_4;
2461 break;
2462 case DP_TRAIN_VOLTAGE_SWING_600:
2463 signal_levels |= DP_VOLTAGE_0_6;
2464 break;
2465 case DP_TRAIN_VOLTAGE_SWING_800:
2466 signal_levels |= DP_VOLTAGE_0_8;
2467 break;
2468 case DP_TRAIN_VOLTAGE_SWING_1200:
2469 signal_levels |= DP_VOLTAGE_1_2;
2470 break;
2471 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002472 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002473 case DP_TRAIN_PRE_EMPHASIS_0:
2474 default:
2475 signal_levels |= DP_PRE_EMPHASIS_0;
2476 break;
2477 case DP_TRAIN_PRE_EMPHASIS_3_5:
2478 signal_levels |= DP_PRE_EMPHASIS_3_5;
2479 break;
2480 case DP_TRAIN_PRE_EMPHASIS_6:
2481 signal_levels |= DP_PRE_EMPHASIS_6;
2482 break;
2483 case DP_TRAIN_PRE_EMPHASIS_9_5:
2484 signal_levels |= DP_PRE_EMPHASIS_9_5;
2485 break;
2486 }
2487 return signal_levels;
2488}
2489
Zhenyu Wange3421a12010-04-08 09:43:27 +08002490/* Gen6's DP voltage swing and pre-emphasis control */
2491static uint32_t
2492intel_gen6_edp_signal_levels(uint8_t train_set)
2493{
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002494 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2495 DP_TRAIN_PRE_EMPHASIS_MASK);
2496 switch (signal_levels) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08002497 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002498 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2499 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2500 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2501 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002502 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002503 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2504 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002505 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002506 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2507 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002508 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002509 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2510 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002511 default:
Yuanhan Liu3c5a62b2011-01-06 18:26:08 +08002512 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2513 "0x%x\n", signal_levels);
2514 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
Zhenyu Wange3421a12010-04-08 09:43:27 +08002515 }
2516}
2517
Keith Packard1a2eb462011-11-16 16:26:07 -08002518/* Gen7's DP voltage swing and pre-emphasis control */
2519static uint32_t
2520intel_gen7_edp_signal_levels(uint8_t train_set)
2521{
2522 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2523 DP_TRAIN_PRE_EMPHASIS_MASK);
2524 switch (signal_levels) {
2525 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2526 return EDP_LINK_TRAIN_400MV_0DB_IVB;
2527 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2528 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
2529 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2530 return EDP_LINK_TRAIN_400MV_6DB_IVB;
2531
2532 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2533 return EDP_LINK_TRAIN_600MV_0DB_IVB;
2534 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2535 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
2536
2537 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2538 return EDP_LINK_TRAIN_800MV_0DB_IVB;
2539 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2540 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
2541
2542 default:
2543 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2544 "0x%x\n", signal_levels);
2545 return EDP_LINK_TRAIN_500MV_0DB_IVB;
2546 }
2547}
2548
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002549/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
2550static uint32_t
Paulo Zanonif0a34242012-12-06 16:51:50 -02002551intel_hsw_signal_levels(uint8_t train_set)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002552{
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002553 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2554 DP_TRAIN_PRE_EMPHASIS_MASK);
2555 switch (signal_levels) {
2556 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2557 return DDI_BUF_EMP_400MV_0DB_HSW;
2558 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2559 return DDI_BUF_EMP_400MV_3_5DB_HSW;
2560 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2561 return DDI_BUF_EMP_400MV_6DB_HSW;
2562 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
2563 return DDI_BUF_EMP_400MV_9_5DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002564
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002565 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2566 return DDI_BUF_EMP_600MV_0DB_HSW;
2567 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2568 return DDI_BUF_EMP_600MV_3_5DB_HSW;
2569 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2570 return DDI_BUF_EMP_600MV_6DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002571
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002572 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2573 return DDI_BUF_EMP_800MV_0DB_HSW;
2574 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2575 return DDI_BUF_EMP_800MV_3_5DB_HSW;
2576 default:
2577 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2578 "0x%x\n", signal_levels);
2579 return DDI_BUF_EMP_400MV_0DB_HSW;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002580 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002581}
2582
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002583static uint32_t
2584intel_bdw_signal_levels(uint8_t train_set)
2585{
2586 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2587 DP_TRAIN_PRE_EMPHASIS_MASK);
2588 switch (signal_levels) {
2589 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2590 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2591 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
2592 return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */
2593 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2594 return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */
2595
2596 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
2597 return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */
2598 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2599 return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */
2600 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
2601 return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */
2602
2603 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2604 return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */
2605 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
2606 return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */
2607
2608 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
2609 return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */
2610
2611 default:
2612 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
2613 "0x%x\n", signal_levels);
2614 return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */
2615 }
2616}
2617
Paulo Zanonif0a34242012-12-06 16:51:50 -02002618/* Properly updates "DP" with the correct signal levels. */
2619static void
2620intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
2621{
2622 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002623 enum port port = intel_dig_port->port;
Paulo Zanonif0a34242012-12-06 16:51:50 -02002624 struct drm_device *dev = intel_dig_port->base.base.dev;
2625 uint32_t signal_levels, mask;
2626 uint8_t train_set = intel_dp->train_set[0];
2627
Paulo Zanoni8f93f4f2013-11-02 21:07:43 -07002628 if (IS_BROADWELL(dev)) {
2629 signal_levels = intel_bdw_signal_levels(train_set);
2630 mask = DDI_BUF_EMP_MASK;
2631 } else if (IS_HASWELL(dev)) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002632 signal_levels = intel_hsw_signal_levels(train_set);
2633 mask = DDI_BUF_EMP_MASK;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03002634 } else if (IS_CHERRYVIEW(dev)) {
2635 signal_levels = intel_chv_signal_levels(intel_dp);
2636 mask = 0;
Pallavi Ge2fa6fb2013-04-18 14:44:28 -07002637 } else if (IS_VALLEYVIEW(dev)) {
2638 signal_levels = intel_vlv_signal_levels(intel_dp);
2639 mask = 0;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002640 } else if (IS_GEN7(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002641 signal_levels = intel_gen7_edp_signal_levels(train_set);
2642 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
Imre Deakbc7d38a2013-05-16 14:40:36 +03002643 } else if (IS_GEN6(dev) && port == PORT_A) {
Paulo Zanonif0a34242012-12-06 16:51:50 -02002644 signal_levels = intel_gen6_edp_signal_levels(train_set);
2645 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
2646 } else {
2647 signal_levels = intel_gen4_signal_levels(train_set);
2648 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
2649 }
2650
2651 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
2652
2653 *DP = (*DP & ~mask) | signal_levels;
2654}
2655
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002656static bool
Chris Wilsonea5b2132010-08-04 13:50:23 +01002657intel_dp_set_link_train(struct intel_dp *intel_dp,
Jani Nikula70aff662013-09-27 15:10:44 +03002658 uint32_t *DP,
Chris Wilson58e10eb2010-10-03 10:56:11 +01002659 uint8_t dp_train_pat)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002660{
Paulo Zanoni174edf12012-10-26 19:05:50 -02002661 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2662 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002663 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02002664 enum port port = intel_dig_port->port;
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002665 uint8_t buf[sizeof(intel_dp->train_set) + 1];
2666 int ret, len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002667
Paulo Zanoni22b8bf12013-02-18 19:00:23 -03002668 if (HAS_DDI(dev)) {
Imre Deak3ab9c632013-05-03 12:57:41 +03002669 uint32_t temp = I915_READ(DP_TP_CTL(port));
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002670
2671 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2672 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2673 else
2674 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2675
2676 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2677 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2678 case DP_TRAINING_PATTERN_DISABLE:
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002679 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2680
2681 break;
2682 case DP_TRAINING_PATTERN_1:
2683 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2684 break;
2685 case DP_TRAINING_PATTERN_2:
2686 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2687 break;
2688 case DP_TRAINING_PATTERN_3:
2689 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2690 break;
2691 }
Paulo Zanoni174edf12012-10-26 19:05:50 -02002692 I915_WRITE(DP_TP_CTL(port), temp);
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002693
Imre Deakbc7d38a2013-05-16 14:40:36 +03002694 } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Jani Nikula70aff662013-09-27 15:10:44 +03002695 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002696
2697 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2698 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03002699 *DP |= DP_LINK_TRAIN_OFF_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002700 break;
2701 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03002702 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002703 break;
2704 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03002705 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002706 break;
2707 case DP_TRAINING_PATTERN_3:
2708 DRM_ERROR("DP training pattern 3 not supported\n");
Jani Nikula70aff662013-09-27 15:10:44 +03002709 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002710 break;
2711 }
2712
2713 } else {
Jani Nikula70aff662013-09-27 15:10:44 +03002714 *DP &= ~DP_LINK_TRAIN_MASK;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002715
2716 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2717 case DP_TRAINING_PATTERN_DISABLE:
Jani Nikula70aff662013-09-27 15:10:44 +03002718 *DP |= DP_LINK_TRAIN_OFF;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002719 break;
2720 case DP_TRAINING_PATTERN_1:
Jani Nikula70aff662013-09-27 15:10:44 +03002721 *DP |= DP_LINK_TRAIN_PAT_1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002722 break;
2723 case DP_TRAINING_PATTERN_2:
Jani Nikula70aff662013-09-27 15:10:44 +03002724 *DP |= DP_LINK_TRAIN_PAT_2;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002725 break;
2726 case DP_TRAINING_PATTERN_3:
2727 DRM_ERROR("DP training pattern 3 not supported\n");
Jani Nikula70aff662013-09-27 15:10:44 +03002728 *DP |= DP_LINK_TRAIN_PAT_2;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002729 break;
2730 }
2731 }
2732
Jani Nikula70aff662013-09-27 15:10:44 +03002733 I915_WRITE(intel_dp->output_reg, *DP);
Chris Wilsonea5b2132010-08-04 13:50:23 +01002734 POSTING_READ(intel_dp->output_reg);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002735
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002736 buf[0] = dp_train_pat;
2737 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002738 DP_TRAINING_PATTERN_DISABLE) {
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002739 /* don't write DP_TRAINING_LANEx_SET on disable */
2740 len = 1;
2741 } else {
2742 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
2743 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
2744 len = intel_dp->lane_count + 1;
Paulo Zanoni47ea7542012-07-17 16:55:16 -03002745 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002746
Jani Nikula9d1a1032014-03-14 16:51:15 +02002747 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
2748 buf, len);
Jani Nikula2cdfe6c2013-10-04 15:08:48 +03002749
2750 return ret == len;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002751}
2752
Jani Nikula70aff662013-09-27 15:10:44 +03002753static bool
2754intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
2755 uint8_t dp_train_pat)
2756{
Jani Nikula953d22e2013-10-04 15:08:47 +03002757 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
Jani Nikula70aff662013-09-27 15:10:44 +03002758 intel_dp_set_signal_levels(intel_dp, DP);
2759 return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
2760}
2761
2762static bool
2763intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
Jani Nikula0301b3a2013-10-15 09:36:08 +03002764 const uint8_t link_status[DP_LINK_STATUS_SIZE])
Jani Nikula70aff662013-09-27 15:10:44 +03002765{
2766 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2767 struct drm_device *dev = intel_dig_port->base.base.dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 int ret;
2770
2771 intel_get_adjust_train(intel_dp, link_status);
2772 intel_dp_set_signal_levels(intel_dp, DP);
2773
2774 I915_WRITE(intel_dp->output_reg, *DP);
2775 POSTING_READ(intel_dp->output_reg);
2776
Jani Nikula9d1a1032014-03-14 16:51:15 +02002777 ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
2778 intel_dp->train_set, intel_dp->lane_count);
Jani Nikula70aff662013-09-27 15:10:44 +03002779
2780 return ret == intel_dp->lane_count;
2781}
2782
Imre Deak3ab9c632013-05-03 12:57:41 +03002783static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
2784{
2785 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2786 struct drm_device *dev = intel_dig_port->base.base.dev;
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 enum port port = intel_dig_port->port;
2789 uint32_t val;
2790
2791 if (!HAS_DDI(dev))
2792 return;
2793
2794 val = I915_READ(DP_TP_CTL(port));
2795 val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2796 val |= DP_TP_CTL_LINK_TRAIN_IDLE;
2797 I915_WRITE(DP_TP_CTL(port), val);
2798
2799 /*
2800 * On PORT_A we can have only eDP in SST mode. There the only reason
2801 * we need to set idle transmission mode is to work around a HW issue
2802 * where we enable the pipe while not in idle link-training mode.
2803 * In this case there is requirement to wait for a minimum number of
2804 * idle patterns to be sent.
2805 */
2806 if (port == PORT_A)
2807 return;
2808
2809 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
2810 1))
2811 DRM_ERROR("Timed out waiting for DP idle patterns\n");
2812}
2813
Jesse Barnes33a34e42010-09-08 12:42:02 -07002814/* Enable corresponding port and start training pattern 1 */
Paulo Zanonic19b0662012-10-15 15:51:41 -03002815void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002816intel_dp_start_link_train(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002817{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002818 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
Paulo Zanonic19b0662012-10-15 15:51:41 -03002819 struct drm_device *dev = encoder->dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002820 int i;
2821 uint8_t voltage;
Keith Packardcdb0e952011-11-01 20:00:06 -07002822 int voltage_tries, loop_tries;
Chris Wilsonea5b2132010-08-04 13:50:23 +01002823 uint32_t DP = intel_dp->DP;
Jani Nikula6aba5b62013-10-04 15:08:10 +03002824 uint8_t link_config[2];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002825
Paulo Zanoniaffa9352012-11-23 15:30:39 -02002826 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03002827 intel_ddi_prepare_link_retrain(encoder);
2828
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002829 /* Write the link configuration data */
Jani Nikula6aba5b62013-10-04 15:08:10 +03002830 link_config[0] = intel_dp->link_bw;
2831 link_config[1] = intel_dp->lane_count;
2832 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2833 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
Jani Nikula9d1a1032014-03-14 16:51:15 +02002834 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
Jani Nikula6aba5b62013-10-04 15:08:10 +03002835
2836 link_config[0] = 0;
2837 link_config[1] = DP_SET_ANSI_8B10B;
Jani Nikula9d1a1032014-03-14 16:51:15 +02002838 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002839
2840 DP |= DP_PORT_EN;
Keith Packard1a2eb462011-11-16 16:26:07 -08002841
Jani Nikula70aff662013-09-27 15:10:44 +03002842 /* clock recovery */
2843 if (!intel_dp_reset_link_train(intel_dp, &DP,
2844 DP_TRAINING_PATTERN_1 |
2845 DP_LINK_SCRAMBLING_DISABLE)) {
2846 DRM_ERROR("failed to enable link training\n");
2847 return;
2848 }
2849
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002850 voltage = 0xff;
Keith Packardcdb0e952011-11-01 20:00:06 -07002851 voltage_tries = 0;
2852 loop_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002853 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03002854 uint8_t link_status[DP_LINK_STATUS_SIZE];
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002855
Daniel Vettera7c96552012-10-18 10:15:30 +02002856 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
Keith Packard93f62da2011-11-01 19:45:03 -07002857 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2858 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002859 break;
Keith Packard93f62da2011-11-01 19:45:03 -07002860 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002861
Daniel Vetter01916272012-10-18 10:15:25 +02002862 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Keith Packard93f62da2011-11-01 19:45:03 -07002863 DRM_DEBUG_KMS("clock recovery OK\n");
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002864 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002865 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002866
2867 /* Check to see if we've tried the max voltage */
2868 for (i = 0; i < intel_dp->lane_count; i++)
2869 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2870 break;
Takashi Iwai3b4f8192013-03-11 18:40:16 +01002871 if (i == intel_dp->lane_count) {
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002872 ++loop_tries;
2873 if (loop_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03002874 DRM_ERROR("too many full retries, give up\n");
Keith Packardcdb0e952011-11-01 20:00:06 -07002875 break;
2876 }
Jani Nikula70aff662013-09-27 15:10:44 +03002877 intel_dp_reset_link_train(intel_dp, &DP,
2878 DP_TRAINING_PATTERN_1 |
2879 DP_LINK_SCRAMBLING_DISABLE);
Keith Packardcdb0e952011-11-01 20:00:06 -07002880 voltage_tries = 0;
2881 continue;
2882 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002883
2884 /* Check to see if we've tried the same voltage 5 times */
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002885 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
Chris Wilson24773672012-09-26 16:48:30 +01002886 ++voltage_tries;
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002887 if (voltage_tries == 5) {
Jani Nikula3def84b2013-10-05 16:13:56 +03002888 DRM_ERROR("too many voltage retries, give up\n");
Daniel Vetterb06fbda2012-10-16 09:50:25 +02002889 break;
2890 }
2891 } else
2892 voltage_tries = 0;
2893 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002894
Jani Nikula70aff662013-09-27 15:10:44 +03002895 /* Update training set as requested by target */
2896 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2897 DRM_ERROR("failed to update link training\n");
2898 break;
2899 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002900 }
2901
Jesse Barnes33a34e42010-09-08 12:42:02 -07002902 intel_dp->DP = DP;
2903}
2904
Paulo Zanonic19b0662012-10-15 15:51:41 -03002905void
Jesse Barnes33a34e42010-09-08 12:42:02 -07002906intel_dp_complete_link_train(struct intel_dp *intel_dp)
2907{
Jesse Barnes33a34e42010-09-08 12:42:02 -07002908 bool channel_eq = false;
Jesse Barnes37f80972011-01-05 14:45:24 -08002909 int tries, cr_tries;
Jesse Barnes33a34e42010-09-08 12:42:02 -07002910 uint32_t DP = intel_dp->DP;
Todd Previte06ea66b2014-01-20 10:19:39 -07002911 uint32_t training_pattern = DP_TRAINING_PATTERN_2;
2912
2913 /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
2914 if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
2915 training_pattern = DP_TRAINING_PATTERN_3;
Jesse Barnes33a34e42010-09-08 12:42:02 -07002916
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002917 /* channel equalization */
Jani Nikula70aff662013-09-27 15:10:44 +03002918 if (!intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002919 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002920 DP_LINK_SCRAMBLING_DISABLE)) {
2921 DRM_ERROR("failed to start channel equalization\n");
2922 return;
2923 }
2924
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002925 tries = 0;
Jesse Barnes37f80972011-01-05 14:45:24 -08002926 cr_tries = 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002927 channel_eq = false;
2928 for (;;) {
Jani Nikula70aff662013-09-27 15:10:44 +03002929 uint8_t link_status[DP_LINK_STATUS_SIZE];
Zhenyu Wange3421a12010-04-08 09:43:27 +08002930
Jesse Barnes37f80972011-01-05 14:45:24 -08002931 if (cr_tries > 5) {
2932 DRM_ERROR("failed to train DP, aborting\n");
Jesse Barnes37f80972011-01-05 14:45:24 -08002933 break;
2934 }
2935
Daniel Vettera7c96552012-10-18 10:15:30 +02002936 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
Jani Nikula70aff662013-09-27 15:10:44 +03002937 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2938 DRM_ERROR("failed to get link status\n");
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002939 break;
Jani Nikula70aff662013-09-27 15:10:44 +03002940 }
Jesse Barnes869184a2010-10-07 16:01:22 -07002941
Jesse Barnes37f80972011-01-05 14:45:24 -08002942 /* Make sure clock is still ok */
Daniel Vetter01916272012-10-18 10:15:25 +02002943 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
Jesse Barnes37f80972011-01-05 14:45:24 -08002944 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03002945 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002946 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002947 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08002948 cr_tries++;
2949 continue;
2950 }
2951
Daniel Vetter1ffdff12012-10-18 10:15:24 +02002952 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002953 channel_eq = true;
2954 break;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002955 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002956
Jesse Barnes37f80972011-01-05 14:45:24 -08002957 /* Try 5 times, then try clock recovery if that fails */
2958 if (tries > 5) {
2959 intel_dp_link_down(intel_dp);
2960 intel_dp_start_link_train(intel_dp);
Jani Nikula70aff662013-09-27 15:10:44 +03002961 intel_dp_set_link_train(intel_dp, &DP,
Todd Previte06ea66b2014-01-20 10:19:39 -07002962 training_pattern |
Jani Nikula70aff662013-09-27 15:10:44 +03002963 DP_LINK_SCRAMBLING_DISABLE);
Jesse Barnes37f80972011-01-05 14:45:24 -08002964 tries = 0;
2965 cr_tries++;
2966 continue;
2967 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002968
Jani Nikula70aff662013-09-27 15:10:44 +03002969 /* Update training set as requested by target */
2970 if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
2971 DRM_ERROR("failed to update link training\n");
2972 break;
2973 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002974 ++tries;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002975 }
Chris Wilson3cf2efb2010-11-29 10:09:55 +00002976
Imre Deak3ab9c632013-05-03 12:57:41 +03002977 intel_dp_set_idle_link_train(intel_dp);
2978
2979 intel_dp->DP = DP;
2980
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002981 if (channel_eq)
Masanari Iida07f42252013-03-20 11:00:34 +09002982 DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
Paulo Zanonid6c0d722012-10-15 15:51:34 -03002983
Imre Deak3ab9c632013-05-03 12:57:41 +03002984}
2985
2986void intel_dp_stop_link_train(struct intel_dp *intel_dp)
2987{
Jani Nikula70aff662013-09-27 15:10:44 +03002988 intel_dp_set_link_train(intel_dp, &intel_dp->DP,
Imre Deak3ab9c632013-05-03 12:57:41 +03002989 DP_TRAINING_PATTERN_DISABLE);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002990}
2991
2992static void
Chris Wilsonea5b2132010-08-04 13:50:23 +01002993intel_dp_link_down(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002994{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002995 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Imre Deakbc7d38a2013-05-16 14:40:36 +03002996 enum port port = intel_dig_port->port;
Paulo Zanonida63a9f2012-10-26 19:05:46 -02002997 struct drm_device *dev = intel_dig_port->base.base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07002998 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetterab527ef2012-11-29 15:59:33 +01002999 struct intel_crtc *intel_crtc =
3000 to_intel_crtc(intel_dig_port->base.base.crtc);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003001 uint32_t DP = intel_dp->DP;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003002
Paulo Zanonic19b0662012-10-15 15:51:41 -03003003 /*
3004 * DDI code has a strict mode set sequence and we should try to respect
3005 * it, otherwise we might hang the machine in many different ways. So we
3006 * really should be disabling the port only on a complete crtc_disable
3007 * sequence. This function is just called under two conditions on DDI
3008 * code:
3009 * - Link train failed while doing crtc_enable, and on this case we
3010 * really should respect the mode set sequence and wait for a
3011 * crtc_disable.
3012 * - Someone turned the monitor off and intel_dp_check_link_status
3013 * called us. We don't need to disable the whole port on this case, so
3014 * when someone turns the monitor on again,
3015 * intel_ddi_prepare_link_retrain will take care of redoing the link
3016 * train.
3017 */
Paulo Zanoniaffa9352012-11-23 15:30:39 -02003018 if (HAS_DDI(dev))
Paulo Zanonic19b0662012-10-15 15:51:41 -03003019 return;
3020
Daniel Vetter0c33d8d2012-09-06 22:15:43 +02003021 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
Chris Wilson1b39d6f2010-12-06 11:20:45 +00003022 return;
3023
Zhao Yakui28c97732009-10-09 11:39:41 +08003024 DRM_DEBUG_KMS("\n");
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003025
Imre Deakbc7d38a2013-05-16 14:40:36 +03003026 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
Zhenyu Wange3421a12010-04-08 09:43:27 +08003027 DP &= ~DP_LINK_TRAIN_MASK_CPT;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003028 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
Zhenyu Wange3421a12010-04-08 09:43:27 +08003029 } else {
3030 DP &= ~DP_LINK_TRAIN_MASK;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003031 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
Zhenyu Wange3421a12010-04-08 09:43:27 +08003032 }
Chris Wilsonfe255d02010-09-11 21:37:48 +01003033 POSTING_READ(intel_dp->output_reg);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003034
Daniel Vetter493a7082012-05-30 12:31:56 +02003035 if (HAS_PCH_IBX(dev) &&
Chris Wilson1b39d6f2010-12-06 11:20:45 +00003036 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003037 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
Chris Wilson31acbcc2011-04-17 06:38:35 +01003038
Eric Anholt5bddd172010-11-18 09:32:59 +08003039 /* Hardware workaround: leaving our transcoder select
3040 * set to transcoder B while it's off will prevent the
3041 * corresponding HDMI output on transcoder A.
3042 *
3043 * Combine this with another hardware workaround:
3044 * transcoder select bit can only be cleared while the
3045 * port is enabled.
3046 */
3047 DP &= ~DP_PIPEB_SELECT;
3048 I915_WRITE(intel_dp->output_reg, DP);
3049
3050 /* Changes to enable or select take place the vblank
3051 * after being written.
3052 */
Daniel Vetterff50afe2012-11-29 15:59:34 +01003053 if (WARN_ON(crtc == NULL)) {
3054 /* We should never try to disable a port without a crtc
3055 * attached. For paranoia keep the code around for a
3056 * bit. */
Chris Wilson31acbcc2011-04-17 06:38:35 +01003057 POSTING_READ(intel_dp->output_reg);
3058 msleep(50);
3059 } else
Daniel Vetterab527ef2012-11-29 15:59:33 +01003060 intel_wait_for_vblank(dev, intel_crtc->pipe);
Eric Anholt5bddd172010-11-18 09:32:59 +08003061 }
3062
Wu Fengguang832afda2011-12-09 20:42:21 +08003063 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
Chris Wilsonea5b2132010-08-04 13:50:23 +01003064 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
3065 POSTING_READ(intel_dp->output_reg);
Keith Packardf01eca22011-09-28 16:48:10 -07003066 msleep(intel_dp->panel_power_down_delay);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003067}
3068
Keith Packard26d61aa2011-07-25 20:01:09 -07003069static bool
3070intel_dp_get_dpcd(struct intel_dp *intel_dp)
Keith Packard92fd8fd2011-07-25 19:50:10 -07003071{
Rodrigo Vivia031d702013-10-03 16:15:06 -03003072 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3073 struct drm_device *dev = dig_port->base.base.dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075
Damien Lespiau577c7a52012-12-13 16:09:02 +00003076 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
3077
Jani Nikula9d1a1032014-03-14 16:51:15 +02003078 if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3079 sizeof(intel_dp->dpcd)) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003080 return false; /* aux transfer failed */
Keith Packard92fd8fd2011-07-25 19:50:10 -07003081
Damien Lespiau577c7a52012-12-13 16:09:02 +00003082 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
3083 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
3084 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
3085
Adam Jacksonedb39242012-09-18 10:58:49 -04003086 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3087 return false; /* DPCD not present */
3088
Shobhit Kumar2293bb52013-07-11 18:44:56 -03003089 /* Check if the panel supports PSR */
3090 memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
Jani Nikula50003932013-09-20 16:42:17 +03003091 if (is_edp(intel_dp)) {
Jani Nikula9d1a1032014-03-14 16:51:15 +02003092 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3093 intel_dp->psr_dpcd,
3094 sizeof(intel_dp->psr_dpcd));
Rodrigo Vivia031d702013-10-03 16:15:06 -03003095 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3096 dev_priv->psr.sink_support = true;
Jani Nikula50003932013-09-20 16:42:17 +03003097 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
Rodrigo Vivia031d702013-10-03 16:15:06 -03003098 }
Jani Nikula50003932013-09-20 16:42:17 +03003099 }
3100
Todd Previte06ea66b2014-01-20 10:19:39 -07003101 /* Training Pattern 3 support */
3102 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
3103 intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
3104 intel_dp->use_tps3 = true;
3105 DRM_DEBUG_KMS("Displayport TPS3 supported");
3106 } else
3107 intel_dp->use_tps3 = false;
3108
Adam Jacksonedb39242012-09-18 10:58:49 -04003109 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3110 DP_DWN_STRM_PORT_PRESENT))
3111 return true; /* native DP sink */
3112
3113 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3114 return true; /* no per-port downstream info */
3115
Jani Nikula9d1a1032014-03-14 16:51:15 +02003116 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3117 intel_dp->downstream_ports,
3118 DP_MAX_DOWNSTREAM_PORTS) < 0)
Adam Jacksonedb39242012-09-18 10:58:49 -04003119 return false; /* downstream port status fetch failed */
3120
3121 return true;
Keith Packard92fd8fd2011-07-25 19:50:10 -07003122}
3123
Adam Jackson0d198322012-05-14 16:05:47 -04003124static void
3125intel_dp_probe_oui(struct intel_dp *intel_dp)
3126{
3127 u8 buf[3];
3128
3129 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3130 return;
3131
Jani Nikula24f3e092014-03-17 16:43:36 +02003132 intel_edp_panel_vdd_on(intel_dp);
Daniel Vetter351cfc32012-06-12 13:20:47 +02003133
Jani Nikula9d1a1032014-03-14 16:51:15 +02003134 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003135 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3136 buf[0], buf[1], buf[2]);
3137
Jani Nikula9d1a1032014-03-14 16:51:15 +02003138 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
Adam Jackson0d198322012-05-14 16:05:47 -04003139 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3140 buf[0], buf[1], buf[2]);
Daniel Vetter351cfc32012-06-12 13:20:47 +02003141
Daniel Vetter4be73782014-01-17 14:39:48 +01003142 edp_panel_vdd_off(intel_dp, false);
Adam Jackson0d198322012-05-14 16:05:47 -04003143}
3144
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003145int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3146{
3147 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3148 struct drm_device *dev = intel_dig_port->base.base.dev;
3149 struct intel_crtc *intel_crtc =
3150 to_intel_crtc(intel_dig_port->base.base.crtc);
3151 u8 buf[1];
3152
Jani Nikula9d1a1032014-03-14 16:51:15 +02003153 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003154 return -EAGAIN;
3155
3156 if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
3157 return -ENOTTY;
3158
Jani Nikula9d1a1032014-03-14 16:51:15 +02003159 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3160 DP_TEST_SINK_START) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003161 return -EAGAIN;
3162
3163 /* Wait 2 vblanks to be sure we will have the correct CRC value */
3164 intel_wait_for_vblank(dev, intel_crtc->pipe);
3165 intel_wait_for_vblank(dev, intel_crtc->pipe);
3166
Jani Nikula9d1a1032014-03-14 16:51:15 +02003167 if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003168 return -EAGAIN;
3169
Jani Nikula9d1a1032014-03-14 16:51:15 +02003170 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
Rodrigo Vivid2e216d2014-01-24 13:36:17 -02003171 return 0;
3172}
3173
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003174static bool
3175intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3176{
Jani Nikula9d1a1032014-03-14 16:51:15 +02003177 return intel_dp_dpcd_read_wake(&intel_dp->aux,
3178 DP_DEVICE_SERVICE_IRQ_VECTOR,
3179 sink_irq_vector, 1) == 1;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003180}
3181
3182static void
3183intel_dp_handle_test_request(struct intel_dp *intel_dp)
3184{
3185 /* NAK by default */
Jani Nikula9d1a1032014-03-14 16:51:15 +02003186 drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003187}
3188
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003189/*
3190 * According to DP spec
3191 * 5.1.2:
3192 * 1. Read DPCD
3193 * 2. Configure link according to Receiver Capabilities
3194 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
3195 * 4. Check link status on receipt of hot-plug interrupt
3196 */
3197
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003198void
Chris Wilsonea5b2132010-08-04 13:50:23 +01003199intel_dp_check_link_status(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003200{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003201 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003202 u8 sink_irq_vector;
Keith Packard93f62da2011-11-01 19:45:03 -07003203 u8 link_status[DP_LINK_STATUS_SIZE];
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003204
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003205 if (!intel_encoder->connectors_active)
Keith Packardd2b996a2011-07-25 22:37:51 -07003206 return;
Jesse Barnes59cd09e2011-07-07 11:10:59 -07003207
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003208 if (WARN_ON(!intel_encoder->base.crtc))
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003209 return;
3210
Keith Packard92fd8fd2011-07-25 19:50:10 -07003211 /* Try to read receiver status if the link appears to be up */
Keith Packard93f62da2011-11-01 19:45:03 -07003212 if (!intel_dp_get_link_status(intel_dp, link_status)) {
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003213 return;
3214 }
3215
Keith Packard92fd8fd2011-07-25 19:50:10 -07003216 /* Now read the DPCD to see if it's actually running */
Keith Packard26d61aa2011-07-25 20:01:09 -07003217 if (!intel_dp_get_dpcd(intel_dp)) {
Jesse Barnes59cd09e2011-07-07 11:10:59 -07003218 return;
3219 }
3220
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003221 /* Try to read the source of the interrupt */
3222 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3223 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
3224 /* Clear interrupt source */
Jani Nikula9d1a1032014-03-14 16:51:15 +02003225 drm_dp_dpcd_writeb(&intel_dp->aux,
3226 DP_DEVICE_SERVICE_IRQ_VECTOR,
3227 sink_irq_vector);
Jesse Barnesa60f0e32011-10-20 15:09:17 -07003228
3229 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
3230 intel_dp_handle_test_request(intel_dp);
3231 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
3232 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
3233 }
3234
Daniel Vetter1ffdff12012-10-18 10:15:24 +02003235 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
Keith Packard92fd8fd2011-07-25 19:50:10 -07003236 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003237 drm_get_encoder_name(&intel_encoder->base));
Jesse Barnes33a34e42010-09-08 12:42:02 -07003238 intel_dp_start_link_train(intel_dp);
3239 intel_dp_complete_link_train(intel_dp);
Imre Deak3ab9c632013-05-03 12:57:41 +03003240 intel_dp_stop_link_train(intel_dp);
Jesse Barnes33a34e42010-09-08 12:42:02 -07003241 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003242}
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003243
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003244/* XXX this is probably wrong for multiple downstream ports */
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003245static enum drm_connector_status
Keith Packard26d61aa2011-07-25 20:01:09 -07003246intel_dp_detect_dpcd(struct intel_dp *intel_dp)
Adam Jackson71ba90002011-07-12 17:38:04 -04003247{
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003248 uint8_t *dpcd = intel_dp->dpcd;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003249 uint8_t type;
3250
3251 if (!intel_dp_get_dpcd(intel_dp))
3252 return connector_status_disconnected;
3253
3254 /* if there's no downstream port, we're done */
3255 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
Keith Packard26d61aa2011-07-25 20:01:09 -07003256 return connector_status_connected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003257
3258 /* If we're HPD-aware, SINK_COUNT changes dynamically */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003259 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
3260 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
Adam Jackson23235172012-09-20 16:42:45 -04003261 uint8_t reg;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003262
3263 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
3264 &reg, 1) < 0)
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003265 return connector_status_unknown;
Jani Nikula9d1a1032014-03-14 16:51:15 +02003266
Adam Jackson23235172012-09-20 16:42:45 -04003267 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
3268 : connector_status_disconnected;
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003269 }
3270
3271 /* If no HPD, poke DDC gently */
Jani Nikula0b998362014-03-14 16:51:17 +02003272 if (drm_probe_ddc(&intel_dp->aux.ddc))
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003273 return connector_status_connected;
3274
3275 /* Well we tried, say unknown for unreliable port types */
Jani Nikulac9ff1602013-09-27 14:48:42 +03003276 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
3277 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
3278 if (type == DP_DS_PORT_TYPE_VGA ||
3279 type == DP_DS_PORT_TYPE_NON_EDID)
3280 return connector_status_unknown;
3281 } else {
3282 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3283 DP_DWN_STRM_PORT_TYPE_MASK;
3284 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
3285 type == DP_DWN_STRM_PORT_TYPE_OTHER)
3286 return connector_status_unknown;
3287 }
Adam Jacksoncaf9ab22012-09-18 10:58:50 -04003288
3289 /* Anything else is out of spec, warn and ignore */
3290 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
Keith Packard26d61aa2011-07-25 20:01:09 -07003291 return connector_status_disconnected;
Adam Jackson71ba90002011-07-12 17:38:04 -04003292}
3293
3294static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003295ironlake_dp_detect(struct intel_dp *intel_dp)
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003296{
Paulo Zanoni30add222012-10-26 19:05:45 -02003297 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Damien Lespiau1b469632012-12-13 16:09:01 +00003298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003300 enum drm_connector_status status;
3301
Chris Wilsonfe16d942011-02-12 10:29:38 +00003302 /* Can't disconnect eDP, but you can close the lid... */
3303 if (is_edp(intel_dp)) {
Paulo Zanoni30add222012-10-26 19:05:45 -02003304 status = intel_panel_detect(dev);
Chris Wilsonfe16d942011-02-12 10:29:38 +00003305 if (status == connector_status_unknown)
3306 status = connector_status_connected;
3307 return status;
3308 }
Jesse Barnes01cb9ea2010-10-07 16:01:12 -07003309
Damien Lespiau1b469632012-12-13 16:09:01 +00003310 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
3311 return connector_status_disconnected;
3312
Keith Packard26d61aa2011-07-25 20:01:09 -07003313 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003314}
3315
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003316static enum drm_connector_status
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003317g4x_dp_detect(struct intel_dp *intel_dp)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003318{
Paulo Zanoni30add222012-10-26 19:05:45 -02003319 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003320 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä34f2be42013-01-24 15:29:27 +02003321 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Chris Wilson10f76a32012-05-11 18:01:32 +01003322 uint32_t bit;
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08003323
Jesse Barnes35aad752013-03-01 13:14:31 -08003324 /* Can't disconnect eDP, but you can close the lid... */
3325 if (is_edp(intel_dp)) {
3326 enum drm_connector_status status;
3327
3328 status = intel_panel_detect(dev);
3329 if (status == connector_status_unknown)
3330 status = connector_status_connected;
3331 return status;
3332 }
3333
Todd Previte232a6ee2014-01-23 00:13:41 -07003334 if (IS_VALLEYVIEW(dev)) {
3335 switch (intel_dig_port->port) {
3336 case PORT_B:
3337 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
3338 break;
3339 case PORT_C:
3340 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
3341 break;
3342 case PORT_D:
3343 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
3344 break;
3345 default:
3346 return connector_status_unknown;
3347 }
3348 } else {
3349 switch (intel_dig_port->port) {
3350 case PORT_B:
3351 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
3352 break;
3353 case PORT_C:
3354 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
3355 break;
3356 case PORT_D:
3357 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
3358 break;
3359 default:
3360 return connector_status_unknown;
3361 }
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003362 }
3363
Chris Wilson10f76a32012-05-11 18:01:32 +01003364 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003365 return connector_status_disconnected;
3366
Keith Packard26d61aa2011-07-25 20:01:09 -07003367 return intel_dp_detect_dpcd(intel_dp);
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003368}
3369
Keith Packard8c241fe2011-09-28 16:38:44 -07003370static struct edid *
3371intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
3372{
Jani Nikula9cd300e2012-10-19 14:51:52 +03003373 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07003374
Jani Nikula9cd300e2012-10-19 14:51:52 +03003375 /* use cached edid if we have one */
3376 if (intel_connector->edid) {
Jani Nikula9cd300e2012-10-19 14:51:52 +03003377 /* invalid edid */
3378 if (IS_ERR(intel_connector->edid))
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003379 return NULL;
3380
Jani Nikula55e9ede2013-10-01 10:38:54 +03003381 return drm_edid_duplicate(intel_connector->edid);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003382 }
3383
Jani Nikula9cd300e2012-10-19 14:51:52 +03003384 return drm_get_edid(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07003385}
3386
3387static int
3388intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
3389{
Jani Nikula9cd300e2012-10-19 14:51:52 +03003390 struct intel_connector *intel_connector = to_intel_connector(connector);
Keith Packard8c241fe2011-09-28 16:38:44 -07003391
Jani Nikula9cd300e2012-10-19 14:51:52 +03003392 /* use cached edid if we have one */
3393 if (intel_connector->edid) {
3394 /* invalid edid */
3395 if (IS_ERR(intel_connector->edid))
3396 return 0;
3397
3398 return intel_connector_update_modes(connector,
3399 intel_connector->edid);
Jesse Barnesd6f24d02012-06-14 15:28:33 -04003400 }
3401
Jani Nikula9cd300e2012-10-19 14:51:52 +03003402 return intel_ddc_get_modes(connector, adapter);
Keith Packard8c241fe2011-09-28 16:38:44 -07003403}
3404
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003405static enum drm_connector_status
3406intel_dp_detect(struct drm_connector *connector, bool force)
3407{
3408 struct intel_dp *intel_dp = intel_attached_dp(connector);
Paulo Zanonid63885d2012-10-26 19:05:49 -02003409 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3410 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003411 struct drm_device *dev = connector->dev;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003412 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003413 enum drm_connector_status status;
Imre Deak671dedd2014-03-05 16:20:53 +02003414 enum intel_display_power_domain power_domain;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003415 struct edid *edid = NULL;
3416
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003417 intel_runtime_pm_get(dev_priv);
3418
Imre Deak671dedd2014-03-05 16:20:53 +02003419 power_domain = intel_display_port_power_domain(intel_encoder);
3420 intel_display_power_get(dev_priv, power_domain);
3421
Chris Wilson164c8592013-07-20 20:27:08 +01003422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3423 connector->base.id, drm_get_connector_name(connector));
3424
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003425 intel_dp->has_audio = false;
3426
3427 if (HAS_PCH_SPLIT(dev))
3428 status = ironlake_dp_detect(intel_dp);
3429 else
3430 status = g4x_dp_detect(intel_dp);
Adam Jackson1b9be9d2011-07-12 17:38:01 -04003431
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003432 if (status != connector_status_connected)
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003433 goto out;
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003434
Adam Jackson0d198322012-05-14 16:05:47 -04003435 intel_dp_probe_oui(intel_dp);
3436
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003437 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
3438 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
Chris Wilsonf6849602010-09-19 09:29:33 +01003439 } else {
Jani Nikula0b998362014-03-14 16:51:17 +02003440 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
Chris Wilsonf6849602010-09-19 09:29:33 +01003441 if (edid) {
3442 intel_dp->has_audio = drm_detect_monitor_audio(edid);
Chris Wilsonf6849602010-09-19 09:29:33 +01003443 kfree(edid);
3444 }
Zhenyu Wanga9756bb2010-09-19 13:09:06 +08003445 }
3446
Paulo Zanonid63885d2012-10-26 19:05:49 -02003447 if (intel_encoder->type != INTEL_OUTPUT_EDP)
3448 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003449 status = connector_status_connected;
3450
3451out:
Imre Deak671dedd2014-03-05 16:20:53 +02003452 intel_display_power_put(dev_priv, power_domain);
3453
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003454 intel_runtime_pm_put(dev_priv);
Imre Deak671dedd2014-03-05 16:20:53 +02003455
Paulo Zanonic8c8fb32013-11-27 18:21:54 -02003456 return status;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003457}
3458
3459static int intel_dp_get_modes(struct drm_connector *connector)
3460{
Chris Wilsondf0e9242010-09-09 16:20:55 +01003461 struct intel_dp *intel_dp = intel_attached_dp(connector);
Imre Deak671dedd2014-03-05 16:20:53 +02003462 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3463 struct intel_encoder *intel_encoder = &intel_dig_port->base;
Jani Nikuladd06f902012-10-19 14:51:50 +03003464 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003465 struct drm_device *dev = connector->dev;
Imre Deak671dedd2014-03-05 16:20:53 +02003466 struct drm_i915_private *dev_priv = dev->dev_private;
3467 enum intel_display_power_domain power_domain;
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003468 int ret;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003469
3470 /* We should parse the EDID data and find out if it has an audio sink
3471 */
3472
Imre Deak671dedd2014-03-05 16:20:53 +02003473 power_domain = intel_display_port_power_domain(intel_encoder);
3474 intel_display_power_get(dev_priv, power_domain);
3475
Jani Nikula0b998362014-03-14 16:51:17 +02003476 ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
Imre Deak671dedd2014-03-05 16:20:53 +02003477 intel_display_power_put(dev_priv, power_domain);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003478 if (ret)
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003479 return ret;
3480
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003481 /* if eDP has no EDID, fall back to fixed mode */
Jani Nikuladd06f902012-10-19 14:51:50 +03003482 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003483 struct drm_display_mode *mode;
Jani Nikuladd06f902012-10-19 14:51:50 +03003484 mode = drm_mode_duplicate(dev,
3485 intel_connector->panel.fixed_mode);
Jani Nikulaf8779fd2012-10-19 14:51:48 +03003486 if (mode) {
Zhenyu Wang32f9d652009-07-24 01:00:32 +08003487 drm_mode_probed_add(connector, mode);
3488 return 1;
3489 }
3490 }
3491 return 0;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003492}
3493
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003494static bool
3495intel_dp_detect_audio(struct drm_connector *connector)
3496{
3497 struct intel_dp *intel_dp = intel_attached_dp(connector);
Imre Deak671dedd2014-03-05 16:20:53 +02003498 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3499 struct intel_encoder *intel_encoder = &intel_dig_port->base;
3500 struct drm_device *dev = connector->dev;
3501 struct drm_i915_private *dev_priv = dev->dev_private;
3502 enum intel_display_power_domain power_domain;
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003503 struct edid *edid;
3504 bool has_audio = false;
3505
Imre Deak671dedd2014-03-05 16:20:53 +02003506 power_domain = intel_display_port_power_domain(intel_encoder);
3507 intel_display_power_get(dev_priv, power_domain);
3508
Jani Nikula0b998362014-03-14 16:51:17 +02003509 edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003510 if (edid) {
3511 has_audio = drm_detect_monitor_audio(edid);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003512 kfree(edid);
3513 }
3514
Imre Deak671dedd2014-03-05 16:20:53 +02003515 intel_display_power_put(dev_priv, power_domain);
3516
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003517 return has_audio;
3518}
3519
Chris Wilsonf6849602010-09-19 09:29:33 +01003520static int
3521intel_dp_set_property(struct drm_connector *connector,
3522 struct drm_property *property,
3523 uint64_t val)
3524{
Chris Wilsone953fd72011-02-21 22:23:52 +00003525 struct drm_i915_private *dev_priv = connector->dev->dev_private;
Yuly Novikov53b41832012-10-26 12:04:00 +03003526 struct intel_connector *intel_connector = to_intel_connector(connector);
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003527 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
3528 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonf6849602010-09-19 09:29:33 +01003529 int ret;
3530
Rob Clark662595d2012-10-11 20:36:04 -05003531 ret = drm_object_property_set_value(&connector->base, property, val);
Chris Wilsonf6849602010-09-19 09:29:33 +01003532 if (ret)
3533 return ret;
3534
Chris Wilson3f43c482011-05-12 22:17:24 +01003535 if (property == dev_priv->force_audio_property) {
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003536 int i = val;
3537 bool has_audio;
3538
3539 if (i == intel_dp->force_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003540 return 0;
3541
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003542 intel_dp->force_audio = i;
Chris Wilsonf6849602010-09-19 09:29:33 +01003543
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003544 if (i == HDMI_AUDIO_AUTO)
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003545 has_audio = intel_dp_detect_audio(connector);
3546 else
Daniel Vetterc3e5f672012-02-23 17:14:47 +01003547 has_audio = (i == HDMI_AUDIO_ON);
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003548
3549 if (has_audio == intel_dp->has_audio)
Chris Wilsonf6849602010-09-19 09:29:33 +01003550 return 0;
3551
Chris Wilson1aad7ac2011-02-09 18:46:58 +00003552 intel_dp->has_audio = has_audio;
Chris Wilsonf6849602010-09-19 09:29:33 +01003553 goto done;
3554 }
3555
Chris Wilsone953fd72011-02-21 22:23:52 +00003556 if (property == dev_priv->broadcast_rgb_property) {
Daniel Vetterae4edb82013-04-22 17:07:23 +02003557 bool old_auto = intel_dp->color_range_auto;
3558 uint32_t old_range = intel_dp->color_range;
3559
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003560 switch (val) {
3561 case INTEL_BROADCAST_RGB_AUTO:
3562 intel_dp->color_range_auto = true;
3563 break;
3564 case INTEL_BROADCAST_RGB_FULL:
3565 intel_dp->color_range_auto = false;
3566 intel_dp->color_range = 0;
3567 break;
3568 case INTEL_BROADCAST_RGB_LIMITED:
3569 intel_dp->color_range_auto = false;
3570 intel_dp->color_range = DP_COLOR_RANGE_16_235;
3571 break;
3572 default:
3573 return -EINVAL;
3574 }
Daniel Vetterae4edb82013-04-22 17:07:23 +02003575
3576 if (old_auto == intel_dp->color_range_auto &&
3577 old_range == intel_dp->color_range)
3578 return 0;
3579
Chris Wilsone953fd72011-02-21 22:23:52 +00003580 goto done;
3581 }
3582
Yuly Novikov53b41832012-10-26 12:04:00 +03003583 if (is_edp(intel_dp) &&
3584 property == connector->dev->mode_config.scaling_mode_property) {
3585 if (val == DRM_MODE_SCALE_NONE) {
3586 DRM_DEBUG_KMS("no scaling not supported\n");
3587 return -EINVAL;
3588 }
3589
3590 if (intel_connector->panel.fitting_mode == val) {
3591 /* the eDP scaling property is not changed */
3592 return 0;
3593 }
3594 intel_connector->panel.fitting_mode = val;
3595
3596 goto done;
3597 }
3598
Chris Wilsonf6849602010-09-19 09:29:33 +01003599 return -EINVAL;
3600
3601done:
Chris Wilsonc0c36b942012-12-19 16:08:43 +00003602 if (intel_encoder->base.crtc)
3603 intel_crtc_restore_mode(intel_encoder->base.crtc);
Chris Wilsonf6849602010-09-19 09:29:33 +01003604
3605 return 0;
3606}
3607
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003608static void
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003609intel_dp_connector_destroy(struct drm_connector *connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003610{
Jani Nikula1d508702012-10-19 14:51:49 +03003611 struct intel_connector *intel_connector = to_intel_connector(connector);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003612
Jani Nikula9cd300e2012-10-19 14:51:52 +03003613 if (!IS_ERR_OR_NULL(intel_connector->edid))
3614 kfree(intel_connector->edid);
3615
Paulo Zanoniacd8db102013-06-12 17:27:23 -03003616 /* Can't call is_edp() since the encoder may have been destroyed
3617 * already. */
3618 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
Jani Nikula1d508702012-10-19 14:51:49 +03003619 intel_panel_fini(&intel_connector->panel);
Matthew Garrettaaa6fd22011-08-12 12:11:33 +02003620
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003621 drm_connector_cleanup(connector);
Zhenyu Wang55f78c42010-03-29 16:13:57 +08003622 kfree(connector);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003623}
3624
Paulo Zanoni00c09d72012-10-26 19:05:52 -02003625void intel_dp_encoder_destroy(struct drm_encoder *encoder)
Daniel Vetter24d05922010-08-20 18:08:28 +02003626{
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003627 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
3628 struct intel_dp *intel_dp = &intel_dig_port->dp;
Daniel Vetterbd173812013-03-25 11:24:10 +01003629 struct drm_device *dev = intel_dp_to_dev(intel_dp);
Daniel Vetter24d05922010-08-20 18:08:28 +02003630
Jani Nikula0b998362014-03-14 16:51:17 +02003631 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Daniel Vetter24d05922010-08-20 18:08:28 +02003632 drm_encoder_cleanup(encoder);
Keith Packardbd943152011-09-18 23:09:52 -07003633 if (is_edp(intel_dp)) {
3634 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
Daniel Vetterbd173812013-03-25 11:24:10 +01003635 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01003636 edp_panel_vdd_off_sync(intel_dp);
Daniel Vetterbd173812013-03-25 11:24:10 +01003637 mutex_unlock(&dev->mode_config.mutex);
Keith Packardbd943152011-09-18 23:09:52 -07003638 }
Paulo Zanonida63a9f2012-10-26 19:05:46 -02003639 kfree(intel_dig_port);
Daniel Vetter24d05922010-08-20 18:08:28 +02003640}
3641
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003642static const struct drm_connector_funcs intel_dp_connector_funcs = {
Daniel Vetter2bd2ad62012-09-06 22:15:41 +02003643 .dpms = intel_connector_dpms,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003644 .detect = intel_dp_detect,
3645 .fill_modes = drm_helper_probe_single_connector_modes,
Chris Wilsonf6849602010-09-19 09:29:33 +01003646 .set_property = intel_dp_set_property,
Paulo Zanoni73845ad2013-06-12 17:27:30 -03003647 .destroy = intel_dp_connector_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003648};
3649
3650static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
3651 .get_modes = intel_dp_get_modes,
3652 .mode_valid = intel_dp_mode_valid,
Chris Wilsondf0e9242010-09-09 16:20:55 +01003653 .best_encoder = intel_best_encoder,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003654};
3655
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003656static const struct drm_encoder_funcs intel_dp_enc_funcs = {
Daniel Vetter24d05922010-08-20 18:08:28 +02003657 .destroy = intel_dp_encoder_destroy,
Keith Packarda4fc5ed2009-04-07 16:16:42 -07003658};
3659
Chris Wilson995b67622010-08-20 13:23:26 +01003660static void
Eric Anholt21d40d32010-03-25 11:11:14 -07003661intel_dp_hot_plug(struct intel_encoder *intel_encoder)
Keith Packardc8110e52009-05-06 11:51:10 -07003662{
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003663 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
Keith Packardc8110e52009-05-06 11:51:10 -07003664
Jesse Barnes885a5012011-07-07 11:11:01 -07003665 intel_dp_check_link_status(intel_dp);
Keith Packardc8110e52009-05-06 11:51:10 -07003666}
3667
Zhenyu Wange3421a12010-04-08 09:43:27 +08003668/* Return which DP Port should be selected for Transcoder DP control */
3669int
Akshay Joshi0206e352011-08-16 15:34:10 -04003670intel_trans_dp_port_sel(struct drm_crtc *crtc)
Zhenyu Wange3421a12010-04-08 09:43:27 +08003671{
3672 struct drm_device *dev = crtc->dev;
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003673 struct intel_encoder *intel_encoder;
3674 struct intel_dp *intel_dp;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003675
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003676 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3677 intel_dp = enc_to_intel_dp(&intel_encoder->base);
Chris Wilsonea5b2132010-08-04 13:50:23 +01003678
Paulo Zanonifa90ece2012-10-26 19:05:44 -02003679 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
3680 intel_encoder->type == INTEL_OUTPUT_EDP)
Chris Wilsonea5b2132010-08-04 13:50:23 +01003681 return intel_dp->output_reg;
Zhenyu Wange3421a12010-04-08 09:43:27 +08003682 }
Chris Wilsonea5b2132010-08-04 13:50:23 +01003683
Zhenyu Wange3421a12010-04-08 09:43:27 +08003684 return -1;
3685}
3686
Zhao Yakui36e83a12010-06-12 14:32:21 +08003687/* check the VBT to see whether the eDP is on DP-D port */
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003688bool intel_dp_is_edp(struct drm_device *dev, enum port port)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003689{
3690 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni768f69c2013-09-11 18:02:47 -03003691 union child_device_config *p_child;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003692 int i;
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003693 static const short port_mapping[] = {
3694 [PORT_B] = PORT_IDPB,
3695 [PORT_C] = PORT_IDPC,
3696 [PORT_D] = PORT_IDPD,
3697 };
Zhao Yakui36e83a12010-06-12 14:32:21 +08003698
Ville Syrjälä3b32a352013-11-01 18:22:41 +02003699 if (port == PORT_A)
3700 return true;
3701
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003702 if (!dev_priv->vbt.child_dev_num)
Zhao Yakui36e83a12010-06-12 14:32:21 +08003703 return false;
3704
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003705 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
3706 p_child = dev_priv->vbt.child_dev + i;
Zhao Yakui36e83a12010-06-12 14:32:21 +08003707
Ville Syrjälä5d8a7752013-11-01 18:22:39 +02003708 if (p_child->common.dvo_port == port_mapping[port] &&
Ville Syrjäläf02586d2013-11-01 20:32:08 +02003709 (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
3710 (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
Zhao Yakui36e83a12010-06-12 14:32:21 +08003711 return true;
3712 }
3713 return false;
3714}
3715
Chris Wilsonf6849602010-09-19 09:29:33 +01003716static void
3717intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
3718{
Yuly Novikov53b41832012-10-26 12:04:00 +03003719 struct intel_connector *intel_connector = to_intel_connector(connector);
3720
Chris Wilson3f43c482011-05-12 22:17:24 +01003721 intel_attach_force_audio_property(connector);
Chris Wilsone953fd72011-02-21 22:23:52 +00003722 intel_attach_broadcast_rgb_property(connector);
Ville Syrjälä55bc60d2013-01-17 16:31:29 +02003723 intel_dp->color_range_auto = true;
Yuly Novikov53b41832012-10-26 12:04:00 +03003724
3725 if (is_edp(intel_dp)) {
3726 drm_mode_create_scaling_mode_property(connector->dev);
Rob Clark6de6d842012-10-11 20:36:04 -05003727 drm_object_attach_property(
3728 &connector->base,
Yuly Novikov53b41832012-10-26 12:04:00 +03003729 connector->dev->mode_config.scaling_mode_property,
Yuly Novikov8e740cd2012-10-26 12:04:01 +03003730 DRM_MODE_SCALE_ASPECT);
3731 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
Yuly Novikov53b41832012-10-26 12:04:00 +03003732 }
Chris Wilsonf6849602010-09-19 09:29:33 +01003733}
3734
Imre Deakdada1a92014-01-29 13:25:41 +02003735static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
3736{
3737 intel_dp->last_power_cycle = jiffies;
3738 intel_dp->last_power_on = jiffies;
3739 intel_dp->last_backlight_off = jiffies;
3740}
3741
Daniel Vetter67a54562012-10-20 20:57:45 +02003742static void
3743intel_dp_init_panel_power_sequencer(struct drm_device *dev,
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003744 struct intel_dp *intel_dp,
3745 struct edp_power_seq *out)
Daniel Vetter67a54562012-10-20 20:57:45 +02003746{
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct edp_power_seq cur, vbt, spec, final;
3749 u32 pp_on, pp_off, pp_div, pp;
Jani Nikulabf13e812013-09-06 07:40:05 +03003750 int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
Jesse Barnes453c5422013-03-28 09:55:41 -07003751
3752 if (HAS_PCH_SPLIT(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003753 pp_ctrl_reg = PCH_PP_CONTROL;
Jesse Barnes453c5422013-03-28 09:55:41 -07003754 pp_on_reg = PCH_PP_ON_DELAYS;
3755 pp_off_reg = PCH_PP_OFF_DELAYS;
3756 pp_div_reg = PCH_PP_DIVISOR;
3757 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003758 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3759
3760 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
3761 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3762 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3763 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003764 }
Daniel Vetter67a54562012-10-20 20:57:45 +02003765
3766 /* Workaround: Need to write PP_CONTROL with the unlock key as
3767 * the very first thing. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003768 pp = ironlake_get_pp_control(intel_dp);
Jani Nikulabf13e812013-09-06 07:40:05 +03003769 I915_WRITE(pp_ctrl_reg, pp);
Daniel Vetter67a54562012-10-20 20:57:45 +02003770
Jesse Barnes453c5422013-03-28 09:55:41 -07003771 pp_on = I915_READ(pp_on_reg);
3772 pp_off = I915_READ(pp_off_reg);
3773 pp_div = I915_READ(pp_div_reg);
Daniel Vetter67a54562012-10-20 20:57:45 +02003774
3775 /* Pull timing values out of registers */
3776 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
3777 PANEL_POWER_UP_DELAY_SHIFT;
3778
3779 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
3780 PANEL_LIGHT_ON_DELAY_SHIFT;
3781
3782 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
3783 PANEL_LIGHT_OFF_DELAY_SHIFT;
3784
3785 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
3786 PANEL_POWER_DOWN_DELAY_SHIFT;
3787
3788 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
3789 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
3790
3791 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3792 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
3793
Rodrigo Vivi41aa3442013-05-09 20:03:18 -03003794 vbt = dev_priv->vbt.edp_pps;
Daniel Vetter67a54562012-10-20 20:57:45 +02003795
3796 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
3797 * our hw here, which are all in 100usec. */
3798 spec.t1_t3 = 210 * 10;
3799 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
3800 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
3801 spec.t10 = 500 * 10;
3802 /* This one is special and actually in units of 100ms, but zero
3803 * based in the hw (so we need to add 100 ms). But the sw vbt
3804 * table multiplies it with 1000 to make it in units of 100usec,
3805 * too. */
3806 spec.t11_t12 = (510 + 100) * 10;
3807
3808 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
3809 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
3810
3811 /* Use the max of the register settings and vbt. If both are
3812 * unset, fall back to the spec limits. */
3813#define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
3814 spec.field : \
3815 max(cur.field, vbt.field))
3816 assign_final(t1_t3);
3817 assign_final(t8);
3818 assign_final(t9);
3819 assign_final(t10);
3820 assign_final(t11_t12);
3821#undef assign_final
3822
3823#define get_delay(field) (DIV_ROUND_UP(final.field, 10))
3824 intel_dp->panel_power_up_delay = get_delay(t1_t3);
3825 intel_dp->backlight_on_delay = get_delay(t8);
3826 intel_dp->backlight_off_delay = get_delay(t9);
3827 intel_dp->panel_power_down_delay = get_delay(t10);
3828 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
3829#undef get_delay
3830
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003831 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
3832 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
3833 intel_dp->panel_power_cycle_delay);
3834
3835 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
3836 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
3837
3838 if (out)
3839 *out = final;
3840}
3841
3842static void
3843intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
3844 struct intel_dp *intel_dp,
3845 struct edp_power_seq *seq)
3846{
3847 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes453c5422013-03-28 09:55:41 -07003848 u32 pp_on, pp_off, pp_div, port_sel = 0;
3849 int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
3850 int pp_on_reg, pp_off_reg, pp_div_reg;
3851
3852 if (HAS_PCH_SPLIT(dev)) {
3853 pp_on_reg = PCH_PP_ON_DELAYS;
3854 pp_off_reg = PCH_PP_OFF_DELAYS;
3855 pp_div_reg = PCH_PP_DIVISOR;
3856 } else {
Jani Nikulabf13e812013-09-06 07:40:05 +03003857 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
3858
3859 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
3860 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
3861 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
Jesse Barnes453c5422013-03-28 09:55:41 -07003862 }
3863
Paulo Zanonib2f19d12013-12-19 14:29:44 -02003864 /*
3865 * And finally store the new values in the power sequencer. The
3866 * backlight delays are set to 1 because we do manual waits on them. For
3867 * T8, even BSpec recommends doing it. For T9, if we don't do this,
3868 * we'll end up waiting for the backlight off delay twice: once when we
3869 * do the manual sleep, and once when we disable the panel and wait for
3870 * the PP_STATUS bit to become zero.
3871 */
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003872 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
Paulo Zanonib2f19d12013-12-19 14:29:44 -02003873 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
3874 pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003875 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
Daniel Vetter67a54562012-10-20 20:57:45 +02003876 /* Compute the divisor for the pp clock, simply match the Bspec
3877 * formula. */
Jesse Barnes453c5422013-03-28 09:55:41 -07003878 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
Jani Nikulaf30d26e2013-01-16 10:53:40 +02003879 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
Daniel Vetter67a54562012-10-20 20:57:45 +02003880 << PANEL_POWER_CYCLE_DELAY_SHIFT);
3881
3882 /* Haswell doesn't have any port selection bits for the panel
3883 * power sequencer any more. */
Imre Deakbc7d38a2013-05-16 14:40:36 +03003884 if (IS_VALLEYVIEW(dev)) {
Jani Nikulabf13e812013-09-06 07:40:05 +03003885 if (dp_to_dig_port(intel_dp)->port == PORT_B)
3886 port_sel = PANEL_PORT_SELECT_DPB_VLV;
3887 else
3888 port_sel = PANEL_PORT_SELECT_DPC_VLV;
Imre Deakbc7d38a2013-05-16 14:40:36 +03003889 } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
3890 if (dp_to_dig_port(intel_dp)->port == PORT_A)
Jani Nikulaa24c1442013-09-05 16:44:46 +03003891 port_sel = PANEL_PORT_SELECT_DPA;
Daniel Vetter67a54562012-10-20 20:57:45 +02003892 else
Jani Nikulaa24c1442013-09-05 16:44:46 +03003893 port_sel = PANEL_PORT_SELECT_DPD;
Daniel Vetter67a54562012-10-20 20:57:45 +02003894 }
3895
Jesse Barnes453c5422013-03-28 09:55:41 -07003896 pp_on |= port_sel;
3897
3898 I915_WRITE(pp_on_reg, pp_on);
3899 I915_WRITE(pp_off_reg, pp_off);
3900 I915_WRITE(pp_div_reg, pp_div);
Daniel Vetter67a54562012-10-20 20:57:45 +02003901
Daniel Vetter67a54562012-10-20 20:57:45 +02003902 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
Jesse Barnes453c5422013-03-28 09:55:41 -07003903 I915_READ(pp_on_reg),
3904 I915_READ(pp_off_reg),
3905 I915_READ(pp_div_reg));
Keith Packardc8110e52009-05-06 11:51:10 -07003906}
3907
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05303908void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
3909{
3910 struct drm_i915_private *dev_priv = dev->dev_private;
3911 struct intel_encoder *encoder;
3912 struct intel_dp *intel_dp = NULL;
3913 struct intel_crtc_config *config = NULL;
3914 struct intel_crtc *intel_crtc = NULL;
3915 struct intel_connector *intel_connector = dev_priv->drrs.connector;
3916 u32 reg, val;
3917 enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;
3918
3919 if (refresh_rate <= 0) {
3920 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
3921 return;
3922 }
3923
3924 if (intel_connector == NULL) {
3925 DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
3926 return;
3927 }
3928
3929 if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
3930 DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
3931 return;
3932 }
3933
3934 encoder = intel_attached_encoder(&intel_connector->base);
3935 intel_dp = enc_to_intel_dp(&encoder->base);
3936 intel_crtc = encoder->new_crtc;
3937
3938 if (!intel_crtc) {
3939 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
3940 return;
3941 }
3942
3943 config = &intel_crtc->config;
3944
3945 if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
3946 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
3947 return;
3948 }
3949
3950 if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
3951 index = DRRS_LOW_RR;
3952
3953 if (index == intel_dp->drrs_state.refresh_rate_type) {
3954 DRM_DEBUG_KMS(
3955 "DRRS requested for previously set RR...ignoring\n");
3956 return;
3957 }
3958
3959 if (!intel_crtc->active) {
3960 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
3961 return;
3962 }
3963
3964 if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
3965 reg = PIPECONF(intel_crtc->config.cpu_transcoder);
3966 val = I915_READ(reg);
3967 if (index > DRRS_HIGH_RR) {
3968 val |= PIPECONF_EDP_RR_MODE_SWITCH;
3969 intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
3970 } else {
3971 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
3972 }
3973 I915_WRITE(reg, val);
3974 }
3975
3976 /*
3977 * mutex taken to ensure that there is no race between differnt
3978 * drrs calls trying to update refresh rate. This scenario may occur
3979 * in future when idleness detection based DRRS in kernel and
3980 * possible calls from user space to set differnt RR are made.
3981 */
3982
3983 mutex_lock(&intel_dp->drrs_state.mutex);
3984
3985 intel_dp->drrs_state.refresh_rate_type = index;
3986
3987 mutex_unlock(&intel_dp->drrs_state.mutex);
3988
3989 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
3990}
3991
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05303992static struct drm_display_mode *
3993intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
3994 struct intel_connector *intel_connector,
3995 struct drm_display_mode *fixed_mode)
3996{
3997 struct drm_connector *connector = &intel_connector->base;
3998 struct intel_dp *intel_dp = &intel_dig_port->dp;
3999 struct drm_device *dev = intel_dig_port->base.base.dev;
4000 struct drm_i915_private *dev_priv = dev->dev_private;
4001 struct drm_display_mode *downclock_mode = NULL;
4002
4003 if (INTEL_INFO(dev)->gen <= 6) {
4004 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
4005 return NULL;
4006 }
4007
4008 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4009 DRM_INFO("VBT doesn't support DRRS\n");
4010 return NULL;
4011 }
4012
4013 downclock_mode = intel_find_panel_downclock
4014 (dev, fixed_mode, connector);
4015
4016 if (!downclock_mode) {
4017 DRM_INFO("DRRS not supported\n");
4018 return NULL;
4019 }
4020
Pradeep Bhat439d7ac2014-04-05 12:13:28 +05304021 dev_priv->drrs.connector = intel_connector;
4022
4023 mutex_init(&intel_dp->drrs_state.mutex);
4024
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304025 intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;
4026
4027 intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4028 DRM_INFO("seamless DRRS supported for eDP panel.\n");
4029 return downclock_mode;
4030}
4031
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004032static bool intel_edp_init_connector(struct intel_dp *intel_dp,
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004033 struct intel_connector *intel_connector,
4034 struct edp_power_seq *power_seq)
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004035{
4036 struct drm_connector *connector = &intel_connector->base;
4037 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
Paulo Zanoni63635212014-04-22 19:55:42 -03004038 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4039 struct drm_device *dev = intel_encoder->base.dev;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004040 struct drm_i915_private *dev_priv = dev->dev_private;
4041 struct drm_display_mode *fixed_mode = NULL;
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304042 struct drm_display_mode *downclock_mode = NULL;
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004043 bool has_dpcd;
4044 struct drm_display_mode *scan;
4045 struct edid *edid;
4046
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304047 intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;
4048
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004049 if (!is_edp(intel_dp))
4050 return true;
4051
Paulo Zanoni63635212014-04-22 19:55:42 -03004052 /* The VDD bit needs a power domain reference, so if the bit is already
4053 * enabled when we boot, grab this reference. */
4054 if (edp_have_panel_vdd(intel_dp)) {
4055 enum intel_display_power_domain power_domain;
4056 power_domain = intel_display_port_power_domain(intel_encoder);
4057 intel_display_power_get(dev_priv, power_domain);
4058 }
4059
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004060 /* Cache DPCD and EDID for edp. */
Jani Nikula24f3e092014-03-17 16:43:36 +02004061 intel_edp_panel_vdd_on(intel_dp);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004062 has_dpcd = intel_dp_get_dpcd(intel_dp);
Daniel Vetter4be73782014-01-17 14:39:48 +01004063 edp_panel_vdd_off(intel_dp, false);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004064
4065 if (has_dpcd) {
4066 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
4067 dev_priv->no_aux_handshake =
4068 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
4069 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
4070 } else {
4071 /* if this fails, presume the device is a ghost */
4072 DRM_INFO("failed to retrieve link info, disabling eDP\n");
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004073 return false;
4074 }
4075
4076 /* We now know it's not a ghost, init power sequence regs. */
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004077 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004078
Daniel Vetter060c8772014-03-21 23:22:35 +01004079 mutex_lock(&dev->mode_config.mutex);
Jani Nikula0b998362014-03-14 16:51:17 +02004080 edid = drm_get_edid(connector, &intel_dp->aux.ddc);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004081 if (edid) {
4082 if (drm_add_edid_modes(connector, edid)) {
4083 drm_mode_connector_update_edid_property(connector,
4084 edid);
4085 drm_edid_to_eld(connector, edid);
4086 } else {
4087 kfree(edid);
4088 edid = ERR_PTR(-EINVAL);
4089 }
4090 } else {
4091 edid = ERR_PTR(-ENOENT);
4092 }
4093 intel_connector->edid = edid;
4094
4095 /* prefer fixed mode from EDID if available */
4096 list_for_each_entry(scan, &connector->probed_modes, head) {
4097 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
4098 fixed_mode = drm_mode_duplicate(dev, scan);
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304099 downclock_mode = intel_dp_drrs_init(
4100 intel_dig_port,
4101 intel_connector, fixed_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004102 break;
4103 }
4104 }
4105
4106 /* fallback to VBT if available for eDP */
4107 if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
4108 fixed_mode = drm_mode_duplicate(dev,
4109 dev_priv->vbt.lfp_lvds_vbt_mode);
4110 if (fixed_mode)
4111 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
4112 }
Daniel Vetter060c8772014-03-21 23:22:35 +01004113 mutex_unlock(&dev->mode_config.mutex);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004114
Pradeep Bhat4f9db5b2014-04-05 12:12:31 +05304115 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
Paulo Zanonied92f0b2013-06-12 17:27:24 -03004116 intel_panel_setup_backlight(connector);
4117
4118 return true;
4119}
4120
Paulo Zanoni16c25532013-06-12 17:27:25 -03004121bool
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004122intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
4123 struct intel_connector *intel_connector)
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004124{
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004125 struct drm_connector *connector = &intel_connector->base;
4126 struct intel_dp *intel_dp = &intel_dig_port->dp;
4127 struct intel_encoder *intel_encoder = &intel_dig_port->base;
4128 struct drm_device *dev = intel_encoder->base.dev;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004129 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni174edf12012-10-26 19:05:50 -02004130 enum port port = intel_dig_port->port;
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004131 struct edp_power_seq power_seq = { 0 };
Jani Nikula0b998362014-03-14 16:51:17 +02004132 int type;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004133
Damien Lespiauec5b01d2014-01-21 13:35:39 +00004134 /* intel_dp vfuncs */
4135 if (IS_VALLEYVIEW(dev))
4136 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
4137 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4138 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
4139 else if (HAS_PCH_SPLIT(dev))
4140 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
4141 else
4142 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
4143
Damien Lespiau153b1102014-01-21 13:37:15 +00004144 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
4145
Daniel Vetter07679352012-09-06 22:15:42 +02004146 /* Preserve the current hw state. */
4147 intel_dp->DP = I915_READ(intel_dp->output_reg);
Jani Nikuladd06f902012-10-19 14:51:50 +03004148 intel_dp->attached_connector = intel_connector;
Chris Wilson3d3dc142011-02-12 10:33:12 +00004149
Ville Syrjälä3b32a352013-11-01 18:22:41 +02004150 if (intel_dp_is_edp(dev, port))
Gajanan Bhat19c03922012-09-27 19:13:07 +05304151 type = DRM_MODE_CONNECTOR_eDP;
Ville Syrjälä3b32a352013-11-01 18:22:41 +02004152 else
4153 type = DRM_MODE_CONNECTOR_DisplayPort;
Adam Jacksonb3295302010-07-16 14:46:28 -04004154
Imre Deakf7d24902013-05-08 13:14:05 +03004155 /*
4156 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
4157 * for DP the encoder type can be set by the caller to
4158 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
4159 */
4160 if (type == DRM_MODE_CONNECTOR_eDP)
4161 intel_encoder->type = INTEL_OUTPUT_EDP;
4162
Imre Deake7281ea2013-05-08 13:14:08 +03004163 DRM_DEBUG_KMS("Adding %s connector on port %c\n",
4164 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
4165 port_name(port));
4166
Adam Jacksonb3295302010-07-16 14:46:28 -04004167 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004168 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
4169
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004170 connector->interlace_allowed = true;
4171 connector->doublescan_allowed = 0;
Ma Lingf8aed702009-08-24 13:50:24 +08004172
Daniel Vetter66a92782012-07-12 20:08:18 +02004173 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
Daniel Vetter4be73782014-01-17 14:39:48 +01004174 edp_panel_vdd_work);
Zhenyu Wang6251ec02010-01-12 05:38:32 +08004175
Chris Wilsondf0e9242010-09-09 16:20:55 +01004176 intel_connector_attach_encoder(intel_connector, intel_encoder);
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004177 drm_sysfs_connector_add(connector);
4178
Paulo Zanoniaffa9352012-11-23 15:30:39 -02004179 if (HAS_DDI(dev))
Paulo Zanonibcbc8892012-10-26 19:05:51 -02004180 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
4181 else
4182 intel_connector->get_hw_state = intel_connector_get_hw_state;
Imre Deak80f65de2014-02-11 17:12:49 +02004183 intel_connector->unregister = intel_dp_connector_unregister;
Paulo Zanonibcbc8892012-10-26 19:05:51 -02004184
Jani Nikula0b998362014-03-14 16:51:17 +02004185 /* Set up the hotplug pin. */
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004186 switch (port) {
4187 case PORT_A:
Egbert Eich1d843f92013-02-25 12:06:49 -05004188 intel_encoder->hpd_pin = HPD_PORT_A;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004189 break;
4190 case PORT_B:
Egbert Eich1d843f92013-02-25 12:06:49 -05004191 intel_encoder->hpd_pin = HPD_PORT_B;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004192 break;
4193 case PORT_C:
Egbert Eich1d843f92013-02-25 12:06:49 -05004194 intel_encoder->hpd_pin = HPD_PORT_C;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004195 break;
4196 case PORT_D:
Egbert Eich1d843f92013-02-25 12:06:49 -05004197 intel_encoder->hpd_pin = HPD_PORT_D;
Paulo Zanoniab9d7c32012-07-17 17:53:45 -03004198 break;
4199 default:
Damien Lespiauad1c0b12013-03-07 15:30:28 +00004200 BUG();
Zhenyu Wang5eb08b62009-07-24 01:00:31 +08004201 }
4202
Imre Deakdada1a92014-01-29 13:25:41 +02004203 if (is_edp(intel_dp)) {
4204 intel_dp_init_panel_power_timestamps(intel_dp);
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004205 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
Imre Deakdada1a92014-01-29 13:25:41 +02004206 }
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004207
Jani Nikula9d1a1032014-03-14 16:51:15 +02004208 intel_dp_aux_init(intel_dp, intel_connector);
Dave Airliec1f05262012-08-30 11:06:18 +10004209
Rodrigo Vivi2b28bb12013-07-11 18:44:58 -03004210 intel_dp->psr_setup_done = false;
4211
Paulo Zanoni0095e6d2013-12-19 14:29:39 -02004212 if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
Jani Nikula0b998362014-03-14 16:51:17 +02004213 drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004214 if (is_edp(intel_dp)) {
4215 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4216 mutex_lock(&dev->mode_config.mutex);
Daniel Vetter4be73782014-01-17 14:39:48 +01004217 edp_panel_vdd_off_sync(intel_dp);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004218 mutex_unlock(&dev->mode_config.mutex);
4219 }
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004220 drm_sysfs_connector_remove(connector);
4221 drm_connector_cleanup(connector);
Paulo Zanoni16c25532013-06-12 17:27:25 -03004222 return false;
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004223 }
Zhenyu Wang32f9d652009-07-24 01:00:32 +08004224
Chris Wilsonf6849602010-09-19 09:29:33 +01004225 intel_dp_add_properties(intel_dp, connector);
4226
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004227 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
4228 * 0xd. Failure to do so will result in spurious interrupts being
4229 * generated on the port when a cable is not attached.
4230 */
4231 if (IS_G4X(dev) && !IS_GM45(dev)) {
4232 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
4233 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
4234 }
Paulo Zanoni16c25532013-06-12 17:27:25 -03004235
4236 return true;
Keith Packarda4fc5ed2009-04-07 16:16:42 -07004237}
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004238
4239void
4240intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
4241{
4242 struct intel_digital_port *intel_dig_port;
4243 struct intel_encoder *intel_encoder;
4244 struct drm_encoder *encoder;
4245 struct intel_connector *intel_connector;
4246
Daniel Vetterb14c5672013-09-19 12:18:32 +02004247 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004248 if (!intel_dig_port)
4249 return;
4250
Daniel Vetterb14c5672013-09-19 12:18:32 +02004251 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004252 if (!intel_connector) {
4253 kfree(intel_dig_port);
4254 return;
4255 }
4256
4257 intel_encoder = &intel_dig_port->base;
4258 encoder = &intel_encoder->base;
4259
4260 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
4261 DRM_MODE_ENCODER_TMDS);
4262
Daniel Vetter5bfe2ac2013-03-27 00:44:55 +01004263 intel_encoder->compute_config = intel_dp_compute_config;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004264 intel_encoder->disable = intel_disable_dp;
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004265 intel_encoder->get_hw_state = intel_dp_get_hw_state;
Jesse Barnes045ac3b2013-05-14 17:08:26 -07004266 intel_encoder->get_config = intel_dp_get_config;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03004267 if (IS_CHERRYVIEW(dev)) {
4268 intel_encoder->pre_enable = chv_pre_enable_dp;
4269 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä580d3812014-04-09 13:29:00 +03004270 intel_encoder->post_disable = chv_post_disable_dp;
Chon Ming Leee4a1d842014-04-09 13:28:20 +03004271 } else if (IS_VALLEYVIEW(dev)) {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004272 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004273 intel_encoder->pre_enable = vlv_pre_enable_dp;
4274 intel_encoder->enable = vlv_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004275 intel_encoder->post_disable = vlv_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004276 } else {
Jani Nikulaecff4f32013-09-06 07:38:29 +03004277 intel_encoder->pre_enable = g4x_pre_enable_dp;
4278 intel_encoder->enable = g4x_enable_dp;
Ville Syrjälä49277c32014-03-31 18:21:26 +03004279 intel_encoder->post_disable = g4x_post_disable_dp;
Jani Nikulaab1f90f2013-07-30 12:20:30 +03004280 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004281
Paulo Zanoni174edf12012-10-26 19:05:50 -02004282 intel_dig_port->port = port;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004283 intel_dig_port->dp.output_reg = output_reg;
4284
Paulo Zanoni00c09d72012-10-26 19:05:52 -02004285 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Ville Syrjälä882ec382014-04-28 14:07:43 +03004286 if (IS_CHERRYVIEW(dev)) {
4287 if (port == PORT_D)
4288 intel_encoder->crtc_mask = 1 << 2;
4289 else
4290 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
4291 } else {
4292 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4293 }
Ville Syrjäläbc079e82014-03-03 16:15:28 +02004294 intel_encoder->cloneable = 0;
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004295 intel_encoder->hot_plug = intel_dp_hot_plug;
4296
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004297 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
4298 drm_encoder_cleanup(encoder);
4299 kfree(intel_dig_port);
Paulo Zanonib2f246a2013-06-12 17:27:26 -03004300 kfree(intel_connector);
Paulo Zanoni15b1d172013-06-12 17:27:27 -03004301 }
Paulo Zanonif0fec3f2012-10-26 19:05:48 -02004302}