Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 37 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 40 | |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 41 | struct dp_link_dpll { |
| 42 | int link_bw; |
| 43 | struct dpll dpll; |
| 44 | }; |
| 45 | |
| 46 | static const struct dp_link_dpll gen4_dpll[] = { |
| 47 | { DP_LINK_BW_1_62, |
| 48 | { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, |
| 49 | { DP_LINK_BW_2_7, |
| 50 | { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } |
| 51 | }; |
| 52 | |
| 53 | static const struct dp_link_dpll pch_dpll[] = { |
| 54 | { DP_LINK_BW_1_62, |
| 55 | { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, |
| 56 | { DP_LINK_BW_2_7, |
| 57 | { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } |
| 58 | }; |
| 59 | |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 60 | static const struct dp_link_dpll vlv_dpll[] = { |
| 61 | { DP_LINK_BW_1_62, |
Chon Ming Lee | 58f6e63 | 2013-09-25 15:47:51 +0800 | [diff] [blame] | 62 | { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 63 | { DP_LINK_BW_2_7, |
| 64 | { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } |
| 65 | }; |
| 66 | |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 67 | /* |
| 68 | * CHV supports eDP 1.4 that have more link rates. |
| 69 | * Below only provides the fixed rate but exclude variable rate. |
| 70 | */ |
| 71 | static const struct dp_link_dpll chv_dpll[] = { |
| 72 | /* |
| 73 | * CHV requires to program fractional division for m2. |
| 74 | * m2 is stored in fixed point format using formula below |
| 75 | * (m2_int << 22) | m2_fraction |
| 76 | */ |
| 77 | { DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ |
| 78 | { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, |
| 79 | { DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ |
| 80 | { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, |
| 81 | { DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ |
| 82 | { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } |
| 83 | }; |
| 84 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 85 | /** |
| 86 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 87 | * @intel_dp: DP struct |
| 88 | * |
| 89 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 90 | * will return true, and false otherwise. |
| 91 | */ |
| 92 | static bool is_edp(struct intel_dp *intel_dp) |
| 93 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 94 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 95 | |
| 96 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 97 | } |
| 98 | |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 99 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 100 | { |
Imre Deak | 68b4d82 | 2013-05-08 13:14:06 +0300 | [diff] [blame] | 101 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 102 | |
| 103 | return intel_dig_port->base.base.dev; |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 104 | } |
| 105 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 106 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 107 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 108 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 109 | } |
| 110 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 111 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 112 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 113 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 114 | |
| 115 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 116 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 117 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 118 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 119 | struct drm_device *dev = intel_dp->attached_connector->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 120 | |
| 121 | switch (max_link_bw) { |
| 122 | case DP_LINK_BW_1_62: |
| 123 | case DP_LINK_BW_2_7: |
| 124 | break; |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 125 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 126 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && |
| 127 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
| 128 | max_link_bw = DP_LINK_BW_5_4; |
| 129 | else |
| 130 | max_link_bw = DP_LINK_BW_2_7; |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 131 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 132 | default: |
Imre Deak | d4eead5 | 2013-07-09 17:05:26 +0300 | [diff] [blame] | 133 | WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n", |
| 134 | max_link_bw); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 135 | max_link_bw = DP_LINK_BW_1_62; |
| 136 | break; |
| 137 | } |
| 138 | return max_link_bw; |
| 139 | } |
| 140 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 141 | /* |
| 142 | * The units on the numbers in the next two are... bizarre. Examples will |
| 143 | * make it clearer; this one parallels an example in the eDP spec. |
| 144 | * |
| 145 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 146 | * |
| 147 | * 270000 * 1 * 8 / 10 == 216000 |
| 148 | * |
| 149 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 150 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 151 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 152 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 153 | * |
| 154 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 155 | * get the result in decakilobits instead of kilobits. |
| 156 | */ |
| 157 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 158 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 159 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 160 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 161 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 162 | } |
| 163 | |
| 164 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 165 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 166 | { |
| 167 | return (max_link_clock * max_lanes * 8) / 10; |
| 168 | } |
| 169 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 170 | static enum drm_mode_status |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 171 | intel_dp_mode_valid(struct drm_connector *connector, |
| 172 | struct drm_display_mode *mode) |
| 173 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 174 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 175 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 176 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 177 | int target_clock = mode->clock; |
| 178 | int max_rate, mode_rate, max_lanes, max_link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 179 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 180 | if (is_edp(intel_dp) && fixed_mode) { |
| 181 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 182 | return MODE_PANEL; |
| 183 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 184 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 185 | return MODE_PANEL; |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 186 | |
| 187 | target_clock = fixed_mode->clock; |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 188 | } |
| 189 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 190 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
| 191 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
| 192 | |
| 193 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 194 | mode_rate = intel_dp_link_required(target_clock, 18); |
| 195 | |
| 196 | if (mode_rate > max_rate) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 197 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 198 | |
| 199 | if (mode->clock < 10000) |
| 200 | return MODE_CLOCK_LOW; |
| 201 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 202 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 203 | return MODE_H_ILLEGAL; |
| 204 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 205 | return MODE_OK; |
| 206 | } |
| 207 | |
| 208 | static uint32_t |
| 209 | pack_aux(uint8_t *src, int src_bytes) |
| 210 | { |
| 211 | int i; |
| 212 | uint32_t v = 0; |
| 213 | |
| 214 | if (src_bytes > 4) |
| 215 | src_bytes = 4; |
| 216 | for (i = 0; i < src_bytes; i++) |
| 217 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 218 | return v; |
| 219 | } |
| 220 | |
| 221 | static void |
| 222 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 223 | { |
| 224 | int i; |
| 225 | if (dst_bytes > 4) |
| 226 | dst_bytes = 4; |
| 227 | for (i = 0; i < dst_bytes; i++) |
| 228 | dst[i] = src >> ((3-i) * 8); |
| 229 | } |
| 230 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 231 | /* hrawclock is 1/4 the FSB frequency */ |
| 232 | static int |
| 233 | intel_hrawclk(struct drm_device *dev) |
| 234 | { |
| 235 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 236 | uint32_t clkcfg; |
| 237 | |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 238 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 239 | if (IS_VALLEYVIEW(dev)) |
| 240 | return 200; |
| 241 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 242 | clkcfg = I915_READ(CLKCFG); |
| 243 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 244 | case CLKCFG_FSB_400: |
| 245 | return 100; |
| 246 | case CLKCFG_FSB_533: |
| 247 | return 133; |
| 248 | case CLKCFG_FSB_667: |
| 249 | return 166; |
| 250 | case CLKCFG_FSB_800: |
| 251 | return 200; |
| 252 | case CLKCFG_FSB_1067: |
| 253 | return 266; |
| 254 | case CLKCFG_FSB_1333: |
| 255 | return 333; |
| 256 | /* these two are just a guess; one of them might be right */ |
| 257 | case CLKCFG_FSB_1600: |
| 258 | case CLKCFG_FSB_1600_ALT: |
| 259 | return 400; |
| 260 | default: |
| 261 | return 133; |
| 262 | } |
| 263 | } |
| 264 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 265 | static void |
| 266 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
| 267 | struct intel_dp *intel_dp, |
| 268 | struct edp_power_seq *out); |
| 269 | static void |
| 270 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 271 | struct intel_dp *intel_dp, |
| 272 | struct edp_power_seq *out); |
| 273 | |
| 274 | static enum pipe |
| 275 | vlv_power_sequencer_pipe(struct intel_dp *intel_dp) |
| 276 | { |
| 277 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 278 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 279 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 280 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 281 | enum port port = intel_dig_port->port; |
| 282 | enum pipe pipe; |
| 283 | |
| 284 | /* modeset should have pipe */ |
| 285 | if (crtc) |
| 286 | return to_intel_crtc(crtc)->pipe; |
| 287 | |
| 288 | /* init time, try to find a pipe with this port selected */ |
| 289 | for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { |
| 290 | u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & |
| 291 | PANEL_PORT_SELECT_MASK; |
| 292 | if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B) |
| 293 | return pipe; |
| 294 | if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C) |
| 295 | return pipe; |
| 296 | } |
| 297 | |
| 298 | /* shrug */ |
| 299 | return PIPE_A; |
| 300 | } |
| 301 | |
| 302 | static u32 _pp_ctrl_reg(struct intel_dp *intel_dp) |
| 303 | { |
| 304 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 305 | |
| 306 | if (HAS_PCH_SPLIT(dev)) |
| 307 | return PCH_PP_CONTROL; |
| 308 | else |
| 309 | return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp)); |
| 310 | } |
| 311 | |
| 312 | static u32 _pp_stat_reg(struct intel_dp *intel_dp) |
| 313 | { |
| 314 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 315 | |
| 316 | if (HAS_PCH_SPLIT(dev)) |
| 317 | return PCH_PP_STATUS; |
| 318 | else |
| 319 | return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp)); |
| 320 | } |
| 321 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 322 | static bool edp_have_panel_power(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 323 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 324 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 325 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 326 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 327 | return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 328 | } |
| 329 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 330 | static bool edp_have_panel_vdd(struct intel_dp *intel_dp) |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 331 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 332 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 333 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | bb4932c | 2014-04-14 20:24:33 +0300 | [diff] [blame] | 334 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 335 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 336 | enum intel_display_power_domain power_domain; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 337 | |
Imre Deak | bb4932c | 2014-04-14 20:24:33 +0300 | [diff] [blame] | 338 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 339 | return intel_display_power_enabled(dev_priv, power_domain) && |
Paulo Zanoni | efbc20a | 2014-04-01 14:55:09 -0300 | [diff] [blame] | 340 | (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 341 | } |
| 342 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 343 | static void |
| 344 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 345 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 346 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 347 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 348 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 349 | if (!is_edp(intel_dp)) |
| 350 | return; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 351 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 352 | if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 353 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 354 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 355 | I915_READ(_pp_stat_reg(intel_dp)), |
| 356 | I915_READ(_pp_ctrl_reg(intel_dp))); |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 357 | } |
| 358 | } |
| 359 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 360 | static uint32_t |
| 361 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
| 362 | { |
| 363 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 364 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 366 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 367 | uint32_t status; |
| 368 | bool done; |
| 369 | |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 370 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 371 | if (has_aux_irq) |
Paulo Zanoni | b18ac46 | 2013-02-18 19:00:24 -0300 | [diff] [blame] | 372 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
Imre Deak | 3598706 | 2013-05-21 20:03:20 +0300 | [diff] [blame] | 373 | msecs_to_jiffies_timeout(10)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 374 | else |
| 375 | done = wait_for_atomic(C, 10) == 0; |
| 376 | if (!done) |
| 377 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
| 378 | has_aux_irq); |
| 379 | #undef C |
| 380 | |
| 381 | return status; |
| 382 | } |
| 383 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 384 | static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 385 | { |
| 386 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 387 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 388 | |
| 389 | /* |
| 390 | * The clock divider is based off the hrawclk, and would like to run at |
| 391 | * 2MHz. So, take the hrawclk value and divide by 2 and use that |
| 392 | */ |
| 393 | return index ? 0 : intel_hrawclk(dev) / 2; |
| 394 | } |
| 395 | |
| 396 | static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 397 | { |
| 398 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 399 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 400 | |
| 401 | if (index) |
| 402 | return 0; |
| 403 | |
| 404 | if (intel_dig_port->port == PORT_A) { |
| 405 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 406 | return 200; /* SNB & IVB eDP input clock at 400Mhz */ |
| 407 | else |
| 408 | return 225; /* eDP input clock at 450Mhz */ |
| 409 | } else { |
| 410 | return DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
| 411 | } |
| 412 | } |
| 413 | |
| 414 | static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 415 | { |
| 416 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 417 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 418 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 419 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 420 | if (intel_dig_port->port == PORT_A) { |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 421 | if (index) |
| 422 | return 0; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 423 | return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 424 | } else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) { |
| 425 | /* Workaround for non-ULT HSW */ |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 426 | switch (index) { |
| 427 | case 0: return 63; |
| 428 | case 1: return 72; |
| 429 | default: return 0; |
| 430 | } |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 431 | } else { |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 432 | return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
Rodrigo Vivi | b84a1cf | 2013-07-11 18:44:57 -0300 | [diff] [blame] | 433 | } |
| 434 | } |
| 435 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 436 | static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index) |
| 437 | { |
| 438 | return index ? 0 : 100; |
| 439 | } |
| 440 | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 441 | static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp, |
| 442 | bool has_aux_irq, |
| 443 | int send_bytes, |
| 444 | uint32_t aux_clock_divider) |
| 445 | { |
| 446 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 447 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 448 | uint32_t precharge, timeout; |
| 449 | |
| 450 | if (IS_GEN6(dev)) |
| 451 | precharge = 3; |
| 452 | else |
| 453 | precharge = 5; |
| 454 | |
| 455 | if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL) |
| 456 | timeout = DP_AUX_CH_CTL_TIME_OUT_600us; |
| 457 | else |
| 458 | timeout = DP_AUX_CH_CTL_TIME_OUT_400us; |
| 459 | |
| 460 | return DP_AUX_CH_CTL_SEND_BUSY | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 461 | DP_AUX_CH_CTL_DONE | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 462 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 463 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 464 | timeout | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 465 | DP_AUX_CH_CTL_RECEIVE_ERROR | |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 466 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 467 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
Damien Lespiau | 788d443 | 2014-01-20 15:52:31 +0000 | [diff] [blame] | 468 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 469 | } |
| 470 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 471 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 472 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 473 | uint8_t *send, int send_bytes, |
| 474 | uint8_t *recv, int recv_size) |
| 475 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 476 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 477 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 478 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 9ed35ab | 2013-02-18 19:00:25 -0300 | [diff] [blame] | 479 | uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 480 | uint32_t ch_data = ch_ctl + 4; |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 481 | uint32_t aux_clock_divider; |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 482 | int i, ret, recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 483 | uint32_t status; |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 484 | int try, clock = 0; |
Daniel Vetter | 4e6b788 | 2014-02-07 16:33:20 +0100 | [diff] [blame] | 485 | bool has_aux_irq = HAS_AUX_IRQ(dev); |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 486 | bool vdd; |
| 487 | |
| 488 | vdd = _edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 489 | |
| 490 | /* dp aux is extremely sensitive to irq latency, hence request the |
| 491 | * lowest possible wakeup latency and so prevent the cpu from going into |
| 492 | * deep sleep states. |
| 493 | */ |
| 494 | pm_qos_update_request(&dev_priv->pm_qos, 0); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 495 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 496 | intel_dp_check_edp(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 497 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 498 | intel_aux_display_runtime_get(dev_priv); |
| 499 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 500 | /* Try to wait for any previous AUX channel activity */ |
| 501 | for (try = 0; try < 3; try++) { |
Daniel Vetter | ef04f00 | 2012-12-01 21:03:59 +0100 | [diff] [blame] | 502 | status = I915_READ_NOTRACE(ch_ctl); |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 503 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 504 | break; |
| 505 | msleep(1); |
| 506 | } |
| 507 | |
| 508 | if (try == 3) { |
| 509 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 510 | I915_READ(ch_ctl)); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 511 | ret = -EBUSY; |
| 512 | goto out; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 513 | } |
| 514 | |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 515 | /* Only 5 data registers! */ |
| 516 | if (WARN_ON(send_bytes > 20 || recv_size > 20)) { |
| 517 | ret = -E2BIG; |
| 518 | goto out; |
| 519 | } |
| 520 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 521 | while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 522 | u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, |
| 523 | has_aux_irq, |
| 524 | send_bytes, |
| 525 | aux_clock_divider); |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 526 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 527 | /* Must try at least 3 times according to DP spec */ |
| 528 | for (try = 0; try < 5; try++) { |
| 529 | /* Load the send data into the aux channel data registers */ |
| 530 | for (i = 0; i < send_bytes; i += 4) |
| 531 | I915_WRITE(ch_data + i, |
| 532 | pack_aux(send + i, send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 533 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 534 | /* Send the command and wait for it to complete */ |
Damien Lespiau | 5ed12a1 | 2014-01-20 15:52:30 +0000 | [diff] [blame] | 535 | I915_WRITE(ch_ctl, send_ctl); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 536 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 537 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 538 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 539 | /* Clear done status and any errors */ |
| 540 | I915_WRITE(ch_ctl, |
| 541 | status | |
| 542 | DP_AUX_CH_CTL_DONE | |
| 543 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 544 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 545 | |
Chris Wilson | bc86625 | 2013-07-21 16:00:03 +0100 | [diff] [blame] | 546 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 547 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 548 | continue; |
| 549 | if (status & DP_AUX_CH_CTL_DONE) |
| 550 | break; |
| 551 | } |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 552 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 553 | break; |
| 554 | } |
| 555 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 556 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 557 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 558 | ret = -EBUSY; |
| 559 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 560 | } |
| 561 | |
| 562 | /* Check for timeout or receive error. |
| 563 | * Timeouts occur when the sink is not connected |
| 564 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 565 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 566 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 567 | ret = -EIO; |
| 568 | goto out; |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 569 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 570 | |
| 571 | /* Timeouts occur when the device isn't connected, so they're |
| 572 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 573 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 574 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 575 | ret = -ETIMEDOUT; |
| 576 | goto out; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 577 | } |
| 578 | |
| 579 | /* Unload any bytes sent back from the other side */ |
| 580 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 581 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 582 | if (recv_bytes > recv_size) |
| 583 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 584 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 585 | for (i = 0; i < recv_bytes; i += 4) |
| 586 | unpack_aux(I915_READ(ch_data + i), |
| 587 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 588 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 589 | ret = recv_bytes; |
| 590 | out: |
| 591 | pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 592 | intel_aux_display_runtime_put(dev_priv); |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 593 | |
Jani Nikula | 884f19e | 2014-03-14 16:51:14 +0200 | [diff] [blame] | 594 | if (vdd) |
| 595 | edp_panel_vdd_off(intel_dp, false); |
| 596 | |
Daniel Vetter | 9ee32fea | 2012-12-01 13:53:48 +0100 | [diff] [blame] | 597 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 598 | } |
| 599 | |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 600 | #define BARE_ADDRESS_SIZE 3 |
| 601 | #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 602 | static ssize_t |
| 603 | intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 604 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 605 | struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); |
| 606 | uint8_t txbuf[20], rxbuf[20]; |
| 607 | size_t txsize, rxsize; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 608 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 609 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 610 | txbuf[0] = msg->request << 4; |
| 611 | txbuf[1] = msg->address >> 8; |
| 612 | txbuf[2] = msg->address & 0xff; |
| 613 | txbuf[3] = msg->size - 1; |
Paulo Zanoni | 46a5ae9 | 2013-09-17 11:14:10 -0300 | [diff] [blame] | 614 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 615 | switch (msg->request & ~DP_AUX_I2C_MOT) { |
| 616 | case DP_AUX_NATIVE_WRITE: |
| 617 | case DP_AUX_I2C_WRITE: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 618 | txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 619 | rxsize = 1; |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 620 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 621 | if (WARN_ON(txsize > 20)) |
| 622 | return -E2BIG; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 623 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 624 | memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 625 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 626 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 627 | if (ret > 0) { |
| 628 | msg->reply = rxbuf[0] >> 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 629 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 630 | /* Return payload size. */ |
| 631 | ret = msg->size; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 632 | } |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 633 | break; |
| 634 | |
| 635 | case DP_AUX_NATIVE_READ: |
| 636 | case DP_AUX_I2C_READ: |
Jani Nikula | a6c8aff0 | 2014-04-07 12:37:25 +0300 | [diff] [blame] | 637 | txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 638 | rxsize = msg->size + 1; |
| 639 | |
| 640 | if (WARN_ON(rxsize > 20)) |
| 641 | return -E2BIG; |
| 642 | |
| 643 | ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize); |
| 644 | if (ret > 0) { |
| 645 | msg->reply = rxbuf[0] >> 4; |
| 646 | /* |
| 647 | * Assume happy day, and copy the data. The caller is |
| 648 | * expected to check msg->reply before touching it. |
| 649 | * |
| 650 | * Return payload size. |
| 651 | */ |
| 652 | ret--; |
| 653 | memcpy(msg->buffer, rxbuf + 1, ret); |
| 654 | } |
| 655 | break; |
| 656 | |
| 657 | default: |
| 658 | ret = -EINVAL; |
| 659 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 660 | } |
Jani Nikula | f51a44b | 2014-02-11 11:52:05 +0200 | [diff] [blame] | 661 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 662 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 663 | } |
| 664 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 665 | static void |
| 666 | intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 667 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 668 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 669 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 670 | enum port port = intel_dig_port->port; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 671 | const char *name = NULL; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 672 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 673 | |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 674 | switch (port) { |
| 675 | case PORT_A: |
| 676 | intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 677 | name = "DPDDC-A"; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 678 | break; |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 679 | case PORT_B: |
| 680 | intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 681 | name = "DPDDC-B"; |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 682 | break; |
| 683 | case PORT_C: |
| 684 | intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 685 | name = "DPDDC-C"; |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 686 | break; |
| 687 | case PORT_D: |
| 688 | intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 689 | name = "DPDDC-D"; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 690 | break; |
| 691 | default: |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 692 | BUG(); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 693 | } |
| 694 | |
Jani Nikula | 33ad662 | 2014-03-14 16:51:16 +0200 | [diff] [blame] | 695 | if (!HAS_DDI(dev)) |
| 696 | intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 697 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 698 | intel_dp->aux.name = name; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 699 | intel_dp->aux.dev = dev->dev; |
| 700 | intel_dp->aux.transfer = intel_dp_aux_transfer; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 701 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 702 | DRM_DEBUG_KMS("registering %s bus for %s\n", name, |
| 703 | connector->base.kdev->kobj.name); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 704 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 705 | ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux); |
| 706 | if (ret < 0) { |
| 707 | DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n", |
| 708 | name, ret); |
| 709 | return; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 710 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 711 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 712 | ret = sysfs_create_link(&connector->base.kdev->kobj, |
| 713 | &intel_dp->aux.ddc.dev.kobj, |
| 714 | intel_dp->aux.ddc.dev.kobj.name); |
| 715 | if (ret < 0) { |
| 716 | DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret); |
| 717 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 718 | } |
| 719 | } |
| 720 | |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 721 | static void |
| 722 | intel_dp_connector_unregister(struct intel_connector *intel_connector) |
| 723 | { |
| 724 | struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base); |
| 725 | |
| 726 | sysfs_remove_link(&intel_connector->base.kdev->kobj, |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 727 | intel_dp->aux.ddc.dev.kobj.name); |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 728 | intel_connector_unregister(intel_connector); |
| 729 | } |
| 730 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 731 | static void |
| 732 | intel_dp_set_clock(struct intel_encoder *encoder, |
| 733 | struct intel_crtc_config *pipe_config, int link_bw) |
| 734 | { |
| 735 | struct drm_device *dev = encoder->base.dev; |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 736 | const struct dp_link_dpll *divisor = NULL; |
| 737 | int i, count = 0; |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 738 | |
| 739 | if (IS_G4X(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 740 | divisor = gen4_dpll; |
| 741 | count = ARRAY_SIZE(gen4_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 742 | } else if (IS_HASWELL(dev)) { |
| 743 | /* Haswell has special-purpose DP DDI clocks. */ |
| 744 | } else if (HAS_PCH_SPLIT(dev)) { |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 745 | divisor = pch_dpll; |
| 746 | count = ARRAY_SIZE(pch_dpll); |
Chon Ming Lee | ef9348c | 2014-04-09 13:28:18 +0300 | [diff] [blame] | 747 | } else if (IS_CHERRYVIEW(dev)) { |
| 748 | divisor = chv_dpll; |
| 749 | count = ARRAY_SIZE(chv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 750 | } else if (IS_VALLEYVIEW(dev)) { |
Chon Ming Lee | 65ce4bf | 2013-09-04 01:30:38 +0800 | [diff] [blame] | 751 | divisor = vlv_dpll; |
| 752 | count = ARRAY_SIZE(vlv_dpll); |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 753 | } |
Chon Ming Lee | 9dd4ffd | 2013-09-04 01:30:37 +0800 | [diff] [blame] | 754 | |
| 755 | if (divisor && count) { |
| 756 | for (i = 0; i < count; i++) { |
| 757 | if (link_bw == divisor[i].link_bw) { |
| 758 | pipe_config->dpll = divisor[i].dpll; |
| 759 | pipe_config->clock_set = true; |
| 760 | break; |
| 761 | } |
| 762 | } |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 763 | } |
| 764 | } |
| 765 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 766 | static void |
| 767 | intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) |
| 768 | { |
| 769 | struct drm_device *dev = crtc->base.dev; |
| 770 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 771 | enum transcoder transcoder = crtc->config.cpu_transcoder; |
| 772 | |
| 773 | I915_WRITE(PIPE_DATA_M2(transcoder), |
| 774 | TU_SIZE(m_n->tu) | m_n->gmch_m); |
| 775 | I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); |
| 776 | I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); |
| 777 | I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); |
| 778 | } |
| 779 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 780 | bool |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 781 | intel_dp_compute_config(struct intel_encoder *encoder, |
| 782 | struct intel_crtc_config *pipe_config) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 783 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 784 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 785 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 786 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 787 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 788 | enum port port = dp_to_dig_port(intel_dp)->port; |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 789 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 790 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 791 | int lane_count, clock; |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 792 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 793 | /* Conveniently, the link BW constants become indices with a shift...*/ |
| 794 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 795 | int bpp, mode_rate; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 796 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 797 | int link_avail, link_clock; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 798 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 799 | if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A) |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 800 | pipe_config->has_pch_encoder = true; |
| 801 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 802 | pipe_config->has_dp_encoder = true; |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 803 | pipe_config->has_audio = intel_dp->has_audio; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 804 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 805 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 806 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 807 | adjusted_mode); |
Jesse Barnes | 2dd2455 | 2013-04-25 12:55:01 -0700 | [diff] [blame] | 808 | if (!HAS_PCH_SPLIT(dev)) |
| 809 | intel_gmch_panel_fitting(intel_crtc, pipe_config, |
| 810 | intel_connector->panel.fitting_mode); |
| 811 | else |
Jesse Barnes | b074cec | 2013-04-25 12:55:02 -0700 | [diff] [blame] | 812 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
| 813 | intel_connector->panel.fitting_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 814 | } |
| 815 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 816 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 817 | return false; |
| 818 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 819 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 820 | "max bw %02x pixel clock %iKHz\n", |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 821 | max_lane_count, bws[max_clock], |
| 822 | adjusted_mode->crtc_clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 823 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 824 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
| 825 | * bpc in between. */ |
Daniel Vetter | 3e7ca98 | 2013-06-01 19:45:56 +0200 | [diff] [blame] | 826 | bpp = pipe_config->pipe_bpp; |
Jani Nikula | 6da7f10 | 2013-10-16 17:06:17 +0300 | [diff] [blame] | 827 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 828 | dev_priv->vbt.edp_bpp < bpp) { |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 829 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
| 830 | dev_priv->vbt.edp_bpp); |
Jani Nikula | 6da7f10 | 2013-10-16 17:06:17 +0300 | [diff] [blame] | 831 | bpp = dev_priv->vbt.edp_bpp; |
Imre Deak | 7984211 | 2013-07-18 17:44:13 +0300 | [diff] [blame] | 832 | } |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 833 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 834 | for (; bpp >= 6*3; bpp -= 2*3) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 835 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
| 836 | bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 837 | |
Daniel Vetter | 38aecea | 2014-03-03 11:18:10 +0100 | [diff] [blame] | 838 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
| 839 | for (clock = 0; clock <= max_clock; clock++) { |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 840 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
| 841 | link_avail = intel_dp_max_data_rate(link_clock, |
| 842 | lane_count); |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 843 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 844 | if (mode_rate <= link_avail) { |
| 845 | goto found; |
| 846 | } |
| 847 | } |
| 848 | } |
| 849 | } |
| 850 | |
| 851 | return false; |
| 852 | |
| 853 | found: |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 854 | if (intel_dp->color_range_auto) { |
| 855 | /* |
| 856 | * See: |
| 857 | * CEA-861-E - 5.1 Default Encoding Parameters |
| 858 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
| 859 | */ |
Thierry Reding | 18316c8 | 2012-12-20 15:41:44 +0100 | [diff] [blame] | 860 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 861 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 862 | else |
| 863 | intel_dp->color_range = 0; |
| 864 | } |
| 865 | |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 866 | if (intel_dp->color_range) |
Daniel Vetter | 50f3b01 | 2013-03-27 00:44:56 +0100 | [diff] [blame] | 867 | pipe_config->limited_color_range = true; |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 868 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 869 | intel_dp->link_bw = bws[clock]; |
| 870 | intel_dp->lane_count = lane_count; |
Daniel Vetter | 657445f | 2013-05-04 10:09:18 +0200 | [diff] [blame] | 871 | pipe_config->pipe_bpp = bpp; |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 872 | pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 873 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 874 | DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n", |
| 875 | intel_dp->link_bw, intel_dp->lane_count, |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 876 | pipe_config->port_clock, bpp); |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 877 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 878 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 879 | |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 880 | intel_link_compute_m_n(bpp, lane_count, |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 881 | adjusted_mode->crtc_clock, |
| 882 | pipe_config->port_clock, |
Daniel Vetter | 03afc4a | 2013-04-02 23:42:31 +0200 | [diff] [blame] | 883 | &pipe_config->dp_m_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 884 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 885 | if (intel_connector->panel.downclock_mode != NULL && |
| 886 | intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { |
| 887 | intel_link_compute_m_n(bpp, lane_count, |
| 888 | intel_connector->panel.downclock_mode->clock, |
| 889 | pipe_config->port_clock, |
| 890 | &pipe_config->dp_m2_n2); |
| 891 | } |
| 892 | |
Daniel Vetter | c6bb353 | 2013-04-19 11:14:33 +0200 | [diff] [blame] | 893 | intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); |
| 894 | |
Daniel Vetter | 3600836 | 2013-03-27 00:44:59 +0100 | [diff] [blame] | 895 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 896 | } |
| 897 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 898 | static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp) |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 899 | { |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 900 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 901 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 902 | struct drm_device *dev = crtc->base.dev; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 903 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 904 | u32 dpa_ctl; |
| 905 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 906 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock); |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 907 | dpa_ctl = I915_READ(DP_A); |
| 908 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
| 909 | |
Daniel Vetter | ff9a675 | 2013-06-01 17:16:21 +0200 | [diff] [blame] | 910 | if (crtc->config.port_clock == 162000) { |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 911 | /* For a long time we've carried around a ILK-DevA w/a for the |
| 912 | * 160MHz clock. If we're really unlucky, it's still required. |
| 913 | */ |
| 914 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 915 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 916 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 917 | } else { |
| 918 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 919 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 920 | } |
Daniel Vetter | 1ce1703 | 2012-11-29 15:59:32 +0100 | [diff] [blame] | 921 | |
Daniel Vetter | ea9b600 | 2012-11-29 15:59:31 +0100 | [diff] [blame] | 922 | I915_WRITE(DP_A, dpa_ctl); |
| 923 | |
| 924 | POSTING_READ(DP_A); |
| 925 | udelay(500); |
| 926 | } |
| 927 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 928 | static void intel_dp_prepare(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 929 | { |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 930 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 931 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 932 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 933 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 934 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
| 935 | struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 936 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 937 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 938 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 939 | * |
| 940 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 941 | * SNB CPU |
| 942 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 943 | * CPT PCH |
| 944 | * |
| 945 | * IBX PCH and CPU are the same for almost everything, |
| 946 | * except that the CPU DP PLL is configured in this |
| 947 | * register |
| 948 | * |
| 949 | * CPT PCH is quite different, having many bits moved |
| 950 | * to the TRANS_DP_CTL register instead. That |
| 951 | * configuration happens (oddly) in ironlake_pch_enable |
| 952 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 953 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 954 | /* Preserve the BIOS-computed detected bit. This is |
| 955 | * supposed to be read-only. |
| 956 | */ |
| 957 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 958 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 959 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 960 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Daniel Vetter | 17aa6be | 2013-04-30 14:01:40 +0200 | [diff] [blame] | 961 | intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 962 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 963 | if (crtc->config.has_audio) { |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 964 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 965 | pipe_name(crtc->pipe)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 966 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Daniel Vetter | b934223d | 2013-07-21 21:37:05 +0200 | [diff] [blame] | 967 | intel_write_eld(&encoder->base, adjusted_mode); |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 968 | } |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 969 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 970 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 971 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 972 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 973 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 974 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 975 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 976 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 977 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 978 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 979 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 980 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 981 | |
Daniel Vetter | 7c62a16 | 2013-06-01 17:16:20 +0200 | [diff] [blame] | 982 | intel_dp->DP |= crtc->pipe << 29; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 983 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 984 | if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev)) |
Ville Syrjälä | 3685a8f | 2013-01-17 16:31:28 +0200 | [diff] [blame] | 985 | intel_dp->DP |= intel_dp->color_range; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 986 | |
| 987 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 988 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 989 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 990 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 991 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 992 | |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 993 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 994 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 995 | |
Chon Ming Lee | 44f37d1 | 2014-04-09 13:28:21 +0300 | [diff] [blame] | 996 | if (!IS_CHERRYVIEW(dev)) { |
| 997 | if (crtc->pipe == 1) |
| 998 | intel_dp->DP |= DP_PIPEB_SELECT; |
| 999 | } else { |
| 1000 | intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe); |
| 1001 | } |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1002 | } else { |
| 1003 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1004 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1005 | } |
| 1006 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1007 | #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 1008 | #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1009 | |
Paulo Zanoni | 1a5ef5b | 2013-12-19 14:29:43 -0200 | [diff] [blame] | 1010 | #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) |
| 1011 | #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1012 | |
Paulo Zanoni | ffd6749d | 2013-12-19 14:29:42 -0200 | [diff] [blame] | 1013 | #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 1014 | #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1015 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1016 | static void wait_panel_status(struct intel_dp *intel_dp, |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1017 | u32 mask, |
| 1018 | u32 value) |
| 1019 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1020 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1021 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1022 | u32 pp_stat_reg, pp_ctrl_reg; |
| 1023 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1024 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1025 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1026 | |
| 1027 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1028 | mask, value, |
| 1029 | I915_READ(pp_stat_reg), |
| 1030 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1031 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1032 | if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1033 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1034 | I915_READ(pp_stat_reg), |
| 1035 | I915_READ(pp_ctrl_reg)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1036 | } |
Chris Wilson | 54c136d | 2013-12-02 09:57:16 +0000 | [diff] [blame] | 1037 | |
| 1038 | DRM_DEBUG_KMS("Wait complete\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1039 | } |
| 1040 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1041 | static void wait_panel_on(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1042 | { |
| 1043 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1044 | wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1045 | } |
| 1046 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1047 | static void wait_panel_off(struct intel_dp *intel_dp) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1048 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1049 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1050 | wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1051 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1052 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1053 | static void wait_panel_power_cycle(struct intel_dp *intel_dp) |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1054 | { |
| 1055 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1056 | |
| 1057 | /* When we disable the VDD override bit last we have to do the manual |
| 1058 | * wait. */ |
| 1059 | wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle, |
| 1060 | intel_dp->panel_power_cycle_delay); |
| 1061 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1062 | wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1063 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1064 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1065 | static void wait_backlight_on(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1066 | { |
| 1067 | wait_remaining_ms_from_jiffies(intel_dp->last_power_on, |
| 1068 | intel_dp->backlight_on_delay); |
| 1069 | } |
| 1070 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1071 | static void edp_wait_backlight_off(struct intel_dp *intel_dp) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1072 | { |
| 1073 | wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, |
| 1074 | intel_dp->backlight_off_delay); |
| 1075 | } |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1076 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1077 | /* Read the current pp_control value, unlocking the register if it |
| 1078 | * is locked |
| 1079 | */ |
| 1080 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1081 | static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1082 | { |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1083 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1084 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1085 | u32 control; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1086 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1087 | control = I915_READ(_pp_ctrl_reg(intel_dp)); |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1088 | control &= ~PANEL_UNLOCK_MASK; |
| 1089 | control |= PANEL_UNLOCK_REGS; |
| 1090 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1091 | } |
| 1092 | |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1093 | static bool _edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1094 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1095 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1096 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1097 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1098 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1099 | enum intel_display_power_domain power_domain; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1100 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1101 | u32 pp_stat_reg, pp_ctrl_reg; |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1102 | bool need_to_disable = !intel_dp->want_panel_vdd; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1103 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1104 | if (!is_edp(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1105 | return false; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1106 | |
| 1107 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1108 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1109 | if (edp_have_panel_vdd(intel_dp)) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1110 | return need_to_disable; |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1111 | |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1112 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1113 | intel_display_power_get(dev_priv, power_domain); |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1114 | |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1115 | DRM_DEBUG_KMS("Turning eDP VDD on\n"); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1116 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1117 | if (!edp_have_panel_power(intel_dp)) |
| 1118 | wait_panel_power_cycle(intel_dp); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1119 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1120 | pp = ironlake_get_pp_control(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1121 | pp |= EDP_FORCE_VDD; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1122 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1123 | pp_stat_reg = _pp_stat_reg(intel_dp); |
| 1124 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1125 | |
| 1126 | I915_WRITE(pp_ctrl_reg, pp); |
| 1127 | POSTING_READ(pp_ctrl_reg); |
| 1128 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1129 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1130 | /* |
| 1131 | * If the panel wasn't on, delay before accessing aux channel |
| 1132 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1133 | if (!edp_have_panel_power(intel_dp)) { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1134 | DRM_DEBUG_KMS("eDP was not running\n"); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1135 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1136 | } |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1137 | |
| 1138 | return need_to_disable; |
| 1139 | } |
| 1140 | |
Daniel Vetter | b80d6c7 | 2014-03-19 15:54:37 +0100 | [diff] [blame] | 1141 | void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) |
Jani Nikula | adddaaf | 2014-03-14 16:51:13 +0200 | [diff] [blame] | 1142 | { |
| 1143 | if (is_edp(intel_dp)) { |
| 1144 | bool vdd = _edp_panel_vdd_on(intel_dp); |
| 1145 | |
| 1146 | WARN(!vdd, "eDP VDD already requested on\n"); |
| 1147 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1148 | } |
| 1149 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1150 | static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1151 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1152 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1153 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1154 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1155 | u32 pp_stat_reg, pp_ctrl_reg; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1156 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1157 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
| 1158 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1159 | if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1160 | struct intel_digital_port *intel_dig_port = |
| 1161 | dp_to_dig_port(intel_dp); |
| 1162 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 1163 | enum intel_display_power_domain power_domain; |
| 1164 | |
Paulo Zanoni | b0665d5 | 2013-10-30 19:50:27 -0200 | [diff] [blame] | 1165 | DRM_DEBUG_KMS("Turning eDP VDD off\n"); |
| 1166 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1167 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1168 | pp &= ~EDP_FORCE_VDD; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1169 | |
Paulo Zanoni | 9f08ef5 | 2013-10-31 12:44:21 -0200 | [diff] [blame] | 1170 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
| 1171 | pp_stat_reg = _pp_stat_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1172 | |
| 1173 | I915_WRITE(pp_ctrl_reg, pp); |
| 1174 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1175 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1176 | /* Make sure sequencer is idle before allowing subsequent activity */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1177 | DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", |
| 1178 | I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); |
Paulo Zanoni | 90791a5 | 2013-12-06 17:32:42 -0200 | [diff] [blame] | 1179 | |
| 1180 | if ((pp & POWER_TARGET_ON) == 0) |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1181 | intel_dp->last_power_cycle = jiffies; |
Paulo Zanoni | e9cb81a | 2013-11-21 13:47:23 -0200 | [diff] [blame] | 1182 | |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1183 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1184 | intel_display_power_put(dev_priv, power_domain); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1185 | } |
| 1186 | } |
| 1187 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1188 | static void edp_panel_vdd_work(struct work_struct *__work) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1189 | { |
| 1190 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1191 | struct intel_dp, panel_vdd_work); |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1192 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1193 | |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1194 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1195 | edp_panel_vdd_off_sync(intel_dp); |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1196 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1197 | } |
| 1198 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1199 | static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1200 | { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1201 | if (!is_edp(intel_dp)) |
| 1202 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1203 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1204 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1205 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1206 | intel_dp->want_panel_vdd = false; |
| 1207 | |
| 1208 | if (sync) { |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1209 | edp_panel_vdd_off_sync(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1210 | } else { |
| 1211 | /* |
| 1212 | * Queue the timer to fire a long |
| 1213 | * time from now (relative to the power down delay) |
| 1214 | * to keep the panel power up across a sequence of operations |
| 1215 | */ |
| 1216 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
| 1217 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
| 1218 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1219 | } |
| 1220 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1221 | void intel_edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1222 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1223 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1224 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1225 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1226 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1227 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1228 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1229 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1230 | |
| 1231 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
| 1232 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1233 | if (edp_have_panel_power(intel_dp)) { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1234 | DRM_DEBUG_KMS("eDP power already on\n"); |
Keith Packard | 7d639f3 | 2011-09-29 16:05:34 -0700 | [diff] [blame] | 1235 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1236 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1237 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1238 | wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1239 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1240 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1241 | pp = ironlake_get_pp_control(intel_dp); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1242 | if (IS_GEN5(dev)) { |
| 1243 | /* ILK workaround: disable reset around power sequence */ |
| 1244 | pp &= ~PANEL_POWER_RESET; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1245 | I915_WRITE(pp_ctrl_reg, pp); |
| 1246 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1247 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1248 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1249 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1250 | if (!IS_GEN5(dev)) |
| 1251 | pp |= PANEL_POWER_RESET; |
| 1252 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1253 | I915_WRITE(pp_ctrl_reg, pp); |
| 1254 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1255 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1256 | wait_panel_on(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1257 | intel_dp->last_power_on = jiffies; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1258 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1259 | if (IS_GEN5(dev)) { |
| 1260 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1261 | I915_WRITE(pp_ctrl_reg, pp); |
| 1262 | POSTING_READ(pp_ctrl_reg); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1263 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1264 | } |
| 1265 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1266 | void intel_edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1267 | { |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1268 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1269 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1270 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1271 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1272 | enum intel_display_power_domain power_domain; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1273 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1274 | u32 pp_ctrl_reg; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1275 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1276 | if (!is_edp(intel_dp)) |
| 1277 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1278 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1279 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1280 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1281 | edp_wait_backlight_off(intel_dp); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1282 | |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 1283 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
| 1284 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1285 | pp = ironlake_get_pp_control(intel_dp); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1286 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 1287 | * panels get very unhappy and cease to work. */ |
Patrik Jakobsson | b306415 | 2014-03-04 00:42:44 +0100 | [diff] [blame] | 1288 | pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | |
| 1289 | EDP_BLC_ENABLE); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1290 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1291 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1292 | |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 1293 | intel_dp->want_panel_vdd = false; |
| 1294 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1295 | I915_WRITE(pp_ctrl_reg, pp); |
| 1296 | POSTING_READ(pp_ctrl_reg); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1297 | |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1298 | intel_dp->last_power_cycle = jiffies; |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1299 | wait_panel_off(intel_dp); |
Paulo Zanoni | 849e39f | 2014-03-07 20:05:20 -0300 | [diff] [blame] | 1300 | |
| 1301 | /* We got a reference when we enabled the VDD. */ |
Imre Deak | 4e6e1a5 | 2014-03-27 17:45:11 +0200 | [diff] [blame] | 1302 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 1303 | intel_display_power_put(dev_priv, power_domain); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1304 | } |
| 1305 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1306 | void intel_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1307 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1308 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1309 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1310 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1311 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1312 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1313 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1314 | if (!is_edp(intel_dp)) |
| 1315 | return; |
| 1316 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1317 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1318 | /* |
| 1319 | * If we enable the backlight right away following a panel power |
| 1320 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1321 | * link. So delay a bit to make sure the image is solid before |
| 1322 | * allowing it to appear. |
| 1323 | */ |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1324 | wait_backlight_on(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1325 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1326 | pp |= EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1327 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1328 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1329 | |
| 1330 | I915_WRITE(pp_ctrl_reg, pp); |
| 1331 | POSTING_READ(pp_ctrl_reg); |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1332 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1333 | intel_panel_enable_backlight(intel_dp->attached_connector); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1334 | } |
| 1335 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1336 | void intel_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1337 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 1338 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1339 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1340 | u32 pp; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1341 | u32 pp_ctrl_reg; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1342 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1343 | if (!is_edp(intel_dp)) |
| 1344 | return; |
| 1345 | |
Jesse Barnes | 752aa88 | 2013-10-31 18:55:49 +0200 | [diff] [blame] | 1346 | intel_panel_disable_backlight(intel_dp->attached_connector); |
Daniel Vetter | 035aa3d | 2012-10-20 20:57:42 +0200 | [diff] [blame] | 1347 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1348 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1349 | pp = ironlake_get_pp_control(intel_dp); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1350 | pp &= ~EDP_BLC_ENABLE; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1351 | |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1352 | pp_ctrl_reg = _pp_ctrl_reg(intel_dp); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 1353 | |
| 1354 | I915_WRITE(pp_ctrl_reg, pp); |
| 1355 | POSTING_READ(pp_ctrl_reg); |
Paulo Zanoni | dce56b3 | 2013-12-19 14:29:40 -0200 | [diff] [blame] | 1356 | intel_dp->last_backlight_off = jiffies; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1357 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1358 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1359 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1360 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1361 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1362 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1363 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1364 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1365 | u32 dpa_ctl; |
| 1366 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1367 | assert_pipe_disabled(dev_priv, |
| 1368 | to_intel_crtc(crtc)->pipe); |
| 1369 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1370 | DRM_DEBUG_KMS("\n"); |
| 1371 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1372 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
| 1373 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1374 | |
| 1375 | /* We don't adjust intel_dp->DP while tearing down the link, to |
| 1376 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
| 1377 | * enable bits here to ensure that we don't enable too much. */ |
| 1378 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 1379 | intel_dp->DP |= DP_PLL_ENABLE; |
| 1380 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1381 | POSTING_READ(DP_A); |
| 1382 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1383 | } |
| 1384 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1385 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1386 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 1387 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 1388 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
| 1389 | struct drm_device *dev = crtc->dev; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1390 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1391 | u32 dpa_ctl; |
| 1392 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1393 | assert_pipe_disabled(dev_priv, |
| 1394 | to_intel_crtc(crtc)->pipe); |
| 1395 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1396 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1397 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
| 1398 | "dp pll off, should be on\n"); |
| 1399 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1400 | |
| 1401 | /* We can't rely on the value tracked for the DP register in |
| 1402 | * intel_dp->DP because link_down must not change that (otherwise link |
| 1403 | * re-training will fail. */ |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1404 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1405 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 1406 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1407 | udelay(200); |
| 1408 | } |
| 1409 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1410 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1411 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1412 | { |
| 1413 | int ret, i; |
| 1414 | |
| 1415 | /* Should have a valid DPCD by this point */ |
| 1416 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1417 | return; |
| 1418 | |
| 1419 | if (mode != DRM_MODE_DPMS_ON) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1420 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 1421 | DP_SET_POWER_D3); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1422 | if (ret != 1) |
| 1423 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 1424 | } else { |
| 1425 | /* |
| 1426 | * When turning on, we need to retry for 1ms to give the sink |
| 1427 | * time to wake up. |
| 1428 | */ |
| 1429 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1430 | ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, |
| 1431 | DP_SET_POWER_D0); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1432 | if (ret == 1) |
| 1433 | break; |
| 1434 | msleep(1); |
| 1435 | } |
| 1436 | } |
| 1437 | } |
| 1438 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1439 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 1440 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1441 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1442 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1443 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1444 | struct drm_device *dev = encoder->base.dev; |
| 1445 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 1446 | enum intel_display_power_domain power_domain; |
| 1447 | u32 tmp; |
| 1448 | |
| 1449 | power_domain = intel_display_port_power_domain(encoder); |
| 1450 | if (!intel_display_power_enabled(dev_priv, power_domain)) |
| 1451 | return false; |
| 1452 | |
| 1453 | tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1454 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1455 | if (!(tmp & DP_PORT_EN)) |
| 1456 | return false; |
| 1457 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1458 | if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1459 | *pipe = PORT_TO_PIPE_CPT(tmp); |
Ville Syrjälä | 71485e0 | 2014-04-09 13:28:55 +0300 | [diff] [blame] | 1460 | } else if (IS_CHERRYVIEW(dev)) { |
| 1461 | *pipe = DP_PORT_TO_PIPE_CHV(tmp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1462 | } else if (!HAS_PCH_CPT(dev) || port == PORT_A) { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1463 | *pipe = PORT_TO_PIPE(tmp); |
| 1464 | } else { |
| 1465 | u32 trans_sel; |
| 1466 | u32 trans_dp; |
| 1467 | int i; |
| 1468 | |
| 1469 | switch (intel_dp->output_reg) { |
| 1470 | case PCH_DP_B: |
| 1471 | trans_sel = TRANS_DP_PORT_SEL_B; |
| 1472 | break; |
| 1473 | case PCH_DP_C: |
| 1474 | trans_sel = TRANS_DP_PORT_SEL_C; |
| 1475 | break; |
| 1476 | case PCH_DP_D: |
| 1477 | trans_sel = TRANS_DP_PORT_SEL_D; |
| 1478 | break; |
| 1479 | default: |
| 1480 | return true; |
| 1481 | } |
| 1482 | |
| 1483 | for_each_pipe(i) { |
| 1484 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
| 1485 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
| 1486 | *pipe = i; |
| 1487 | return true; |
| 1488 | } |
| 1489 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1490 | |
Daniel Vetter | 4a0833e | 2012-10-26 10:58:11 +0200 | [diff] [blame] | 1491 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
| 1492 | intel_dp->output_reg); |
| 1493 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1494 | |
| 1495 | return true; |
| 1496 | } |
| 1497 | |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1498 | static void intel_dp_get_config(struct intel_encoder *encoder, |
| 1499 | struct intel_crtc_config *pipe_config) |
| 1500 | { |
| 1501 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1502 | u32 tmp, flags = 0; |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1503 | struct drm_device *dev = encoder->base.dev; |
| 1504 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1505 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1506 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1507 | int dotclock; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1508 | |
Daniel Vetter | 9ed109a | 2014-04-24 23:54:52 +0200 | [diff] [blame] | 1509 | tmp = I915_READ(intel_dp->output_reg); |
| 1510 | if (tmp & DP_AUDIO_OUTPUT_ENABLE) |
| 1511 | pipe_config->has_audio = true; |
| 1512 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1513 | if ((port == PORT_A) || !HAS_PCH_CPT(dev)) { |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1514 | if (tmp & DP_SYNC_HS_HIGH) |
| 1515 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1516 | else |
| 1517 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1518 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1519 | if (tmp & DP_SYNC_VS_HIGH) |
| 1520 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1521 | else |
| 1522 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1523 | } else { |
| 1524 | tmp = I915_READ(TRANS_DP_CTL(crtc->pipe)); |
| 1525 | if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH) |
| 1526 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 1527 | else |
| 1528 | flags |= DRM_MODE_FLAG_NHSYNC; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1529 | |
Xiong Zhang | 63000ef | 2013-06-28 12:59:06 +0800 | [diff] [blame] | 1530 | if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH) |
| 1531 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 1532 | else |
| 1533 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 1534 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1535 | |
| 1536 | pipe_config->adjusted_mode.flags |= flags; |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 1537 | |
Ville Syrjälä | eb14cb7 | 2013-09-10 17:02:54 +0300 | [diff] [blame] | 1538 | pipe_config->has_dp_encoder = true; |
| 1539 | |
| 1540 | intel_dp_get_m_n(crtc, pipe_config); |
| 1541 | |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1542 | if (port == PORT_A) { |
Jesse Barnes | f1f644d | 2013-06-27 00:39:25 +0300 | [diff] [blame] | 1543 | if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ) |
| 1544 | pipe_config->port_clock = 162000; |
| 1545 | else |
| 1546 | pipe_config->port_clock = 270000; |
| 1547 | } |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 1548 | |
| 1549 | dotclock = intel_dotclock_calculate(pipe_config->port_clock, |
| 1550 | &pipe_config->dp_m_n); |
| 1551 | |
| 1552 | if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A) |
| 1553 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
| 1554 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1555 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
Daniel Vetter | 7f16e5c | 2013-11-04 16:28:47 +0100 | [diff] [blame] | 1556 | |
Jani Nikula | c6cd2ee | 2013-10-21 10:52:07 +0300 | [diff] [blame] | 1557 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && |
| 1558 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { |
| 1559 | /* |
| 1560 | * This is a big fat ugly hack. |
| 1561 | * |
| 1562 | * Some machines in UEFI boot mode provide us a VBT that has 18 |
| 1563 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons |
| 1564 | * unknown we fail to light up. Yet the same BIOS boots up with |
| 1565 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as |
| 1566 | * max, not what it tells us to use. |
| 1567 | * |
| 1568 | * Note: This will still be broken if the eDP panel is not lit |
| 1569 | * up by the BIOS, and thus we can't get the mode at module |
| 1570 | * load. |
| 1571 | */ |
| 1572 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", |
| 1573 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); |
| 1574 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; |
| 1575 | } |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 1576 | } |
| 1577 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1578 | static bool is_edp_psr(struct drm_device *dev) |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 1579 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1580 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1581 | |
| 1582 | return dev_priv->psr.sink_support; |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 1583 | } |
| 1584 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1585 | static bool intel_edp_is_psr_enabled(struct drm_device *dev) |
| 1586 | { |
| 1587 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1588 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1589 | if (!HAS_PSR(dev)) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1590 | return false; |
| 1591 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1592 | return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1593 | } |
| 1594 | |
| 1595 | static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp, |
| 1596 | struct edp_vsc_psr *vsc_psr) |
| 1597 | { |
| 1598 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1599 | struct drm_device *dev = dig_port->base.base.dev; |
| 1600 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1601 | struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); |
| 1602 | u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder); |
| 1603 | u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder); |
| 1604 | uint32_t *data = (uint32_t *) vsc_psr; |
| 1605 | unsigned int i; |
| 1606 | |
| 1607 | /* As per BSPec (Pipe Video Data Island Packet), we need to disable |
| 1608 | the video DIP being updated before program video DIP data buffer |
| 1609 | registers for DIP being updated. */ |
| 1610 | I915_WRITE(ctl_reg, 0); |
| 1611 | POSTING_READ(ctl_reg); |
| 1612 | |
| 1613 | for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) { |
| 1614 | if (i < sizeof(struct edp_vsc_psr)) |
| 1615 | I915_WRITE(data_reg + i, *data++); |
| 1616 | else |
| 1617 | I915_WRITE(data_reg + i, 0); |
| 1618 | } |
| 1619 | |
| 1620 | I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW); |
| 1621 | POSTING_READ(ctl_reg); |
| 1622 | } |
| 1623 | |
| 1624 | static void intel_edp_psr_setup(struct intel_dp *intel_dp) |
| 1625 | { |
| 1626 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1627 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1628 | struct edp_vsc_psr psr_vsc; |
| 1629 | |
| 1630 | if (intel_dp->psr_setup_done) |
| 1631 | return; |
| 1632 | |
| 1633 | /* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */ |
| 1634 | memset(&psr_vsc, 0, sizeof(psr_vsc)); |
| 1635 | psr_vsc.sdp_header.HB0 = 0; |
| 1636 | psr_vsc.sdp_header.HB1 = 0x7; |
| 1637 | psr_vsc.sdp_header.HB2 = 0x2; |
| 1638 | psr_vsc.sdp_header.HB3 = 0x8; |
| 1639 | intel_edp_psr_write_vsc(intel_dp, &psr_vsc); |
| 1640 | |
| 1641 | /* Avoid continuous PSR exit by masking memup and hpd */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1642 | I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP | |
Rodrigo Vivi | 0cc4b69 | 2013-10-03 13:31:26 -0300 | [diff] [blame] | 1643 | EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1644 | |
| 1645 | intel_dp->psr_setup_done = true; |
| 1646 | } |
| 1647 | |
| 1648 | static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp) |
| 1649 | { |
| 1650 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1651 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 1652 | uint32_t aux_clock_divider; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1653 | int precharge = 0x3; |
| 1654 | int msg_size = 5; /* Header(4) + Message(1) */ |
| 1655 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 1656 | aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); |
| 1657 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1658 | /* Enable PSR in sink */ |
| 1659 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1660 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
| 1661 | DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1662 | else |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 1663 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, |
| 1664 | DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1665 | |
| 1666 | /* Setup AUX registers */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1667 | I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND); |
| 1668 | I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION); |
| 1669 | I915_WRITE(EDP_PSR_AUX_CTL(dev), |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1670 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 1671 | (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 1672 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 1673 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT)); |
| 1674 | } |
| 1675 | |
| 1676 | static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) |
| 1677 | { |
| 1678 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1679 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1680 | uint32_t max_sleep_time = 0x1f; |
| 1681 | uint32_t idle_frames = 1; |
| 1682 | uint32_t val = 0x0; |
Ben Widawsky | ed8546a | 2013-11-04 22:45:05 -0800 | [diff] [blame] | 1683 | const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1684 | |
| 1685 | if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { |
| 1686 | val |= EDP_PSR_LINK_STANDBY; |
| 1687 | val |= EDP_PSR_TP2_TP3_TIME_0us; |
| 1688 | val |= EDP_PSR_TP1_TIME_0us; |
| 1689 | val |= EDP_PSR_SKIP_AUX_EXIT; |
| 1690 | } else |
| 1691 | val |= EDP_PSR_LINK_DISABLE; |
| 1692 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1693 | I915_WRITE(EDP_PSR_CTL(dev), val | |
Ben Widawsky | 24bd9bf | 2014-03-04 22:38:10 -0800 | [diff] [blame] | 1694 | (IS_BROADWELL(dev) ? 0 : link_entry_time) | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1695 | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | |
| 1696 | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | |
| 1697 | EDP_PSR_ENABLE); |
| 1698 | } |
| 1699 | |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1700 | static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp) |
| 1701 | { |
| 1702 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 1703 | struct drm_device *dev = dig_port->base.base.dev; |
| 1704 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1705 | struct drm_crtc *crtc = dig_port->base.base.crtc; |
| 1706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1707 | struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1708 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
| 1709 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1710 | dev_priv->psr.source_ok = false; |
| 1711 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1712 | if (!HAS_PSR(dev)) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1713 | DRM_DEBUG_KMS("PSR not supported on this platform\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1714 | return false; |
| 1715 | } |
| 1716 | |
| 1717 | if ((intel_encoder->type != INTEL_OUTPUT_EDP) || |
| 1718 | (dig_port->port != PORT_A)) { |
| 1719 | DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1720 | return false; |
| 1721 | } |
| 1722 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 1723 | if (!i915.enable_psr) { |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1724 | DRM_DEBUG_KMS("PSR disable by flag\n"); |
Rodrigo Vivi | 105b7c1 | 2013-07-11 18:45:02 -0300 | [diff] [blame] | 1725 | return false; |
| 1726 | } |
| 1727 | |
Chris Wilson | cd234b0 | 2013-08-02 20:39:49 +0100 | [diff] [blame] | 1728 | crtc = dig_port->base.base.crtc; |
| 1729 | if (crtc == NULL) { |
| 1730 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
Chris Wilson | cd234b0 | 2013-08-02 20:39:49 +0100 | [diff] [blame] | 1731 | return false; |
| 1732 | } |
| 1733 | |
| 1734 | intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 20ddf66 | 2013-09-04 18:25:25 +0300 | [diff] [blame] | 1735 | if (!intel_crtc_active(crtc)) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1736 | DRM_DEBUG_KMS("crtc not active for PSR\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1737 | return false; |
| 1738 | } |
| 1739 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1740 | obj = to_intel_framebuffer(crtc->primary->fb)->obj; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1741 | if (obj->tiling_mode != I915_TILING_X || |
| 1742 | obj->fence_reg == I915_FENCE_REG_NONE) { |
| 1743 | DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1744 | return false; |
| 1745 | } |
| 1746 | |
| 1747 | if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) { |
| 1748 | DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1749 | return false; |
| 1750 | } |
| 1751 | |
| 1752 | if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) & |
| 1753 | S3D_ENABLE) { |
| 1754 | DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1755 | return false; |
| 1756 | } |
| 1757 | |
Ville Syrjälä | ca73b4f | 2013-09-04 18:25:24 +0300 | [diff] [blame] | 1758 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1759 | DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n"); |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1760 | return false; |
| 1761 | } |
| 1762 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1763 | dev_priv->psr.source_ok = true; |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1764 | return true; |
| 1765 | } |
| 1766 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1767 | static void intel_edp_psr_do_enable(struct intel_dp *intel_dp) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1768 | { |
| 1769 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1770 | |
Rodrigo Vivi | 3f51e47 | 2013-07-11 18:45:00 -0300 | [diff] [blame] | 1771 | if (!intel_edp_psr_match_conditions(intel_dp) || |
| 1772 | intel_edp_is_psr_enabled(dev)) |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1773 | return; |
| 1774 | |
| 1775 | /* Setup PSR once */ |
| 1776 | intel_edp_psr_setup(intel_dp); |
| 1777 | |
| 1778 | /* Enable PSR on the panel */ |
| 1779 | intel_edp_psr_enable_sink(intel_dp); |
| 1780 | |
| 1781 | /* Enable PSR on the host */ |
| 1782 | intel_edp_psr_enable_source(intel_dp); |
| 1783 | } |
| 1784 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1785 | void intel_edp_psr_enable(struct intel_dp *intel_dp) |
| 1786 | { |
| 1787 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1788 | |
| 1789 | if (intel_edp_psr_match_conditions(intel_dp) && |
| 1790 | !intel_edp_is_psr_enabled(dev)) |
| 1791 | intel_edp_psr_do_enable(intel_dp); |
| 1792 | } |
| 1793 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1794 | void intel_edp_psr_disable(struct intel_dp *intel_dp) |
| 1795 | { |
| 1796 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 1797 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1798 | |
| 1799 | if (!intel_edp_is_psr_enabled(dev)) |
| 1800 | return; |
| 1801 | |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1802 | I915_WRITE(EDP_PSR_CTL(dev), |
| 1803 | I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1804 | |
| 1805 | /* Wait till PSR is idle */ |
Ben Widawsky | 18b5992 | 2013-09-20 09:35:30 -0700 | [diff] [blame] | 1806 | if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 1807 | EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10)) |
| 1808 | DRM_ERROR("Timed out waiting for PSR Idle State\n"); |
| 1809 | } |
| 1810 | |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1811 | void intel_edp_psr_update(struct drm_device *dev) |
| 1812 | { |
| 1813 | struct intel_encoder *encoder; |
| 1814 | struct intel_dp *intel_dp = NULL; |
| 1815 | |
| 1816 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) |
| 1817 | if (encoder->type == INTEL_OUTPUT_EDP) { |
| 1818 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 1819 | |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 1820 | if (!is_edp_psr(dev)) |
Rodrigo Vivi | 3d739d9 | 2013-07-11 18:45:01 -0300 | [diff] [blame] | 1821 | return; |
| 1822 | |
| 1823 | if (!intel_edp_psr_match_conditions(intel_dp)) |
| 1824 | intel_edp_psr_disable(intel_dp); |
| 1825 | else |
| 1826 | if (!intel_edp_is_psr_enabled(dev)) |
| 1827 | intel_edp_psr_do_enable(intel_dp); |
| 1828 | } |
| 1829 | } |
| 1830 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1831 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1832 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1833 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1834 | enum port port = dp_to_dig_port(intel_dp)->port; |
| 1835 | struct drm_device *dev = encoder->base.dev; |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1836 | |
| 1837 | /* Make sure the panel is off before trying to change the mode. But also |
| 1838 | * ensure that we have vdd while we switch off the panel. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 1839 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1840 | intel_edp_backlight_off(intel_dp); |
Jani Nikula | fdbc3b1 | 2013-11-12 17:10:13 +0200 | [diff] [blame] | 1841 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1842 | intel_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1843 | |
| 1844 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1845 | if (!(port == PORT_A || IS_VALLEYVIEW(dev))) |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1846 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1847 | } |
| 1848 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 1849 | static void g4x_post_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1850 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1851 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | 982a386 | 2013-05-23 19:39:40 +0300 | [diff] [blame] | 1852 | enum port port = dp_to_dig_port(intel_dp)->port; |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1853 | |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 1854 | if (port != PORT_A) |
| 1855 | return; |
| 1856 | |
| 1857 | intel_dp_link_down(intel_dp); |
| 1858 | ironlake_edp_pll_off(intel_dp); |
| 1859 | } |
| 1860 | |
| 1861 | static void vlv_post_disable_dp(struct intel_encoder *encoder) |
| 1862 | { |
| 1863 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1864 | |
| 1865 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1866 | } |
| 1867 | |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame^] | 1868 | static void chv_post_disable_dp(struct intel_encoder *encoder) |
| 1869 | { |
| 1870 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1871 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 1872 | struct drm_device *dev = encoder->base.dev; |
| 1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1874 | struct intel_crtc *intel_crtc = |
| 1875 | to_intel_crtc(encoder->base.crtc); |
| 1876 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 1877 | enum pipe pipe = intel_crtc->pipe; |
| 1878 | u32 val; |
| 1879 | |
| 1880 | intel_dp_link_down(intel_dp); |
| 1881 | |
| 1882 | mutex_lock(&dev_priv->dpio_lock); |
| 1883 | |
| 1884 | /* Propagate soft reset to data lane reset */ |
| 1885 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch)); |
| 1886 | val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 1887 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val); |
| 1888 | |
| 1889 | mutex_unlock(&dev_priv->dpio_lock); |
| 1890 | } |
| 1891 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1892 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1893 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1894 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1895 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1896 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1897 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1898 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1899 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 1900 | return; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1901 | |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 1902 | intel_edp_panel_vdd_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1903 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
| 1904 | intel_dp_start_link_train(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1905 | intel_edp_panel_on(intel_dp); |
| 1906 | edp_panel_vdd_off(intel_dp, true); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1907 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 1908 | intel_dp_stop_link_train(intel_dp); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1909 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1910 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1911 | static void g4x_enable_dp(struct intel_encoder *encoder) |
| 1912 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 1913 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1914 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1915 | intel_enable_dp(encoder); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1916 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1917 | } |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1918 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1919 | static void vlv_enable_dp(struct intel_encoder *encoder) |
| 1920 | { |
Jani Nikula | 828f5c6 | 2013-09-05 16:44:45 +0300 | [diff] [blame] | 1921 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1922 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 1923 | intel_edp_backlight_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1924 | } |
| 1925 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1926 | static void g4x_pre_enable_dp(struct intel_encoder *encoder) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1927 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1928 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 1929 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1930 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 1931 | intel_dp_prepare(encoder); |
| 1932 | |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 1933 | /* Only ilk+ has port A */ |
| 1934 | if (dport->port == PORT_A) { |
| 1935 | ironlake_set_pll_cpu_edp(intel_dp); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1936 | ironlake_edp_pll_on(intel_dp); |
Daniel Vetter | d41f1ef | 2014-04-24 23:54:53 +0200 | [diff] [blame] | 1937 | } |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1938 | } |
| 1939 | |
| 1940 | static void vlv_pre_enable_dp(struct intel_encoder *encoder) |
| 1941 | { |
| 1942 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1943 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Jesse Barnes | b263401 | 2013-03-28 09:55:40 -0700 | [diff] [blame] | 1944 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1945 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1946 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1947 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1948 | int pipe = intel_crtc->pipe; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1949 | struct edp_power_seq power_seq; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1950 | u32 val; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1951 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1952 | mutex_lock(&dev_priv->dpio_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1953 | |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1954 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1955 | val = 0; |
| 1956 | if (pipe) |
| 1957 | val |= (1<<21); |
| 1958 | else |
| 1959 | val &= ~(1<<21); |
| 1960 | val |= 0x001000c4; |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1961 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); |
| 1962 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); |
| 1963 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1964 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1965 | mutex_unlock(&dev_priv->dpio_lock); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1966 | |
Imre Deak | 2cac613 | 2014-01-30 16:50:42 +0200 | [diff] [blame] | 1967 | if (is_edp(intel_dp)) { |
| 1968 | /* init power sequencer on this pipe and port */ |
| 1969 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 1970 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 1971 | &power_seq); |
| 1972 | } |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 1973 | |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 1974 | intel_enable_dp(encoder); |
| 1975 | |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1976 | vlv_wait_port_ready(dev_priv, dport); |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1977 | } |
| 1978 | |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 1979 | static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1980 | { |
| 1981 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
| 1982 | struct drm_device *dev = encoder->base.dev; |
| 1983 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1984 | struct intel_crtc *intel_crtc = |
| 1985 | to_intel_crtc(encoder->base.crtc); |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 1986 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 1987 | int pipe = intel_crtc->pipe; |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1988 | |
Daniel Vetter | 8ac33ed | 2014-04-24 23:54:54 +0200 | [diff] [blame] | 1989 | intel_dp_prepare(encoder); |
| 1990 | |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1991 | /* Program Tx lane resets to default */ |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 1992 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1993 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1994 | DPIO_PCS_TX_LANE2_RESET | |
| 1995 | DPIO_PCS_TX_LANE1_RESET); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 1996 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), |
Jesse Barnes | 89b667f | 2013-04-18 14:51:36 -0700 | [diff] [blame] | 1997 | DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | |
| 1998 | DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | |
| 1999 | (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | |
| 2000 | DPIO_PCS_CLK_SOFT_RESET); |
| 2001 | |
| 2002 | /* Fix up inter-pair skew failure */ |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2003 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); |
| 2004 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); |
| 2005 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2006 | mutex_unlock(&dev_priv->dpio_lock); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2007 | } |
| 2008 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2009 | static void chv_pre_enable_dp(struct intel_encoder *encoder) |
| 2010 | { |
| 2011 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 2012 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2013 | struct drm_device *dev = encoder->base.dev; |
| 2014 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2015 | struct edp_power_seq power_seq; |
| 2016 | struct intel_crtc *intel_crtc = |
| 2017 | to_intel_crtc(encoder->base.crtc); |
| 2018 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2019 | int pipe = intel_crtc->pipe; |
| 2020 | int data, i; |
Ville Syrjälä | 949c1d4 | 2014-04-09 13:28:58 +0300 | [diff] [blame] | 2021 | u32 val; |
| 2022 | |
| 2023 | mutex_lock(&dev_priv->dpio_lock); |
| 2024 | |
| 2025 | /* Deassert soft data lane reset*/ |
| 2026 | val = vlv_dpio_read(dev_priv, pipe, VLV_PCS_DW0(ch)); |
| 2027 | val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); |
| 2028 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(ch), val); |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2029 | |
| 2030 | /* Program Tx lane latency optimal setting*/ |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2031 | for (i = 0; i < 4; i++) { |
| 2032 | /* Set the latency optimal bit */ |
| 2033 | data = (i == 1) ? 0x0 : 0x6; |
| 2034 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i), |
| 2035 | data << DPIO_FRC_LATENCY_SHFIT); |
| 2036 | |
| 2037 | /* Set the upar bit */ |
| 2038 | data = (i == 1) ? 0x0 : 0x1; |
| 2039 | vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), |
| 2040 | data << DPIO_UPAR_SHIFT); |
| 2041 | } |
| 2042 | |
| 2043 | /* Data lane stagger programming */ |
| 2044 | /* FIXME: Fix up value only after power analysis */ |
| 2045 | |
| 2046 | mutex_unlock(&dev_priv->dpio_lock); |
| 2047 | |
| 2048 | if (is_edp(intel_dp)) { |
| 2049 | /* init power sequencer on this pipe and port */ |
| 2050 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
| 2051 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
| 2052 | &power_seq); |
| 2053 | } |
| 2054 | |
| 2055 | intel_enable_dp(encoder); |
| 2056 | |
| 2057 | vlv_wait_port_ready(dev_priv, dport); |
| 2058 | } |
| 2059 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2060 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2061 | * Native read with retry for link status and receiver capability reads for |
| 2062 | * cases where the sink may still be asleep. |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2063 | * |
| 2064 | * Sinks are *supposed* to come up within 1ms from an off state, but we're also |
| 2065 | * supposed to retry 3 times per the spec. |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2066 | */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2067 | static ssize_t |
| 2068 | intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset, |
| 2069 | void *buffer, size_t size) |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2070 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2071 | ssize_t ret; |
| 2072 | int i; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2073 | |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2074 | for (i = 0; i < 3; i++) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2075 | ret = drm_dp_dpcd_read(aux, offset, buffer, size); |
| 2076 | if (ret == size) |
| 2077 | return ret; |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 2078 | msleep(1); |
| 2079 | } |
| 2080 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2081 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2082 | } |
| 2083 | |
| 2084 | /* |
| 2085 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 2086 | * link status information |
| 2087 | */ |
| 2088 | static bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2089 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2090 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2091 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 2092 | DP_LANE0_1_STATUS, |
| 2093 | link_status, |
| 2094 | DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2095 | } |
| 2096 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2097 | /* |
| 2098 | * These are source-specific values; current Intel hardware supports |
| 2099 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 2100 | */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2101 | |
| 2102 | static uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2103 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2104 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2105 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2106 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2107 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2108 | if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev)) |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2109 | return DP_TRAIN_VOLTAGE_SWING_1200; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2110 | else if (IS_GEN7(dev) && port == PORT_A) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2111 | return DP_TRAIN_VOLTAGE_SWING_800; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2112 | else if (HAS_PCH_CPT(dev) && port != PORT_A) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2113 | return DP_TRAIN_VOLTAGE_SWING_1200; |
| 2114 | else |
| 2115 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 2116 | } |
| 2117 | |
| 2118 | static uint8_t |
| 2119 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 2120 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 2121 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2122 | enum port port = dp_to_dig_port(intel_dp)->port; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2123 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2124 | if (IS_BROADWELL(dev)) { |
| 2125 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2126 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2127 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2128 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2129 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2130 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2131 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2132 | default: |
| 2133 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2134 | } |
| 2135 | } else if (IS_HASWELL(dev)) { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2136 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2137 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2138 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 2139 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2140 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2141 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2142 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2143 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2144 | default: |
| 2145 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2146 | } |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2147 | } else if (IS_VALLEYVIEW(dev)) { |
| 2148 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2149 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2150 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 2151 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2152 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2153 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2154 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2155 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2156 | default: |
| 2157 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2158 | } |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2159 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2160 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2161 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2162 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2163 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2164 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2165 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2166 | default: |
| 2167 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2168 | } |
| 2169 | } else { |
| 2170 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2171 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2172 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2173 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2174 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 2175 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2176 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 2177 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2178 | default: |
| 2179 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 2180 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2181 | } |
| 2182 | } |
| 2183 | |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2184 | static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp) |
| 2185 | { |
| 2186 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2187 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2188 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2189 | struct intel_crtc *intel_crtc = |
| 2190 | to_intel_crtc(dport->base.base.crtc); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2191 | unsigned long demph_reg_value, preemph_reg_value, |
| 2192 | uniqtranscale_reg_value; |
| 2193 | uint8_t train_set = intel_dp->train_set[0]; |
Chon Ming Lee | e4607fc | 2013-11-06 14:36:35 +0800 | [diff] [blame] | 2194 | enum dpio_channel port = vlv_dport_to_channel(dport); |
Chon Ming Lee | 5e69f97 | 2013-09-05 20:41:49 +0800 | [diff] [blame] | 2195 | int pipe = intel_crtc->pipe; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2196 | |
| 2197 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 2198 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 2199 | preemph_reg_value = 0x0004000; |
| 2200 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2201 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2202 | demph_reg_value = 0x2B405555; |
| 2203 | uniqtranscale_reg_value = 0x552AB83A; |
| 2204 | break; |
| 2205 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2206 | demph_reg_value = 0x2B404040; |
| 2207 | uniqtranscale_reg_value = 0x5548B83A; |
| 2208 | break; |
| 2209 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2210 | demph_reg_value = 0x2B245555; |
| 2211 | uniqtranscale_reg_value = 0x5560B83A; |
| 2212 | break; |
| 2213 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2214 | demph_reg_value = 0x2B405555; |
| 2215 | uniqtranscale_reg_value = 0x5598DA3A; |
| 2216 | break; |
| 2217 | default: |
| 2218 | return 0; |
| 2219 | } |
| 2220 | break; |
| 2221 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2222 | preemph_reg_value = 0x0002000; |
| 2223 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2224 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2225 | demph_reg_value = 0x2B404040; |
| 2226 | uniqtranscale_reg_value = 0x5552B83A; |
| 2227 | break; |
| 2228 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2229 | demph_reg_value = 0x2B404848; |
| 2230 | uniqtranscale_reg_value = 0x5580B83A; |
| 2231 | break; |
| 2232 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2233 | demph_reg_value = 0x2B404040; |
| 2234 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2235 | break; |
| 2236 | default: |
| 2237 | return 0; |
| 2238 | } |
| 2239 | break; |
| 2240 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 2241 | preemph_reg_value = 0x0000000; |
| 2242 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2243 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2244 | demph_reg_value = 0x2B305555; |
| 2245 | uniqtranscale_reg_value = 0x5570B83A; |
| 2246 | break; |
| 2247 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2248 | demph_reg_value = 0x2B2B4040; |
| 2249 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2250 | break; |
| 2251 | default: |
| 2252 | return 0; |
| 2253 | } |
| 2254 | break; |
| 2255 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2256 | preemph_reg_value = 0x0006000; |
| 2257 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2258 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2259 | demph_reg_value = 0x1B405555; |
| 2260 | uniqtranscale_reg_value = 0x55ADDA3A; |
| 2261 | break; |
| 2262 | default: |
| 2263 | return 0; |
| 2264 | } |
| 2265 | break; |
| 2266 | default: |
| 2267 | return 0; |
| 2268 | } |
| 2269 | |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2270 | mutex_lock(&dev_priv->dpio_lock); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2271 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); |
| 2272 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); |
| 2273 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2274 | uniqtranscale_reg_value); |
Chon Ming Lee | ab3c759 | 2013-11-07 10:43:30 +0800 | [diff] [blame] | 2275 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); |
| 2276 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); |
| 2277 | vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); |
| 2278 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); |
Chris Wilson | 0980a60 | 2013-07-26 19:57:35 +0100 | [diff] [blame] | 2279 | mutex_unlock(&dev_priv->dpio_lock); |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2280 | |
| 2281 | return 0; |
| 2282 | } |
| 2283 | |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2284 | static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp) |
| 2285 | { |
| 2286 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
| 2287 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2288 | struct intel_digital_port *dport = dp_to_dig_port(intel_dp); |
| 2289 | struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc); |
| 2290 | u32 deemph_reg_value, margin_reg_value, val, tx_dw2; |
| 2291 | uint8_t train_set = intel_dp->train_set[0]; |
| 2292 | enum dpio_channel ch = vlv_dport_to_channel(dport); |
| 2293 | int pipe = intel_crtc->pipe; |
| 2294 | |
| 2295 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
| 2296 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 2297 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2298 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2299 | deemph_reg_value = 128; |
| 2300 | margin_reg_value = 52; |
| 2301 | break; |
| 2302 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2303 | deemph_reg_value = 128; |
| 2304 | margin_reg_value = 77; |
| 2305 | break; |
| 2306 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2307 | deemph_reg_value = 128; |
| 2308 | margin_reg_value = 102; |
| 2309 | break; |
| 2310 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2311 | deemph_reg_value = 128; |
| 2312 | margin_reg_value = 154; |
| 2313 | /* FIXME extra to set for 1200 */ |
| 2314 | break; |
| 2315 | default: |
| 2316 | return 0; |
| 2317 | } |
| 2318 | break; |
| 2319 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2320 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2321 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2322 | deemph_reg_value = 85; |
| 2323 | margin_reg_value = 78; |
| 2324 | break; |
| 2325 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2326 | deemph_reg_value = 85; |
| 2327 | margin_reg_value = 116; |
| 2328 | break; |
| 2329 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2330 | deemph_reg_value = 85; |
| 2331 | margin_reg_value = 154; |
| 2332 | break; |
| 2333 | default: |
| 2334 | return 0; |
| 2335 | } |
| 2336 | break; |
| 2337 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 2338 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2339 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2340 | deemph_reg_value = 64; |
| 2341 | margin_reg_value = 104; |
| 2342 | break; |
| 2343 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2344 | deemph_reg_value = 64; |
| 2345 | margin_reg_value = 154; |
| 2346 | break; |
| 2347 | default: |
| 2348 | return 0; |
| 2349 | } |
| 2350 | break; |
| 2351 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2352 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 2353 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2354 | deemph_reg_value = 43; |
| 2355 | margin_reg_value = 154; |
| 2356 | break; |
| 2357 | default: |
| 2358 | return 0; |
| 2359 | } |
| 2360 | break; |
| 2361 | default: |
| 2362 | return 0; |
| 2363 | } |
| 2364 | |
| 2365 | mutex_lock(&dev_priv->dpio_lock); |
| 2366 | |
| 2367 | /* Clear calc init */ |
| 2368 | vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), 0); |
| 2369 | |
| 2370 | /* Program swing deemph */ |
| 2371 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW4(ch)); |
| 2372 | val &= ~DPIO_SWING_DEEMPH9P5_MASK; |
| 2373 | val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; |
| 2374 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(ch), val); |
| 2375 | |
| 2376 | /* Program swing margin */ |
| 2377 | tx_dw2 = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)); |
| 2378 | tx_dw2 &= ~DPIO_SWING_MARGIN_MASK; |
| 2379 | tx_dw2 |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT; |
| 2380 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2); |
| 2381 | |
| 2382 | /* Disable unique transition scale */ |
| 2383 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); |
| 2384 | val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 2385 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); |
| 2386 | |
| 2387 | if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK) |
| 2388 | == DP_TRAIN_PRE_EMPHASIS_0) && |
| 2389 | ((train_set & DP_TRAIN_VOLTAGE_SWING_MASK) |
| 2390 | == DP_TRAIN_VOLTAGE_SWING_1200)) { |
| 2391 | |
| 2392 | /* |
| 2393 | * The document said it needs to set bit 27 for ch0 and bit 26 |
| 2394 | * for ch1. Might be a typo in the doc. |
| 2395 | * For now, for this unique transition scale selection, set bit |
| 2396 | * 27 for ch0 and ch1. |
| 2397 | */ |
| 2398 | val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch)); |
| 2399 | val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; |
| 2400 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val); |
| 2401 | |
| 2402 | tx_dw2 |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT); |
| 2403 | vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch), tx_dw2); |
| 2404 | } |
| 2405 | |
| 2406 | /* Start swing calculation */ |
| 2407 | vlv_dpio_write(dev_priv, pipe, CHV_PCS_DW10(ch), |
| 2408 | (DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3)); |
| 2409 | |
| 2410 | /* LRC Bypass */ |
| 2411 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); |
| 2412 | val |= DPIO_LRC_BYPASS; |
| 2413 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); |
| 2414 | |
| 2415 | mutex_unlock(&dev_priv->dpio_lock); |
| 2416 | |
| 2417 | return 0; |
| 2418 | } |
| 2419 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2420 | static void |
Jani Nikula | 0301b3a | 2013-10-15 09:36:08 +0300 | [diff] [blame] | 2421 | intel_get_adjust_train(struct intel_dp *intel_dp, |
| 2422 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2423 | { |
| 2424 | uint8_t v = 0; |
| 2425 | uint8_t p = 0; |
| 2426 | int lane; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2427 | uint8_t voltage_max; |
| 2428 | uint8_t preemph_max; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2429 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2430 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 2431 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 2432 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2433 | |
| 2434 | if (this_v > v) |
| 2435 | v = this_v; |
| 2436 | if (this_p > p) |
| 2437 | p = this_p; |
| 2438 | } |
| 2439 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2440 | voltage_max = intel_dp_voltage_max(intel_dp); |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2441 | if (v >= voltage_max) |
| 2442 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2443 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2444 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 2445 | if (p >= preemph_max) |
| 2446 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2447 | |
| 2448 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2449 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2450 | } |
| 2451 | |
| 2452 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2453 | intel_gen4_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2454 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2455 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2456 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2457 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2458 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 2459 | default: |
| 2460 | signal_levels |= DP_VOLTAGE_0_4; |
| 2461 | break; |
| 2462 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 2463 | signal_levels |= DP_VOLTAGE_0_6; |
| 2464 | break; |
| 2465 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 2466 | signal_levels |= DP_VOLTAGE_0_8; |
| 2467 | break; |
| 2468 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 2469 | signal_levels |= DP_VOLTAGE_1_2; |
| 2470 | break; |
| 2471 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2472 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2473 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 2474 | default: |
| 2475 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 2476 | break; |
| 2477 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2478 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 2479 | break; |
| 2480 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 2481 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 2482 | break; |
| 2483 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2484 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 2485 | break; |
| 2486 | } |
| 2487 | return signal_levels; |
| 2488 | } |
| 2489 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2490 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 2491 | static uint32_t |
| 2492 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 2493 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2494 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2495 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2496 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2497 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2498 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2499 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 2500 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2501 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2502 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2503 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2504 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2505 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2506 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2507 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2508 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2509 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2510 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2511 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 2512 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2513 | "0x%x\n", signal_levels); |
| 2514 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2515 | } |
| 2516 | } |
| 2517 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2518 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 2519 | static uint32_t |
| 2520 | intel_gen7_edp_signal_levels(uint8_t train_set) |
| 2521 | { |
| 2522 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2523 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2524 | switch (signal_levels) { |
| 2525 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2526 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 2527 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2528 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 2529 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2530 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 2531 | |
| 2532 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2533 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 2534 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2535 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 2536 | |
| 2537 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2538 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 2539 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2540 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 2541 | |
| 2542 | default: |
| 2543 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2544 | "0x%x\n", signal_levels); |
| 2545 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 2546 | } |
| 2547 | } |
| 2548 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2549 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
| 2550 | static uint32_t |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2551 | intel_hsw_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2552 | { |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2553 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2554 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2555 | switch (signal_levels) { |
| 2556 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2557 | return DDI_BUF_EMP_400MV_0DB_HSW; |
| 2558 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2559 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
| 2560 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2561 | return DDI_BUF_EMP_400MV_6DB_HSW; |
| 2562 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
| 2563 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2564 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2565 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2566 | return DDI_BUF_EMP_600MV_0DB_HSW; |
| 2567 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2568 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
| 2569 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2570 | return DDI_BUF_EMP_600MV_6DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2571 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2572 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2573 | return DDI_BUF_EMP_800MV_0DB_HSW; |
| 2574 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2575 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
| 2576 | default: |
| 2577 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2578 | "0x%x\n", signal_levels); |
| 2579 | return DDI_BUF_EMP_400MV_0DB_HSW; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2580 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2581 | } |
| 2582 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2583 | static uint32_t |
| 2584 | intel_bdw_signal_levels(uint8_t train_set) |
| 2585 | { |
| 2586 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 2587 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 2588 | switch (signal_levels) { |
| 2589 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2590 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
| 2591 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2592 | return DDI_BUF_EMP_400MV_3_5DB_BDW; /* Sel1 */ |
| 2593 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2594 | return DDI_BUF_EMP_400MV_6DB_BDW; /* Sel2 */ |
| 2595 | |
| 2596 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2597 | return DDI_BUF_EMP_600MV_0DB_BDW; /* Sel3 */ |
| 2598 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2599 | return DDI_BUF_EMP_600MV_3_5DB_BDW; /* Sel4 */ |
| 2600 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 2601 | return DDI_BUF_EMP_600MV_6DB_BDW; /* Sel5 */ |
| 2602 | |
| 2603 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2604 | return DDI_BUF_EMP_800MV_0DB_BDW; /* Sel6 */ |
| 2605 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 2606 | return DDI_BUF_EMP_800MV_3_5DB_BDW; /* Sel7 */ |
| 2607 | |
| 2608 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 2609 | return DDI_BUF_EMP_1200MV_0DB_BDW; /* Sel8 */ |
| 2610 | |
| 2611 | default: |
| 2612 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 2613 | "0x%x\n", signal_levels); |
| 2614 | return DDI_BUF_EMP_400MV_0DB_BDW; /* Sel0 */ |
| 2615 | } |
| 2616 | } |
| 2617 | |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2618 | /* Properly updates "DP" with the correct signal levels. */ |
| 2619 | static void |
| 2620 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
| 2621 | { |
| 2622 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2623 | enum port port = intel_dig_port->port; |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2624 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2625 | uint32_t signal_levels, mask; |
| 2626 | uint8_t train_set = intel_dp->train_set[0]; |
| 2627 | |
Paulo Zanoni | 8f93f4f | 2013-11-02 21:07:43 -0700 | [diff] [blame] | 2628 | if (IS_BROADWELL(dev)) { |
| 2629 | signal_levels = intel_bdw_signal_levels(train_set); |
| 2630 | mask = DDI_BUF_EMP_MASK; |
| 2631 | } else if (IS_HASWELL(dev)) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2632 | signal_levels = intel_hsw_signal_levels(train_set); |
| 2633 | mask = DDI_BUF_EMP_MASK; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 2634 | } else if (IS_CHERRYVIEW(dev)) { |
| 2635 | signal_levels = intel_chv_signal_levels(intel_dp); |
| 2636 | mask = 0; |
Pallavi G | e2fa6fb | 2013-04-18 14:44:28 -0700 | [diff] [blame] | 2637 | } else if (IS_VALLEYVIEW(dev)) { |
| 2638 | signal_levels = intel_vlv_signal_levels(intel_dp); |
| 2639 | mask = 0; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2640 | } else if (IS_GEN7(dev) && port == PORT_A) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2641 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
| 2642 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2643 | } else if (IS_GEN6(dev) && port == PORT_A) { |
Paulo Zanoni | f0a3424 | 2012-12-06 16:51:50 -0200 | [diff] [blame] | 2644 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
| 2645 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
| 2646 | } else { |
| 2647 | signal_levels = intel_gen4_signal_levels(train_set); |
| 2648 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
| 2649 | } |
| 2650 | |
| 2651 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
| 2652 | |
| 2653 | *DP = (*DP & ~mask) | signal_levels; |
| 2654 | } |
| 2655 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2656 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2657 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2658 | uint32_t *DP, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 2659 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2660 | { |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2661 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2662 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2663 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2664 | enum port port = intel_dig_port->port; |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2665 | uint8_t buf[sizeof(intel_dp->train_set) + 1]; |
| 2666 | int ret, len; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2667 | |
Paulo Zanoni | 22b8bf1 | 2013-02-18 19:00:23 -0300 | [diff] [blame] | 2668 | if (HAS_DDI(dev)) { |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2669 | uint32_t temp = I915_READ(DP_TP_CTL(port)); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2670 | |
| 2671 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 2672 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2673 | else |
| 2674 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 2675 | |
| 2676 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2677 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2678 | case DP_TRAINING_PATTERN_DISABLE: |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2679 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 2680 | |
| 2681 | break; |
| 2682 | case DP_TRAINING_PATTERN_1: |
| 2683 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 2684 | break; |
| 2685 | case DP_TRAINING_PATTERN_2: |
| 2686 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 2687 | break; |
| 2688 | case DP_TRAINING_PATTERN_3: |
| 2689 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 2690 | break; |
| 2691 | } |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 2692 | I915_WRITE(DP_TP_CTL(port), temp); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2693 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2694 | } else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2695 | *DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2696 | |
| 2697 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2698 | case DP_TRAINING_PATTERN_DISABLE: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2699 | *DP |= DP_LINK_TRAIN_OFF_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2700 | break; |
| 2701 | case DP_TRAINING_PATTERN_1: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2702 | *DP |= DP_LINK_TRAIN_PAT_1_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2703 | break; |
| 2704 | case DP_TRAINING_PATTERN_2: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2705 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2706 | break; |
| 2707 | case DP_TRAINING_PATTERN_3: |
| 2708 | DRM_ERROR("DP training pattern 3 not supported\n"); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2709 | *DP |= DP_LINK_TRAIN_PAT_2_CPT; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2710 | break; |
| 2711 | } |
| 2712 | |
| 2713 | } else { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2714 | *DP &= ~DP_LINK_TRAIN_MASK; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2715 | |
| 2716 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 2717 | case DP_TRAINING_PATTERN_DISABLE: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2718 | *DP |= DP_LINK_TRAIN_OFF; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2719 | break; |
| 2720 | case DP_TRAINING_PATTERN_1: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2721 | *DP |= DP_LINK_TRAIN_PAT_1; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2722 | break; |
| 2723 | case DP_TRAINING_PATTERN_2: |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2724 | *DP |= DP_LINK_TRAIN_PAT_2; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2725 | break; |
| 2726 | case DP_TRAINING_PATTERN_3: |
| 2727 | DRM_ERROR("DP training pattern 3 not supported\n"); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2728 | *DP |= DP_LINK_TRAIN_PAT_2; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2729 | break; |
| 2730 | } |
| 2731 | } |
| 2732 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2733 | I915_WRITE(intel_dp->output_reg, *DP); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2734 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2735 | |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2736 | buf[0] = dp_train_pat; |
| 2737 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) == |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2738 | DP_TRAINING_PATTERN_DISABLE) { |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2739 | /* don't write DP_TRAINING_LANEx_SET on disable */ |
| 2740 | len = 1; |
| 2741 | } else { |
| 2742 | /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ |
| 2743 | memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); |
| 2744 | len = intel_dp->lane_count + 1; |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 2745 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2746 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2747 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET, |
| 2748 | buf, len); |
Jani Nikula | 2cdfe6c | 2013-10-04 15:08:48 +0300 | [diff] [blame] | 2749 | |
| 2750 | return ret == len; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2751 | } |
| 2752 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2753 | static bool |
| 2754 | intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
| 2755 | uint8_t dp_train_pat) |
| 2756 | { |
Jani Nikula | 953d22e | 2013-10-04 15:08:47 +0300 | [diff] [blame] | 2757 | memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2758 | intel_dp_set_signal_levels(intel_dp, DP); |
| 2759 | return intel_dp_set_link_train(intel_dp, DP, dp_train_pat); |
| 2760 | } |
| 2761 | |
| 2762 | static bool |
| 2763 | intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP, |
Jani Nikula | 0301b3a | 2013-10-15 09:36:08 +0300 | [diff] [blame] | 2764 | const uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2765 | { |
| 2766 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2767 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2768 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2769 | int ret; |
| 2770 | |
| 2771 | intel_get_adjust_train(intel_dp, link_status); |
| 2772 | intel_dp_set_signal_levels(intel_dp, DP); |
| 2773 | |
| 2774 | I915_WRITE(intel_dp->output_reg, *DP); |
| 2775 | POSTING_READ(intel_dp->output_reg); |
| 2776 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2777 | ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, |
| 2778 | intel_dp->train_set, intel_dp->lane_count); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2779 | |
| 2780 | return ret == intel_dp->lane_count; |
| 2781 | } |
| 2782 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2783 | static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) |
| 2784 | { |
| 2785 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 2786 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 2787 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2788 | enum port port = intel_dig_port->port; |
| 2789 | uint32_t val; |
| 2790 | |
| 2791 | if (!HAS_DDI(dev)) |
| 2792 | return; |
| 2793 | |
| 2794 | val = I915_READ(DP_TP_CTL(port)); |
| 2795 | val &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 2796 | val |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 2797 | I915_WRITE(DP_TP_CTL(port), val); |
| 2798 | |
| 2799 | /* |
| 2800 | * On PORT_A we can have only eDP in SST mode. There the only reason |
| 2801 | * we need to set idle transmission mode is to work around a HW issue |
| 2802 | * where we enable the pipe while not in idle link-training mode. |
| 2803 | * In this case there is requirement to wait for a minimum number of |
| 2804 | * idle patterns to be sent. |
| 2805 | */ |
| 2806 | if (port == PORT_A) |
| 2807 | return; |
| 2808 | |
| 2809 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE), |
| 2810 | 1)) |
| 2811 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 2812 | } |
| 2813 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2814 | /* Enable corresponding port and start training pattern 1 */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2815 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2816 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2817 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2818 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2819 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2820 | int i; |
| 2821 | uint8_t voltage; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2822 | int voltage_tries, loop_tries; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2823 | uint32_t DP = intel_dp->DP; |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 2824 | uint8_t link_config[2]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2825 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 2826 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2827 | intel_ddi_prepare_link_retrain(encoder); |
| 2828 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2829 | /* Write the link configuration data */ |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 2830 | link_config[0] = intel_dp->link_bw; |
| 2831 | link_config[1] = intel_dp->lane_count; |
| 2832 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
| 2833 | link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2834 | drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); |
Jani Nikula | 6aba5b6 | 2013-10-04 15:08:10 +0300 | [diff] [blame] | 2835 | |
| 2836 | link_config[0] = 0; |
| 2837 | link_config[1] = DP_SET_ANSI_8B10B; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 2838 | drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2839 | |
| 2840 | DP |= DP_PORT_EN; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 2841 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2842 | /* clock recovery */ |
| 2843 | if (!intel_dp_reset_link_train(intel_dp, &DP, |
| 2844 | DP_TRAINING_PATTERN_1 | |
| 2845 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 2846 | DRM_ERROR("failed to enable link training\n"); |
| 2847 | return; |
| 2848 | } |
| 2849 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2850 | voltage = 0xff; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2851 | voltage_tries = 0; |
| 2852 | loop_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2853 | for (;;) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2854 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2855 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2856 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2857 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 2858 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2859 | break; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2860 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2861 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2862 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2863 | DRM_DEBUG_KMS("clock recovery OK\n"); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2864 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2865 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2866 | |
| 2867 | /* Check to see if we've tried the max voltage */ |
| 2868 | for (i = 0; i < intel_dp->lane_count; i++) |
| 2869 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 2870 | break; |
Takashi Iwai | 3b4f819 | 2013-03-11 18:40:16 +0100 | [diff] [blame] | 2871 | if (i == intel_dp->lane_count) { |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2872 | ++loop_tries; |
| 2873 | if (loop_tries == 5) { |
Jani Nikula | 3def84b | 2013-10-05 16:13:56 +0300 | [diff] [blame] | 2874 | DRM_ERROR("too many full retries, give up\n"); |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2875 | break; |
| 2876 | } |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2877 | intel_dp_reset_link_train(intel_dp, &DP, |
| 2878 | DP_TRAINING_PATTERN_1 | |
| 2879 | DP_LINK_SCRAMBLING_DISABLE); |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 2880 | voltage_tries = 0; |
| 2881 | continue; |
| 2882 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2883 | |
| 2884 | /* Check to see if we've tried the same voltage 5 times */ |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2885 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 2886 | ++voltage_tries; |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2887 | if (voltage_tries == 5) { |
Jani Nikula | 3def84b | 2013-10-05 16:13:56 +0300 | [diff] [blame] | 2888 | DRM_ERROR("too many voltage retries, give up\n"); |
Daniel Vetter | b06fbda | 2012-10-16 09:50:25 +0200 | [diff] [blame] | 2889 | break; |
| 2890 | } |
| 2891 | } else |
| 2892 | voltage_tries = 0; |
| 2893 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2894 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2895 | /* Update training set as requested by target */ |
| 2896 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 2897 | DRM_ERROR("failed to update link training\n"); |
| 2898 | break; |
| 2899 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2900 | } |
| 2901 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2902 | intel_dp->DP = DP; |
| 2903 | } |
| 2904 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 2905 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2906 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 2907 | { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2908 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2909 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2910 | uint32_t DP = intel_dp->DP; |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2911 | uint32_t training_pattern = DP_TRAINING_PATTERN_2; |
| 2912 | |
| 2913 | /* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/ |
| 2914 | if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3) |
| 2915 | training_pattern = DP_TRAINING_PATTERN_3; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2916 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2917 | /* channel equalization */ |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2918 | if (!intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2919 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2920 | DP_LINK_SCRAMBLING_DISABLE)) { |
| 2921 | DRM_ERROR("failed to start channel equalization\n"); |
| 2922 | return; |
| 2923 | } |
| 2924 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2925 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2926 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2927 | channel_eq = false; |
| 2928 | for (;;) { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2929 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2930 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2931 | if (cr_tries > 5) { |
| 2932 | DRM_ERROR("failed to train DP, aborting\n"); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2933 | break; |
| 2934 | } |
| 2935 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 2936 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2937 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 2938 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2939 | break; |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2940 | } |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 2941 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2942 | /* Make sure clock is still ok */ |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 2943 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2944 | intel_dp_start_link_train(intel_dp); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2945 | intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2946 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2947 | DP_LINK_SCRAMBLING_DISABLE); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2948 | cr_tries++; |
| 2949 | continue; |
| 2950 | } |
| 2951 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 2952 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2953 | channel_eq = true; |
| 2954 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2955 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2956 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2957 | /* Try 5 times, then try clock recovery if that fails */ |
| 2958 | if (tries > 5) { |
| 2959 | intel_dp_link_down(intel_dp); |
| 2960 | intel_dp_start_link_train(intel_dp); |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2961 | intel_dp_set_link_train(intel_dp, &DP, |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 2962 | training_pattern | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2963 | DP_LINK_SCRAMBLING_DISABLE); |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 2964 | tries = 0; |
| 2965 | cr_tries++; |
| 2966 | continue; |
| 2967 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2968 | |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2969 | /* Update training set as requested by target */ |
| 2970 | if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) { |
| 2971 | DRM_ERROR("failed to update link training\n"); |
| 2972 | break; |
| 2973 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2974 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2975 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 2976 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2977 | intel_dp_set_idle_link_train(intel_dp); |
| 2978 | |
| 2979 | intel_dp->DP = DP; |
| 2980 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2981 | if (channel_eq) |
Masanari Iida | 07f4225 | 2013-03-20 11:00:34 +0900 | [diff] [blame] | 2982 | DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n"); |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 2983 | |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2984 | } |
| 2985 | |
| 2986 | void intel_dp_stop_link_train(struct intel_dp *intel_dp) |
| 2987 | { |
Jani Nikula | 70aff66 | 2013-09-27 15:10:44 +0300 | [diff] [blame] | 2988 | intel_dp_set_link_train(intel_dp, &intel_dp->DP, |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 2989 | DP_TRAINING_PATTERN_DISABLE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2990 | } |
| 2991 | |
| 2992 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2993 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2994 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2995 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 2996 | enum port port = intel_dig_port->port; |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 2997 | struct drm_device *dev = intel_dig_port->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2998 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 2999 | struct intel_crtc *intel_crtc = |
| 3000 | to_intel_crtc(intel_dig_port->base.base.crtc); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3001 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3002 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3003 | /* |
| 3004 | * DDI code has a strict mode set sequence and we should try to respect |
| 3005 | * it, otherwise we might hang the machine in many different ways. So we |
| 3006 | * really should be disabling the port only on a complete crtc_disable |
| 3007 | * sequence. This function is just called under two conditions on DDI |
| 3008 | * code: |
| 3009 | * - Link train failed while doing crtc_enable, and on this case we |
| 3010 | * really should respect the mode set sequence and wait for a |
| 3011 | * crtc_disable. |
| 3012 | * - Someone turned the monitor off and intel_dp_check_link_status |
| 3013 | * called us. We don't need to disable the whole port on this case, so |
| 3014 | * when someone turns the monitor on again, |
| 3015 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
| 3016 | * train. |
| 3017 | */ |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 3018 | if (HAS_DDI(dev)) |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 3019 | return; |
| 3020 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 3021 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3022 | return; |
| 3023 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 3024 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3025 | |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3026 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3027 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3028 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3029 | } else { |
| 3030 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3031 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3032 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 3033 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3034 | |
Daniel Vetter | 493a708 | 2012-05-30 12:31:56 +0200 | [diff] [blame] | 3035 | if (HAS_PCH_IBX(dev) && |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 3036 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3037 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 3038 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3039 | /* Hardware workaround: leaving our transcoder select |
| 3040 | * set to transcoder B while it's off will prevent the |
| 3041 | * corresponding HDMI output on transcoder A. |
| 3042 | * |
| 3043 | * Combine this with another hardware workaround: |
| 3044 | * transcoder select bit can only be cleared while the |
| 3045 | * port is enabled. |
| 3046 | */ |
| 3047 | DP &= ~DP_PIPEB_SELECT; |
| 3048 | I915_WRITE(intel_dp->output_reg, DP); |
| 3049 | |
| 3050 | /* Changes to enable or select take place the vblank |
| 3051 | * after being written. |
| 3052 | */ |
Daniel Vetter | ff50afe | 2012-11-29 15:59:34 +0100 | [diff] [blame] | 3053 | if (WARN_ON(crtc == NULL)) { |
| 3054 | /* We should never try to disable a port without a crtc |
| 3055 | * attached. For paranoia keep the code around for a |
| 3056 | * bit. */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 3057 | POSTING_READ(intel_dp->output_reg); |
| 3058 | msleep(50); |
| 3059 | } else |
Daniel Vetter | ab527ef | 2012-11-29 15:59:33 +0100 | [diff] [blame] | 3060 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 3061 | } |
| 3062 | |
Wu Fengguang | 832afda | 2011-12-09 20:42:21 +0800 | [diff] [blame] | 3063 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3064 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 3065 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 3066 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3067 | } |
| 3068 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3069 | static bool |
| 3070 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3071 | { |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3072 | struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); |
| 3073 | struct drm_device *dev = dig_port->base.base.dev; |
| 3074 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3075 | |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3076 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
| 3077 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3078 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, |
| 3079 | sizeof(intel_dp->dpcd)) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3080 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3081 | |
Damien Lespiau | 577c7a5 | 2012-12-13 16:09:02 +0000 | [diff] [blame] | 3082 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
| 3083 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
| 3084 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
| 3085 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3086 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 3087 | return false; /* DPCD not present */ |
| 3088 | |
Shobhit Kumar | 2293bb5 | 2013-07-11 18:44:56 -0300 | [diff] [blame] | 3089 | /* Check if the panel supports PSR */ |
| 3090 | memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd)); |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3091 | if (is_edp(intel_dp)) { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3092 | intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT, |
| 3093 | intel_dp->psr_dpcd, |
| 3094 | sizeof(intel_dp->psr_dpcd)); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3095 | if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) { |
| 3096 | dev_priv->psr.sink_support = true; |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3097 | DRM_DEBUG_KMS("Detected EDP PSR Panel.\n"); |
Rodrigo Vivi | a031d70 | 2013-10-03 16:15:06 -0300 | [diff] [blame] | 3098 | } |
Jani Nikula | 5000393 | 2013-09-20 16:42:17 +0300 | [diff] [blame] | 3099 | } |
| 3100 | |
Todd Previte | 06ea66b | 2014-01-20 10:19:39 -0700 | [diff] [blame] | 3101 | /* Training Pattern 3 support */ |
| 3102 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 && |
| 3103 | intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) { |
| 3104 | intel_dp->use_tps3 = true; |
| 3105 | DRM_DEBUG_KMS("Displayport TPS3 supported"); |
| 3106 | } else |
| 3107 | intel_dp->use_tps3 = false; |
| 3108 | |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3109 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3110 | DP_DWN_STRM_PORT_PRESENT)) |
| 3111 | return true; /* native DP sink */ |
| 3112 | |
| 3113 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 3114 | return true; /* no per-port downstream info */ |
| 3115 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3116 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, |
| 3117 | intel_dp->downstream_ports, |
| 3118 | DP_MAX_DOWNSTREAM_PORTS) < 0) |
Adam Jackson | edb3924 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 3119 | return false; /* downstream port status fetch failed */ |
| 3120 | |
| 3121 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3122 | } |
| 3123 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3124 | static void |
| 3125 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 3126 | { |
| 3127 | u8 buf[3]; |
| 3128 | |
| 3129 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 3130 | return; |
| 3131 | |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 3132 | intel_edp_panel_vdd_on(intel_dp); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 3133 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3134 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3135 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 3136 | buf[0], buf[1], buf[2]); |
| 3137 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3138 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3) |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3139 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 3140 | buf[0], buf[1], buf[2]); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 3141 | |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3142 | edp_panel_vdd_off(intel_dp, false); |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3143 | } |
| 3144 | |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3145 | int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc) |
| 3146 | { |
| 3147 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3148 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 3149 | struct intel_crtc *intel_crtc = |
| 3150 | to_intel_crtc(intel_dig_port->base.base.crtc); |
| 3151 | u8 buf[1]; |
| 3152 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3153 | if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3154 | return -EAGAIN; |
| 3155 | |
| 3156 | if (!(buf[0] & DP_TEST_CRC_SUPPORTED)) |
| 3157 | return -ENOTTY; |
| 3158 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3159 | if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, |
| 3160 | DP_TEST_SINK_START) < 0) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3161 | return -EAGAIN; |
| 3162 | |
| 3163 | /* Wait 2 vblanks to be sure we will have the correct CRC value */ |
| 3164 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3165 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
| 3166 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3167 | if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3168 | return -EAGAIN; |
| 3169 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3170 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0); |
Rodrigo Vivi | d2e216d | 2014-01-24 13:36:17 -0200 | [diff] [blame] | 3171 | return 0; |
| 3172 | } |
| 3173 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3174 | static bool |
| 3175 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 3176 | { |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3177 | return intel_dp_dpcd_read_wake(&intel_dp->aux, |
| 3178 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3179 | sink_irq_vector, 1) == 1; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3180 | } |
| 3181 | |
| 3182 | static void |
| 3183 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 3184 | { |
| 3185 | /* NAK by default */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3186 | drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3187 | } |
| 3188 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3189 | /* |
| 3190 | * According to DP spec |
| 3191 | * 5.1.2: |
| 3192 | * 1. Read DPCD |
| 3193 | * 2. Configure link according to Receiver Capabilities |
| 3194 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 3195 | * 4. Check link status on receipt of hot-plug interrupt |
| 3196 | */ |
| 3197 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3198 | void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3199 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3200 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3201 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3202 | u8 sink_irq_vector; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3203 | u8 link_status[DP_LINK_STATUS_SIZE]; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3204 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3205 | if (!intel_encoder->connectors_active) |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 3206 | return; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 3207 | |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3208 | if (WARN_ON(!intel_encoder->base.crtc)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3209 | return; |
| 3210 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3211 | /* Try to read receiver status if the link appears to be up */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 3212 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3213 | return; |
| 3214 | } |
| 3215 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3216 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3217 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 3218 | return; |
| 3219 | } |
| 3220 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3221 | /* Try to read the source of the interrupt */ |
| 3222 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 3223 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 3224 | /* Clear interrupt source */ |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3225 | drm_dp_dpcd_writeb(&intel_dp->aux, |
| 3226 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 3227 | sink_irq_vector); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 3228 | |
| 3229 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 3230 | intel_dp_handle_test_request(intel_dp); |
| 3231 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 3232 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 3233 | } |
| 3234 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 3235 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 3236 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3237 | drm_get_encoder_name(&intel_encoder->base)); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 3238 | intel_dp_start_link_train(intel_dp); |
| 3239 | intel_dp_complete_link_train(intel_dp); |
Imre Deak | 3ab9c63 | 2013-05-03 12:57:41 +0300 | [diff] [blame] | 3240 | intel_dp_stop_link_train(intel_dp); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 3241 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3242 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3243 | |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3244 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3245 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3246 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 3247 | { |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3248 | uint8_t *dpcd = intel_dp->dpcd; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3249 | uint8_t type; |
| 3250 | |
| 3251 | if (!intel_dp_get_dpcd(intel_dp)) |
| 3252 | return connector_status_disconnected; |
| 3253 | |
| 3254 | /* if there's no downstream port, we're done */ |
| 3255 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3256 | return connector_status_connected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3257 | |
| 3258 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 3259 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 3260 | intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 3261 | uint8_t reg; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3262 | |
| 3263 | if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT, |
| 3264 | ®, 1) < 0) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3265 | return connector_status_unknown; |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 3266 | |
Adam Jackson | 2323517 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 3267 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 3268 | : connector_status_disconnected; |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3269 | } |
| 3270 | |
| 3271 | /* If no HPD, poke DDC gently */ |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 3272 | if (drm_probe_ddc(&intel_dp->aux.ddc)) |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3273 | return connector_status_connected; |
| 3274 | |
| 3275 | /* Well we tried, say unknown for unreliable port types */ |
Jani Nikula | c9ff160 | 2013-09-27 14:48:42 +0300 | [diff] [blame] | 3276 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { |
| 3277 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 3278 | if (type == DP_DS_PORT_TYPE_VGA || |
| 3279 | type == DP_DS_PORT_TYPE_NON_EDID) |
| 3280 | return connector_status_unknown; |
| 3281 | } else { |
| 3282 | type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 3283 | DP_DWN_STRM_PORT_TYPE_MASK; |
| 3284 | if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || |
| 3285 | type == DP_DWN_STRM_PORT_TYPE_OTHER) |
| 3286 | return connector_status_unknown; |
| 3287 | } |
Adam Jackson | caf9ab2 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 3288 | |
| 3289 | /* Anything else is out of spec, warn and ignore */ |
| 3290 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3291 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 3292 | } |
| 3293 | |
| 3294 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3295 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3296 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3297 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 3298 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3299 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3300 | enum drm_connector_status status; |
| 3301 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 3302 | /* Can't disconnect eDP, but you can close the lid... */ |
| 3303 | if (is_edp(intel_dp)) { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3304 | status = intel_panel_detect(dev); |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 3305 | if (status == connector_status_unknown) |
| 3306 | status = connector_status_connected; |
| 3307 | return status; |
| 3308 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 3309 | |
Damien Lespiau | 1b46963 | 2012-12-13 16:09:01 +0000 | [diff] [blame] | 3310 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
| 3311 | return connector_status_disconnected; |
| 3312 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3313 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3314 | } |
| 3315 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3316 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3317 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3318 | { |
Paulo Zanoni | 30add22 | 2012-10-26 19:05:45 -0200 | [diff] [blame] | 3319 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3320 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 34f2be4 | 2013-01-24 15:29:27 +0200 | [diff] [blame] | 3321 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 3322 | uint32_t bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 3323 | |
Jesse Barnes | 35aad75 | 2013-03-01 13:14:31 -0800 | [diff] [blame] | 3324 | /* Can't disconnect eDP, but you can close the lid... */ |
| 3325 | if (is_edp(intel_dp)) { |
| 3326 | enum drm_connector_status status; |
| 3327 | |
| 3328 | status = intel_panel_detect(dev); |
| 3329 | if (status == connector_status_unknown) |
| 3330 | status = connector_status_connected; |
| 3331 | return status; |
| 3332 | } |
| 3333 | |
Todd Previte | 232a6ee | 2014-01-23 00:13:41 -0700 | [diff] [blame] | 3334 | if (IS_VALLEYVIEW(dev)) { |
| 3335 | switch (intel_dig_port->port) { |
| 3336 | case PORT_B: |
| 3337 | bit = PORTB_HOTPLUG_LIVE_STATUS_VLV; |
| 3338 | break; |
| 3339 | case PORT_C: |
| 3340 | bit = PORTC_HOTPLUG_LIVE_STATUS_VLV; |
| 3341 | break; |
| 3342 | case PORT_D: |
| 3343 | bit = PORTD_HOTPLUG_LIVE_STATUS_VLV; |
| 3344 | break; |
| 3345 | default: |
| 3346 | return connector_status_unknown; |
| 3347 | } |
| 3348 | } else { |
| 3349 | switch (intel_dig_port->port) { |
| 3350 | case PORT_B: |
| 3351 | bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; |
| 3352 | break; |
| 3353 | case PORT_C: |
| 3354 | bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; |
| 3355 | break; |
| 3356 | case PORT_D: |
| 3357 | bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; |
| 3358 | break; |
| 3359 | default: |
| 3360 | return connector_status_unknown; |
| 3361 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3362 | } |
| 3363 | |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 3364 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3365 | return connector_status_disconnected; |
| 3366 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 3367 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3368 | } |
| 3369 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3370 | static struct edid * |
| 3371 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 3372 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3373 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3374 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3375 | /* use cached edid if we have one */ |
| 3376 | if (intel_connector->edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3377 | /* invalid edid */ |
| 3378 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3379 | return NULL; |
| 3380 | |
Jani Nikula | 55e9ede | 2013-10-01 10:38:54 +0300 | [diff] [blame] | 3381 | return drm_edid_duplicate(intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3382 | } |
| 3383 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3384 | return drm_get_edid(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3385 | } |
| 3386 | |
| 3387 | static int |
| 3388 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 3389 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3390 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3391 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3392 | /* use cached edid if we have one */ |
| 3393 | if (intel_connector->edid) { |
| 3394 | /* invalid edid */ |
| 3395 | if (IS_ERR(intel_connector->edid)) |
| 3396 | return 0; |
| 3397 | |
| 3398 | return intel_connector_update_modes(connector, |
| 3399 | intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 3400 | } |
| 3401 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3402 | return intel_ddc_get_modes(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 3403 | } |
| 3404 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3405 | static enum drm_connector_status |
| 3406 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 3407 | { |
| 3408 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 3409 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3410 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3411 | struct drm_device *dev = connector->dev; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3412 | struct drm_i915_private *dev_priv = dev->dev_private; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3413 | enum drm_connector_status status; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3414 | enum intel_display_power_domain power_domain; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3415 | struct edid *edid = NULL; |
| 3416 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3417 | intel_runtime_pm_get(dev_priv); |
| 3418 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3419 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3420 | intel_display_power_get(dev_priv, power_domain); |
| 3421 | |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 3422 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
| 3423 | connector->base.id, drm_get_connector_name(connector)); |
| 3424 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3425 | intel_dp->has_audio = false; |
| 3426 | |
| 3427 | if (HAS_PCH_SPLIT(dev)) |
| 3428 | status = ironlake_dp_detect(intel_dp); |
| 3429 | else |
| 3430 | status = g4x_dp_detect(intel_dp); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 3431 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3432 | if (status != connector_status_connected) |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3433 | goto out; |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3434 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 3435 | intel_dp_probe_oui(intel_dp); |
| 3436 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3437 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
| 3438 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3439 | } else { |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 3440 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3441 | if (edid) { |
| 3442 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3443 | kfree(edid); |
| 3444 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 3445 | } |
| 3446 | |
Paulo Zanoni | d63885d | 2012-10-26 19:05:49 -0200 | [diff] [blame] | 3447 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
| 3448 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3449 | status = connector_status_connected; |
| 3450 | |
| 3451 | out: |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3452 | intel_display_power_put(dev_priv, power_domain); |
| 3453 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3454 | intel_runtime_pm_put(dev_priv); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3455 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 3456 | return status; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3457 | } |
| 3458 | |
| 3459 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 3460 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3461 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3462 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3463 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3464 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3465 | struct drm_device *dev = connector->dev; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3466 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3467 | enum intel_display_power_domain power_domain; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3468 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3469 | |
| 3470 | /* We should parse the EDID data and find out if it has an audio sink |
| 3471 | */ |
| 3472 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3473 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3474 | intel_display_power_get(dev_priv, power_domain); |
| 3475 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 3476 | ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3477 | intel_display_power_put(dev_priv, power_domain); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3478 | if (ret) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3479 | return ret; |
| 3480 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3481 | /* if eDP has no EDID, fall back to fixed mode */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3482 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3483 | struct drm_display_mode *mode; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 3484 | mode = drm_mode_duplicate(dev, |
| 3485 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 3486 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 3487 | drm_mode_probed_add(connector, mode); |
| 3488 | return 1; |
| 3489 | } |
| 3490 | } |
| 3491 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3492 | } |
| 3493 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3494 | static bool |
| 3495 | intel_dp_detect_audio(struct drm_connector *connector) |
| 3496 | { |
| 3497 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3498 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
| 3499 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 3500 | struct drm_device *dev = connector->dev; |
| 3501 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3502 | enum intel_display_power_domain power_domain; |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3503 | struct edid *edid; |
| 3504 | bool has_audio = false; |
| 3505 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3506 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 3507 | intel_display_power_get(dev_priv, power_domain); |
| 3508 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 3509 | edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3510 | if (edid) { |
| 3511 | has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3512 | kfree(edid); |
| 3513 | } |
| 3514 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 3515 | intel_display_power_put(dev_priv, power_domain); |
| 3516 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3517 | return has_audio; |
| 3518 | } |
| 3519 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3520 | static int |
| 3521 | intel_dp_set_property(struct drm_connector *connector, |
| 3522 | struct drm_property *property, |
| 3523 | uint64_t val) |
| 3524 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3525 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3526 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3527 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
| 3528 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3529 | int ret; |
| 3530 | |
Rob Clark | 662595d | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 3531 | ret = drm_object_property_set_value(&connector->base, property, val); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3532 | if (ret) |
| 3533 | return ret; |
| 3534 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 3535 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3536 | int i = val; |
| 3537 | bool has_audio; |
| 3538 | |
| 3539 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3540 | return 0; |
| 3541 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3542 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3543 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3544 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3545 | has_audio = intel_dp_detect_audio(connector); |
| 3546 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 3547 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3548 | |
| 3549 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3550 | return 0; |
| 3551 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 3552 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3553 | goto done; |
| 3554 | } |
| 3555 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3556 | if (property == dev_priv->broadcast_rgb_property) { |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 3557 | bool old_auto = intel_dp->color_range_auto; |
| 3558 | uint32_t old_range = intel_dp->color_range; |
| 3559 | |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 3560 | switch (val) { |
| 3561 | case INTEL_BROADCAST_RGB_AUTO: |
| 3562 | intel_dp->color_range_auto = true; |
| 3563 | break; |
| 3564 | case INTEL_BROADCAST_RGB_FULL: |
| 3565 | intel_dp->color_range_auto = false; |
| 3566 | intel_dp->color_range = 0; |
| 3567 | break; |
| 3568 | case INTEL_BROADCAST_RGB_LIMITED: |
| 3569 | intel_dp->color_range_auto = false; |
| 3570 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
| 3571 | break; |
| 3572 | default: |
| 3573 | return -EINVAL; |
| 3574 | } |
Daniel Vetter | ae4edb8 | 2013-04-22 17:07:23 +0200 | [diff] [blame] | 3575 | |
| 3576 | if (old_auto == intel_dp->color_range_auto && |
| 3577 | old_range == intel_dp->color_range) |
| 3578 | return 0; |
| 3579 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3580 | goto done; |
| 3581 | } |
| 3582 | |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3583 | if (is_edp(intel_dp) && |
| 3584 | property == connector->dev->mode_config.scaling_mode_property) { |
| 3585 | if (val == DRM_MODE_SCALE_NONE) { |
| 3586 | DRM_DEBUG_KMS("no scaling not supported\n"); |
| 3587 | return -EINVAL; |
| 3588 | } |
| 3589 | |
| 3590 | if (intel_connector->panel.fitting_mode == val) { |
| 3591 | /* the eDP scaling property is not changed */ |
| 3592 | return 0; |
| 3593 | } |
| 3594 | intel_connector->panel.fitting_mode = val; |
| 3595 | |
| 3596 | goto done; |
| 3597 | } |
| 3598 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3599 | return -EINVAL; |
| 3600 | |
| 3601 | done: |
Chris Wilson | c0c36b94 | 2012-12-19 16:08:43 +0000 | [diff] [blame] | 3602 | if (intel_encoder->base.crtc) |
| 3603 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3604 | |
| 3605 | return 0; |
| 3606 | } |
| 3607 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3608 | static void |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 3609 | intel_dp_connector_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3610 | { |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 3611 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 3612 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 3613 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 3614 | kfree(intel_connector->edid); |
| 3615 | |
Paulo Zanoni | acd8db10 | 2013-06-12 17:27:23 -0300 | [diff] [blame] | 3616 | /* Can't call is_edp() since the encoder may have been destroyed |
| 3617 | * already. */ |
| 3618 | if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 3619 | intel_panel_fini(&intel_connector->panel); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 3620 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3621 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 3622 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3623 | } |
| 3624 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 3625 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3626 | { |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3627 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
| 3628 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3629 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3630 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 3631 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3632 | drm_encoder_cleanup(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 3633 | if (is_edp(intel_dp)) { |
| 3634 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3635 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 3636 | edp_panel_vdd_off_sync(intel_dp); |
Daniel Vetter | bd17381 | 2013-03-25 11:24:10 +0100 | [diff] [blame] | 3637 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 3638 | } |
Paulo Zanoni | da63a9f | 2012-10-26 19:05:46 -0200 | [diff] [blame] | 3639 | kfree(intel_dig_port); |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3640 | } |
| 3641 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3642 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 3643 | .dpms = intel_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3644 | .detect = intel_dp_detect, |
| 3645 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3646 | .set_property = intel_dp_set_property, |
Paulo Zanoni | 73845ad | 2013-06-12 17:27:30 -0300 | [diff] [blame] | 3647 | .destroy = intel_dp_connector_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3648 | }; |
| 3649 | |
| 3650 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 3651 | .get_modes = intel_dp_get_modes, |
| 3652 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 3653 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3654 | }; |
| 3655 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3656 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 3657 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 3658 | }; |
| 3659 | |
Chris Wilson | 995b6762 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 3660 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 3661 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3662 | { |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3663 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3664 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 3665 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3666 | } |
| 3667 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3668 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 3669 | int |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 3670 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3671 | { |
| 3672 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3673 | struct intel_encoder *intel_encoder; |
| 3674 | struct intel_dp *intel_dp; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3675 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3676 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
| 3677 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3678 | |
Paulo Zanoni | fa90ece | 2012-10-26 19:05:44 -0200 | [diff] [blame] | 3679 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
| 3680 | intel_encoder->type == INTEL_OUTPUT_EDP) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3681 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3682 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 3683 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 3684 | return -1; |
| 3685 | } |
| 3686 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3687 | /* check the VBT to see whether the eDP is on DP-D port */ |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3688 | bool intel_dp_is_edp(struct drm_device *dev, enum port port) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3689 | { |
| 3690 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 768f69c | 2013-09-11 18:02:47 -0300 | [diff] [blame] | 3691 | union child_device_config *p_child; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3692 | int i; |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3693 | static const short port_mapping[] = { |
| 3694 | [PORT_B] = PORT_IDPB, |
| 3695 | [PORT_C] = PORT_IDPC, |
| 3696 | [PORT_D] = PORT_IDPD, |
| 3697 | }; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3698 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 3699 | if (port == PORT_A) |
| 3700 | return true; |
| 3701 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3702 | if (!dev_priv->vbt.child_dev_num) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3703 | return false; |
| 3704 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3705 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
| 3706 | p_child = dev_priv->vbt.child_dev + i; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3707 | |
Ville Syrjälä | 5d8a775 | 2013-11-01 18:22:39 +0200 | [diff] [blame] | 3708 | if (p_child->common.dvo_port == port_mapping[port] && |
Ville Syrjälä | f02586d | 2013-11-01 20:32:08 +0200 | [diff] [blame] | 3709 | (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) == |
| 3710 | (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS)) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 3711 | return true; |
| 3712 | } |
| 3713 | return false; |
| 3714 | } |
| 3715 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3716 | static void |
| 3717 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 3718 | { |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3719 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 3720 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 3721 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 3722 | intel_attach_broadcast_rgb_property(connector); |
Ville Syrjälä | 55bc60d | 2013-01-17 16:31:29 +0200 | [diff] [blame] | 3723 | intel_dp->color_range_auto = true; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3724 | |
| 3725 | if (is_edp(intel_dp)) { |
| 3726 | drm_mode_create_scaling_mode_property(connector->dev); |
Rob Clark | 6de6d84 | 2012-10-11 20:36:04 -0500 | [diff] [blame] | 3727 | drm_object_attach_property( |
| 3728 | &connector->base, |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3729 | connector->dev->mode_config.scaling_mode_property, |
Yuly Novikov | 8e740cd | 2012-10-26 12:04:01 +0300 | [diff] [blame] | 3730 | DRM_MODE_SCALE_ASPECT); |
| 3731 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
Yuly Novikov | 53b4183 | 2012-10-26 12:04:00 +0300 | [diff] [blame] | 3732 | } |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 3733 | } |
| 3734 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 3735 | static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) |
| 3736 | { |
| 3737 | intel_dp->last_power_cycle = jiffies; |
| 3738 | intel_dp->last_power_on = jiffies; |
| 3739 | intel_dp->last_backlight_off = jiffies; |
| 3740 | } |
| 3741 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3742 | static void |
| 3743 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3744 | struct intel_dp *intel_dp, |
| 3745 | struct edp_power_seq *out) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3746 | { |
| 3747 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3748 | struct edp_power_seq cur, vbt, spec, final; |
| 3749 | u32 pp_on, pp_off, pp_div, pp; |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3750 | int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3751 | |
| 3752 | if (HAS_PCH_SPLIT(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3753 | pp_ctrl_reg = PCH_PP_CONTROL; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3754 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 3755 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 3756 | pp_div_reg = PCH_PP_DIVISOR; |
| 3757 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3758 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 3759 | |
| 3760 | pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe); |
| 3761 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 3762 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 3763 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3764 | } |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3765 | |
| 3766 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
| 3767 | * the very first thing. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3768 | pp = ironlake_get_pp_control(intel_dp); |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3769 | I915_WRITE(pp_ctrl_reg, pp); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3770 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3771 | pp_on = I915_READ(pp_on_reg); |
| 3772 | pp_off = I915_READ(pp_off_reg); |
| 3773 | pp_div = I915_READ(pp_div_reg); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3774 | |
| 3775 | /* Pull timing values out of registers */ |
| 3776 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 3777 | PANEL_POWER_UP_DELAY_SHIFT; |
| 3778 | |
| 3779 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 3780 | PANEL_LIGHT_ON_DELAY_SHIFT; |
| 3781 | |
| 3782 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 3783 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 3784 | |
| 3785 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 3786 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 3787 | |
| 3788 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 3789 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 3790 | |
| 3791 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 3792 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 3793 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 3794 | vbt = dev_priv->vbt.edp_pps; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3795 | |
| 3796 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
| 3797 | * our hw here, which are all in 100usec. */ |
| 3798 | spec.t1_t3 = 210 * 10; |
| 3799 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
| 3800 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
| 3801 | spec.t10 = 500 * 10; |
| 3802 | /* This one is special and actually in units of 100ms, but zero |
| 3803 | * based in the hw (so we need to add 100 ms). But the sw vbt |
| 3804 | * table multiplies it with 1000 to make it in units of 100usec, |
| 3805 | * too. */ |
| 3806 | spec.t11_t12 = (510 + 100) * 10; |
| 3807 | |
| 3808 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 3809 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 3810 | |
| 3811 | /* Use the max of the register settings and vbt. If both are |
| 3812 | * unset, fall back to the spec limits. */ |
| 3813 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
| 3814 | spec.field : \ |
| 3815 | max(cur.field, vbt.field)) |
| 3816 | assign_final(t1_t3); |
| 3817 | assign_final(t8); |
| 3818 | assign_final(t9); |
| 3819 | assign_final(t10); |
| 3820 | assign_final(t11_t12); |
| 3821 | #undef assign_final |
| 3822 | |
| 3823 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
| 3824 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 3825 | intel_dp->backlight_on_delay = get_delay(t8); |
| 3826 | intel_dp->backlight_off_delay = get_delay(t9); |
| 3827 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 3828 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 3829 | #undef get_delay |
| 3830 | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3831 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 3832 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 3833 | intel_dp->panel_power_cycle_delay); |
| 3834 | |
| 3835 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 3836 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
| 3837 | |
| 3838 | if (out) |
| 3839 | *out = final; |
| 3840 | } |
| 3841 | |
| 3842 | static void |
| 3843 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
| 3844 | struct intel_dp *intel_dp, |
| 3845 | struct edp_power_seq *seq) |
| 3846 | { |
| 3847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3848 | u32 pp_on, pp_off, pp_div, port_sel = 0; |
| 3849 | int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev); |
| 3850 | int pp_on_reg, pp_off_reg, pp_div_reg; |
| 3851 | |
| 3852 | if (HAS_PCH_SPLIT(dev)) { |
| 3853 | pp_on_reg = PCH_PP_ON_DELAYS; |
| 3854 | pp_off_reg = PCH_PP_OFF_DELAYS; |
| 3855 | pp_div_reg = PCH_PP_DIVISOR; |
| 3856 | } else { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3857 | enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); |
| 3858 | |
| 3859 | pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe); |
| 3860 | pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe); |
| 3861 | pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe); |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3862 | } |
| 3863 | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 3864 | /* |
| 3865 | * And finally store the new values in the power sequencer. The |
| 3866 | * backlight delays are set to 1 because we do manual waits on them. For |
| 3867 | * T8, even BSpec recommends doing it. For T9, if we don't do this, |
| 3868 | * we'll end up waiting for the backlight off delay twice: once when we |
| 3869 | * do the manual sleep, and once when we disable the panel and wait for |
| 3870 | * the PP_STATUS bit to become zero. |
| 3871 | */ |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3872 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
Paulo Zanoni | b2f19d1 | 2013-12-19 14:29:44 -0200 | [diff] [blame] | 3873 | (1 << PANEL_LIGHT_ON_DELAY_SHIFT); |
| 3874 | pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3875 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3876 | /* Compute the divisor for the pp clock, simply match the Bspec |
| 3877 | * formula. */ |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3878 | pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT; |
Jani Nikula | f30d26e | 2013-01-16 10:53:40 +0200 | [diff] [blame] | 3879 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3880 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
| 3881 | |
| 3882 | /* Haswell doesn't have any port selection bits for the panel |
| 3883 | * power sequencer any more. */ |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3884 | if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | bf13e81 | 2013-09-06 07:40:05 +0300 | [diff] [blame] | 3885 | if (dp_to_dig_port(intel_dp)->port == PORT_B) |
| 3886 | port_sel = PANEL_PORT_SELECT_DPB_VLV; |
| 3887 | else |
| 3888 | port_sel = PANEL_PORT_SELECT_DPC_VLV; |
Imre Deak | bc7d38a | 2013-05-16 14:40:36 +0300 | [diff] [blame] | 3889 | } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
| 3890 | if (dp_to_dig_port(intel_dp)->port == PORT_A) |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 3891 | port_sel = PANEL_PORT_SELECT_DPA; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3892 | else |
Jani Nikula | a24c144 | 2013-09-05 16:44:46 +0300 | [diff] [blame] | 3893 | port_sel = PANEL_PORT_SELECT_DPD; |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3894 | } |
| 3895 | |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3896 | pp_on |= port_sel; |
| 3897 | |
| 3898 | I915_WRITE(pp_on_reg, pp_on); |
| 3899 | I915_WRITE(pp_off_reg, pp_off); |
| 3900 | I915_WRITE(pp_div_reg, pp_div); |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3901 | |
Daniel Vetter | 67a5456 | 2012-10-20 20:57:45 +0200 | [diff] [blame] | 3902 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
Jesse Barnes | 453c542 | 2013-03-28 09:55:41 -0700 | [diff] [blame] | 3903 | I915_READ(pp_on_reg), |
| 3904 | I915_READ(pp_off_reg), |
| 3905 | I915_READ(pp_div_reg)); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 3906 | } |
| 3907 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 3908 | void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate) |
| 3909 | { |
| 3910 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3911 | struct intel_encoder *encoder; |
| 3912 | struct intel_dp *intel_dp = NULL; |
| 3913 | struct intel_crtc_config *config = NULL; |
| 3914 | struct intel_crtc *intel_crtc = NULL; |
| 3915 | struct intel_connector *intel_connector = dev_priv->drrs.connector; |
| 3916 | u32 reg, val; |
| 3917 | enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR; |
| 3918 | |
| 3919 | if (refresh_rate <= 0) { |
| 3920 | DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); |
| 3921 | return; |
| 3922 | } |
| 3923 | |
| 3924 | if (intel_connector == NULL) { |
| 3925 | DRM_DEBUG_KMS("DRRS supported for eDP only.\n"); |
| 3926 | return; |
| 3927 | } |
| 3928 | |
| 3929 | if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) { |
| 3930 | DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); |
| 3931 | return; |
| 3932 | } |
| 3933 | |
| 3934 | encoder = intel_attached_encoder(&intel_connector->base); |
| 3935 | intel_dp = enc_to_intel_dp(&encoder->base); |
| 3936 | intel_crtc = encoder->new_crtc; |
| 3937 | |
| 3938 | if (!intel_crtc) { |
| 3939 | DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); |
| 3940 | return; |
| 3941 | } |
| 3942 | |
| 3943 | config = &intel_crtc->config; |
| 3944 | |
| 3945 | if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) { |
| 3946 | DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); |
| 3947 | return; |
| 3948 | } |
| 3949 | |
| 3950 | if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate) |
| 3951 | index = DRRS_LOW_RR; |
| 3952 | |
| 3953 | if (index == intel_dp->drrs_state.refresh_rate_type) { |
| 3954 | DRM_DEBUG_KMS( |
| 3955 | "DRRS requested for previously set RR...ignoring\n"); |
| 3956 | return; |
| 3957 | } |
| 3958 | |
| 3959 | if (!intel_crtc->active) { |
| 3960 | DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); |
| 3961 | return; |
| 3962 | } |
| 3963 | |
| 3964 | if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) { |
| 3965 | reg = PIPECONF(intel_crtc->config.cpu_transcoder); |
| 3966 | val = I915_READ(reg); |
| 3967 | if (index > DRRS_HIGH_RR) { |
| 3968 | val |= PIPECONF_EDP_RR_MODE_SWITCH; |
| 3969 | intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); |
| 3970 | } else { |
| 3971 | val &= ~PIPECONF_EDP_RR_MODE_SWITCH; |
| 3972 | } |
| 3973 | I915_WRITE(reg, val); |
| 3974 | } |
| 3975 | |
| 3976 | /* |
| 3977 | * mutex taken to ensure that there is no race between differnt |
| 3978 | * drrs calls trying to update refresh rate. This scenario may occur |
| 3979 | * in future when idleness detection based DRRS in kernel and |
| 3980 | * possible calls from user space to set differnt RR are made. |
| 3981 | */ |
| 3982 | |
| 3983 | mutex_lock(&intel_dp->drrs_state.mutex); |
| 3984 | |
| 3985 | intel_dp->drrs_state.refresh_rate_type = index; |
| 3986 | |
| 3987 | mutex_unlock(&intel_dp->drrs_state.mutex); |
| 3988 | |
| 3989 | DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); |
| 3990 | } |
| 3991 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 3992 | static struct drm_display_mode * |
| 3993 | intel_dp_drrs_init(struct intel_digital_port *intel_dig_port, |
| 3994 | struct intel_connector *intel_connector, |
| 3995 | struct drm_display_mode *fixed_mode) |
| 3996 | { |
| 3997 | struct drm_connector *connector = &intel_connector->base; |
| 3998 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 3999 | struct drm_device *dev = intel_dig_port->base.base.dev; |
| 4000 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4001 | struct drm_display_mode *downclock_mode = NULL; |
| 4002 | |
| 4003 | if (INTEL_INFO(dev)->gen <= 6) { |
| 4004 | DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); |
| 4005 | return NULL; |
| 4006 | } |
| 4007 | |
| 4008 | if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { |
| 4009 | DRM_INFO("VBT doesn't support DRRS\n"); |
| 4010 | return NULL; |
| 4011 | } |
| 4012 | |
| 4013 | downclock_mode = intel_find_panel_downclock |
| 4014 | (dev, fixed_mode, connector); |
| 4015 | |
| 4016 | if (!downclock_mode) { |
| 4017 | DRM_INFO("DRRS not supported\n"); |
| 4018 | return NULL; |
| 4019 | } |
| 4020 | |
Pradeep Bhat | 439d7ac | 2014-04-05 12:13:28 +0530 | [diff] [blame] | 4021 | dev_priv->drrs.connector = intel_connector; |
| 4022 | |
| 4023 | mutex_init(&intel_dp->drrs_state.mutex); |
| 4024 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 4025 | intel_dp->drrs_state.type = dev_priv->vbt.drrs_type; |
| 4026 | |
| 4027 | intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR; |
| 4028 | DRM_INFO("seamless DRRS supported for eDP panel.\n"); |
| 4029 | return downclock_mode; |
| 4030 | } |
| 4031 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4032 | static bool intel_edp_init_connector(struct intel_dp *intel_dp, |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4033 | struct intel_connector *intel_connector, |
| 4034 | struct edp_power_seq *power_seq) |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4035 | { |
| 4036 | struct drm_connector *connector = &intel_connector->base; |
| 4037 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 4038 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4039 | struct drm_device *dev = intel_encoder->base.dev; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4040 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4041 | struct drm_display_mode *fixed_mode = NULL; |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 4042 | struct drm_display_mode *downclock_mode = NULL; |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4043 | bool has_dpcd; |
| 4044 | struct drm_display_mode *scan; |
| 4045 | struct edid *edid; |
| 4046 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 4047 | intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED; |
| 4048 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4049 | if (!is_edp(intel_dp)) |
| 4050 | return true; |
| 4051 | |
Paulo Zanoni | 6363521 | 2014-04-22 19:55:42 -0300 | [diff] [blame] | 4052 | /* The VDD bit needs a power domain reference, so if the bit is already |
| 4053 | * enabled when we boot, grab this reference. */ |
| 4054 | if (edp_have_panel_vdd(intel_dp)) { |
| 4055 | enum intel_display_power_domain power_domain; |
| 4056 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 4057 | intel_display_power_get(dev_priv, power_domain); |
| 4058 | } |
| 4059 | |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4060 | /* Cache DPCD and EDID for edp. */ |
Jani Nikula | 24f3e09 | 2014-03-17 16:43:36 +0200 | [diff] [blame] | 4061 | intel_edp_panel_vdd_on(intel_dp); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4062 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4063 | edp_panel_vdd_off(intel_dp, false); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4064 | |
| 4065 | if (has_dpcd) { |
| 4066 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 4067 | dev_priv->no_aux_handshake = |
| 4068 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
| 4069 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 4070 | } else { |
| 4071 | /* if this fails, presume the device is a ghost */ |
| 4072 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4073 | return false; |
| 4074 | } |
| 4075 | |
| 4076 | /* We now know it's not a ghost, init power sequence regs. */ |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4077 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4078 | |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 4079 | mutex_lock(&dev->mode_config.mutex); |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4080 | edid = drm_get_edid(connector, &intel_dp->aux.ddc); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4081 | if (edid) { |
| 4082 | if (drm_add_edid_modes(connector, edid)) { |
| 4083 | drm_mode_connector_update_edid_property(connector, |
| 4084 | edid); |
| 4085 | drm_edid_to_eld(connector, edid); |
| 4086 | } else { |
| 4087 | kfree(edid); |
| 4088 | edid = ERR_PTR(-EINVAL); |
| 4089 | } |
| 4090 | } else { |
| 4091 | edid = ERR_PTR(-ENOENT); |
| 4092 | } |
| 4093 | intel_connector->edid = edid; |
| 4094 | |
| 4095 | /* prefer fixed mode from EDID if available */ |
| 4096 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 4097 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 4098 | fixed_mode = drm_mode_duplicate(dev, scan); |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 4099 | downclock_mode = intel_dp_drrs_init( |
| 4100 | intel_dig_port, |
| 4101 | intel_connector, fixed_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4102 | break; |
| 4103 | } |
| 4104 | } |
| 4105 | |
| 4106 | /* fallback to VBT if available for eDP */ |
| 4107 | if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) { |
| 4108 | fixed_mode = drm_mode_duplicate(dev, |
| 4109 | dev_priv->vbt.lfp_lvds_vbt_mode); |
| 4110 | if (fixed_mode) |
| 4111 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 4112 | } |
Daniel Vetter | 060c877 | 2014-03-21 23:22:35 +0100 | [diff] [blame] | 4113 | mutex_unlock(&dev->mode_config.mutex); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4114 | |
Pradeep Bhat | 4f9db5b | 2014-04-05 12:12:31 +0530 | [diff] [blame] | 4115 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
Paulo Zanoni | ed92f0b | 2013-06-12 17:27:24 -0300 | [diff] [blame] | 4116 | intel_panel_setup_backlight(connector); |
| 4117 | |
| 4118 | return true; |
| 4119 | } |
| 4120 | |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 4121 | bool |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4122 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
| 4123 | struct intel_connector *intel_connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4124 | { |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4125 | struct drm_connector *connector = &intel_connector->base; |
| 4126 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
| 4127 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
| 4128 | struct drm_device *dev = intel_encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4129 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 4130 | enum port port = intel_dig_port->port; |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4131 | struct edp_power_seq power_seq = { 0 }; |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4132 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4133 | |
Damien Lespiau | ec5b01d | 2014-01-21 13:35:39 +0000 | [diff] [blame] | 4134 | /* intel_dp vfuncs */ |
| 4135 | if (IS_VALLEYVIEW(dev)) |
| 4136 | intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider; |
| 4137 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
| 4138 | intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; |
| 4139 | else if (HAS_PCH_SPLIT(dev)) |
| 4140 | intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; |
| 4141 | else |
| 4142 | intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider; |
| 4143 | |
Damien Lespiau | 153b110 | 2014-01-21 13:37:15 +0000 | [diff] [blame] | 4144 | intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl; |
| 4145 | |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 4146 | /* Preserve the current hw state. */ |
| 4147 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 4148 | intel_dp->attached_connector = intel_connector; |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 4149 | |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 4150 | if (intel_dp_is_edp(dev, port)) |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 4151 | type = DRM_MODE_CONNECTOR_eDP; |
Ville Syrjälä | 3b32a35 | 2013-11-01 18:22:41 +0200 | [diff] [blame] | 4152 | else |
| 4153 | type = DRM_MODE_CONNECTOR_DisplayPort; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 4154 | |
Imre Deak | f7d2490 | 2013-05-08 13:14:05 +0300 | [diff] [blame] | 4155 | /* |
| 4156 | * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but |
| 4157 | * for DP the encoder type can be set by the caller to |
| 4158 | * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. |
| 4159 | */ |
| 4160 | if (type == DRM_MODE_CONNECTOR_eDP) |
| 4161 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 4162 | |
Imre Deak | e7281ea | 2013-05-08 13:14:08 +0300 | [diff] [blame] | 4163 | DRM_DEBUG_KMS("Adding %s connector on port %c\n", |
| 4164 | type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", |
| 4165 | port_name(port)); |
| 4166 | |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 4167 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4168 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 4169 | |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4170 | connector->interlace_allowed = true; |
| 4171 | connector->doublescan_allowed = 0; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 4172 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 4173 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4174 | edp_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 4175 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 4176 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4177 | drm_sysfs_connector_add(connector); |
| 4178 | |
Paulo Zanoni | affa935 | 2012-11-23 15:30:39 -0200 | [diff] [blame] | 4179 | if (HAS_DDI(dev)) |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 4180 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
| 4181 | else |
| 4182 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 80f65de | 2014-02-11 17:12:49 +0200 | [diff] [blame] | 4183 | intel_connector->unregister = intel_dp_connector_unregister; |
Paulo Zanoni | bcbc889 | 2012-10-26 19:05:51 -0200 | [diff] [blame] | 4184 | |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4185 | /* Set up the hotplug pin. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 4186 | switch (port) { |
| 4187 | case PORT_A: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 4188 | intel_encoder->hpd_pin = HPD_PORT_A; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 4189 | break; |
| 4190 | case PORT_B: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 4191 | intel_encoder->hpd_pin = HPD_PORT_B; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 4192 | break; |
| 4193 | case PORT_C: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 4194 | intel_encoder->hpd_pin = HPD_PORT_C; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 4195 | break; |
| 4196 | case PORT_D: |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 4197 | intel_encoder->hpd_pin = HPD_PORT_D; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 4198 | break; |
| 4199 | default: |
Damien Lespiau | ad1c0b1 | 2013-03-07 15:30:28 +0000 | [diff] [blame] | 4200 | BUG(); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 4201 | } |
| 4202 | |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4203 | if (is_edp(intel_dp)) { |
| 4204 | intel_dp_init_panel_power_timestamps(intel_dp); |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4205 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
Imre Deak | dada1a9 | 2014-01-29 13:25:41 +0200 | [diff] [blame] | 4206 | } |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4207 | |
Jani Nikula | 9d1a103 | 2014-03-14 16:51:15 +0200 | [diff] [blame] | 4208 | intel_dp_aux_init(intel_dp, intel_connector); |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 4209 | |
Rodrigo Vivi | 2b28bb1 | 2013-07-11 18:44:58 -0300 | [diff] [blame] | 4210 | intel_dp->psr_setup_done = false; |
| 4211 | |
Paulo Zanoni | 0095e6d | 2013-12-19 14:29:39 -0200 | [diff] [blame] | 4212 | if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) { |
Jani Nikula | 0b99836 | 2014-03-14 16:51:17 +0200 | [diff] [blame] | 4213 | drm_dp_aux_unregister_i2c_bus(&intel_dp->aux); |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 4214 | if (is_edp(intel_dp)) { |
| 4215 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 4216 | mutex_lock(&dev->mode_config.mutex); |
Daniel Vetter | 4be7378 | 2014-01-17 14:39:48 +0100 | [diff] [blame] | 4217 | edp_panel_vdd_off_sync(intel_dp); |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 4218 | mutex_unlock(&dev->mode_config.mutex); |
| 4219 | } |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 4220 | drm_sysfs_connector_remove(connector); |
| 4221 | drm_connector_cleanup(connector); |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 4222 | return false; |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 4223 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 4224 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 4225 | intel_dp_add_properties(intel_dp, connector); |
| 4226 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4227 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 4228 | * 0xd. Failure to do so will result in spurious interrupts being |
| 4229 | * generated on the port when a cable is not attached. |
| 4230 | */ |
| 4231 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 4232 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 4233 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 4234 | } |
Paulo Zanoni | 16c2553 | 2013-06-12 17:27:25 -0300 | [diff] [blame] | 4235 | |
| 4236 | return true; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 4237 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4238 | |
| 4239 | void |
| 4240 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
| 4241 | { |
| 4242 | struct intel_digital_port *intel_dig_port; |
| 4243 | struct intel_encoder *intel_encoder; |
| 4244 | struct drm_encoder *encoder; |
| 4245 | struct intel_connector *intel_connector; |
| 4246 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 4247 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4248 | if (!intel_dig_port) |
| 4249 | return; |
| 4250 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 4251 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4252 | if (!intel_connector) { |
| 4253 | kfree(intel_dig_port); |
| 4254 | return; |
| 4255 | } |
| 4256 | |
| 4257 | intel_encoder = &intel_dig_port->base; |
| 4258 | encoder = &intel_encoder->base; |
| 4259 | |
| 4260 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
| 4261 | DRM_MODE_ENCODER_TMDS); |
| 4262 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 4263 | intel_encoder->compute_config = intel_dp_compute_config; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4264 | intel_encoder->disable = intel_disable_dp; |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4265 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 4266 | intel_encoder->get_config = intel_dp_get_config; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 4267 | if (IS_CHERRYVIEW(dev)) { |
| 4268 | intel_encoder->pre_enable = chv_pre_enable_dp; |
| 4269 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 580d381 | 2014-04-09 13:29:00 +0300 | [diff] [blame^] | 4270 | intel_encoder->post_disable = chv_post_disable_dp; |
Chon Ming Lee | e4a1d84 | 2014-04-09 13:28:20 +0300 | [diff] [blame] | 4271 | } else if (IS_VALLEYVIEW(dev)) { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 4272 | intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 4273 | intel_encoder->pre_enable = vlv_pre_enable_dp; |
| 4274 | intel_encoder->enable = vlv_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 4275 | intel_encoder->post_disable = vlv_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 4276 | } else { |
Jani Nikula | ecff4f3 | 2013-09-06 07:38:29 +0300 | [diff] [blame] | 4277 | intel_encoder->pre_enable = g4x_pre_enable_dp; |
| 4278 | intel_encoder->enable = g4x_enable_dp; |
Ville Syrjälä | 49277c3 | 2014-03-31 18:21:26 +0300 | [diff] [blame] | 4279 | intel_encoder->post_disable = g4x_post_disable_dp; |
Jani Nikula | ab1f90f | 2013-07-30 12:20:30 +0300 | [diff] [blame] | 4280 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4281 | |
Paulo Zanoni | 174edf1 | 2012-10-26 19:05:50 -0200 | [diff] [blame] | 4282 | intel_dig_port->port = port; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4283 | intel_dig_port->dp.output_reg = output_reg; |
| 4284 | |
Paulo Zanoni | 00c09d7 | 2012-10-26 19:05:52 -0200 | [diff] [blame] | 4285 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
Ville Syrjälä | 882ec38 | 2014-04-28 14:07:43 +0300 | [diff] [blame] | 4286 | if (IS_CHERRYVIEW(dev)) { |
| 4287 | if (port == PORT_D) |
| 4288 | intel_encoder->crtc_mask = 1 << 2; |
| 4289 | else |
| 4290 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
| 4291 | } else { |
| 4292 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
| 4293 | } |
Ville Syrjälä | bc079e8 | 2014-03-03 16:15:28 +0200 | [diff] [blame] | 4294 | intel_encoder->cloneable = 0; |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4295 | intel_encoder->hot_plug = intel_dp_hot_plug; |
| 4296 | |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 4297 | if (!intel_dp_init_connector(intel_dig_port, intel_connector)) { |
| 4298 | drm_encoder_cleanup(encoder); |
| 4299 | kfree(intel_dig_port); |
Paulo Zanoni | b2f246a | 2013-06-12 17:27:26 -0300 | [diff] [blame] | 4300 | kfree(intel_connector); |
Paulo Zanoni | 15b1d17 | 2013-06-12 17:27:27 -0300 | [diff] [blame] | 4301 | } |
Paulo Zanoni | f0fec3f | 2012-10-26 19:05:48 -0200 | [diff] [blame] | 4302 | } |