Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2006-2007 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | */ |
| 26 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 27 | #include <linux/dmi.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 30 | #include <drm/drmP.h> |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 31 | #include <drm/drm_atomic_helper.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_edid.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 37 | #include "i915_drv.h" |
| 38 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 39 | /* Here's the desired hotplug mode */ |
| 40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ |
| 41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ |
| 42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ |
| 43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ |
| 44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ |
| 45 | ADPA_CRT_HOTPLUG_ENABLE) |
| 46 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 47 | struct intel_crt { |
| 48 | struct intel_encoder base; |
Adam Jackson | 637f44d | 2013-03-25 15:40:05 -0400 | [diff] [blame] | 49 | /* DPMS state is stored in the connector, which we need in the |
| 50 | * encoder's enable/disable callbacks */ |
| 51 | struct intel_connector *connector; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 52 | bool force_hotplug_required; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 53 | i915_reg_t adpa_reg; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 54 | }; |
| 55 | |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 57 | { |
Daniel Vetter | 540a895 | 2012-07-11 16:27:57 +0200 | [diff] [blame] | 58 | return container_of(encoder, struct intel_crt, base); |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 59 | } |
| 60 | |
Daniel Vetter | eebe6f0 | 2013-07-21 21:37:03 +0200 | [diff] [blame] | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
| 62 | { |
| 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
| 64 | } |
| 65 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
| 67 | enum pipe *pipe) |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 68 | { |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 69 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 72 | enum intel_display_power_domain power_domain; |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 73 | u32 tmp; |
Imre Deak | 1c8fdda | 2016-02-12 18:55:15 +0200 | [diff] [blame] | 74 | bool ret; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 75 | |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 76 | power_domain = intel_display_port_power_domain(encoder); |
Imre Deak | 1c8fdda | 2016-02-12 18:55:15 +0200 | [diff] [blame] | 77 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
Imre Deak | 6d129be | 2014-03-05 16:20:54 +0200 | [diff] [blame] | 78 | return false; |
| 79 | |
Imre Deak | 1c8fdda | 2016-02-12 18:55:15 +0200 | [diff] [blame] | 80 | ret = false; |
| 81 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 82 | tmp = I915_READ(crt->adpa_reg); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 83 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 84 | if (!(tmp & ADPA_DAC_ENABLE)) |
Imre Deak | 1c8fdda | 2016-02-12 18:55:15 +0200 | [diff] [blame] | 85 | goto out; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 86 | |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 87 | if (HAS_PCH_CPT(dev)) |
| 88 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 89 | else |
| 90 | *pipe = PORT_TO_PIPE(tmp); |
| 91 | |
Imre Deak | 1c8fdda | 2016-02-12 18:55:15 +0200 | [diff] [blame] | 92 | ret = true; |
| 93 | out: |
| 94 | intel_display_power_put(dev_priv, power_domain); |
| 95 | |
| 96 | return ret; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 97 | } |
| 98 | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 99 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 100 | { |
| 101 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
| 102 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
| 103 | u32 tmp, flags = 0; |
| 104 | |
| 105 | tmp = I915_READ(crt->adpa_reg); |
| 106 | |
| 107 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) |
| 108 | flags |= DRM_MODE_FLAG_PHSYNC; |
| 109 | else |
| 110 | flags |= DRM_MODE_FLAG_NHSYNC; |
| 111 | |
| 112 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) |
| 113 | flags |= DRM_MODE_FLAG_PVSYNC; |
| 114 | else |
| 115 | flags |= DRM_MODE_FLAG_NVSYNC; |
| 116 | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 117 | return flags; |
| 118 | } |
| 119 | |
| 120 | static void intel_crt_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 121 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 122 | { |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 123 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
Ville Syrjälä | 18442d0 | 2013-09-13 16:00:08 +0300 | [diff] [blame] | 124 | |
Ville Syrjälä | e3b247d | 2016-02-17 21:41:09 +0200 | [diff] [blame] | 125 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
Jesse Barnes | 045ac3b | 2013-05-14 17:08:26 -0700 | [diff] [blame] | 126 | } |
| 127 | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 128 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 129 | struct intel_crtc_state *pipe_config) |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 130 | { |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 131 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
| 132 | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 133 | intel_ddi_get_config(encoder, pipe_config); |
| 134 | |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 135 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 136 | DRM_MODE_FLAG_NHSYNC | |
| 137 | DRM_MODE_FLAG_PVSYNC | |
| 138 | DRM_MODE_FLAG_NVSYNC); |
Ander Conselvan de Oliveira | 2d112de | 2015-01-15 14:55:22 +0200 | [diff] [blame] | 139 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
Ville Syrjälä | 8802e5b | 2016-02-17 21:41:12 +0200 | [diff] [blame] | 140 | |
| 141 | pipe_config->base.adjusted_mode.crtc_clock = lpt_get_iclkip(dev_priv); |
Ville Syrjälä | 6801c18 | 2013-09-24 14:24:05 +0300 | [diff] [blame] | 142 | } |
| 143 | |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 144 | /* Note: The caller is required to filter out dpms modes not supported by the |
| 145 | * platform. */ |
| 146 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 147 | { |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 148 | struct drm_device *dev = encoder->base.dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 149 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 150 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 151 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
Ville Syrjälä | 7c5f93b | 2015-09-08 13:40:49 +0300 | [diff] [blame] | 152 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 153 | u32 adpa; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 154 | |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 155 | if (INTEL_INFO(dev)->gen >= 5) |
| 156 | adpa = ADPA_HOTPLUG_BITS; |
| 157 | else |
| 158 | adpa = 0; |
| 159 | |
| 160 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 161 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; |
| 162 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 163 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; |
| 164 | |
| 165 | /* For CPT allow 3 pipe config, for others just use A or B */ |
| 166 | if (HAS_PCH_LPT(dev)) |
| 167 | ; /* Those bits don't exist here */ |
| 168 | else if (HAS_PCH_CPT(dev)) |
| 169 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); |
| 170 | else if (crtc->pipe == 0) |
| 171 | adpa |= ADPA_PIPE_A_SELECT; |
| 172 | else |
| 173 | adpa |= ADPA_PIPE_B_SELECT; |
| 174 | |
| 175 | if (!HAS_PCH_SPLIT(dev)) |
| 176 | I915_WRITE(BCLRPAT(crtc->pipe), 0); |
Jesse Barnes | bd9e841 | 2012-06-15 11:55:18 -0700 | [diff] [blame] | 177 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 178 | switch (mode) { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 179 | case DRM_MODE_DPMS_ON: |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 180 | adpa |= ADPA_DAC_ENABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 181 | break; |
| 182 | case DRM_MODE_DPMS_STANDBY: |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 183 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 184 | break; |
| 185 | case DRM_MODE_DPMS_SUSPEND: |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 186 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 187 | break; |
| 188 | case DRM_MODE_DPMS_OFF: |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 189 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 190 | break; |
| 191 | } |
| 192 | |
Daniel Vetter | 894ed1e | 2014-04-24 23:54:44 +0200 | [diff] [blame] | 193 | I915_WRITE(crt->adpa_reg, adpa); |
Daniel Vetter | b2cabb0 | 2012-07-01 22:42:24 +0200 | [diff] [blame] | 194 | } |
| 195 | |
Adam Jackson | 637f44d | 2013-03-25 15:40:05 -0400 | [diff] [blame] | 196 | static void intel_disable_crt(struct intel_encoder *encoder) |
| 197 | { |
| 198 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); |
| 199 | } |
| 200 | |
Ville Syrjälä | 1ea56e2 | 2015-05-05 17:17:37 +0300 | [diff] [blame] | 201 | static void pch_disable_crt(struct intel_encoder *encoder) |
| 202 | { |
| 203 | } |
| 204 | |
| 205 | static void pch_post_disable_crt(struct intel_encoder *encoder) |
| 206 | { |
| 207 | intel_disable_crt(encoder); |
| 208 | } |
Daniel Vetter | abfdc1e | 2014-06-25 22:01:52 +0300 | [diff] [blame] | 209 | |
Adam Jackson | 637f44d | 2013-03-25 15:40:05 -0400 | [diff] [blame] | 210 | static void intel_enable_crt(struct intel_encoder *encoder) |
| 211 | { |
Maarten Lankhorst | 7bb4afb | 2016-02-17 09:18:38 +0100 | [diff] [blame] | 212 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_ON); |
Adam Jackson | 637f44d | 2013-03-25 15:40:05 -0400 | [diff] [blame] | 213 | } |
| 214 | |
Damien Lespiau | c19de8e | 2013-11-28 15:29:18 +0000 | [diff] [blame] | 215 | static enum drm_mode_status |
| 216 | intel_crt_mode_valid(struct drm_connector *connector, |
| 217 | struct drm_display_mode *mode) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 218 | { |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 219 | struct drm_device *dev = connector->dev; |
Mika Kahola | f8700b3 | 2016-02-02 15:16:42 +0200 | [diff] [blame] | 220 | int max_dotclk = to_i915(dev)->max_dotclk_freq; |
Ville Syrjälä | debded8 | 2016-02-17 21:41:13 +0200 | [diff] [blame] | 221 | int max_clock; |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 222 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 223 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
| 224 | return MODE_NO_DBLESCAN; |
| 225 | |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 226 | if (mode->clock < 25000) |
| 227 | return MODE_CLOCK_LOW; |
| 228 | |
Ville Syrjälä | debded8 | 2016-02-17 21:41:13 +0200 | [diff] [blame] | 229 | if (HAS_PCH_LPT(dev)) |
| 230 | max_clock = 180000; |
| 231 | else if (IS_VALLEYVIEW(dev)) |
| 232 | /* |
| 233 | * 270 MHz due to current DPLL limits, |
| 234 | * DAC limit supposedly 355 MHz. |
| 235 | */ |
| 236 | max_clock = 270000; |
| 237 | else if (IS_GEN3(dev) || IS_GEN4(dev)) |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 238 | max_clock = 400000; |
Ville Syrjälä | debded8 | 2016-02-17 21:41:13 +0200 | [diff] [blame] | 239 | else |
| 240 | max_clock = 350000; |
Zhao Yakui | 6bcdcd9 | 2009-03-03 18:06:42 +0800 | [diff] [blame] | 241 | if (mode->clock > max_clock) |
| 242 | return MODE_CLOCK_HIGH; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 243 | |
Mika Kahola | f8700b3 | 2016-02-02 15:16:42 +0200 | [diff] [blame] | 244 | if (mode->clock > max_dotclk) |
| 245 | return MODE_CLOCK_HIGH; |
| 246 | |
Paulo Zanoni | d4b1931 | 2012-11-29 11:29:32 -0200 | [diff] [blame] | 247 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
| 248 | if (HAS_PCH_LPT(dev) && |
| 249 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) |
| 250 | return MODE_CLOCK_HIGH; |
| 251 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 252 | return MODE_OK; |
| 253 | } |
| 254 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 255 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
Ander Conselvan de Oliveira | 5cec258 | 2015-01-15 14:55:21 +0200 | [diff] [blame] | 256 | struct intel_crtc_state *pipe_config) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 257 | { |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 258 | struct drm_device *dev = encoder->base.dev; |
| 259 | |
| 260 | if (HAS_PCH_SPLIT(dev)) |
| 261 | pipe_config->has_pch_encoder = true; |
| 262 | |
Daniel Vetter | 2a7acee | 2013-04-19 11:24:39 +0200 | [diff] [blame] | 263 | /* LPT FDI RX only supports 8bpc. */ |
Daniel Vetter | f58a1ac | 2016-05-03 10:33:01 +0200 | [diff] [blame] | 264 | if (HAS_PCH_LPT(dev)) { |
| 265 | if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { |
| 266 | DRM_DEBUG_KMS("LPT only supports 24bpp\n"); |
| 267 | return false; |
| 268 | } |
| 269 | |
Daniel Vetter | 2a7acee | 2013-04-19 11:24:39 +0200 | [diff] [blame] | 270 | pipe_config->pipe_bpp = 24; |
Daniel Vetter | f58a1ac | 2016-05-03 10:33:01 +0200 | [diff] [blame] | 271 | } |
Daniel Vetter | 2a7acee | 2013-04-19 11:24:39 +0200 | [diff] [blame] | 272 | |
Ville Syrjälä | 8f7abfd | 2014-02-27 14:23:12 +0200 | [diff] [blame] | 273 | /* FDI must always be 2.7 GHz */ |
Ander Conselvan de Oliveira | daedf20 | 2016-03-08 17:46:23 +0200 | [diff] [blame] | 274 | if (HAS_DDI(dev)) |
Ville Syrjälä | 8f7abfd | 2014-02-27 14:23:12 +0200 | [diff] [blame] | 275 | pipe_config->port_clock = 135000 * 2; |
Maarten Lankhorst | 00490c2 | 2015-11-16 14:42:12 +0100 | [diff] [blame] | 276 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 277 | return true; |
| 278 | } |
| 279 | |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 280 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 281 | { |
| 282 | struct drm_device *dev = connector->dev; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 283 | struct intel_crt *crt = intel_attached_crt(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 284 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 285 | u32 adpa; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 286 | bool ret; |
| 287 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 288 | /* The first time through, trigger an explicit detection cycle */ |
| 289 | if (crt->force_hotplug_required) { |
| 290 | bool turn_off_dac = HAS_PCH_SPLIT(dev); |
| 291 | u32 save_adpa; |
Zhenyu Wang | 67941da | 2009-07-24 01:00:33 +0800 | [diff] [blame] | 292 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 293 | crt->force_hotplug_required = 0; |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 294 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 295 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 296 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
Dave Airlie | d5dd96c | 2010-08-04 15:52:19 +1000 | [diff] [blame] | 297 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 298 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 299 | if (turn_off_dac) |
| 300 | adpa &= ~ADPA_DAC_ENABLE; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 301 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 302 | I915_WRITE(crt->adpa_reg, adpa); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 303 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 304 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 305 | 1000)) |
| 306 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 307 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 308 | if (turn_off_dac) { |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 309 | I915_WRITE(crt->adpa_reg, save_adpa); |
| 310 | POSTING_READ(crt->adpa_reg); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 311 | } |
Zhenyu Wang | a4a6b90 | 2010-04-07 16:15:55 +0800 | [diff] [blame] | 312 | } |
| 313 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 314 | /* Check the status to see if both blue and green are on now */ |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 315 | adpa = I915_READ(crt->adpa_reg); |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 316 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 317 | ret = true; |
| 318 | else |
| 319 | ret = false; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 320 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 321 | |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 322 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 323 | } |
| 324 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 325 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
| 326 | { |
| 327 | struct drm_device *dev = connector->dev; |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 328 | struct intel_crt *crt = intel_attached_crt(connector); |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 329 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 330 | u32 adpa; |
| 331 | bool ret; |
| 332 | u32 save_adpa; |
| 333 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 334 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 335 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
| 336 | |
| 337 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; |
| 338 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 339 | I915_WRITE(crt->adpa_reg, adpa); |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 340 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 341 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 342 | 1000)) { |
| 343 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 344 | I915_WRITE(crt->adpa_reg, save_adpa); |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 345 | } |
| 346 | |
| 347 | /* Check the status to see if both blue and green are on now */ |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 348 | adpa = I915_READ(crt->adpa_reg); |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 349 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
| 350 | ret = true; |
| 351 | else |
| 352 | ret = false; |
| 353 | |
| 354 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); |
| 355 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 356 | return ret; |
| 357 | } |
| 358 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 359 | /** |
| 360 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. |
| 361 | * |
| 362 | * Not for i915G/i915GM |
| 363 | * |
| 364 | * \return true if CRT is connected. |
| 365 | * \return false if CRT is disconnected. |
| 366 | */ |
| 367 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) |
| 368 | { |
| 369 | struct drm_device *dev = connector->dev; |
| 370 | struct drm_i915_private *dev_priv = dev->dev_private; |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 371 | u32 stat; |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 372 | bool ret = false; |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 373 | int i, tries = 0; |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 374 | |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 375 | if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 376 | return intel_ironlake_crt_detect_hotplug(connector); |
Zhenyu Wang | 2c07245 | 2009-06-05 15:38:42 +0800 | [diff] [blame] | 377 | |
Jesse Barnes | 7d2c24e | 2012-06-15 11:55:15 -0700 | [diff] [blame] | 378 | if (IS_VALLEYVIEW(dev)) |
| 379 | return valleyview_crt_detect_hotplug(connector); |
| 380 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 381 | /* |
| 382 | * On 4 series desktop, CRT detect sequence need to be done twice |
| 383 | * to get a reliable result. |
| 384 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 385 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 386 | if (IS_G4X(dev) && !IS_GM45(dev)) |
| 387 | tries = 2; |
| 388 | else |
| 389 | tries = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 390 | |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 391 | for (i = 0; i < tries ; i++) { |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 392 | /* turn on the FORCE_DETECT */ |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 393 | i915_hotplug_interrupt_update(dev_priv, |
| 394 | CRT_HOTPLUG_FORCE_DETECT, |
| 395 | CRT_HOTPLUG_FORCE_DETECT); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 396 | /* wait for FORCE_DETECT to go off */ |
Chris Wilson | 913d8d1 | 2010-08-07 11:01:35 +0100 | [diff] [blame] | 397 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
| 398 | CRT_HOTPLUG_FORCE_DETECT) == 0, |
Chris Wilson | 481b6af | 2010-08-23 17:43:35 +0100 | [diff] [blame] | 399 | 1000)) |
Chris Wilson | 7907731 | 2010-09-12 19:58:04 +0100 | [diff] [blame] | 400 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
Zhao Yakui | 771cb08 | 2009-03-03 18:07:52 +0800 | [diff] [blame] | 401 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 402 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 403 | stat = I915_READ(PORT_HOTPLUG_STAT); |
| 404 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) |
| 405 | ret = true; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 406 | |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 407 | /* clear the interrupt we just generated, if any */ |
| 408 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); |
| 409 | |
Egbert Eich | 0706f17 | 2015-09-23 16:15:27 +0200 | [diff] [blame] | 410 | i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); |
Adam Jackson | 7a772c4 | 2010-05-24 16:46:29 -0400 | [diff] [blame] | 411 | |
| 412 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 413 | } |
| 414 | |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 415 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
| 416 | struct i2c_adapter *i2c) |
| 417 | { |
| 418 | struct edid *edid; |
| 419 | |
| 420 | edid = drm_get_edid(connector, i2c); |
| 421 | |
| 422 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { |
| 423 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); |
| 424 | intel_gmbus_force_bit(i2c, true); |
| 425 | edid = drm_get_edid(connector, i2c); |
| 426 | intel_gmbus_force_bit(i2c, false); |
| 427 | } |
| 428 | |
| 429 | return edid; |
| 430 | } |
| 431 | |
| 432 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ |
| 433 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, |
| 434 | struct i2c_adapter *adapter) |
| 435 | { |
| 436 | struct edid *edid; |
Jani Nikula | ebda95a | 2012-10-19 14:51:51 +0300 | [diff] [blame] | 437 | int ret; |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 438 | |
| 439 | edid = intel_crt_get_edid(connector, adapter); |
| 440 | if (!edid) |
| 441 | return 0; |
| 442 | |
Jani Nikula | ebda95a | 2012-10-19 14:51:51 +0300 | [diff] [blame] | 443 | ret = intel_connector_update_modes(connector, edid); |
| 444 | kfree(edid); |
| 445 | |
| 446 | return ret; |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 447 | } |
| 448 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 449 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 450 | { |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 451 | struct intel_crt *crt = intel_attached_crt(connector); |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 452 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 453 | struct edid *edid; |
| 454 | struct i2c_adapter *i2c; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 455 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 456 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 457 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 458 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 459 | edid = intel_crt_get_edid(connector, i2c); |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 460 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 461 | if (edid) { |
| 462 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; |
| 463 | |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 464 | /* |
| 465 | * This may be a DVI-I connector with a shared DDC |
| 466 | * link between analog and digital outputs, so we |
| 467 | * have to check the EDID input spec of the attached device. |
| 468 | */ |
David Müller | f5afcd3 | 2011-01-06 12:29:32 +0000 | [diff] [blame] | 469 | if (!is_digital) { |
| 470 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); |
| 471 | return true; |
| 472 | } |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 473 | |
| 474 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); |
| 475 | } else { |
| 476 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 477 | } |
| 478 | |
Daniel Vetter | a2bd1f5 | 2012-07-11 12:31:52 +0200 | [diff] [blame] | 479 | kfree(edid); |
| 480 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 481 | return false; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 482 | } |
| 483 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 484 | static enum drm_connector_status |
Maarten Lankhorst | c8ecb2f | 2016-02-17 09:18:36 +0100 | [diff] [blame] | 485 | intel_crt_load_detect(struct intel_crt *crt, uint32_t pipe) |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 486 | { |
Chris Wilson | 7173188 | 2011-04-19 23:10:58 +0100 | [diff] [blame] | 487 | struct drm_device *dev = crt->base.base.dev; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 488 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 489 | uint32_t save_bclrpat; |
| 490 | uint32_t save_vtotal; |
| 491 | uint32_t vtotal, vactive; |
| 492 | uint32_t vsample; |
| 493 | uint32_t vblank, vblank_start, vblank_end; |
| 494 | uint32_t dsl; |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 495 | i915_reg_t bclrpat_reg, vtotal_reg, |
| 496 | vblank_reg, vsync_reg, pipeconf_reg, pipe_dsl_reg; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 497 | uint8_t st00; |
| 498 | enum drm_connector_status status; |
| 499 | |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 500 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
| 501 | |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 502 | bclrpat_reg = BCLRPAT(pipe); |
| 503 | vtotal_reg = VTOTAL(pipe); |
| 504 | vblank_reg = VBLANK(pipe); |
| 505 | vsync_reg = VSYNC(pipe); |
| 506 | pipeconf_reg = PIPECONF(pipe); |
| 507 | pipe_dsl_reg = PIPEDSL(pipe); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 508 | |
| 509 | save_bclrpat = I915_READ(bclrpat_reg); |
| 510 | save_vtotal = I915_READ(vtotal_reg); |
| 511 | vblank = I915_READ(vblank_reg); |
| 512 | |
| 513 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; |
| 514 | vactive = (save_vtotal & 0x7ff) + 1; |
| 515 | |
| 516 | vblank_start = (vblank & 0xfff) + 1; |
| 517 | vblank_end = ((vblank >> 16) & 0xfff) + 1; |
| 518 | |
| 519 | /* Set the border color to purple. */ |
| 520 | I915_WRITE(bclrpat_reg, 0x500050); |
| 521 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 522 | if (!IS_GEN2(dev)) { |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 523 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
| 524 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); |
Chris Wilson | 19c55da | 2010-08-09 14:50:53 +0100 | [diff] [blame] | 525 | POSTING_READ(pipeconf_reg); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 526 | /* Wait for next Vblank to substitue |
| 527 | * border color for Color info */ |
Jesse Barnes | 9d0498a | 2010-08-18 13:20:54 -0700 | [diff] [blame] | 528 | intel_wait_for_vblank(dev, pipe); |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 529 | st00 = I915_READ8(_VGA_MSR_WRITE); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 530 | status = ((st00 & (1 << 4)) != 0) ? |
| 531 | connector_status_connected : |
| 532 | connector_status_disconnected; |
| 533 | |
| 534 | I915_WRITE(pipeconf_reg, pipeconf); |
| 535 | } else { |
| 536 | bool restore_vblank = false; |
| 537 | int count, detect; |
| 538 | |
| 539 | /* |
| 540 | * If there isn't any border, add some. |
| 541 | * Yes, this will flicker |
| 542 | */ |
| 543 | if (vblank_start <= vactive && vblank_end >= vtotal) { |
| 544 | uint32_t vsync = I915_READ(vsync_reg); |
| 545 | uint32_t vsync_start = (vsync & 0xffff) + 1; |
| 546 | |
| 547 | vblank_start = vsync_start; |
| 548 | I915_WRITE(vblank_reg, |
| 549 | (vblank_start - 1) | |
| 550 | ((vblank_end - 1) << 16)); |
| 551 | restore_vblank = true; |
| 552 | } |
| 553 | /* sample in the vertical border, selecting the larger one */ |
| 554 | if (vblank_start - vactive >= vtotal - vblank_end) |
| 555 | vsample = (vblank_start + vactive) >> 1; |
| 556 | else |
| 557 | vsample = (vtotal + vblank_end) >> 1; |
| 558 | |
| 559 | /* |
| 560 | * Wait for the border to be displayed |
| 561 | */ |
| 562 | while (I915_READ(pipe_dsl_reg) >= vactive) |
| 563 | ; |
| 564 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) |
| 565 | ; |
| 566 | /* |
| 567 | * Watch ST00 for an entire scanline |
| 568 | */ |
| 569 | detect = 0; |
| 570 | count = 0; |
| 571 | do { |
| 572 | count++; |
| 573 | /* Read the ST00 VGA status register */ |
Ville Syrjälä | f0f59a0 | 2015-11-18 15:33:26 +0200 | [diff] [blame] | 574 | st00 = I915_READ8(_VGA_MSR_WRITE); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 575 | if (st00 & (1 << 4)) |
| 576 | detect++; |
| 577 | } while ((I915_READ(pipe_dsl_reg) == dsl)); |
| 578 | |
| 579 | /* restore vblank if necessary */ |
| 580 | if (restore_vblank) |
| 581 | I915_WRITE(vblank_reg, vblank); |
| 582 | /* |
| 583 | * If more than 3/4 of the scanline detected a monitor, |
| 584 | * then it is assumed to be present. This works even on i830, |
| 585 | * where there isn't any way to force the border color across |
| 586 | * the screen |
| 587 | */ |
| 588 | status = detect * 4 > count * 3 ? |
| 589 | connector_status_connected : |
| 590 | connector_status_disconnected; |
| 591 | } |
| 592 | |
| 593 | /* Restore previous settings */ |
| 594 | I915_WRITE(bclrpat_reg, save_bclrpat); |
| 595 | |
| 596 | return status; |
| 597 | } |
| 598 | |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 599 | static enum drm_connector_status |
Chris Wilson | 930a9e2 | 2010-09-14 11:07:23 +0100 | [diff] [blame] | 600 | intel_crt_detect(struct drm_connector *connector, bool force) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 601 | { |
| 602 | struct drm_device *dev = connector->dev; |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 603 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 604 | struct intel_crt *crt = intel_attached_crt(connector); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 605 | struct intel_encoder *intel_encoder = &crt->base; |
| 606 | enum intel_display_power_domain power_domain; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 607 | enum drm_connector_status status; |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 608 | struct intel_load_detect_pipe tmp; |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 609 | struct drm_modeset_acquire_ctx ctx; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 610 | |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 611 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
Jani Nikula | c23cc41 | 2014-06-03 14:56:17 +0300 | [diff] [blame] | 612 | connector->base.id, connector->name, |
Chris Wilson | 164c859 | 2013-07-20 20:27:08 +0100 | [diff] [blame] | 613 | force); |
| 614 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 615 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 616 | intel_display_power_get(dev_priv, power_domain); |
| 617 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 618 | if (I915_HAS_HOTPLUG(dev)) { |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 619 | /* We can not rely on the HPD pin always being correctly wired |
| 620 | * up, for example many KVM do not pass it through, and so |
| 621 | * only trust an assertion that the monitor is connected. |
| 622 | */ |
Chris Wilson | 6ec3d0c | 2010-09-22 18:17:01 +0100 | [diff] [blame] | 623 | if (intel_crt_detect_hotplug(connector)) { |
| 624 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 625 | status = connector_status_connected; |
| 626 | goto out; |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 627 | } else |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 628 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 629 | } |
| 630 | |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 631 | if (intel_crt_detect_ddc(connector)) { |
| 632 | status = connector_status_connected; |
| 633 | goto out; |
| 634 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 635 | |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 636 | /* Load detection is broken on HPD capable machines. Whoever wants a |
| 637 | * broken monitor (without edid) to work behind a broken kvm (that fails |
| 638 | * to have the right resistors for HP detection) needs to fix this up. |
| 639 | * For now just bail out. */ |
Daniel Vetter | 5bedeb2 | 2015-03-03 18:03:47 +0100 | [diff] [blame] | 640 | if (I915_HAS_HOTPLUG(dev) && !i915.load_detect_test) { |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 641 | status = connector_status_disconnected; |
| 642 | goto out; |
| 643 | } |
Daniel Vetter | aaa3773 | 2012-06-16 15:30:32 +0200 | [diff] [blame] | 644 | |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 645 | if (!force) { |
| 646 | status = connector->status; |
| 647 | goto out; |
| 648 | } |
Chris Wilson | 7b334fc | 2010-09-09 23:51:02 +0100 | [diff] [blame] | 649 | |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 650 | drm_modeset_acquire_init(&ctx, 0); |
| 651 | |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 652 | /* for pre-945g platforms use load detect */ |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 653 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 654 | if (intel_crt_detect_ddc(connector)) |
| 655 | status = connector_status_connected; |
Daniel Vetter | 5bedeb2 | 2015-03-03 18:03:47 +0100 | [diff] [blame] | 656 | else if (INTEL_INFO(dev)->gen < 4) |
Maarten Lankhorst | c8ecb2f | 2016-02-17 09:18:36 +0100 | [diff] [blame] | 657 | status = intel_crt_load_detect(crt, |
| 658 | to_intel_crtc(connector->state->crtc)->pipe); |
Maarten Lankhorst | 32fff61 | 2016-03-01 17:04:01 +0100 | [diff] [blame] | 659 | else if (i915.load_detect_test) |
| 660 | status = connector_status_disconnected; |
Daniel Vetter | 5bedeb2 | 2015-03-03 18:03:47 +0100 | [diff] [blame] | 661 | else |
| 662 | status = connector_status_unknown; |
Ander Conselvan de Oliveira | 49172fe | 2015-03-20 16:18:02 +0200 | [diff] [blame] | 663 | intel_release_load_detect_pipe(connector, &tmp, &ctx); |
Daniel Vetter | e95c843 | 2012-04-20 21:03:36 +0200 | [diff] [blame] | 664 | } else |
| 665 | status = connector_status_unknown; |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 666 | |
Ville Syrjälä | 208bf9f | 2014-08-11 13:15:35 +0300 | [diff] [blame] | 667 | drm_modeset_drop_locks(&ctx); |
| 668 | drm_modeset_acquire_fini(&ctx); |
| 669 | |
Paulo Zanoni | c19a0df | 2014-02-21 13:52:22 -0300 | [diff] [blame] | 670 | out: |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 671 | intel_display_power_put(dev_priv, power_domain); |
Ma Ling | e4a5d54 | 2009-05-26 11:31:00 +0800 | [diff] [blame] | 672 | return status; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 673 | } |
| 674 | |
| 675 | static void intel_crt_destroy(struct drm_connector *connector) |
| 676 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 677 | drm_connector_cleanup(connector); |
| 678 | kfree(connector); |
| 679 | } |
| 680 | |
| 681 | static int intel_crt_get_modes(struct drm_connector *connector) |
| 682 | { |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 683 | struct drm_device *dev = connector->dev; |
Chris Wilson | f899fc6 | 2010-07-20 15:44:45 -0700 | [diff] [blame] | 684 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 685 | struct intel_crt *crt = intel_attached_crt(connector); |
| 686 | struct intel_encoder *intel_encoder = &crt->base; |
| 687 | enum intel_display_power_domain power_domain; |
Chris Wilson | 890f335 | 2010-09-14 16:46:59 +0100 | [diff] [blame] | 688 | int ret; |
Daniel Kurtz | 3bd7d90 | 2012-03-28 02:36:14 +0800 | [diff] [blame] | 689 | struct i2c_adapter *i2c; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 690 | |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 691 | power_domain = intel_display_port_power_domain(intel_encoder); |
| 692 | intel_display_power_get(dev_priv, power_domain); |
| 693 | |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 694 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
Jani Nikula | f1a2f5b | 2012-08-13 13:22:35 +0300 | [diff] [blame] | 695 | ret = intel_crt_ddc_get_modes(connector, i2c); |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 696 | if (ret || !IS_G4X(dev)) |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 697 | goto out; |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 698 | |
ling.ma@intel.com | 8e4d36b | 2009-06-30 11:35:34 +0800 | [diff] [blame] | 699 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
Jani Nikula | 988c701 | 2015-03-27 00:20:19 +0200 | [diff] [blame] | 700 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB); |
Imre Deak | 671dedd | 2014-03-05 16:20:53 +0200 | [diff] [blame] | 701 | ret = intel_crt_ddc_get_modes(connector, i2c); |
| 702 | |
| 703 | out: |
| 704 | intel_display_power_put(dev_priv, power_domain); |
| 705 | |
| 706 | return ret; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 707 | } |
| 708 | |
| 709 | static int intel_crt_set_property(struct drm_connector *connector, |
| 710 | struct drm_property *property, |
| 711 | uint64_t value) |
| 712 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 713 | return 0; |
| 714 | } |
| 715 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 716 | static void intel_crt_reset(struct drm_connector *connector) |
| 717 | { |
| 718 | struct drm_device *dev = connector->dev; |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 719 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 720 | struct intel_crt *crt = intel_attached_crt(connector); |
| 721 | |
Chris Wilson | 10603ca | 2013-08-26 19:51:06 -0300 | [diff] [blame] | 722 | if (INTEL_INFO(dev)->gen >= 5) { |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 723 | u32 adpa; |
| 724 | |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 725 | adpa = I915_READ(crt->adpa_reg); |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 726 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
| 727 | adpa |= ADPA_HOTPLUG_BITS; |
Ville Syrjälä | ca54b81 | 2013-01-25 21:44:42 +0200 | [diff] [blame] | 728 | I915_WRITE(crt->adpa_reg, adpa); |
| 729 | POSTING_READ(crt->adpa_reg); |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 730 | |
Ville Syrjälä | 0039a4b3 | 2014-10-16 20:52:30 +0300 | [diff] [blame] | 731 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 732 | crt->force_hotplug_required = 1; |
Daniel Vetter | 2e93889 | 2012-10-11 20:08:24 +0200 | [diff] [blame] | 733 | } |
| 734 | |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 735 | } |
| 736 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 737 | /* |
| 738 | * Routines for controlling stuff on the analog port |
| 739 | */ |
| 740 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 741 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
Chris Wilson | f326905 | 2011-01-24 15:17:08 +0000 | [diff] [blame] | 742 | .reset = intel_crt_reset, |
Maarten Lankhorst | 4d688a2 | 2015-08-05 12:37:06 +0200 | [diff] [blame] | 743 | .dpms = drm_atomic_helper_connector_dpms, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 744 | .detect = intel_crt_detect, |
| 745 | .fill_modes = drm_helper_probe_single_connector_modes, |
| 746 | .destroy = intel_crt_destroy, |
| 747 | .set_property = intel_crt_set_property, |
Matt Roper | c6f95f2 | 2015-01-22 16:50:32 -0800 | [diff] [blame] | 748 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
Ander Conselvan de Oliveira | 9896972 | 2015-03-20 16:18:06 +0200 | [diff] [blame] | 749 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
Matt Roper | 2545e4a | 2015-01-22 16:51:27 -0800 | [diff] [blame] | 750 | .atomic_get_property = intel_connector_atomic_get_property, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 751 | }; |
| 752 | |
| 753 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { |
| 754 | .mode_valid = intel_crt_mode_valid, |
| 755 | .get_modes = intel_crt_get_modes, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 756 | .best_encoder = intel_best_encoder, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 757 | }; |
| 758 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 759 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 760 | .destroy = intel_encoder_destroy, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 761 | }; |
| 762 | |
Mathias Krause | bbe1c27 | 2014-08-27 18:41:19 +0200 | [diff] [blame] | 763 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 764 | { |
Daniel Vetter | bc0daf4 | 2012-04-01 13:16:49 +0200 | [diff] [blame] | 765 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 766 | return 1; |
| 767 | } |
| 768 | |
| 769 | static const struct dmi_system_id intel_no_crt[] = { |
| 770 | { |
| 771 | .callback = intel_no_crt_dmi_callback, |
| 772 | .ident = "ACER ZGB", |
| 773 | .matches = { |
| 774 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), |
| 775 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), |
| 776 | }, |
| 777 | }, |
Giacomo Comes | 10b6ee4 | 2014-04-03 14:13:55 -0400 | [diff] [blame] | 778 | { |
| 779 | .callback = intel_no_crt_dmi_callback, |
| 780 | .ident = "DELL XPS 8700", |
| 781 | .matches = { |
| 782 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), |
| 783 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), |
| 784 | }, |
| 785 | }, |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 786 | { } |
| 787 | }; |
| 788 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 789 | void intel_crt_init(struct drm_device *dev) |
| 790 | { |
| 791 | struct drm_connector *connector; |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 792 | struct intel_crt *crt; |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 793 | struct intel_connector *intel_connector; |
David Müller (ELSOFT AG) | db54501 | 2009-08-29 08:54:45 +0200 | [diff] [blame] | 794 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 6c03a6b | 2015-11-20 22:35:41 +0200 | [diff] [blame] | 795 | i915_reg_t adpa_reg; |
| 796 | u32 adpa; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 797 | |
Duncan Laurie | 8ca4013 | 2011-10-25 15:42:21 -0700 | [diff] [blame] | 798 | /* Skip machines without VGA that falsely report hotplug events */ |
| 799 | if (dmi_check_system(intel_no_crt)) |
| 800 | return; |
| 801 | |
Ville Syrjälä | 6c03a6b | 2015-11-20 22:35:41 +0200 | [diff] [blame] | 802 | if (HAS_PCH_SPLIT(dev)) |
| 803 | adpa_reg = PCH_ADPA; |
| 804 | else if (IS_VALLEYVIEW(dev)) |
| 805 | adpa_reg = VLV_ADPA; |
| 806 | else |
| 807 | adpa_reg = ADPA; |
| 808 | |
| 809 | adpa = I915_READ(adpa_reg); |
| 810 | if ((adpa & ADPA_DAC_ENABLE) == 0) { |
| 811 | /* |
| 812 | * On some machines (some IVB at least) CRT can be |
| 813 | * fused off, but there's no known fuse bit to |
| 814 | * indicate that. On these machine the ADPA register |
| 815 | * works normally, except the DAC enable bit won't |
| 816 | * take. So the only way to tell is attempt to enable |
| 817 | * it and see what happens. |
| 818 | */ |
| 819 | I915_WRITE(adpa_reg, adpa | ADPA_DAC_ENABLE | |
| 820 | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE); |
| 821 | if ((I915_READ(adpa_reg) & ADPA_DAC_ENABLE) == 0) |
| 822 | return; |
| 823 | I915_WRITE(adpa_reg, adpa); |
| 824 | } |
| 825 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 826 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
| 827 | if (!crt) |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 828 | return; |
| 829 | |
Ander Conselvan de Oliveira | 9bdbd0b | 2015-04-10 10:59:10 +0300 | [diff] [blame] | 830 | intel_connector = intel_connector_alloc(); |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 831 | if (!intel_connector) { |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 832 | kfree(crt); |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 833 | return; |
| 834 | } |
| 835 | |
| 836 | connector = &intel_connector->base; |
Adam Jackson | 637f44d | 2013-03-25 15:40:05 -0400 | [diff] [blame] | 837 | crt->connector = intel_connector; |
Zhenyu Wang | 454c1ca | 2010-03-29 15:53:23 +0800 | [diff] [blame] | 838 | drm_connector_init(dev, &intel_connector->base, |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 839 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
| 840 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 841 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
Ville Syrjälä | 580d8ed | 2016-05-27 20:59:24 +0300 | [diff] [blame^] | 842 | DRM_MODE_ENCODER_DAC, "CRT"); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 843 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 844 | intel_connector_attach_encoder(intel_connector, &crt->base); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 845 | |
Chris Wilson | c9a1c4c | 2010-11-16 10:58:37 +0000 | [diff] [blame] | 846 | crt->base.type = INTEL_OUTPUT_ANALOG; |
Ville Syrjälä | 301ea74 | 2014-03-03 16:15:30 +0200 | [diff] [blame] | 847 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
Paulo Zanoni | d63fa0d | 2012-11-20 13:27:35 -0200 | [diff] [blame] | 848 | if (IS_I830(dev)) |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 849 | crt->base.crtc_mask = (1 << 0); |
| 850 | else |
Keith Packard | 0826874 | 2012-08-13 21:34:45 -0700 | [diff] [blame] | 851 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Eugeni Dodonov | 59c859d | 2012-05-09 15:37:19 -0300 | [diff] [blame] | 852 | |
Daniel Vetter | dbb0257 | 2012-01-28 14:49:23 +0100 | [diff] [blame] | 853 | if (IS_GEN2(dev)) |
| 854 | connector->interlace_allowed = 0; |
| 855 | else |
| 856 | connector->interlace_allowed = 1; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 857 | connector->doublescan_allowed = 0; |
| 858 | |
Ville Syrjälä | 6c03a6b | 2015-11-20 22:35:41 +0200 | [diff] [blame] | 859 | crt->adpa_reg = adpa_reg; |
Jesse Barnes | df0323c | 2012-04-17 15:06:33 -0700 | [diff] [blame] | 860 | |
Daniel Vetter | 5bfe2ac | 2013-03-27 00:44:55 +0100 | [diff] [blame] | 861 | crt->base.compute_config = intel_crt_compute_config; |
Ville Syrjälä | 92966a3 | 2015-12-08 16:05:48 +0200 | [diff] [blame] | 862 | if (HAS_PCH_SPLIT(dev)) { |
Ville Syrjälä | 1ea56e2 | 2015-05-05 17:17:37 +0300 | [diff] [blame] | 863 | crt->base.disable = pch_disable_crt; |
| 864 | crt->base.post_disable = pch_post_disable_crt; |
| 865 | } else { |
| 866 | crt->base.disable = intel_disable_crt; |
| 867 | } |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 868 | crt->base.enable = intel_enable_crt; |
Egbert Eich | 1d843f9 | 2013-02-25 12:06:49 -0500 | [diff] [blame] | 869 | if (I915_HAS_HOTPLUG(dev)) |
| 870 | crt->base.hpd_pin = HPD_CRT; |
Ville Syrjälä | a298579 | 2013-11-07 19:25:59 +0200 | [diff] [blame] | 871 | if (HAS_DDI(dev)) { |
| 872 | crt->base.get_config = hsw_crt_get_config; |
Paulo Zanoni | 4eda01b | 2012-10-31 18:12:21 -0200 | [diff] [blame] | 873 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
Ville Syrjälä | a298579 | 2013-11-07 19:25:59 +0200 | [diff] [blame] | 874 | } else { |
| 875 | crt->base.get_config = intel_crt_get_config; |
Paulo Zanoni | 4eda01b | 2012-10-31 18:12:21 -0200 | [diff] [blame] | 876 | crt->base.get_hw_state = intel_crt_get_hw_state; |
Ville Syrjälä | a298579 | 2013-11-07 19:25:59 +0200 | [diff] [blame] | 877 | } |
Daniel Vetter | e403fc9 | 2012-07-02 13:41:21 +0200 | [diff] [blame] | 878 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Imre Deak | 4932e2c | 2014-02-11 17:12:48 +0200 | [diff] [blame] | 879 | intel_connector->unregister = intel_connector_unregister; |
Daniel Vetter | 2124604 | 2012-07-01 14:58:27 +0200 | [diff] [blame] | 880 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 881 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
| 882 | |
Thomas Wood | 34ea3d3 | 2014-05-29 16:57:41 +0100 | [diff] [blame] | 883 | drm_connector_register(connector); |
Jesse Barnes | b01f2c3 | 2009-12-11 11:07:17 -0800 | [diff] [blame] | 884 | |
Egbert Eich | 821450c | 2013-04-16 13:36:55 +0200 | [diff] [blame] | 885 | if (!I915_HAS_HOTPLUG(dev)) |
| 886 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 887 | |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 888 | /* |
| 889 | * Configure the automatic hotplug detection stuff |
| 890 | */ |
| 891 | crt->force_hotplug_required = 0; |
Keith Packard | e7dbb2f | 2010-11-16 16:03:53 +0800 | [diff] [blame] | 892 | |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 893 | /* |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 894 | * TODO: find a proper way to discover whether we need to set the the |
| 895 | * polarity and link reversal bits or not, instead of relying on the |
| 896 | * BIOS. |
Paulo Zanoni | 68d18ad | 2012-12-01 12:04:26 -0200 | [diff] [blame] | 897 | */ |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 898 | if (HAS_PCH_LPT(dev)) { |
| 899 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | |
| 900 | FDI_RX_LINK_REVERSAL_OVERRIDE; |
| 901 | |
Ville Syrjälä | eede3b5 | 2015-09-18 20:03:30 +0300 | [diff] [blame] | 902 | dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; |
Damien Lespiau | 3e68320 | 2012-12-11 18:48:29 +0000 | [diff] [blame] | 903 | } |
Daniel Vetter | 754970e | 2014-01-16 22:28:44 +0100 | [diff] [blame] | 904 | |
| 905 | intel_crt_reset(connector); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 906 | } |