Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | |
| 33 | #ifndef MLX5_DRIVER_H |
| 34 | #define MLX5_DRIVER_H |
| 35 | |
| 36 | #include <linux/kernel.h> |
| 37 | #include <linux/completion.h> |
| 38 | #include <linux/pci.h> |
| 39 | #include <linux/spinlock_types.h> |
| 40 | #include <linux/semaphore.h> |
Roland Dreier | 6ecde51 | 2014-02-13 20:45:17 -0800 | [diff] [blame] | 41 | #include <linux/slab.h> |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 42 | #include <linux/vmalloc.h> |
| 43 | #include <linux/radix-tree.h> |
Roland Dreier | 6ecde51 | 2014-02-13 20:45:17 -0800 | [diff] [blame] | 44 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 45 | #include <linux/mlx5/device.h> |
| 46 | #include <linux/mlx5/doorbell.h> |
| 47 | |
| 48 | enum { |
| 49 | MLX5_BOARD_ID_LEN = 64, |
| 50 | MLX5_MAX_NAME_LEN = 16, |
| 51 | }; |
| 52 | |
| 53 | enum { |
| 54 | /* one minute for the sake of bringup. Generally, commands must always |
| 55 | * complete and we may need to increase this timeout value |
| 56 | */ |
| 57 | MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, |
| 58 | MLX5_CMD_WQ_MAX_NAME = 32, |
| 59 | }; |
| 60 | |
| 61 | enum { |
| 62 | CMD_OWNER_SW = 0x0, |
| 63 | CMD_OWNER_HW = 0x1, |
| 64 | CMD_STATUS_SUCCESS = 0, |
| 65 | }; |
| 66 | |
| 67 | enum mlx5_sqp_t { |
| 68 | MLX5_SQP_SMI = 0, |
| 69 | MLX5_SQP_GSI = 1, |
| 70 | MLX5_SQP_IEEE_1588 = 2, |
| 71 | MLX5_SQP_SNIFFER = 3, |
| 72 | MLX5_SQP_SYNC_UMR = 4, |
| 73 | }; |
| 74 | |
| 75 | enum { |
| 76 | MLX5_MAX_PORTS = 2, |
| 77 | }; |
| 78 | |
| 79 | enum { |
| 80 | MLX5_EQ_VEC_PAGES = 0, |
| 81 | MLX5_EQ_VEC_CMD = 1, |
| 82 | MLX5_EQ_VEC_ASYNC = 2, |
| 83 | MLX5_EQ_VEC_COMP_BASE, |
| 84 | }; |
| 85 | |
| 86 | enum { |
Sagi Grimberg | ada9f5d | 2013-09-11 16:35:34 +0300 | [diff] [blame] | 87 | MLX5_MAX_EQ_NAME = 32 |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 88 | }; |
| 89 | |
| 90 | enum { |
| 91 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, |
| 92 | MLX5_ATOMIC_MODE_CX = 2 << 16, |
| 93 | MLX5_ATOMIC_MODE_8B = 3 << 16, |
| 94 | MLX5_ATOMIC_MODE_16B = 4 << 16, |
| 95 | MLX5_ATOMIC_MODE_32B = 5 << 16, |
| 96 | MLX5_ATOMIC_MODE_64B = 6 << 16, |
| 97 | MLX5_ATOMIC_MODE_128B = 7 << 16, |
| 98 | MLX5_ATOMIC_MODE_256B = 8 << 16, |
| 99 | }; |
| 100 | |
| 101 | enum { |
| 102 | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, |
| 103 | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, |
| 104 | MLX5_CMD_OP_INIT_HCA = 0x102, |
| 105 | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, |
Eli Cohen | cd23b14 | 2013-07-18 15:31:08 +0300 | [diff] [blame] | 106 | MLX5_CMD_OP_ENABLE_HCA = 0x104, |
| 107 | MLX5_CMD_OP_DISABLE_HCA = 0x105, |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 108 | MLX5_CMD_OP_QUERY_PAGES = 0x107, |
| 109 | MLX5_CMD_OP_MANAGE_PAGES = 0x108, |
| 110 | MLX5_CMD_OP_SET_HCA_CAP = 0x109, |
| 111 | |
| 112 | MLX5_CMD_OP_CREATE_MKEY = 0x200, |
| 113 | MLX5_CMD_OP_QUERY_MKEY = 0x201, |
| 114 | MLX5_CMD_OP_DESTROY_MKEY = 0x202, |
| 115 | MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, |
| 116 | |
| 117 | MLX5_CMD_OP_CREATE_EQ = 0x301, |
| 118 | MLX5_CMD_OP_DESTROY_EQ = 0x302, |
| 119 | MLX5_CMD_OP_QUERY_EQ = 0x303, |
| 120 | |
| 121 | MLX5_CMD_OP_CREATE_CQ = 0x400, |
| 122 | MLX5_CMD_OP_DESTROY_CQ = 0x401, |
| 123 | MLX5_CMD_OP_QUERY_CQ = 0x402, |
| 124 | MLX5_CMD_OP_MODIFY_CQ = 0x403, |
| 125 | |
| 126 | MLX5_CMD_OP_CREATE_QP = 0x500, |
| 127 | MLX5_CMD_OP_DESTROY_QP = 0x501, |
| 128 | MLX5_CMD_OP_RST2INIT_QP = 0x502, |
| 129 | MLX5_CMD_OP_INIT2RTR_QP = 0x503, |
| 130 | MLX5_CMD_OP_RTR2RTS_QP = 0x504, |
| 131 | MLX5_CMD_OP_RTS2RTS_QP = 0x505, |
| 132 | MLX5_CMD_OP_SQERR2RTS_QP = 0x506, |
| 133 | MLX5_CMD_OP_2ERR_QP = 0x507, |
| 134 | MLX5_CMD_OP_RTS2SQD_QP = 0x508, |
| 135 | MLX5_CMD_OP_SQD2RTS_QP = 0x509, |
| 136 | MLX5_CMD_OP_2RST_QP = 0x50a, |
| 137 | MLX5_CMD_OP_QUERY_QP = 0x50b, |
| 138 | MLX5_CMD_OP_CONF_SQP = 0x50c, |
| 139 | MLX5_CMD_OP_MAD_IFC = 0x50d, |
| 140 | MLX5_CMD_OP_INIT2INIT_QP = 0x50e, |
| 141 | MLX5_CMD_OP_SUSPEND_QP = 0x50f, |
| 142 | MLX5_CMD_OP_UNSUSPEND_QP = 0x510, |
| 143 | MLX5_CMD_OP_SQD2SQD_QP = 0x511, |
| 144 | MLX5_CMD_OP_ALLOC_QP_COUNTER_SET = 0x512, |
| 145 | MLX5_CMD_OP_DEALLOC_QP_COUNTER_SET = 0x513, |
| 146 | MLX5_CMD_OP_QUERY_QP_COUNTER_SET = 0x514, |
| 147 | |
| 148 | MLX5_CMD_OP_CREATE_PSV = 0x600, |
| 149 | MLX5_CMD_OP_DESTROY_PSV = 0x601, |
| 150 | MLX5_CMD_OP_QUERY_PSV = 0x602, |
| 151 | MLX5_CMD_OP_QUERY_SIG_RULE_TABLE = 0x603, |
| 152 | MLX5_CMD_OP_QUERY_BLOCK_SIZE_TABLE = 0x604, |
| 153 | |
| 154 | MLX5_CMD_OP_CREATE_SRQ = 0x700, |
| 155 | MLX5_CMD_OP_DESTROY_SRQ = 0x701, |
| 156 | MLX5_CMD_OP_QUERY_SRQ = 0x702, |
| 157 | MLX5_CMD_OP_ARM_RQ = 0x703, |
| 158 | MLX5_CMD_OP_RESIZE_SRQ = 0x704, |
| 159 | |
| 160 | MLX5_CMD_OP_ALLOC_PD = 0x800, |
| 161 | MLX5_CMD_OP_DEALLOC_PD = 0x801, |
| 162 | MLX5_CMD_OP_ALLOC_UAR = 0x802, |
| 163 | MLX5_CMD_OP_DEALLOC_UAR = 0x803, |
| 164 | |
| 165 | MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, |
| 166 | MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, |
| 167 | |
| 168 | |
| 169 | MLX5_CMD_OP_ALLOC_XRCD = 0x80e, |
| 170 | MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, |
| 171 | |
| 172 | MLX5_CMD_OP_ACCESS_REG = 0x805, |
| 173 | MLX5_CMD_OP_MAX = 0x810, |
| 174 | }; |
| 175 | |
| 176 | enum { |
| 177 | MLX5_REG_PCAP = 0x5001, |
| 178 | MLX5_REG_PMTU = 0x5003, |
| 179 | MLX5_REG_PTYS = 0x5004, |
| 180 | MLX5_REG_PAOS = 0x5006, |
| 181 | MLX5_REG_PMAOS = 0x5012, |
| 182 | MLX5_REG_PUDE = 0x5009, |
| 183 | MLX5_REG_PMPE = 0x5010, |
| 184 | MLX5_REG_PELC = 0x500e, |
| 185 | MLX5_REG_PMLP = 0, /* TBD */ |
| 186 | MLX5_REG_NODE_DESC = 0x6001, |
| 187 | MLX5_REG_HOST_ENDIANNESS = 0x7004, |
| 188 | }; |
| 189 | |
| 190 | enum dbg_rsc_type { |
| 191 | MLX5_DBG_RSC_QP, |
| 192 | MLX5_DBG_RSC_EQ, |
| 193 | MLX5_DBG_RSC_CQ, |
| 194 | }; |
| 195 | |
| 196 | struct mlx5_field_desc { |
| 197 | struct dentry *dent; |
| 198 | int i; |
| 199 | }; |
| 200 | |
| 201 | struct mlx5_rsc_debug { |
| 202 | struct mlx5_core_dev *dev; |
| 203 | void *object; |
| 204 | enum dbg_rsc_type type; |
| 205 | struct dentry *root; |
| 206 | struct mlx5_field_desc fields[0]; |
| 207 | }; |
| 208 | |
| 209 | enum mlx5_dev_event { |
| 210 | MLX5_DEV_EVENT_SYS_ERROR, |
| 211 | MLX5_DEV_EVENT_PORT_UP, |
| 212 | MLX5_DEV_EVENT_PORT_DOWN, |
| 213 | MLX5_DEV_EVENT_PORT_INITIALIZED, |
| 214 | MLX5_DEV_EVENT_LID_CHANGE, |
| 215 | MLX5_DEV_EVENT_PKEY_CHANGE, |
| 216 | MLX5_DEV_EVENT_GUID_CHANGE, |
| 217 | MLX5_DEV_EVENT_CLIENT_REREG, |
| 218 | }; |
| 219 | |
| 220 | struct mlx5_uuar_info { |
| 221 | struct mlx5_uar *uars; |
| 222 | int num_uars; |
| 223 | int num_low_latency_uuars; |
| 224 | unsigned long *bitmap; |
| 225 | unsigned int *count; |
| 226 | struct mlx5_bf *bfs; |
| 227 | |
| 228 | /* |
| 229 | * protect uuar allocation data structs |
| 230 | */ |
| 231 | struct mutex lock; |
Eli Cohen | 78c0f98 | 2014-01-30 13:49:48 +0200 | [diff] [blame] | 232 | u32 ver; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 233 | }; |
| 234 | |
| 235 | struct mlx5_bf { |
| 236 | void __iomem *reg; |
| 237 | void __iomem *regreg; |
| 238 | int buf_size; |
| 239 | struct mlx5_uar *uar; |
| 240 | unsigned long offset; |
| 241 | int need_lock; |
| 242 | /* protect blue flame buffer selection when needed |
| 243 | */ |
| 244 | spinlock_t lock; |
| 245 | |
| 246 | /* serialize 64 bit writes when done as two 32 bit accesses |
| 247 | */ |
| 248 | spinlock_t lock32; |
| 249 | int uuarn; |
| 250 | }; |
| 251 | |
| 252 | struct mlx5_cmd_first { |
| 253 | __be32 data[4]; |
| 254 | }; |
| 255 | |
| 256 | struct mlx5_cmd_msg { |
| 257 | struct list_head list; |
| 258 | struct cache_ent *cache; |
| 259 | u32 len; |
| 260 | struct mlx5_cmd_first first; |
| 261 | struct mlx5_cmd_mailbox *next; |
| 262 | }; |
| 263 | |
| 264 | struct mlx5_cmd_debug { |
| 265 | struct dentry *dbg_root; |
| 266 | struct dentry *dbg_in; |
| 267 | struct dentry *dbg_out; |
| 268 | struct dentry *dbg_outlen; |
| 269 | struct dentry *dbg_status; |
| 270 | struct dentry *dbg_run; |
| 271 | void *in_msg; |
| 272 | void *out_msg; |
| 273 | u8 status; |
| 274 | u16 inlen; |
| 275 | u16 outlen; |
| 276 | }; |
| 277 | |
| 278 | struct cache_ent { |
| 279 | /* protect block chain allocations |
| 280 | */ |
| 281 | spinlock_t lock; |
| 282 | struct list_head head; |
| 283 | }; |
| 284 | |
| 285 | struct cmd_msg_cache { |
| 286 | struct cache_ent large; |
| 287 | struct cache_ent med; |
| 288 | |
| 289 | }; |
| 290 | |
| 291 | struct mlx5_cmd_stats { |
| 292 | u64 sum; |
| 293 | u64 n; |
| 294 | struct dentry *root; |
| 295 | struct dentry *avg; |
| 296 | struct dentry *count; |
| 297 | /* protect command average calculations */ |
| 298 | spinlock_t lock; |
| 299 | }; |
| 300 | |
| 301 | struct mlx5_cmd { |
| 302 | void *cmd_buf; |
| 303 | dma_addr_t dma; |
| 304 | u16 cmdif_rev; |
| 305 | u8 log_sz; |
| 306 | u8 log_stride; |
| 307 | int max_reg_cmds; |
| 308 | int events; |
| 309 | u32 __iomem *vector; |
| 310 | |
| 311 | /* protect command queue allocations |
| 312 | */ |
| 313 | spinlock_t alloc_lock; |
| 314 | |
| 315 | /* protect token allocations |
| 316 | */ |
| 317 | spinlock_t token_lock; |
| 318 | u8 token; |
| 319 | unsigned long bitmask; |
| 320 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; |
| 321 | struct workqueue_struct *wq; |
| 322 | struct semaphore sem; |
| 323 | struct semaphore pages_sem; |
| 324 | int mode; |
| 325 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
| 326 | struct pci_pool *pool; |
| 327 | struct mlx5_cmd_debug dbg; |
| 328 | struct cmd_msg_cache cache; |
| 329 | int checksum_disabled; |
| 330 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; |
| 331 | }; |
| 332 | |
| 333 | struct mlx5_port_caps { |
| 334 | int gid_table_len; |
| 335 | int pkey_table_len; |
| 336 | }; |
| 337 | |
| 338 | struct mlx5_caps { |
| 339 | u8 log_max_eq; |
| 340 | u8 log_max_cq; |
| 341 | u8 log_max_qp; |
| 342 | u8 log_max_mkey; |
| 343 | u8 log_max_pd; |
| 344 | u8 log_max_srq; |
| 345 | u32 max_cqes; |
| 346 | int max_wqes; |
| 347 | int max_sq_desc_sz; |
| 348 | int max_rq_desc_sz; |
| 349 | u64 flags; |
| 350 | u16 stat_rate_support; |
| 351 | int log_max_msg; |
| 352 | int num_ports; |
| 353 | int max_ra_res_qp; |
| 354 | int max_ra_req_qp; |
| 355 | int max_srq_wqes; |
| 356 | int bf_reg_size; |
| 357 | int bf_regs_per_page; |
| 358 | struct mlx5_port_caps port[MLX5_MAX_PORTS]; |
| 359 | u8 ext_port_cap[MLX5_MAX_PORTS]; |
| 360 | int max_vf; |
| 361 | u32 reserved_lkey; |
| 362 | u8 local_ca_ack_delay; |
| 363 | u8 log_max_mcg; |
Moshe Lazer | 0a324f31 | 2013-08-14 17:46:48 +0300 | [diff] [blame] | 364 | u32 max_qp_mcg; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 365 | int min_page_sz; |
| 366 | }; |
| 367 | |
| 368 | struct mlx5_cmd_mailbox { |
| 369 | void *buf; |
| 370 | dma_addr_t dma; |
| 371 | struct mlx5_cmd_mailbox *next; |
| 372 | }; |
| 373 | |
| 374 | struct mlx5_buf_list { |
| 375 | void *buf; |
| 376 | dma_addr_t map; |
| 377 | }; |
| 378 | |
| 379 | struct mlx5_buf { |
| 380 | struct mlx5_buf_list direct; |
| 381 | struct mlx5_buf_list *page_list; |
| 382 | int nbufs; |
| 383 | int npages; |
| 384 | int page_shift; |
| 385 | int size; |
| 386 | }; |
| 387 | |
| 388 | struct mlx5_eq { |
| 389 | struct mlx5_core_dev *dev; |
| 390 | __be32 __iomem *doorbell; |
| 391 | u32 cons_index; |
| 392 | struct mlx5_buf buf; |
| 393 | int size; |
| 394 | u8 irqn; |
| 395 | u8 eqn; |
| 396 | int nent; |
| 397 | u64 mask; |
| 398 | char name[MLX5_MAX_EQ_NAME]; |
| 399 | struct list_head list; |
| 400 | int index; |
| 401 | struct mlx5_rsc_debug *dbg; |
| 402 | }; |
| 403 | |
Sagi Grimberg | 3121e3c | 2014-02-23 14:19:06 +0200 | [diff] [blame] | 404 | struct mlx5_core_psv { |
| 405 | u32 psv_idx; |
| 406 | struct psv_layout { |
| 407 | u32 pd; |
| 408 | u16 syndrome; |
| 409 | u16 reserved; |
| 410 | u16 bg; |
| 411 | u16 app_tag; |
| 412 | u32 ref_tag; |
| 413 | } psv; |
| 414 | }; |
| 415 | |
| 416 | struct mlx5_core_sig_ctx { |
| 417 | struct mlx5_core_psv psv_memory; |
| 418 | struct mlx5_core_psv psv_wire; |
Sagi Grimberg | d5436ba | 2014-02-23 14:19:12 +0200 | [diff] [blame] | 419 | struct ib_sig_err err_item; |
| 420 | bool sig_status_checked; |
| 421 | bool sig_err_exists; |
| 422 | u32 sigerr_count; |
Sagi Grimberg | 3121e3c | 2014-02-23 14:19:06 +0200 | [diff] [blame] | 423 | }; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 424 | |
| 425 | struct mlx5_core_mr { |
| 426 | u64 iova; |
| 427 | u64 size; |
| 428 | u32 key; |
| 429 | u32 pd; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 430 | }; |
| 431 | |
| 432 | struct mlx5_core_srq { |
| 433 | u32 srqn; |
| 434 | int max; |
| 435 | int max_gs; |
| 436 | int max_avail_gather; |
| 437 | int wqe_shift; |
| 438 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); |
| 439 | |
| 440 | atomic_t refcount; |
| 441 | struct completion free; |
| 442 | }; |
| 443 | |
| 444 | struct mlx5_eq_table { |
| 445 | void __iomem *update_ci; |
| 446 | void __iomem *update_arm_ci; |
| 447 | struct list_head *comp_eq_head; |
| 448 | struct mlx5_eq pages_eq; |
| 449 | struct mlx5_eq async_eq; |
| 450 | struct mlx5_eq cmd_eq; |
| 451 | struct msix_entry *msix_arr; |
| 452 | int num_comp_vectors; |
| 453 | /* protect EQs list |
| 454 | */ |
| 455 | spinlock_t lock; |
| 456 | }; |
| 457 | |
| 458 | struct mlx5_uar { |
| 459 | u32 index; |
| 460 | struct list_head bf_list; |
| 461 | unsigned free_bf_bmap; |
| 462 | void __iomem *wc_map; |
| 463 | void __iomem *map; |
| 464 | }; |
| 465 | |
| 466 | |
| 467 | struct mlx5_core_health { |
| 468 | struct health_buffer __iomem *health; |
| 469 | __be32 __iomem *health_counter; |
| 470 | struct timer_list timer; |
| 471 | struct list_head list; |
| 472 | u32 prev; |
| 473 | int miss_counter; |
| 474 | }; |
| 475 | |
| 476 | struct mlx5_cq_table { |
| 477 | /* protect radix tree |
| 478 | */ |
| 479 | spinlock_t lock; |
| 480 | struct radix_tree_root tree; |
| 481 | }; |
| 482 | |
| 483 | struct mlx5_qp_table { |
| 484 | /* protect radix tree |
| 485 | */ |
| 486 | spinlock_t lock; |
| 487 | struct radix_tree_root tree; |
| 488 | }; |
| 489 | |
| 490 | struct mlx5_srq_table { |
| 491 | /* protect radix tree |
| 492 | */ |
| 493 | spinlock_t lock; |
| 494 | struct radix_tree_root tree; |
| 495 | }; |
| 496 | |
Sagi Grimberg | 3bcdb17 | 2014-02-23 14:19:10 +0200 | [diff] [blame] | 497 | struct mlx5_mr_table { |
| 498 | /* protect radix tree |
| 499 | */ |
| 500 | rwlock_t lock; |
| 501 | struct radix_tree_root tree; |
| 502 | }; |
| 503 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 504 | struct mlx5_priv { |
| 505 | char name[MLX5_MAX_NAME_LEN]; |
| 506 | struct mlx5_eq_table eq_table; |
| 507 | struct mlx5_uuar_info uuari; |
| 508 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); |
| 509 | |
| 510 | /* pages stuff */ |
| 511 | struct workqueue_struct *pg_wq; |
| 512 | struct rb_root page_root; |
| 513 | int fw_pages; |
| 514 | int reg_pages; |
Eli Cohen | bf0bf77 | 2013-10-23 09:53:19 +0300 | [diff] [blame] | 515 | struct list_head free_list; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 516 | |
| 517 | struct mlx5_core_health health; |
| 518 | |
| 519 | struct mlx5_srq_table srq_table; |
| 520 | |
| 521 | /* start: qp staff */ |
| 522 | struct mlx5_qp_table qp_table; |
| 523 | struct dentry *qp_debugfs; |
| 524 | struct dentry *eq_debugfs; |
| 525 | struct dentry *cq_debugfs; |
| 526 | struct dentry *cmdif_debugfs; |
| 527 | /* end: qp staff */ |
| 528 | |
| 529 | /* start: cq staff */ |
| 530 | struct mlx5_cq_table cq_table; |
| 531 | /* end: cq staff */ |
| 532 | |
Sagi Grimberg | 3bcdb17 | 2014-02-23 14:19:10 +0200 | [diff] [blame] | 533 | /* start: mr staff */ |
| 534 | struct mlx5_mr_table mr_table; |
| 535 | /* end: mr staff */ |
| 536 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 537 | /* start: alloc staff */ |
| 538 | struct mutex pgdir_mutex; |
| 539 | struct list_head pgdir_list; |
| 540 | /* end: alloc staff */ |
| 541 | struct dentry *dbg_root; |
| 542 | |
| 543 | /* protect mkey key part */ |
| 544 | spinlock_t mkey_lock; |
| 545 | u8 mkey_key; |
| 546 | }; |
| 547 | |
| 548 | struct mlx5_core_dev { |
| 549 | struct pci_dev *pdev; |
| 550 | u8 rev_id; |
| 551 | char board_id[MLX5_BOARD_ID_LEN]; |
| 552 | struct mlx5_cmd cmd; |
| 553 | struct mlx5_caps caps; |
| 554 | phys_addr_t iseg_base; |
| 555 | struct mlx5_init_seg __iomem *iseg; |
| 556 | void (*event) (struct mlx5_core_dev *dev, |
| 557 | enum mlx5_dev_event event, |
| 558 | void *data); |
| 559 | struct mlx5_priv priv; |
| 560 | struct mlx5_profile *profile; |
| 561 | atomic_t num_qps; |
| 562 | }; |
| 563 | |
| 564 | struct mlx5_db { |
| 565 | __be32 *db; |
| 566 | union { |
| 567 | struct mlx5_db_pgdir *pgdir; |
| 568 | struct mlx5_ib_user_db_page *user_page; |
| 569 | } u; |
| 570 | dma_addr_t dma; |
| 571 | int index; |
| 572 | }; |
| 573 | |
| 574 | enum { |
| 575 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, |
| 576 | }; |
| 577 | |
| 578 | enum { |
| 579 | MLX5_COMP_EQ_SIZE = 1024, |
| 580 | }; |
| 581 | |
| 582 | struct mlx5_db_pgdir { |
| 583 | struct list_head list; |
| 584 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); |
| 585 | __be32 *db_page; |
| 586 | dma_addr_t db_dma; |
| 587 | }; |
| 588 | |
| 589 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
| 590 | |
| 591 | struct mlx5_cmd_work_ent { |
| 592 | struct mlx5_cmd_msg *in; |
| 593 | struct mlx5_cmd_msg *out; |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 594 | void *uout; |
| 595 | int uout_size; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 596 | mlx5_cmd_cbk_t callback; |
| 597 | void *context; |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 598 | int idx; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 599 | struct completion done; |
| 600 | struct mlx5_cmd *cmd; |
| 601 | struct work_struct work; |
| 602 | struct mlx5_cmd_layout *lay; |
| 603 | int ret; |
| 604 | int page_queue; |
| 605 | u8 status; |
| 606 | u8 token; |
| 607 | struct timespec ts1; |
| 608 | struct timespec ts2; |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 609 | u16 op; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 610 | }; |
| 611 | |
| 612 | struct mlx5_pas { |
| 613 | u64 pa; |
| 614 | u8 log_sz; |
| 615 | }; |
| 616 | |
| 617 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
| 618 | { |
| 619 | if (likely(BITS_PER_LONG == 64 || buf->nbufs == 1)) |
| 620 | return buf->direct.buf + offset; |
| 621 | else |
| 622 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
| 623 | (offset & (PAGE_SIZE - 1)); |
| 624 | } |
| 625 | |
| 626 | extern struct workqueue_struct *mlx5_core_wq; |
| 627 | |
| 628 | #define STRUCT_FIELD(header, field) \ |
| 629 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ |
| 630 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field |
| 631 | |
| 632 | struct ib_field { |
| 633 | size_t struct_offset_bytes; |
| 634 | size_t struct_size_bytes; |
| 635 | int offset_bits; |
| 636 | int size_bits; |
| 637 | }; |
| 638 | |
| 639 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
| 640 | { |
| 641 | return pci_get_drvdata(pdev); |
| 642 | } |
| 643 | |
| 644 | extern struct dentry *mlx5_debugfs_root; |
| 645 | |
| 646 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) |
| 647 | { |
| 648 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; |
| 649 | } |
| 650 | |
| 651 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) |
| 652 | { |
| 653 | return ioread32be(&dev->iseg->fw_rev) >> 16; |
| 654 | } |
| 655 | |
| 656 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) |
| 657 | { |
| 658 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; |
| 659 | } |
| 660 | |
| 661 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) |
| 662 | { |
| 663 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; |
| 664 | } |
| 665 | |
| 666 | static inline void *mlx5_vzalloc(unsigned long size) |
| 667 | { |
| 668 | void *rtn; |
| 669 | |
| 670 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); |
| 671 | if (!rtn) |
| 672 | rtn = vzalloc(size); |
| 673 | return rtn; |
| 674 | } |
| 675 | |
| 676 | static inline void mlx5_vfree(const void *addr) |
| 677 | { |
| 678 | if (addr && is_vmalloc_addr(addr)) |
| 679 | vfree(addr); |
| 680 | else |
| 681 | kfree(addr); |
| 682 | } |
| 683 | |
Sagi Grimberg | 3bcdb17 | 2014-02-23 14:19:10 +0200 | [diff] [blame] | 684 | static inline u32 mlx5_base_mkey(const u32 key) |
| 685 | { |
| 686 | return key & 0xffffff00u; |
| 687 | } |
| 688 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 689 | int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev); |
| 690 | void mlx5_dev_cleanup(struct mlx5_core_dev *dev); |
| 691 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
| 692 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); |
| 693 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); |
| 694 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); |
| 695 | int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); |
| 696 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
| 697 | int out_size); |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 698 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
| 699 | void *out, int out_size, mlx5_cmd_cbk_t callback, |
| 700 | void *context); |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 701 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
| 702 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); |
| 703 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); |
| 704 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); |
| 705 | void mlx5_health_cleanup(void); |
| 706 | void __init mlx5_health_init(void); |
| 707 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
| 708 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); |
| 709 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct, |
| 710 | struct mlx5_buf *buf); |
| 711 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
| 712 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
| 713 | gfp_t flags, int npages); |
| 714 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
| 715 | struct mlx5_cmd_mailbox *head); |
| 716 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 717 | struct mlx5_create_srq_mbox_in *in, int inlen); |
| 718 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
| 719 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 720 | struct mlx5_query_srq_mbox_out *out); |
| 721 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, |
| 722 | u16 lwm, int is_srq); |
Sagi Grimberg | 3bcdb17 | 2014-02-23 14:19:10 +0200 | [diff] [blame] | 723 | void mlx5_init_mr_table(struct mlx5_core_dev *dev); |
| 724 | void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 725 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 726 | struct mlx5_create_mkey_mbox_in *in, int inlen, |
| 727 | mlx5_cmd_cbk_t callback, void *context, |
| 728 | struct mlx5_create_mkey_mbox_out *out); |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 729 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); |
| 730 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
| 731 | struct mlx5_query_mkey_mbox_out *out, int outlen); |
| 732 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
| 733 | u32 *mkey); |
| 734 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
| 735 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); |
| 736 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, |
| 737 | u16 opmod, int port); |
| 738 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
| 739 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
| 740 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
| 741 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
| 742 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, |
Moshe Lazer | 0a324f31 | 2013-08-14 17:46:48 +0300 | [diff] [blame] | 743 | s32 npages); |
Eli Cohen | cd23b14 | 2013-07-18 15:31:08 +0300 | [diff] [blame] | 744 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 745 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
| 746 | void mlx5_register_debugfs(void); |
| 747 | void mlx5_unregister_debugfs(void); |
| 748 | int mlx5_eq_init(struct mlx5_core_dev *dev); |
| 749 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); |
| 750 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); |
| 751 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); |
| 752 | void mlx5_qp_event(struct mlx5_core_dev *dev, u32 qpn, int event_type); |
| 753 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
| 754 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); |
| 755 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); |
| 756 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
| 757 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, |
| 758 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); |
| 759 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
| 760 | int mlx5_start_eqs(struct mlx5_core_dev *dev); |
| 761 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); |
| 762 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 763 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
| 764 | |
| 765 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
| 766 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 767 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, |
| 768 | int size_in, void *data_out, int size_out, |
| 769 | u16 reg_num, int arg, int write); |
| 770 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, int port_num, u32 caps); |
| 771 | |
| 772 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
| 773 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
| 774 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, |
| 775 | struct mlx5_query_eq_mbox_out *out, int outlen); |
| 776 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); |
| 777 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 778 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); |
| 779 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); |
| 780 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
| 781 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
| 782 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 783 | const char *mlx5_command_str(int command); |
| 784 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
| 785 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
Sagi Grimberg | 3121e3c | 2014-02-23 14:19:06 +0200 | [diff] [blame] | 786 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
| 787 | int npsvs, u32 *sig_index); |
| 788 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 789 | |
| 790 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
| 791 | { |
| 792 | return mkey >> 8; |
| 793 | } |
| 794 | |
| 795 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) |
| 796 | { |
| 797 | return mkey_idx << 8; |
| 798 | } |
| 799 | |
Eli Cohen | 746b558 | 2013-10-23 09:53:14 +0300 | [diff] [blame] | 800 | static inline u8 mlx5_mkey_variant(u32 mkey) |
| 801 | { |
| 802 | return mkey & 0xff; |
| 803 | } |
| 804 | |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 805 | enum { |
| 806 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, |
Eli Cohen | c1868b8 | 2013-09-11 16:35:25 +0300 | [diff] [blame] | 807 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 808 | }; |
| 809 | |
| 810 | enum { |
| 811 | MAX_MR_CACHE_ENTRIES = 16, |
| 812 | }; |
| 813 | |
| 814 | struct mlx5_profile { |
| 815 | u64 mask; |
| 816 | u32 log_max_qp; |
Eli Cohen | e126ba9 | 2013-07-07 17:25:49 +0300 | [diff] [blame] | 817 | struct { |
| 818 | int size; |
| 819 | int limit; |
| 820 | } mr_cache[MAX_MR_CACHE_ENTRIES]; |
| 821 | }; |
| 822 | |
| 823 | #endif /* MLX5_DRIVER_H */ |