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Ben Dooksc6184e22007-02-17 00:52:37 +01001/* linux/arch/arm/mach-s3c2410/mach-qt2410.c
2 *
3 * Copyright (C) 2006 by OpenMoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
5 * All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 */
23
24#include <linux/kernel.h>
25#include <linux/types.h>
26#include <linux/interrupt.h>
27#include <linux/list.h>
28#include <linux/timer.h>
29#include <linux/init.h>
Ben Dooksec976d62009-05-13 22:52:24 +010030#include <linux/gpio.h>
Ben Dooks333a42e2007-05-20 11:55:53 +010031#include <linux/sysdev.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010032#include <linux/platform_device.h>
33#include <linux/serial_core.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010034#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
Russell Kingfced80c2008-09-06 12:10:45 +010036#include <linux/io.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010037#include <linux/mtd/mtd.h>
38#include <linux/mtd/nand.h>
39#include <linux/mtd/nand_ecc.h>
40#include <linux/mtd/partitions.h>
41
42#include <asm/mach/arch.h>
43#include <asm/mach/map.h>
44#include <asm/mach/irq.h>
45
Russell Kinga09e64f2008-08-05 16:14:15 +010046#include <mach/hardware.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010047#include <asm/irq.h>
48#include <asm/mach-types.h>
49
Russell Kinga09e64f2008-08-05 16:14:15 +010050#include <mach/regs-gpio.h>
51#include <mach/leds-gpio.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010052#include <plat/regs-serial.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010053#include <mach/fb.h>
Ben Dooks7926b5a2008-10-30 10:14:35 +000054#include <plat/nand.h>
Ben Dooks57bd4b92008-10-30 10:14:37 +000055#include <plat/udc.h>
Russell Kinga09e64f2008-08-05 16:14:15 +010056#include <mach/spi.h>
57#include <mach/spi-gpio.h>
Ben Dooks3e1b7762008-10-31 16:14:40 +000058#include <plat/iic.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010059
Ben Dooksd5120ae2008-10-07 23:09:51 +010060#include <plat/common-smdk.h>
Ben Dooks40b956f2010-05-04 14:38:49 +090061#include <plat/gpio-cfg.h>
Ben Dooksa2b7ba92008-10-07 22:26:09 +010062#include <plat/devs.h>
63#include <plat/cpu.h>
64#include <plat/pm.h>
Ben Dooksc6184e22007-02-17 00:52:37 +010065
66static struct map_desc qt2410_iodesc[] __initdata = {
67 { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
68};
69
70#define UCON S3C2410_UCON_DEFAULT
71#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
72#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
73
74static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
75 [0] = {
76 .hwport = 0,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
81 },
82 [1] = {
83 .hwport = 1,
84 .flags = 0,
85 .ucon = UCON,
86 .ulcon = ULCON,
87 .ufcon = UFCON,
88 },
89 [2] = {
90 .hwport = 2,
91 .flags = 0,
92 .ucon = UCON,
93 .ulcon = ULCON,
94 .ufcon = UFCON,
95 }
96};
97
98/* LCD driver info */
99
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700100static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
101 {
102 /* Configuration for 640x480 SHARP LQ080V3DG01 */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700103 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
104 S3C2410_LCDCON5_INVVLINE |
105 S3C2410_LCDCON5_INVVFRAME |
106 S3C2410_LCDCON5_PWREN |
107 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700108
Krzysztof Helt1f411532007-10-16 01:28:57 -0700109 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700110 .width = 640,
111 .height = 480,
112
Krzysztof Helt69816692007-10-16 01:29:06 -0700113 .pixclock = 40000, /* HCLK/4 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700114 .xres = 640,
115 .yres = 480,
116 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700117 .left_margin = 44,
118 .right_margin = 116,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700119 .hsync_len = 96,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700120 .upper_margin = 19,
121 .lower_margin = 11,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700122 .vsync_len = 15,
Ben Dooksc6184e22007-02-17 00:52:37 +0100123 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700124 {
125 /* Configuration for 480x640 toppoly TD028TTEC1 */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700126 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
127 S3C2410_LCDCON5_INVVLINE |
128 S3C2410_LCDCON5_INVVFRAME |
129 S3C2410_LCDCON5_PWREN |
130 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700131
Krzysztof Helt1f411532007-10-16 01:28:57 -0700132 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700133 .width = 480,
134 .height = 640,
Krzysztof Helt69816692007-10-16 01:29:06 -0700135 .pixclock = 40000, /* HCLK/4 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700136 .xres = 480,
137 .yres = 640,
138 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700139 .left_margin = 8,
140 .right_margin = 24,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700141 .hsync_len = 8,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700142 .upper_margin = 2,
143 .lower_margin = 4,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700144 .vsync_len = 2,
Ben Dooksc6184e22007-02-17 00:52:37 +0100145 },
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700146 {
147 /* Config for 240x320 LCD */
Krzysztof Heltf28ef572007-10-16 01:28:58 -0700148 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
149 S3C2410_LCDCON5_INVVLINE |
150 S3C2410_LCDCON5_INVVFRAME |
151 S3C2410_LCDCON5_PWREN |
152 S3C2410_LCDCON5_HWSWP,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700153
Krzysztof Helt1f411532007-10-16 01:28:57 -0700154 .type = S3C2410_LCDCON1_TFT,
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700155 .width = 240,
156 .height = 320,
Krzysztof Helt69816692007-10-16 01:29:06 -0700157 .pixclock = 100000, /* HCLK/10 */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700158 .xres = 240,
159 .yres = 320,
160 .bpp = 16,
Krzysztof Helt1f411532007-10-16 01:28:57 -0700161 .left_margin = 13,
162 .right_margin = 8,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700163 .hsync_len = 4,
Krzysztof Helt5f20f692007-10-16 01:28:59 -0700164 .upper_margin = 2,
165 .lower_margin = 7,
Krzysztof Helt93d11f52007-10-16 01:29:00 -0700166 .vsync_len = 4,
Ben Dooksc6184e22007-02-17 00:52:37 +0100167 },
168};
169
Ben Dooksc6184e22007-02-17 00:52:37 +0100170
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700171static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
172 .displays = qt2410_lcd_cfg,
173 .num_displays = ARRAY_SIZE(qt2410_lcd_cfg),
174 .default_display = 0,
Ben Dooksc6184e22007-02-17 00:52:37 +0100175
176 .lpcsel = ((0xCE6) & ~7) | 1<<4,
Ben Dooksc6184e22007-02-17 00:52:37 +0100177};
178
179/* CS8900 */
180
181static struct resource qt2410_cs89x0_resources[] = {
182 [0] = {
183 .start = 0x19000000,
184 .end = 0x19000000 + 16,
185 .flags = IORESOURCE_MEM,
186 },
187 [1] = {
188 .start = IRQ_EINT9,
189 .end = IRQ_EINT9,
190 .flags = IORESOURCE_IRQ,
191 },
192};
193
194static struct platform_device qt2410_cs89x0 = {
195 .name = "cirrus-cs89x0",
196 .num_resources = ARRAY_SIZE(qt2410_cs89x0_resources),
197 .resource = qt2410_cs89x0_resources,
198};
199
200/* LED */
201
202static struct s3c24xx_led_platdata qt2410_pdata_led = {
Ben Dooks070276d2009-05-17 22:32:23 +0100203 .gpio = S3C2410_GPB(0),
Ben Dooksc6184e22007-02-17 00:52:37 +0100204 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
205 .name = "led",
206 .def_trigger = "timer",
207};
208
209static struct platform_device qt2410_led = {
210 .name = "s3c24xx_led",
211 .id = 0,
212 .dev = {
213 .platform_data = &qt2410_pdata_led,
214 },
215};
216
217/* SPI */
218
219static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
220{
221 switch (cs) {
222 case BITBANG_CS_ACTIVE:
Ben Dooks2d2e0c82010-05-04 12:32:16 +0900223 gpio_set_value(S3C2410_GPB(5), 0);
Ben Dooksc6184e22007-02-17 00:52:37 +0100224 break;
225 case BITBANG_CS_INACTIVE:
Ben Dooks2d2e0c82010-05-04 12:32:16 +0900226 gpio_set_value(S3C2410_GPB(5), 1);
Ben Dooksc6184e22007-02-17 00:52:37 +0100227 break;
228 }
229}
230
231static struct s3c2410_spigpio_info spi_gpio_cfg = {
Ben Dooks070276d2009-05-17 22:32:23 +0100232 .pin_clk = S3C2410_GPG(7),
233 .pin_mosi = S3C2410_GPG(6),
234 .pin_miso = S3C2410_GPG(5),
Ben Dooksc6184e22007-02-17 00:52:37 +0100235 .chip_select = &spi_gpio_cs,
236};
237
238
239static struct platform_device qt2410_spi = {
240 .name = "s3c24xx-spi-gpio",
241 .id = 1,
242 .dev = {
243 .platform_data = &spi_gpio_cfg,
244 },
245};
246
247/* Board devices */
248
249static struct platform_device *qt2410_devices[] __initdata = {
Ben Dooksb8132482009-11-23 00:13:39 +0000250 &s3c_device_ohci,
Ben Dooksc6184e22007-02-17 00:52:37 +0100251 &s3c_device_lcd,
252 &s3c_device_wdt,
Ben Dooks3e1b7762008-10-31 16:14:40 +0000253 &s3c_device_i2c0,
Ben Dooksc6184e22007-02-17 00:52:37 +0100254 &s3c_device_iis,
255 &s3c_device_sdi,
256 &s3c_device_usbgadget,
257 &qt2410_spi,
258 &qt2410_cs89x0,
259 &qt2410_led,
260};
261
Ben Dooks2a3a1802009-09-28 13:59:49 +0300262static struct mtd_partition __initdata qt2410_nand_part[] = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100263 [0] = {
264 .name = "U-Boot",
265 .size = 0x30000,
266 .offset = 0,
267 },
268 [1] = {
269 .name = "U-Boot environment",
270 .offset = 0x30000,
271 .size = 0x4000,
272 },
273 [2] = {
274 .name = "kernel",
275 .offset = 0x34000,
276 .size = SZ_2M,
277 },
278 [3] = {
279 .name = "initrd",
280 .offset = 0x234000,
281 .size = SZ_4M,
282 },
283 [4] = {
284 .name = "jffs2",
285 .offset = 0x634000,
286 .size = 0x39cc000,
287 },
288};
289
Ben Dooks2a3a1802009-09-28 13:59:49 +0300290static struct s3c2410_nand_set __initdata qt2410_nand_sets[] = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100291 [0] = {
292 .name = "NAND",
293 .nr_chips = 1,
294 .nr_partitions = ARRAY_SIZE(qt2410_nand_part),
295 .partitions = qt2410_nand_part,
296 },
297};
298
299/* choose a set of timings which should suit most 512Mbit
300 * chips and beyond.
301 */
302
Ben Dooks2a3a1802009-09-28 13:59:49 +0300303static struct s3c2410_platform_nand __initdata qt2410_nand_info = {
Ben Dooksc6184e22007-02-17 00:52:37 +0100304 .tacls = 20,
305 .twrph0 = 60,
306 .twrph1 = 20,
307 .nr_sets = ARRAY_SIZE(qt2410_nand_sets),
308 .sets = qt2410_nand_sets,
309};
310
311/* UDC */
312
313static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
314};
315
316static char tft_type = 's';
317
318static int __init qt2410_tft_setup(char *str)
319{
320 tft_type = str[0];
321 return 1;
322}
323
324__setup("tft=", qt2410_tft_setup);
325
326static void __init qt2410_map_io(void)
327{
328 s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
329 s3c24xx_init_clocks(12*1000*1000);
330 s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
Ben Dooksc6184e22007-02-17 00:52:37 +0100331}
332
333static void __init qt2410_machine_init(void)
334{
Ben Dooks2a3a1802009-09-28 13:59:49 +0300335 s3c_nand_set_platdata(&qt2410_nand_info);
Ben Dooksc6184e22007-02-17 00:52:37 +0100336
337 switch (tft_type) {
338 case 'p': /* production */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700339 qt2410_fb_info.default_display = 1;
Ben Dooksc6184e22007-02-17 00:52:37 +0100340 break;
341 case 'b': /* big */
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700342 qt2410_fb_info.default_display = 0;
Ben Dooksc6184e22007-02-17 00:52:37 +0100343 break;
344 case 's': /* small */
345 default:
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700346 qt2410_fb_info.default_display = 2;
Ben Dooksc6184e22007-02-17 00:52:37 +0100347 break;
348 }
Krzysztof Helt09fe75f2007-10-16 01:28:56 -0700349 s3c24xx_fb_set_platdata(&qt2410_fb_info);
Ben Dooksc6184e22007-02-17 00:52:37 +0100350
Ben Dooks40b956f2010-05-04 14:38:49 +0900351 s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
Ben Dooks070276d2009-05-17 22:32:23 +0100352 s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
Ben Dooksc6184e22007-02-17 00:52:37 +0100353
354 s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
Ben Dooks3e1b7762008-10-31 16:14:40 +0000355 s3c_i2c0_set_platdata(NULL);
Ben Dooksc6184e22007-02-17 00:52:37 +0100356
Ben Dooks2d2e0c82010-05-04 12:32:16 +0900357 WARN_ON(gpio_request(S3C2410_GPB(5), "spi cs"));
358 gpio_direction_output(S3C2410_GPB(5), 1);
Ben Dooksc6184e22007-02-17 00:52:37 +0100359
Ben Dooks57e51712007-04-20 11:19:16 +0100360 platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
Ben Dooks4e59c252008-12-12 00:24:18 +0000361 s3c_pm_init();
Ben Dooksc6184e22007-02-17 00:52:37 +0100362}
363
364MACHINE_START(QT2410, "QT2410")
Ben Dooksc6184e22007-02-17 00:52:37 +0100365 .boot_params = S3C2410_SDRAM_PA + 0x100,
366 .map_io = qt2410_map_io,
367 .init_irq = s3c24xx_init_irq,
368 .init_machine = qt2410_machine_init,
369 .timer = &s3c24xx_timer,
370MACHINE_END
371
372