Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * CCI cache coherent interconnect driver |
| 3 | * |
| 4 | * Copyright (C) 2013 ARM Ltd. |
| 5 | * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 as |
| 9 | * published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any |
| 12 | * kind, whether express or implied; without even the implied warranty |
| 13 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <linux/arm-cci.h> |
| 18 | #include <linux/io.h> |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 19 | #include <linux/interrupt.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 20 | #include <linux/module.h> |
| 21 | #include <linux/of_address.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_platform.h> |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 24 | #include <linux/perf_event.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 25 | #include <linux/platform_device.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 26 | #include <linux/slab.h> |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 27 | #include <linux/spinlock.h> |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 28 | |
| 29 | #include <asm/cacheflush.h> |
| 30 | #include <asm/smp_plat.h> |
| 31 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 32 | static void __iomem *cci_ctrl_base; |
| 33 | static unsigned long cci_ctrl_phys; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 34 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 35 | #ifdef CONFIG_ARM_CCI400_PORT_CTRL |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 36 | struct cci_nb_ports { |
| 37 | unsigned int nb_ace; |
| 38 | unsigned int nb_ace_lite; |
| 39 | }; |
| 40 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 41 | static const struct cci_nb_ports cci400_ports = { |
| 42 | .nb_ace = 2, |
| 43 | .nb_ace_lite = 3 |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 44 | }; |
| 45 | |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 46 | #define CCI400_PORTS_DATA (&cci400_ports) |
| 47 | #else |
| 48 | #define CCI400_PORTS_DATA (NULL) |
| 49 | #endif |
| 50 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 51 | static const struct of_device_id arm_cci_matches[] = { |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 52 | #ifdef CONFIG_ARM_CCI400_COMMON |
| 53 | {.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA }, |
| 54 | #endif |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 55 | #ifdef CONFIG_ARM_CCI500_PMU |
| 56 | { .compatible = "arm,cci-500", }, |
| 57 | #endif |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 58 | {}, |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 59 | }; |
| 60 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 61 | #ifdef CONFIG_ARM_CCI_PMU |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 62 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 63 | #define DRIVER_NAME "ARM-CCI" |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 64 | #define DRIVER_NAME_PMU DRIVER_NAME " PMU" |
| 65 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 66 | #define CCI_PMCR 0x0100 |
| 67 | #define CCI_PID2 0x0fe8 |
| 68 | |
| 69 | #define CCI_PMCR_CEN 0x00000001 |
| 70 | #define CCI_PMCR_NCNT_MASK 0x0000f800 |
| 71 | #define CCI_PMCR_NCNT_SHIFT 11 |
| 72 | |
| 73 | #define CCI_PID2_REV_MASK 0xf0 |
| 74 | #define CCI_PID2_REV_SHIFT 4 |
| 75 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 76 | #define CCI_PMU_EVT_SEL 0x000 |
| 77 | #define CCI_PMU_CNTR 0x004 |
| 78 | #define CCI_PMU_CNTR_CTRL 0x008 |
| 79 | #define CCI_PMU_OVRFLW 0x00c |
| 80 | |
| 81 | #define CCI_PMU_OVRFLW_FLAG 1 |
| 82 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 83 | #define CCI_PMU_CNTR_SIZE(model) ((model)->cntr_size) |
| 84 | #define CCI_PMU_CNTR_BASE(model, idx) ((idx) * CCI_PMU_CNTR_SIZE(model)) |
| 85 | #define CCI_PMU_CNTR_MASK ((1ULL << 32) -1) |
| 86 | #define CCI_PMU_CNTR_LAST(cci_pmu) (cci_pmu->num_cntrs - 1) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 87 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 88 | #define CCI_PMU_MAX_HW_CNTRS(model) \ |
| 89 | ((model)->num_hw_cntrs + (model)->fixed_hw_cntrs) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 90 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 91 | /* Types of interfaces that can generate events */ |
| 92 | enum { |
| 93 | CCI_IF_SLAVE, |
| 94 | CCI_IF_MASTER, |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 95 | #ifdef CONFIG_ARM_CCI500_PMU |
| 96 | CCI_IF_GLOBAL, |
| 97 | #endif |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 98 | CCI_IF_MAX, |
| 99 | }; |
| 100 | |
| 101 | struct event_range { |
| 102 | u32 min; |
| 103 | u32 max; |
| 104 | }; |
| 105 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 106 | struct cci_pmu_hw_events { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 107 | struct perf_event **events; |
| 108 | unsigned long *used_mask; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 109 | raw_spinlock_t pmu_lock; |
| 110 | }; |
| 111 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 112 | struct cci_pmu; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 113 | /* |
| 114 | * struct cci_pmu_model: |
| 115 | * @fixed_hw_cntrs - Number of fixed event counters |
| 116 | * @num_hw_cntrs - Maximum number of programmable event counters |
| 117 | * @cntr_size - Size of an event counter mapping |
| 118 | */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 119 | struct cci_pmu_model { |
| 120 | char *name; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 121 | u32 fixed_hw_cntrs; |
| 122 | u32 num_hw_cntrs; |
| 123 | u32 cntr_size; |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 124 | struct attribute **format_attrs; |
| 125 | struct attribute **event_attrs; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 126 | struct event_range event_ranges[CCI_IF_MAX]; |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 127 | int (*validate_hw_event)(struct cci_pmu *, unsigned long); |
| 128 | int (*get_event_idx)(struct cci_pmu *, struct cci_pmu_hw_events *, unsigned long); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 129 | }; |
| 130 | |
| 131 | static struct cci_pmu_model cci_pmu_models[]; |
| 132 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 133 | struct cci_pmu { |
| 134 | void __iomem *base; |
| 135 | struct pmu pmu; |
| 136 | int nr_irqs; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 137 | int *irqs; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 138 | unsigned long active_irqs; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 139 | const struct cci_pmu_model *model; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 140 | struct cci_pmu_hw_events hw_events; |
| 141 | struct platform_device *plat_device; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 142 | int num_cntrs; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 143 | atomic_t active_events; |
| 144 | struct mutex reserve_mutex; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 145 | struct notifier_block cpu_nb; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 146 | cpumask_t cpus; |
| 147 | }; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 148 | |
| 149 | #define to_cci_pmu(c) (container_of(c, struct cci_pmu, pmu)) |
| 150 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 151 | enum cci_models { |
| 152 | #ifdef CONFIG_ARM_CCI400_PMU |
| 153 | CCI400_R0, |
| 154 | CCI400_R1, |
| 155 | #endif |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 156 | #ifdef CONFIG_ARM_CCI500_PMU |
| 157 | CCI500_R0, |
| 158 | #endif |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 159 | CCI_MODEL_MAX |
| 160 | }; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 161 | |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 162 | static ssize_t cci_pmu_format_show(struct device *dev, |
| 163 | struct device_attribute *attr, char *buf); |
| 164 | static ssize_t cci_pmu_event_show(struct device *dev, |
| 165 | struct device_attribute *attr, char *buf); |
| 166 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 167 | #define CCI_EXT_ATTR_ENTRY(_name, _func, _config) \ |
| 168 | &((struct dev_ext_attribute[]) { \ |
| 169 | { __ATTR(_name, S_IRUGO, _func, NULL), (void *)_config } \ |
| 170 | })[0].attr.attr |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 171 | |
| 172 | #define CCI_FORMAT_EXT_ATTR_ENTRY(_name, _config) \ |
| 173 | CCI_EXT_ATTR_ENTRY(_name, cci_pmu_format_show, (char *)_config) |
| 174 | #define CCI_EVENT_EXT_ATTR_ENTRY(_name, _config) \ |
| 175 | CCI_EXT_ATTR_ENTRY(_name, cci_pmu_event_show, (unsigned long)_config) |
| 176 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 177 | /* CCI400 PMU Specific definitions */ |
| 178 | |
| 179 | #ifdef CONFIG_ARM_CCI400_PMU |
| 180 | |
| 181 | /* Port ids */ |
| 182 | #define CCI400_PORT_S0 0 |
| 183 | #define CCI400_PORT_S1 1 |
| 184 | #define CCI400_PORT_S2 2 |
| 185 | #define CCI400_PORT_S3 3 |
| 186 | #define CCI400_PORT_S4 4 |
| 187 | #define CCI400_PORT_M0 5 |
| 188 | #define CCI400_PORT_M1 6 |
| 189 | #define CCI400_PORT_M2 7 |
| 190 | |
| 191 | #define CCI400_R1_PX 5 |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 192 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 193 | /* |
| 194 | * Instead of an event id to monitor CCI cycles, a dedicated counter is |
| 195 | * provided. Use 0xff to represent CCI cycles and hope that no future revisions |
| 196 | * make use of this event in hardware. |
| 197 | */ |
| 198 | enum cci400_perf_events { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 199 | CCI400_PMU_CYCLES = 0xff |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 200 | }; |
| 201 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 202 | #define CCI400_PMU_CYCLE_CNTR_IDX 0 |
| 203 | #define CCI400_PMU_CNTR0_IDX 1 |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 204 | |
| 205 | /* |
| 206 | * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8 |
| 207 | * ports and bits 4:0 are event codes. There are different event codes |
| 208 | * associated with each port type. |
| 209 | * |
| 210 | * Additionally, the range of events associated with the port types changed |
| 211 | * between Rev0 and Rev1. |
| 212 | * |
| 213 | * The constants below define the range of valid codes for each port type for |
| 214 | * the different revisions and are used to validate the event to be monitored. |
| 215 | */ |
| 216 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 217 | #define CCI400_PMU_EVENT_MASK 0xffUL |
| 218 | #define CCI400_PMU_EVENT_SOURCE_SHIFT 5 |
| 219 | #define CCI400_PMU_EVENT_SOURCE_MASK 0x7 |
| 220 | #define CCI400_PMU_EVENT_CODE_SHIFT 0 |
| 221 | #define CCI400_PMU_EVENT_CODE_MASK 0x1f |
| 222 | #define CCI400_PMU_EVENT_SOURCE(event) \ |
| 223 | ((event >> CCI400_PMU_EVENT_SOURCE_SHIFT) & \ |
| 224 | CCI400_PMU_EVENT_SOURCE_MASK) |
| 225 | #define CCI400_PMU_EVENT_CODE(event) \ |
| 226 | ((event >> CCI400_PMU_EVENT_CODE_SHIFT) & CCI400_PMU_EVENT_CODE_MASK) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 227 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 228 | #define CCI400_R0_SLAVE_PORT_MIN_EV 0x00 |
| 229 | #define CCI400_R0_SLAVE_PORT_MAX_EV 0x13 |
| 230 | #define CCI400_R0_MASTER_PORT_MIN_EV 0x14 |
| 231 | #define CCI400_R0_MASTER_PORT_MAX_EV 0x1a |
| 232 | |
| 233 | #define CCI400_R1_SLAVE_PORT_MIN_EV 0x00 |
| 234 | #define CCI400_R1_SLAVE_PORT_MAX_EV 0x14 |
| 235 | #define CCI400_R1_MASTER_PORT_MIN_EV 0x00 |
| 236 | #define CCI400_R1_MASTER_PORT_MAX_EV 0x11 |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 237 | |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 238 | #define CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(_name, _config) \ |
| 239 | CCI_EXT_ATTR_ENTRY(_name, cci400_pmu_cycle_event_show, \ |
| 240 | (unsigned long)_config) |
| 241 | |
| 242 | static ssize_t cci400_pmu_cycle_event_show(struct device *dev, |
| 243 | struct device_attribute *attr, char *buf); |
| 244 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 245 | static struct attribute *cci400_pmu_format_attrs[] = { |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 246 | CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"), |
| 247 | CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-7"), |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 248 | NULL |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 249 | }; |
| 250 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 251 | static struct attribute *cci400_r0_pmu_event_attrs[] = { |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 252 | /* Slave events */ |
| 253 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0), |
| 254 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01), |
| 255 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2), |
| 256 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3), |
| 257 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4), |
| 258 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5), |
| 259 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6), |
| 260 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7), |
| 261 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8), |
| 262 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9), |
| 263 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA), |
| 264 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB), |
| 265 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC), |
| 266 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD), |
| 267 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE), |
| 268 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF), |
| 269 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10), |
| 270 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11), |
| 271 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12), |
| 272 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13), |
| 273 | /* Master events */ |
| 274 | CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x14), |
| 275 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_addr_hazard, 0x15), |
| 276 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_id_hazard, 0x16), |
| 277 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_tt_full, 0x17), |
| 278 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x18), |
| 279 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x19), |
| 280 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_tt_full, 0x1A), |
| 281 | /* Special event for cycles counter */ |
| 282 | CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff), |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 283 | NULL |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 284 | }; |
| 285 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 286 | static struct attribute *cci400_r1_pmu_event_attrs[] = { |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 287 | /* Slave events */ |
| 288 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0), |
| 289 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01), |
| 290 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2), |
| 291 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3), |
| 292 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4), |
| 293 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5), |
| 294 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6), |
| 295 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7), |
| 296 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8), |
| 297 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9), |
| 298 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA), |
| 299 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB), |
| 300 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC), |
| 301 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD), |
| 302 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE), |
| 303 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF), |
| 304 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10), |
| 305 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11), |
| 306 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12), |
| 307 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13), |
| 308 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_slave_id_hazard, 0x14), |
| 309 | /* Master events */ |
| 310 | CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x0), |
| 311 | CCI_EVENT_EXT_ATTR_ENTRY(mi_stall_cycle_addr_hazard, 0x1), |
| 312 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_master_id_hazard, 0x2), |
| 313 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_hi_prio_rtq_full, 0x3), |
| 314 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x4), |
| 315 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x5), |
| 316 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_wtq_full, 0x6), |
| 317 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_low_prio_rtq_full, 0x7), |
| 318 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_mid_prio_rtq_full, 0x8), |
| 319 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn0, 0x9), |
| 320 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn1, 0xA), |
| 321 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn2, 0xB), |
| 322 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn3, 0xC), |
| 323 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn0, 0xD), |
| 324 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn1, 0xE), |
| 325 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn2, 0xF), |
| 326 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn3, 0x10), |
| 327 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_unique_or_line_unique_addr_hazard, 0x11), |
| 328 | /* Special event for cycles counter */ |
| 329 | CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff), |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 330 | NULL |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 331 | }; |
| 332 | |
| 333 | static ssize_t cci400_pmu_cycle_event_show(struct device *dev, |
| 334 | struct device_attribute *attr, char *buf) |
| 335 | { |
| 336 | struct dev_ext_attribute *eattr = container_of(attr, |
| 337 | struct dev_ext_attribute, attr); |
| 338 | return snprintf(buf, PAGE_SIZE, "config=0x%lx\n", (unsigned long)eattr->var); |
| 339 | } |
| 340 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 341 | static int cci400_get_event_idx(struct cci_pmu *cci_pmu, |
| 342 | struct cci_pmu_hw_events *hw, |
| 343 | unsigned long cci_event) |
| 344 | { |
| 345 | int idx; |
| 346 | |
| 347 | /* cycles event idx is fixed */ |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 348 | if (cci_event == CCI400_PMU_CYCLES) { |
| 349 | if (test_and_set_bit(CCI400_PMU_CYCLE_CNTR_IDX, hw->used_mask)) |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 350 | return -EAGAIN; |
| 351 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 352 | return CCI400_PMU_CYCLE_CNTR_IDX; |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 353 | } |
| 354 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 355 | for (idx = CCI400_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx) |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 356 | if (!test_and_set_bit(idx, hw->used_mask)) |
| 357 | return idx; |
| 358 | |
| 359 | /* No counters available */ |
| 360 | return -EAGAIN; |
| 361 | } |
| 362 | |
| 363 | static int cci400_validate_hw_event(struct cci_pmu *cci_pmu, unsigned long hw_event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 364 | { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 365 | u8 ev_source = CCI400_PMU_EVENT_SOURCE(hw_event); |
| 366 | u8 ev_code = CCI400_PMU_EVENT_CODE(hw_event); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 367 | int if_type; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 368 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 369 | if (hw_event & ~CCI400_PMU_EVENT_MASK) |
Suzuki K. Poulose | 874c571 | 2015-03-18 12:24:42 +0000 | [diff] [blame] | 370 | return -ENOENT; |
| 371 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 372 | if (hw_event == CCI400_PMU_CYCLES) |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 373 | return hw_event; |
| 374 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 375 | switch (ev_source) { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 376 | case CCI400_PORT_S0: |
| 377 | case CCI400_PORT_S1: |
| 378 | case CCI400_PORT_S2: |
| 379 | case CCI400_PORT_S3: |
| 380 | case CCI400_PORT_S4: |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 381 | /* Slave Interface */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 382 | if_type = CCI_IF_SLAVE; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 383 | break; |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 384 | case CCI400_PORT_M0: |
| 385 | case CCI400_PORT_M1: |
| 386 | case CCI400_PORT_M2: |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 387 | /* Master Interface */ |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 388 | if_type = CCI_IF_MASTER; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 389 | break; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 390 | default: |
| 391 | return -ENOENT; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 392 | } |
| 393 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 394 | if (ev_code >= cci_pmu->model->event_ranges[if_type].min && |
| 395 | ev_code <= cci_pmu->model->event_ranges[if_type].max) |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 396 | return hw_event; |
| 397 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 398 | return -ENOENT; |
| 399 | } |
| 400 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 401 | static int probe_cci400_revision(void) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 402 | { |
| 403 | int rev; |
| 404 | rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK; |
| 405 | rev >>= CCI_PID2_REV_SHIFT; |
| 406 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 407 | if (rev < CCI400_R1_PX) |
| 408 | return CCI400_R0; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 409 | else |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 410 | return CCI400_R1; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 411 | } |
| 412 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 413 | static const struct cci_pmu_model *probe_cci_model(struct platform_device *pdev) |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 414 | { |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 415 | if (platform_has_secure_cci_access()) |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 416 | return &cci_pmu_models[probe_cci400_revision()]; |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 417 | return NULL; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 418 | } |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 419 | #else /* !CONFIG_ARM_CCI400_PMU */ |
| 420 | static inline struct cci_pmu_model *probe_cci_model(struct platform_device *pdev) |
| 421 | { |
| 422 | return NULL; |
| 423 | } |
| 424 | #endif /* CONFIG_ARM_CCI400_PMU */ |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 425 | |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 426 | #ifdef CONFIG_ARM_CCI500_PMU |
| 427 | |
| 428 | /* |
| 429 | * CCI500 provides 8 independent event counters that can count |
| 430 | * any of the events available. |
| 431 | * |
| 432 | * CCI500 PMU event id is an 9-bit value made of two parts. |
| 433 | * bits [8:5] - Source for the event |
| 434 | * 0x0-0x6 - Slave interfaces |
| 435 | * 0x8-0xD - Master interfaces |
| 436 | * 0xf - Global Events |
| 437 | * 0x7,0xe - Reserved |
| 438 | * |
| 439 | * bits [4:0] - Event code (specific to type of interface) |
| 440 | */ |
| 441 | |
| 442 | /* Port ids */ |
| 443 | #define CCI500_PORT_S0 0x0 |
| 444 | #define CCI500_PORT_S1 0x1 |
| 445 | #define CCI500_PORT_S2 0x2 |
| 446 | #define CCI500_PORT_S3 0x3 |
| 447 | #define CCI500_PORT_S4 0x4 |
| 448 | #define CCI500_PORT_S5 0x5 |
| 449 | #define CCI500_PORT_S6 0x6 |
| 450 | |
| 451 | #define CCI500_PORT_M0 0x8 |
| 452 | #define CCI500_PORT_M1 0x9 |
| 453 | #define CCI500_PORT_M2 0xa |
| 454 | #define CCI500_PORT_M3 0xb |
| 455 | #define CCI500_PORT_M4 0xc |
| 456 | #define CCI500_PORT_M5 0xd |
| 457 | |
| 458 | #define CCI500_PORT_GLOBAL 0xf |
| 459 | |
| 460 | #define CCI500_PMU_EVENT_MASK 0x1ffUL |
| 461 | #define CCI500_PMU_EVENT_SOURCE_SHIFT 0x5 |
| 462 | #define CCI500_PMU_EVENT_SOURCE_MASK 0xf |
| 463 | #define CCI500_PMU_EVENT_CODE_SHIFT 0x0 |
| 464 | #define CCI500_PMU_EVENT_CODE_MASK 0x1f |
| 465 | |
| 466 | #define CCI500_PMU_EVENT_SOURCE(event) \ |
| 467 | ((event >> CCI500_PMU_EVENT_SOURCE_SHIFT) & CCI500_PMU_EVENT_SOURCE_MASK) |
| 468 | #define CCI500_PMU_EVENT_CODE(event) \ |
| 469 | ((event >> CCI500_PMU_EVENT_CODE_SHIFT) & CCI500_PMU_EVENT_CODE_MASK) |
| 470 | |
| 471 | #define CCI500_SLAVE_PORT_MIN_EV 0x00 |
| 472 | #define CCI500_SLAVE_PORT_MAX_EV 0x1f |
| 473 | #define CCI500_MASTER_PORT_MIN_EV 0x00 |
| 474 | #define CCI500_MASTER_PORT_MAX_EV 0x06 |
| 475 | #define CCI500_GLOBAL_PORT_MIN_EV 0x00 |
| 476 | #define CCI500_GLOBAL_PORT_MAX_EV 0x0f |
| 477 | |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 478 | |
| 479 | #define CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(_name, _config) \ |
| 480 | CCI_EXT_ATTR_ENTRY(_name, cci500_pmu_global_event_show, \ |
| 481 | (unsigned long) _config) |
| 482 | |
| 483 | static ssize_t cci500_pmu_global_event_show(struct device *dev, |
| 484 | struct device_attribute *attr, char *buf); |
| 485 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 486 | static struct attribute *cci500_pmu_format_attrs[] = { |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 487 | CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"), |
| 488 | CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-8"), |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 489 | NULL, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 490 | }; |
| 491 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 492 | static struct attribute *cci500_pmu_event_attrs[] = { |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 493 | /* Slave events */ |
| 494 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_arvalid, 0x0), |
| 495 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_dev, 0x1), |
| 496 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_nonshareable, 0x2), |
| 497 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_non_alloc, 0x3), |
| 498 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_alloc, 0x4), |
| 499 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_invalidate, 0x5), |
| 500 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maint, 0x6), |
| 501 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7), |
| 502 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rval, 0x8), |
| 503 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rlast_snoop, 0x9), |
| 504 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_awalid, 0xA), |
| 505 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_dev, 0xB), |
| 506 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_non_shareable, 0xC), |
| 507 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wb, 0xD), |
| 508 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wlu, 0xE), |
| 509 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wunique, 0xF), |
| 510 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_evict, 0x10), |
| 511 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_wrevict, 0x11), |
| 512 | CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_beat, 0x12), |
| 513 | CCI_EVENT_EXT_ATTR_ENTRY(si_srq_acvalid, 0x13), |
| 514 | CCI_EVENT_EXT_ATTR_ENTRY(si_srq_read, 0x14), |
| 515 | CCI_EVENT_EXT_ATTR_ENTRY(si_srq_clean, 0x15), |
| 516 | CCI_EVENT_EXT_ATTR_ENTRY(si_srq_data_transfer_low, 0x16), |
| 517 | CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_arvalid, 0x17), |
| 518 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall, 0x18), |
| 519 | CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall, 0x19), |
| 520 | CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_stall, 0x1A), |
| 521 | CCI_EVENT_EXT_ATTR_ENTRY(si_w_resp_stall, 0x1B), |
| 522 | CCI_EVENT_EXT_ATTR_ENTRY(si_srq_stall, 0x1C), |
| 523 | CCI_EVENT_EXT_ATTR_ENTRY(si_s_data_stall, 0x1D), |
| 524 | CCI_EVENT_EXT_ATTR_ENTRY(si_rq_stall_ot_limit, 0x1E), |
| 525 | CCI_EVENT_EXT_ATTR_ENTRY(si_r_stall_arbit, 0x1F), |
| 526 | |
| 527 | /* Master events */ |
| 528 | CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_beat_any, 0x0), |
| 529 | CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_beat_any, 0x1), |
| 530 | CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall, 0x2), |
| 531 | CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_stall, 0x3), |
| 532 | CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall, 0x4), |
| 533 | CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_stall, 0x5), |
| 534 | CCI_EVENT_EXT_ATTR_ENTRY(mi_w_resp_stall, 0x6), |
| 535 | |
| 536 | /* Global events */ |
| 537 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_0_1, 0x0), |
| 538 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_2_3, 0x1), |
| 539 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_4_5, 0x2), |
| 540 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_6_7, 0x3), |
| 541 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_0_1, 0x4), |
| 542 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_2_3, 0x5), |
| 543 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_4_5, 0x6), |
| 544 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_6_7, 0x7), |
| 545 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_back_invalidation, 0x8), |
| 546 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_alloc_busy, 0x9), |
| 547 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_tt_full, 0xA), |
| 548 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB), |
| 549 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC), |
| 550 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD), |
| 551 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snopp_rq_stall_tt_full, 0xE), |
| 552 | CCI500_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF), |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 553 | NULL |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 554 | }; |
| 555 | |
| 556 | static ssize_t cci500_pmu_global_event_show(struct device *dev, |
| 557 | struct device_attribute *attr, char *buf) |
| 558 | { |
| 559 | struct dev_ext_attribute *eattr = container_of(attr, |
| 560 | struct dev_ext_attribute, attr); |
| 561 | /* Global events have single fixed source code */ |
| 562 | return snprintf(buf, PAGE_SIZE, "event=0x%lx,source=0x%x\n", |
| 563 | (unsigned long)eattr->var, CCI500_PORT_GLOBAL); |
| 564 | } |
| 565 | |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 566 | static int cci500_validate_hw_event(struct cci_pmu *cci_pmu, |
| 567 | unsigned long hw_event) |
| 568 | { |
| 569 | u32 ev_source = CCI500_PMU_EVENT_SOURCE(hw_event); |
| 570 | u32 ev_code = CCI500_PMU_EVENT_CODE(hw_event); |
| 571 | int if_type; |
| 572 | |
| 573 | if (hw_event & ~CCI500_PMU_EVENT_MASK) |
| 574 | return -ENOENT; |
| 575 | |
| 576 | switch (ev_source) { |
| 577 | case CCI500_PORT_S0: |
| 578 | case CCI500_PORT_S1: |
| 579 | case CCI500_PORT_S2: |
| 580 | case CCI500_PORT_S3: |
| 581 | case CCI500_PORT_S4: |
| 582 | case CCI500_PORT_S5: |
| 583 | case CCI500_PORT_S6: |
| 584 | if_type = CCI_IF_SLAVE; |
| 585 | break; |
| 586 | case CCI500_PORT_M0: |
| 587 | case CCI500_PORT_M1: |
| 588 | case CCI500_PORT_M2: |
| 589 | case CCI500_PORT_M3: |
| 590 | case CCI500_PORT_M4: |
| 591 | case CCI500_PORT_M5: |
| 592 | if_type = CCI_IF_MASTER; |
| 593 | break; |
| 594 | case CCI500_PORT_GLOBAL: |
| 595 | if_type = CCI_IF_GLOBAL; |
| 596 | break; |
| 597 | default: |
| 598 | return -ENOENT; |
| 599 | } |
| 600 | |
| 601 | if (ev_code >= cci_pmu->model->event_ranges[if_type].min && |
| 602 | ev_code <= cci_pmu->model->event_ranges[if_type].max) |
| 603 | return hw_event; |
| 604 | |
| 605 | return -ENOENT; |
| 606 | } |
| 607 | #endif /* CONFIG_ARM_CCI500_PMU */ |
| 608 | |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 609 | static ssize_t cci_pmu_format_show(struct device *dev, |
| 610 | struct device_attribute *attr, char *buf) |
| 611 | { |
| 612 | struct dev_ext_attribute *eattr = container_of(attr, |
| 613 | struct dev_ext_attribute, attr); |
| 614 | return snprintf(buf, PAGE_SIZE, "%s\n", (char *)eattr->var); |
| 615 | } |
| 616 | |
| 617 | static ssize_t cci_pmu_event_show(struct device *dev, |
| 618 | struct device_attribute *attr, char *buf) |
| 619 | { |
| 620 | struct dev_ext_attribute *eattr = container_of(attr, |
| 621 | struct dev_ext_attribute, attr); |
| 622 | /* source parameter is mandatory for normal PMU events */ |
| 623 | return snprintf(buf, PAGE_SIZE, "source=?,event=0x%lx\n", |
| 624 | (unsigned long)eattr->var); |
| 625 | } |
| 626 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 627 | static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 628 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 629 | return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 630 | } |
| 631 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 632 | static u32 pmu_read_register(struct cci_pmu *cci_pmu, int idx, unsigned int offset) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 633 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 634 | return readl_relaxed(cci_pmu->base + |
| 635 | CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 636 | } |
| 637 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 638 | static void pmu_write_register(struct cci_pmu *cci_pmu, u32 value, |
| 639 | int idx, unsigned int offset) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 640 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 641 | return writel_relaxed(value, cci_pmu->base + |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 642 | CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 643 | } |
| 644 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 645 | static void pmu_disable_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 646 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 647 | pmu_write_register(cci_pmu, 0, idx, CCI_PMU_CNTR_CTRL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 648 | } |
| 649 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 650 | static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 651 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 652 | pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 653 | } |
| 654 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 655 | static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 656 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 657 | pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 658 | } |
| 659 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 660 | /* |
| 661 | * Returns the number of programmable counters actually implemented |
| 662 | * by the cci |
| 663 | */ |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 664 | static u32 pmu_get_max_counters(void) |
| 665 | { |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 666 | return (readl_relaxed(cci_ctrl_base + CCI_PMCR) & |
| 667 | CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 668 | } |
| 669 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 670 | static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 671 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 672 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 673 | unsigned long cci_event = event->hw.config_base; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 674 | int idx; |
| 675 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 676 | if (cci_pmu->model->get_event_idx) |
| 677 | return cci_pmu->model->get_event_idx(cci_pmu, hw, cci_event); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 678 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 679 | /* Generic code to find an unused idx from the mask */ |
| 680 | for(idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 681 | if (!test_and_set_bit(idx, hw->used_mask)) |
| 682 | return idx; |
| 683 | |
| 684 | /* No counters available */ |
| 685 | return -EAGAIN; |
| 686 | } |
| 687 | |
| 688 | static int pmu_map_event(struct perf_event *event) |
| 689 | { |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 690 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 691 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 692 | if (event->attr.type < PERF_TYPE_MAX || |
| 693 | !cci_pmu->model->validate_hw_event) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 694 | return -ENOENT; |
| 695 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 696 | return cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 697 | } |
| 698 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 699 | static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 700 | { |
| 701 | int i; |
| 702 | struct platform_device *pmu_device = cci_pmu->plat_device; |
| 703 | |
| 704 | if (unlikely(!pmu_device)) |
| 705 | return -ENODEV; |
| 706 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 707 | if (cci_pmu->nr_irqs < 1) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 708 | dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n"); |
| 709 | return -ENODEV; |
| 710 | } |
| 711 | |
| 712 | /* |
| 713 | * Register all available CCI PMU interrupts. In the interrupt handler |
| 714 | * we iterate over the counters checking for interrupt source (the |
| 715 | * overflowing counter) and clear it. |
| 716 | * |
| 717 | * This should allow handling of non-unique interrupt for the counters. |
| 718 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 719 | for (i = 0; i < cci_pmu->nr_irqs; i++) { |
| 720 | int err = request_irq(cci_pmu->irqs[i], handler, IRQF_SHARED, |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 721 | "arm-cci-pmu", cci_pmu); |
| 722 | if (err) { |
| 723 | dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n", |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 724 | cci_pmu->irqs[i]); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 725 | return err; |
| 726 | } |
| 727 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 728 | set_bit(i, &cci_pmu->active_irqs); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | return 0; |
| 732 | } |
| 733 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 734 | static void pmu_free_irq(struct cci_pmu *cci_pmu) |
| 735 | { |
| 736 | int i; |
| 737 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 738 | for (i = 0; i < cci_pmu->nr_irqs; i++) { |
| 739 | if (!test_and_clear_bit(i, &cci_pmu->active_irqs)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 740 | continue; |
| 741 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 742 | free_irq(cci_pmu->irqs[i], cci_pmu); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 743 | } |
| 744 | } |
| 745 | |
| 746 | static u32 pmu_read_counter(struct perf_event *event) |
| 747 | { |
| 748 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 749 | struct hw_perf_event *hw_counter = &event->hw; |
| 750 | int idx = hw_counter->idx; |
| 751 | u32 value; |
| 752 | |
| 753 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
| 754 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
| 755 | return 0; |
| 756 | } |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 757 | value = pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 758 | |
| 759 | return value; |
| 760 | } |
| 761 | |
| 762 | static void pmu_write_counter(struct perf_event *event, u32 value) |
| 763 | { |
| 764 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 765 | struct hw_perf_event *hw_counter = &event->hw; |
| 766 | int idx = hw_counter->idx; |
| 767 | |
| 768 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) |
| 769 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
| 770 | else |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 771 | pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 772 | } |
| 773 | |
| 774 | static u64 pmu_event_update(struct perf_event *event) |
| 775 | { |
| 776 | struct hw_perf_event *hwc = &event->hw; |
| 777 | u64 delta, prev_raw_count, new_raw_count; |
| 778 | |
| 779 | do { |
| 780 | prev_raw_count = local64_read(&hwc->prev_count); |
| 781 | new_raw_count = pmu_read_counter(event); |
| 782 | } while (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
| 783 | new_raw_count) != prev_raw_count); |
| 784 | |
| 785 | delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK; |
| 786 | |
| 787 | local64_add(delta, &event->count); |
| 788 | |
| 789 | return new_raw_count; |
| 790 | } |
| 791 | |
| 792 | static void pmu_read(struct perf_event *event) |
| 793 | { |
| 794 | pmu_event_update(event); |
| 795 | } |
| 796 | |
| 797 | void pmu_event_set_period(struct perf_event *event) |
| 798 | { |
| 799 | struct hw_perf_event *hwc = &event->hw; |
| 800 | /* |
| 801 | * The CCI PMU counters have a period of 2^32. To account for the |
| 802 | * possiblity of extreme interrupt latency we program for a period of |
| 803 | * half that. Hopefully we can handle the interrupt before another 2^31 |
| 804 | * events occur and the counter overtakes its previous value. |
| 805 | */ |
| 806 | u64 val = 1ULL << 31; |
| 807 | local64_set(&hwc->prev_count, val); |
| 808 | pmu_write_counter(event, val); |
| 809 | } |
| 810 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 811 | static irqreturn_t pmu_handle_irq(int irq_num, void *dev) |
| 812 | { |
| 813 | unsigned long flags; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 814 | struct cci_pmu *cci_pmu = dev; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 815 | struct cci_pmu_hw_events *events = &cci_pmu->hw_events; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 816 | int idx, handled = IRQ_NONE; |
| 817 | |
| 818 | raw_spin_lock_irqsave(&events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 819 | /* |
| 820 | * Iterate over counters and update the corresponding perf events. |
| 821 | * This should work regardless of whether we have per-counter overflow |
| 822 | * interrupt or a combined overflow interrupt. |
| 823 | */ |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 824 | for (idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 825 | struct perf_event *event = events->events[idx]; |
| 826 | struct hw_perf_event *hw_counter; |
| 827 | |
| 828 | if (!event) |
| 829 | continue; |
| 830 | |
| 831 | hw_counter = &event->hw; |
| 832 | |
| 833 | /* Did this counter overflow? */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 834 | if (!(pmu_read_register(cci_pmu, idx, CCI_PMU_OVRFLW) & |
Himangi Saraogi | fc5130d | 2014-07-30 11:37:35 +0100 | [diff] [blame] | 835 | CCI_PMU_OVRFLW_FLAG)) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 836 | continue; |
| 837 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 838 | pmu_write_register(cci_pmu, CCI_PMU_OVRFLW_FLAG, idx, |
| 839 | CCI_PMU_OVRFLW); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 840 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 841 | pmu_event_update(event); |
| 842 | pmu_event_set_period(event); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 843 | handled = IRQ_HANDLED; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 844 | } |
| 845 | raw_spin_unlock_irqrestore(&events->pmu_lock, flags); |
| 846 | |
| 847 | return IRQ_RETVAL(handled); |
| 848 | } |
| 849 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 850 | static int cci_pmu_get_hw(struct cci_pmu *cci_pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 851 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 852 | int ret = pmu_request_irq(cci_pmu, pmu_handle_irq); |
| 853 | if (ret) { |
| 854 | pmu_free_irq(cci_pmu); |
| 855 | return ret; |
| 856 | } |
| 857 | return 0; |
| 858 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 859 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 860 | static void cci_pmu_put_hw(struct cci_pmu *cci_pmu) |
| 861 | { |
| 862 | pmu_free_irq(cci_pmu); |
| 863 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 864 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 865 | static void hw_perf_event_destroy(struct perf_event *event) |
| 866 | { |
| 867 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 868 | atomic_t *active_events = &cci_pmu->active_events; |
| 869 | struct mutex *reserve_mutex = &cci_pmu->reserve_mutex; |
| 870 | |
| 871 | if (atomic_dec_and_mutex_lock(active_events, reserve_mutex)) { |
| 872 | cci_pmu_put_hw(cci_pmu); |
| 873 | mutex_unlock(reserve_mutex); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 874 | } |
| 875 | } |
| 876 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 877 | static void cci_pmu_enable(struct pmu *pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 878 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 879 | struct cci_pmu *cci_pmu = to_cci_pmu(pmu); |
| 880 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 881 | int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 882 | unsigned long flags; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 883 | u32 val; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 884 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 885 | if (!enabled) |
| 886 | return; |
| 887 | |
| 888 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 889 | |
| 890 | /* Enable all the PMU counters. */ |
| 891 | val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN; |
| 892 | writel(val, cci_ctrl_base + CCI_PMCR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 893 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 894 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 895 | } |
| 896 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 897 | static void cci_pmu_disable(struct pmu *pmu) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 898 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 899 | struct cci_pmu *cci_pmu = to_cci_pmu(pmu); |
| 900 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 901 | unsigned long flags; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 902 | u32 val; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 903 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 904 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 905 | |
| 906 | /* Disable all the PMU counters. */ |
| 907 | val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN; |
| 908 | writel(val, cci_ctrl_base + CCI_PMCR); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 909 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 910 | } |
| 911 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 912 | /* |
| 913 | * Check if the idx represents a non-programmable counter. |
| 914 | * All the fixed event counters are mapped before the programmable |
| 915 | * counters. |
| 916 | */ |
| 917 | static bool pmu_fixed_hw_idx(struct cci_pmu *cci_pmu, int idx) |
| 918 | { |
| 919 | return (idx >= 0) && (idx < cci_pmu->model->fixed_hw_cntrs); |
| 920 | } |
| 921 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 922 | static void cci_pmu_start(struct perf_event *event, int pmu_flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 923 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 924 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 925 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 926 | struct hw_perf_event *hwc = &event->hw; |
| 927 | int idx = hwc->idx; |
| 928 | unsigned long flags; |
| 929 | |
| 930 | /* |
| 931 | * To handle interrupt latency, we always reprogram the period |
| 932 | * regardlesss of PERF_EF_RELOAD. |
| 933 | */ |
| 934 | if (pmu_flags & PERF_EF_RELOAD) |
| 935 | WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE)); |
| 936 | |
| 937 | hwc->state = 0; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 938 | |
| 939 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
| 940 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 941 | return; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 942 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 943 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 944 | raw_spin_lock_irqsave(&hw_events->pmu_lock, flags); |
| 945 | |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 946 | /* Configure the counter unless you are counting a fixed event */ |
| 947 | if (!pmu_fixed_hw_idx(cci_pmu, idx)) |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 948 | pmu_set_event(cci_pmu, idx, hwc->config_base); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 949 | |
| 950 | pmu_event_set_period(event); |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 951 | pmu_enable_counter(cci_pmu, idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 952 | |
| 953 | raw_spin_unlock_irqrestore(&hw_events->pmu_lock, flags); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 954 | } |
| 955 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 956 | static void cci_pmu_stop(struct perf_event *event, int pmu_flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 957 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 958 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 959 | struct hw_perf_event *hwc = &event->hw; |
| 960 | int idx = hwc->idx; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 961 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 962 | if (hwc->state & PERF_HES_STOPPED) |
| 963 | return; |
| 964 | |
| 965 | if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 966 | dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 967 | return; |
| 968 | } |
| 969 | |
| 970 | /* |
| 971 | * We always reprogram the counter, so ignore PERF_EF_UPDATE. See |
| 972 | * cci_pmu_start() |
| 973 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 974 | pmu_disable_counter(cci_pmu, idx); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 975 | pmu_event_update(event); |
| 976 | hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 977 | } |
| 978 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 979 | static int cci_pmu_add(struct perf_event *event, int flags) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 980 | { |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 981 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 982 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 983 | struct hw_perf_event *hwc = &event->hw; |
| 984 | int idx; |
| 985 | int err = 0; |
| 986 | |
| 987 | perf_pmu_disable(event->pmu); |
| 988 | |
| 989 | /* If we don't have a space for the counter then finish early. */ |
| 990 | idx = pmu_get_event_idx(hw_events, event); |
| 991 | if (idx < 0) { |
| 992 | err = idx; |
| 993 | goto out; |
| 994 | } |
| 995 | |
| 996 | event->hw.idx = idx; |
| 997 | hw_events->events[idx] = event; |
| 998 | |
| 999 | hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; |
| 1000 | if (flags & PERF_EF_START) |
| 1001 | cci_pmu_start(event, PERF_EF_RELOAD); |
| 1002 | |
| 1003 | /* Propagate our changes to the userspace mapping. */ |
| 1004 | perf_event_update_userpage(event); |
| 1005 | |
| 1006 | out: |
| 1007 | perf_pmu_enable(event->pmu); |
| 1008 | return err; |
| 1009 | } |
| 1010 | |
| 1011 | static void cci_pmu_del(struct perf_event *event, int flags) |
| 1012 | { |
| 1013 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 1014 | struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events; |
| 1015 | struct hw_perf_event *hwc = &event->hw; |
| 1016 | int idx = hwc->idx; |
| 1017 | |
| 1018 | cci_pmu_stop(event, PERF_EF_UPDATE); |
| 1019 | hw_events->events[idx] = NULL; |
| 1020 | clear_bit(idx, hw_events->used_mask); |
| 1021 | |
| 1022 | perf_event_update_userpage(event); |
| 1023 | } |
| 1024 | |
| 1025 | static int |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 1026 | validate_event(struct pmu *cci_pmu, |
| 1027 | struct cci_pmu_hw_events *hw_events, |
| 1028 | struct perf_event *event) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1029 | { |
| 1030 | if (is_software_event(event)) |
| 1031 | return 1; |
| 1032 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 1033 | /* |
| 1034 | * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The |
| 1035 | * core perf code won't check that the pmu->ctx == leader->ctx |
| 1036 | * until after pmu->event_init(event). |
| 1037 | */ |
| 1038 | if (event->pmu != cci_pmu) |
| 1039 | return 0; |
| 1040 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1041 | if (event->state < PERF_EVENT_STATE_OFF) |
| 1042 | return 1; |
| 1043 | |
| 1044 | if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec) |
| 1045 | return 1; |
| 1046 | |
| 1047 | return pmu_get_event_idx(hw_events, event) >= 0; |
| 1048 | } |
| 1049 | |
| 1050 | static int |
| 1051 | validate_group(struct perf_event *event) |
| 1052 | { |
| 1053 | struct perf_event *sibling, *leader = event->group_leader; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1054 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 1055 | unsigned long mask[BITS_TO_LONGS(cci_pmu->num_cntrs)]; |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1056 | struct cci_pmu_hw_events fake_pmu = { |
| 1057 | /* |
| 1058 | * Initialise the fake PMU. We only need to populate the |
| 1059 | * used_mask for the purposes of validation. |
| 1060 | */ |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1061 | .used_mask = mask, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1062 | }; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1063 | memset(mask, 0, BITS_TO_LONGS(cci_pmu->num_cntrs) * sizeof(unsigned long)); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1064 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 1065 | if (!validate_event(event->pmu, &fake_pmu, leader)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1066 | return -EINVAL; |
| 1067 | |
| 1068 | list_for_each_entry(sibling, &leader->sibling_list, group_entry) { |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 1069 | if (!validate_event(event->pmu, &fake_pmu, sibling)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1070 | return -EINVAL; |
| 1071 | } |
| 1072 | |
Suzuki K. Poulose | b186219 | 2015-03-17 18:15:00 +0000 | [diff] [blame] | 1073 | if (!validate_event(event->pmu, &fake_pmu, event)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1074 | return -EINVAL; |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | static int |
| 1080 | __hw_perf_event_init(struct perf_event *event) |
| 1081 | { |
| 1082 | struct hw_perf_event *hwc = &event->hw; |
| 1083 | int mapping; |
| 1084 | |
| 1085 | mapping = pmu_map_event(event); |
| 1086 | |
| 1087 | if (mapping < 0) { |
| 1088 | pr_debug("event %x:%llx not supported\n", event->attr.type, |
| 1089 | event->attr.config); |
| 1090 | return mapping; |
| 1091 | } |
| 1092 | |
| 1093 | /* |
| 1094 | * We don't assign an index until we actually place the event onto |
| 1095 | * hardware. Use -1 to signify that we haven't decided where to put it |
| 1096 | * yet. |
| 1097 | */ |
| 1098 | hwc->idx = -1; |
| 1099 | hwc->config_base = 0; |
| 1100 | hwc->config = 0; |
| 1101 | hwc->event_base = 0; |
| 1102 | |
| 1103 | /* |
| 1104 | * Store the event encoding into the config_base field. |
| 1105 | */ |
| 1106 | hwc->config_base |= (unsigned long)mapping; |
| 1107 | |
| 1108 | /* |
| 1109 | * Limit the sample_period to half of the counter width. That way, the |
| 1110 | * new counter value is far less likely to overtake the previous one |
| 1111 | * unless you have some serious IRQ latency issues. |
| 1112 | */ |
| 1113 | hwc->sample_period = CCI_PMU_CNTR_MASK >> 1; |
| 1114 | hwc->last_period = hwc->sample_period; |
| 1115 | local64_set(&hwc->period_left, hwc->sample_period); |
| 1116 | |
| 1117 | if (event->group_leader != event) { |
| 1118 | if (validate_group(event) != 0) |
| 1119 | return -EINVAL; |
| 1120 | } |
| 1121 | |
| 1122 | return 0; |
| 1123 | } |
| 1124 | |
| 1125 | static int cci_pmu_event_init(struct perf_event *event) |
| 1126 | { |
| 1127 | struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu); |
| 1128 | atomic_t *active_events = &cci_pmu->active_events; |
| 1129 | int err = 0; |
| 1130 | int cpu; |
| 1131 | |
| 1132 | if (event->attr.type != event->pmu->type) |
| 1133 | return -ENOENT; |
| 1134 | |
| 1135 | /* Shared by all CPUs, no meaningful state to sample */ |
| 1136 | if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) |
| 1137 | return -EOPNOTSUPP; |
| 1138 | |
| 1139 | /* We have no filtering of any kind */ |
| 1140 | if (event->attr.exclude_user || |
| 1141 | event->attr.exclude_kernel || |
| 1142 | event->attr.exclude_hv || |
| 1143 | event->attr.exclude_idle || |
| 1144 | event->attr.exclude_host || |
| 1145 | event->attr.exclude_guest) |
| 1146 | return -EINVAL; |
| 1147 | |
| 1148 | /* |
| 1149 | * Following the example set by other "uncore" PMUs, we accept any CPU |
| 1150 | * and rewrite its affinity dynamically rather than having perf core |
| 1151 | * handle cpu == -1 and pid == -1 for this case. |
| 1152 | * |
| 1153 | * The perf core will pin online CPUs for the duration of this call and |
| 1154 | * the event being installed into its context, so the PMU's CPU can't |
| 1155 | * change under our feet. |
| 1156 | */ |
| 1157 | cpu = cpumask_first(&cci_pmu->cpus); |
| 1158 | if (event->cpu < 0 || cpu < 0) |
| 1159 | return -EINVAL; |
| 1160 | event->cpu = cpu; |
| 1161 | |
| 1162 | event->destroy = hw_perf_event_destroy; |
| 1163 | if (!atomic_inc_not_zero(active_events)) { |
| 1164 | mutex_lock(&cci_pmu->reserve_mutex); |
| 1165 | if (atomic_read(active_events) == 0) |
| 1166 | err = cci_pmu_get_hw(cci_pmu); |
| 1167 | if (!err) |
| 1168 | atomic_inc(active_events); |
| 1169 | mutex_unlock(&cci_pmu->reserve_mutex); |
| 1170 | } |
| 1171 | if (err) |
| 1172 | return err; |
| 1173 | |
| 1174 | err = __hw_perf_event_init(event); |
| 1175 | if (err) |
| 1176 | hw_perf_event_destroy(event); |
| 1177 | |
| 1178 | return err; |
| 1179 | } |
| 1180 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1181 | static ssize_t pmu_cpumask_attr_show(struct device *dev, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1182 | struct device_attribute *attr, char *buf) |
| 1183 | { |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 1184 | struct pmu *pmu = dev_get_drvdata(dev); |
| 1185 | struct cci_pmu *cci_pmu = to_cci_pmu(pmu); |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1186 | |
Tejun Heo | 660e5ec | 2015-02-13 14:37:20 -0800 | [diff] [blame] | 1187 | int n = scnprintf(buf, PAGE_SIZE - 1, "%*pbl", |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1188 | cpumask_pr_args(&cci_pmu->cpus)); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1189 | buf[n++] = '\n'; |
| 1190 | buf[n] = '\0'; |
| 1191 | return n; |
| 1192 | } |
| 1193 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 1194 | static struct device_attribute pmu_cpumask_attr = |
| 1195 | __ATTR(cpumask, S_IRUGO, pmu_cpumask_attr_show, NULL); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1196 | |
| 1197 | static struct attribute *pmu_attrs[] = { |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 1198 | &pmu_cpumask_attr.attr, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1199 | NULL, |
| 1200 | }; |
| 1201 | |
| 1202 | static struct attribute_group pmu_attr_group = { |
| 1203 | .attrs = pmu_attrs, |
| 1204 | }; |
| 1205 | |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1206 | static struct attribute_group pmu_format_attr_group = { |
| 1207 | .name = "format", |
| 1208 | .attrs = NULL, /* Filled in cci_pmu_init_attrs */ |
| 1209 | }; |
| 1210 | |
| 1211 | static struct attribute_group pmu_event_attr_group = { |
| 1212 | .name = "events", |
| 1213 | .attrs = NULL, /* Filled in cci_pmu_init_attrs */ |
| 1214 | }; |
| 1215 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1216 | static const struct attribute_group *pmu_attr_groups[] = { |
| 1217 | &pmu_attr_group, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1218 | &pmu_format_attr_group, |
| 1219 | &pmu_event_attr_group, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1220 | NULL |
| 1221 | }; |
| 1222 | |
| 1223 | static int cci_pmu_init(struct cci_pmu *cci_pmu, struct platform_device *pdev) |
| 1224 | { |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 1225 | const struct cci_pmu_model *model = cci_pmu->model; |
| 1226 | char *name = model->name; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1227 | u32 num_cntrs; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1228 | |
Mark Rutland | 5e442eb | 2016-02-23 10:49:43 +0000 | [diff] [blame^] | 1229 | pmu_event_attr_group.attrs = model->event_attrs; |
| 1230 | pmu_format_attr_group.attrs = model->format_attrs; |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1231 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1232 | cci_pmu->pmu = (struct pmu) { |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1233 | .name = cci_pmu->model->name, |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1234 | .task_ctx_nr = perf_invalid_context, |
| 1235 | .pmu_enable = cci_pmu_enable, |
| 1236 | .pmu_disable = cci_pmu_disable, |
| 1237 | .event_init = cci_pmu_event_init, |
| 1238 | .add = cci_pmu_add, |
| 1239 | .del = cci_pmu_del, |
| 1240 | .start = cci_pmu_start, |
| 1241 | .stop = cci_pmu_stop, |
| 1242 | .read = pmu_read, |
| 1243 | .attr_groups = pmu_attr_groups, |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1244 | }; |
| 1245 | |
| 1246 | cci_pmu->plat_device = pdev; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1247 | num_cntrs = pmu_get_max_counters(); |
| 1248 | if (num_cntrs > cci_pmu->model->num_hw_cntrs) { |
| 1249 | dev_warn(&pdev->dev, |
| 1250 | "PMU implements more counters(%d) than supported by" |
| 1251 | " the model(%d), truncated.", |
| 1252 | num_cntrs, cci_pmu->model->num_hw_cntrs); |
| 1253 | num_cntrs = cci_pmu->model->num_hw_cntrs; |
| 1254 | } |
| 1255 | cci_pmu->num_cntrs = num_cntrs + cci_pmu->model->fixed_hw_cntrs; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1256 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1257 | return perf_pmu_register(&cci_pmu->pmu, name, -1); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1258 | } |
| 1259 | |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1260 | static int cci_pmu_cpu_notifier(struct notifier_block *self, |
| 1261 | unsigned long action, void *hcpu) |
| 1262 | { |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1263 | struct cci_pmu *cci_pmu = container_of(self, |
| 1264 | struct cci_pmu, cpu_nb); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1265 | unsigned int cpu = (long)hcpu; |
| 1266 | unsigned int target; |
| 1267 | |
| 1268 | switch (action & ~CPU_TASKS_FROZEN) { |
| 1269 | case CPU_DOWN_PREPARE: |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1270 | if (!cpumask_test_and_clear_cpu(cpu, &cci_pmu->cpus)) |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1271 | break; |
| 1272 | target = cpumask_any_but(cpu_online_mask, cpu); |
| 1273 | if (target < 0) // UP, last CPU |
| 1274 | break; |
| 1275 | /* |
| 1276 | * TODO: migrate context once core races on event->ctx have |
| 1277 | * been fixed. |
| 1278 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1279 | cpumask_set_cpu(target, &cci_pmu->cpus); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1280 | default: |
| 1281 | break; |
| 1282 | } |
| 1283 | |
| 1284 | return NOTIFY_OK; |
| 1285 | } |
| 1286 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1287 | static struct cci_pmu_model cci_pmu_models[] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1288 | #ifdef CONFIG_ARM_CCI400_PMU |
| 1289 | [CCI400_R0] = { |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1290 | .name = "CCI_400", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1291 | .fixed_hw_cntrs = 1, /* Cycle counter */ |
| 1292 | .num_hw_cntrs = 4, |
| 1293 | .cntr_size = SZ_4K, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1294 | .format_attrs = cci400_pmu_format_attrs, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1295 | .event_attrs = cci400_r0_pmu_event_attrs, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1296 | .event_ranges = { |
| 1297 | [CCI_IF_SLAVE] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1298 | CCI400_R0_SLAVE_PORT_MIN_EV, |
| 1299 | CCI400_R0_SLAVE_PORT_MAX_EV, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1300 | }, |
| 1301 | [CCI_IF_MASTER] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1302 | CCI400_R0_MASTER_PORT_MIN_EV, |
| 1303 | CCI400_R0_MASTER_PORT_MAX_EV, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1304 | }, |
| 1305 | }, |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 1306 | .validate_hw_event = cci400_validate_hw_event, |
| 1307 | .get_event_idx = cci400_get_event_idx, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1308 | }, |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1309 | [CCI400_R1] = { |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1310 | .name = "CCI_400_r1", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1311 | .fixed_hw_cntrs = 1, /* Cycle counter */ |
| 1312 | .num_hw_cntrs = 4, |
| 1313 | .cntr_size = SZ_4K, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1314 | .format_attrs = cci400_pmu_format_attrs, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1315 | .event_attrs = cci400_r1_pmu_event_attrs, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1316 | .event_ranges = { |
| 1317 | [CCI_IF_SLAVE] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1318 | CCI400_R1_SLAVE_PORT_MIN_EV, |
| 1319 | CCI400_R1_SLAVE_PORT_MAX_EV, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1320 | }, |
| 1321 | [CCI_IF_MASTER] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1322 | CCI400_R1_MASTER_PORT_MIN_EV, |
| 1323 | CCI400_R1_MASTER_PORT_MAX_EV, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1324 | }, |
| 1325 | }, |
Suzuki K. Poulose | 3121629 | 2015-05-26 10:53:13 +0100 | [diff] [blame] | 1326 | .validate_hw_event = cci400_validate_hw_event, |
| 1327 | .get_event_idx = cci400_get_event_idx, |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1328 | }, |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1329 | #endif |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 1330 | #ifdef CONFIG_ARM_CCI500_PMU |
| 1331 | [CCI500_R0] = { |
| 1332 | .name = "CCI_500", |
| 1333 | .fixed_hw_cntrs = 0, |
| 1334 | .num_hw_cntrs = 8, |
| 1335 | .cntr_size = SZ_64K, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1336 | .format_attrs = cci500_pmu_format_attrs, |
Suzuki K. Poulose | e14cfad | 2015-05-26 10:53:16 +0100 | [diff] [blame] | 1337 | .event_attrs = cci500_pmu_event_attrs, |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 1338 | .event_ranges = { |
| 1339 | [CCI_IF_SLAVE] = { |
| 1340 | CCI500_SLAVE_PORT_MIN_EV, |
| 1341 | CCI500_SLAVE_PORT_MAX_EV, |
| 1342 | }, |
| 1343 | [CCI_IF_MASTER] = { |
| 1344 | CCI500_MASTER_PORT_MIN_EV, |
| 1345 | CCI500_MASTER_PORT_MAX_EV, |
| 1346 | }, |
| 1347 | [CCI_IF_GLOBAL] = { |
| 1348 | CCI500_GLOBAL_PORT_MIN_EV, |
| 1349 | CCI500_GLOBAL_PORT_MAX_EV, |
| 1350 | }, |
| 1351 | }, |
| 1352 | .validate_hw_event = cci500_validate_hw_event, |
| 1353 | }, |
| 1354 | #endif |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1355 | }; |
| 1356 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1357 | static const struct of_device_id arm_cci_pmu_matches[] = { |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1358 | #ifdef CONFIG_ARM_CCI400_PMU |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1359 | { |
| 1360 | .compatible = "arm,cci-400-pmu", |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 1361 | .data = NULL, |
| 1362 | }, |
| 1363 | { |
| 1364 | .compatible = "arm,cci-400-pmu,r0", |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1365 | .data = &cci_pmu_models[CCI400_R0], |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 1366 | }, |
| 1367 | { |
| 1368 | .compatible = "arm,cci-400-pmu,r1", |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1369 | .data = &cci_pmu_models[CCI400_R1], |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1370 | }, |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1371 | #endif |
Suzuki K. Poulose | a95791e | 2015-05-26 10:53:15 +0100 | [diff] [blame] | 1372 | #ifdef CONFIG_ARM_CCI500_PMU |
| 1373 | { |
| 1374 | .compatible = "arm,cci-500-pmu,r0", |
| 1375 | .data = &cci_pmu_models[CCI500_R0], |
| 1376 | }, |
| 1377 | #endif |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1378 | {}, |
| 1379 | }; |
| 1380 | |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1381 | static inline const struct cci_pmu_model *get_cci_model(struct platform_device *pdev) |
| 1382 | { |
| 1383 | const struct of_device_id *match = of_match_node(arm_cci_pmu_matches, |
| 1384 | pdev->dev.of_node); |
| 1385 | if (!match) |
| 1386 | return NULL; |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 1387 | if (match->data) |
| 1388 | return match->data; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1389 | |
Suzuki K. Poulose | 772742a | 2015-03-18 12:24:40 +0000 | [diff] [blame] | 1390 | dev_warn(&pdev->dev, "DEPRECATED compatible property," |
| 1391 | "requires secure access to CCI registers"); |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1392 | return probe_cci_model(pdev); |
| 1393 | } |
| 1394 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1395 | static bool is_duplicate_irq(int irq, int *irqs, int nr_irqs) |
| 1396 | { |
| 1397 | int i; |
| 1398 | |
| 1399 | for (i = 0; i < nr_irqs; i++) |
| 1400 | if (irq == irqs[i]) |
| 1401 | return true; |
| 1402 | |
| 1403 | return false; |
| 1404 | } |
| 1405 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1406 | static struct cci_pmu *cci_pmu_alloc(struct platform_device *pdev) |
| 1407 | { |
| 1408 | struct cci_pmu *cci_pmu; |
| 1409 | const struct cci_pmu_model *model; |
| 1410 | |
| 1411 | /* |
| 1412 | * All allocations are devm_* hence we don't have to free |
| 1413 | * them explicitly on an error, as it would end up in driver |
| 1414 | * detach. |
| 1415 | */ |
| 1416 | model = get_cci_model(pdev); |
| 1417 | if (!model) { |
| 1418 | dev_warn(&pdev->dev, "CCI PMU version not supported\n"); |
| 1419 | return ERR_PTR(-ENODEV); |
| 1420 | } |
| 1421 | |
| 1422 | cci_pmu = devm_kzalloc(&pdev->dev, sizeof(*cci_pmu), GFP_KERNEL); |
| 1423 | if (!cci_pmu) |
| 1424 | return ERR_PTR(-ENOMEM); |
| 1425 | |
| 1426 | cci_pmu->model = model; |
| 1427 | cci_pmu->irqs = devm_kcalloc(&pdev->dev, CCI_PMU_MAX_HW_CNTRS(model), |
| 1428 | sizeof(*cci_pmu->irqs), GFP_KERNEL); |
| 1429 | if (!cci_pmu->irqs) |
| 1430 | return ERR_PTR(-ENOMEM); |
| 1431 | cci_pmu->hw_events.events = devm_kcalloc(&pdev->dev, |
| 1432 | CCI_PMU_MAX_HW_CNTRS(model), |
| 1433 | sizeof(*cci_pmu->hw_events.events), |
| 1434 | GFP_KERNEL); |
| 1435 | if (!cci_pmu->hw_events.events) |
| 1436 | return ERR_PTR(-ENOMEM); |
| 1437 | cci_pmu->hw_events.used_mask = devm_kcalloc(&pdev->dev, |
| 1438 | BITS_TO_LONGS(CCI_PMU_MAX_HW_CNTRS(model)), |
| 1439 | sizeof(*cci_pmu->hw_events.used_mask), |
| 1440 | GFP_KERNEL); |
| 1441 | if (!cci_pmu->hw_events.used_mask) |
| 1442 | return ERR_PTR(-ENOMEM); |
| 1443 | |
| 1444 | return cci_pmu; |
| 1445 | } |
| 1446 | |
| 1447 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1448 | static int cci_pmu_probe(struct platform_device *pdev) |
| 1449 | { |
| 1450 | struct resource *res; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1451 | struct cci_pmu *cci_pmu; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1452 | int i, ret, irq; |
Suzuki K. Poulose | fc17c83 | 2015-03-18 12:24:39 +0000 | [diff] [blame] | 1453 | |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1454 | cci_pmu = cci_pmu_alloc(pdev); |
| 1455 | if (IS_ERR(cci_pmu)) |
| 1456 | return PTR_ERR(cci_pmu); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1457 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1458 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1459 | cci_pmu->base = devm_ioremap_resource(&pdev->dev, res); |
| 1460 | if (IS_ERR(cci_pmu->base)) |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1461 | return -ENOMEM; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1462 | |
| 1463 | /* |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1464 | * CCI PMU has one overflow interrupt per counter; but some may be tied |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1465 | * together to a common interrupt. |
| 1466 | */ |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1467 | cci_pmu->nr_irqs = 0; |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1468 | for (i = 0; i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model); i++) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1469 | irq = platform_get_irq(pdev, i); |
| 1470 | if (irq < 0) |
| 1471 | break; |
| 1472 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1473 | if (is_duplicate_irq(irq, cci_pmu->irqs, cci_pmu->nr_irqs)) |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1474 | continue; |
| 1475 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1476 | cci_pmu->irqs[cci_pmu->nr_irqs++] = irq; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1477 | } |
| 1478 | |
| 1479 | /* |
| 1480 | * Ensure that the device tree has as many interrupts as the number |
| 1481 | * of counters. |
| 1482 | */ |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1483 | if (i < CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)) { |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1484 | dev_warn(&pdev->dev, "In-correct number of interrupts: %d, should be %d\n", |
Suzuki K. Poulose | ab5b316 | 2015-05-26 10:53:12 +0100 | [diff] [blame] | 1485 | i, CCI_PMU_MAX_HW_CNTRS(cci_pmu->model)); |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1486 | return -EINVAL; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1487 | } |
| 1488 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1489 | raw_spin_lock_init(&cci_pmu->hw_events.pmu_lock); |
| 1490 | mutex_init(&cci_pmu->reserve_mutex); |
| 1491 | atomic_set(&cci_pmu->active_events, 0); |
| 1492 | cpumask_set_cpu(smp_processor_id(), &cci_pmu->cpus); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1493 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1494 | cci_pmu->cpu_nb = (struct notifier_block) { |
| 1495 | .notifier_call = cci_pmu_cpu_notifier, |
| 1496 | /* |
| 1497 | * to migrate uncore events, our notifier should be executed |
| 1498 | * before perf core's notifier. |
| 1499 | */ |
| 1500 | .priority = CPU_PRI_PERF + 1, |
| 1501 | }; |
| 1502 | |
| 1503 | ret = register_cpu_notifier(&cci_pmu->cpu_nb); |
Mark Rutland | c6f85cb | 2014-06-30 12:20:21 +0100 | [diff] [blame] | 1504 | if (ret) |
| 1505 | return ret; |
| 1506 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1507 | ret = cci_pmu_init(cci_pmu, pdev); |
| 1508 | if (ret) { |
| 1509 | unregister_cpu_notifier(&cci_pmu->cpu_nb); |
Wei Yongjun | fee4f2c | 2013-09-22 06:04:23 +0100 | [diff] [blame] | 1510 | return ret; |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1511 | } |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1512 | |
Suzuki K. Poulose | a1a076d | 2015-05-26 10:53:11 +0100 | [diff] [blame] | 1513 | pr_info("ARM %s PMU driver probed", cci_pmu->model->name); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1514 | return 0; |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1515 | } |
| 1516 | |
| 1517 | static int cci_platform_probe(struct platform_device *pdev) |
| 1518 | { |
| 1519 | if (!cci_probed()) |
| 1520 | return -ENODEV; |
| 1521 | |
| 1522 | return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); |
| 1523 | } |
| 1524 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1525 | static struct platform_driver cci_pmu_driver = { |
| 1526 | .driver = { |
| 1527 | .name = DRIVER_NAME_PMU, |
| 1528 | .of_match_table = arm_cci_pmu_matches, |
| 1529 | }, |
| 1530 | .probe = cci_pmu_probe, |
| 1531 | }; |
| 1532 | |
| 1533 | static struct platform_driver cci_platform_driver = { |
| 1534 | .driver = { |
| 1535 | .name = DRIVER_NAME, |
| 1536 | .of_match_table = arm_cci_matches, |
| 1537 | }, |
| 1538 | .probe = cci_platform_probe, |
| 1539 | }; |
| 1540 | |
| 1541 | static int __init cci_platform_init(void) |
| 1542 | { |
| 1543 | int ret; |
| 1544 | |
| 1545 | ret = platform_driver_register(&cci_pmu_driver); |
| 1546 | if (ret) |
| 1547 | return ret; |
| 1548 | |
| 1549 | return platform_driver_register(&cci_platform_driver); |
| 1550 | } |
| 1551 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1552 | #else /* !CONFIG_ARM_CCI_PMU */ |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1553 | |
| 1554 | static int __init cci_platform_init(void) |
| 1555 | { |
| 1556 | return 0; |
| 1557 | } |
| 1558 | |
Suzuki K. Poulose | f4d5893 | 2015-05-26 10:53:14 +0100 | [diff] [blame] | 1559 | #endif /* CONFIG_ARM_CCI_PMU */ |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 1560 | |
| 1561 | #ifdef CONFIG_ARM_CCI400_PORT_CTRL |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1562 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1563 | #define CCI_PORT_CTRL 0x0 |
| 1564 | #define CCI_CTRL_STATUS 0xc |
| 1565 | |
| 1566 | #define CCI_ENABLE_SNOOP_REQ 0x1 |
| 1567 | #define CCI_ENABLE_DVM_REQ 0x2 |
| 1568 | #define CCI_ENABLE_REQ (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ) |
| 1569 | |
| 1570 | enum cci_ace_port_type { |
| 1571 | ACE_INVALID_PORT = 0x0, |
| 1572 | ACE_PORT, |
| 1573 | ACE_LITE_PORT, |
| 1574 | }; |
| 1575 | |
| 1576 | struct cci_ace_port { |
| 1577 | void __iomem *base; |
| 1578 | unsigned long phys; |
| 1579 | enum cci_ace_port_type type; |
| 1580 | struct device_node *dn; |
| 1581 | }; |
| 1582 | |
| 1583 | static struct cci_ace_port *ports; |
| 1584 | static unsigned int nb_cci_ports; |
| 1585 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1586 | struct cpu_port { |
| 1587 | u64 mpidr; |
| 1588 | u32 port; |
| 1589 | }; |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1590 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1591 | /* |
| 1592 | * Use the port MSB as valid flag, shift can be made dynamic |
| 1593 | * by computing number of bits required for port indexes. |
| 1594 | * Code disabling CCI cpu ports runs with D-cache invalidated |
| 1595 | * and SCTLR bit clear so data accesses must be kept to a minimum |
| 1596 | * to improve performance; for now shift is left static to |
| 1597 | * avoid one more data access while disabling the CCI port. |
| 1598 | */ |
| 1599 | #define PORT_VALID_SHIFT 31 |
| 1600 | #define PORT_VALID (0x1 << PORT_VALID_SHIFT) |
| 1601 | |
| 1602 | static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr) |
| 1603 | { |
| 1604 | port->port = PORT_VALID | index; |
| 1605 | port->mpidr = mpidr; |
| 1606 | } |
| 1607 | |
| 1608 | static inline bool cpu_port_is_valid(struct cpu_port *port) |
| 1609 | { |
| 1610 | return !!(port->port & PORT_VALID); |
| 1611 | } |
| 1612 | |
| 1613 | static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr) |
| 1614 | { |
| 1615 | return port->mpidr == (mpidr & MPIDR_HWID_BITMASK); |
| 1616 | } |
| 1617 | |
| 1618 | static struct cpu_port cpu_port[NR_CPUS]; |
| 1619 | |
| 1620 | /** |
| 1621 | * __cci_ace_get_port - Function to retrieve the port index connected to |
| 1622 | * a cpu or device. |
| 1623 | * |
| 1624 | * @dn: device node of the device to look-up |
| 1625 | * @type: port type |
| 1626 | * |
| 1627 | * Return value: |
| 1628 | * - CCI port index if success |
| 1629 | * - -ENODEV if failure |
| 1630 | */ |
| 1631 | static int __cci_ace_get_port(struct device_node *dn, int type) |
| 1632 | { |
| 1633 | int i; |
| 1634 | bool ace_match; |
| 1635 | struct device_node *cci_portn; |
| 1636 | |
| 1637 | cci_portn = of_parse_phandle(dn, "cci-control-port", 0); |
| 1638 | for (i = 0; i < nb_cci_ports; i++) { |
| 1639 | ace_match = ports[i].type == type; |
| 1640 | if (ace_match && cci_portn == ports[i].dn) |
| 1641 | return i; |
| 1642 | } |
| 1643 | return -ENODEV; |
| 1644 | } |
| 1645 | |
| 1646 | int cci_ace_get_port(struct device_node *dn) |
| 1647 | { |
| 1648 | return __cci_ace_get_port(dn, ACE_LITE_PORT); |
| 1649 | } |
| 1650 | EXPORT_SYMBOL_GPL(cci_ace_get_port); |
| 1651 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 1652 | static void cci_ace_init_ports(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1653 | { |
Sudeep KarkadaNagesha | 78b4d6e | 2013-06-17 14:51:48 +0100 | [diff] [blame] | 1654 | int port, cpu; |
| 1655 | struct device_node *cpun; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1656 | |
| 1657 | /* |
| 1658 | * Port index look-up speeds up the function disabling ports by CPU, |
| 1659 | * since the logical to port index mapping is done once and does |
| 1660 | * not change after system boot. |
| 1661 | * The stashed index array is initialized for all possible CPUs |
| 1662 | * at probe time. |
| 1663 | */ |
Sudeep KarkadaNagesha | 78b4d6e | 2013-06-17 14:51:48 +0100 | [diff] [blame] | 1664 | for_each_possible_cpu(cpu) { |
| 1665 | /* too early to use cpu->of_node */ |
| 1666 | cpun = of_get_cpu_node(cpu, NULL); |
| 1667 | |
| 1668 | if (WARN(!cpun, "Missing cpu device node\n")) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1669 | continue; |
| 1670 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1671 | port = __cci_ace_get_port(cpun, ACE_PORT); |
| 1672 | if (port < 0) |
| 1673 | continue; |
| 1674 | |
| 1675 | init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu)); |
| 1676 | } |
| 1677 | |
| 1678 | for_each_possible_cpu(cpu) { |
| 1679 | WARN(!cpu_port_is_valid(&cpu_port[cpu]), |
| 1680 | "CPU %u does not have an associated CCI port\n", |
| 1681 | cpu); |
| 1682 | } |
| 1683 | } |
| 1684 | /* |
| 1685 | * Functions to enable/disable a CCI interconnect slave port |
| 1686 | * |
| 1687 | * They are called by low-level power management code to disable slave |
| 1688 | * interfaces snoops and DVM broadcast. |
| 1689 | * Since they may execute with cache data allocation disabled and |
| 1690 | * after the caches have been cleaned and invalidated the functions provide |
| 1691 | * no explicit locking since they may run with D-cache disabled, so normal |
| 1692 | * cacheable kernel locks based on ldrex/strex may not work. |
| 1693 | * Locking has to be provided by BSP implementations to ensure proper |
| 1694 | * operations. |
| 1695 | */ |
| 1696 | |
| 1697 | /** |
| 1698 | * cci_port_control() - function to control a CCI port |
| 1699 | * |
| 1700 | * @port: index of the port to setup |
| 1701 | * @enable: if true enables the port, if false disables it |
| 1702 | */ |
| 1703 | static void notrace cci_port_control(unsigned int port, bool enable) |
| 1704 | { |
| 1705 | void __iomem *base = ports[port].base; |
| 1706 | |
| 1707 | writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL); |
| 1708 | /* |
| 1709 | * This function is called from power down procedures |
| 1710 | * and must not execute any instruction that might |
| 1711 | * cause the processor to be put in a quiescent state |
| 1712 | * (eg wfi). Hence, cpu_relax() can not be added to this |
| 1713 | * read loop to optimize power, since it might hide possibly |
| 1714 | * disruptive operations. |
| 1715 | */ |
| 1716 | while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1) |
| 1717 | ; |
| 1718 | } |
| 1719 | |
| 1720 | /** |
| 1721 | * cci_disable_port_by_cpu() - function to disable a CCI port by CPU |
| 1722 | * reference |
| 1723 | * |
| 1724 | * @mpidr: mpidr of the CPU whose CCI port should be disabled |
| 1725 | * |
| 1726 | * Disabling a CCI port for a CPU implies disabling the CCI port |
| 1727 | * controlling that CPU cluster. Code disabling CPU CCI ports |
| 1728 | * must make sure that the CPU running the code is the last active CPU |
| 1729 | * in the cluster ie all other CPUs are quiescent in a low power state. |
| 1730 | * |
| 1731 | * Return: |
| 1732 | * 0 on success |
| 1733 | * -ENODEV on port look-up failure |
| 1734 | */ |
| 1735 | int notrace cci_disable_port_by_cpu(u64 mpidr) |
| 1736 | { |
| 1737 | int cpu; |
| 1738 | bool is_valid; |
| 1739 | for (cpu = 0; cpu < nr_cpu_ids; cpu++) { |
| 1740 | is_valid = cpu_port_is_valid(&cpu_port[cpu]); |
| 1741 | if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) { |
| 1742 | cci_port_control(cpu_port[cpu].port, false); |
| 1743 | return 0; |
| 1744 | } |
| 1745 | } |
| 1746 | return -ENODEV; |
| 1747 | } |
| 1748 | EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu); |
| 1749 | |
| 1750 | /** |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1751 | * cci_enable_port_for_self() - enable a CCI port for calling CPU |
| 1752 | * |
| 1753 | * Enabling a CCI port for the calling CPU implies enabling the CCI |
| 1754 | * port controlling that CPU's cluster. Caller must make sure that the |
| 1755 | * CPU running the code is the first active CPU in the cluster and all |
| 1756 | * other CPUs are quiescent in a low power state or waiting for this CPU |
| 1757 | * to complete the CCI initialization. |
| 1758 | * |
| 1759 | * Because this is called when the MMU is still off and with no stack, |
| 1760 | * the code must be position independent and ideally rely on callee |
| 1761 | * clobbered registers only. To achieve this we must code this function |
| 1762 | * entirely in assembler. |
| 1763 | * |
| 1764 | * On success this returns with the proper CCI port enabled. In case of |
| 1765 | * any failure this never returns as the inability to enable the CCI is |
| 1766 | * fatal and there is no possible recovery at this stage. |
| 1767 | */ |
| 1768 | asmlinkage void __naked cci_enable_port_for_self(void) |
| 1769 | { |
| 1770 | asm volatile ("\n" |
Arnd Bergmann | f490249 | 2013-06-03 15:15:36 +0200 | [diff] [blame] | 1771 | " .arch armv7-a\n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1772 | " mrc p15, 0, r0, c0, c0, 5 @ get MPIDR value \n" |
| 1773 | " and r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n" |
| 1774 | " adr r1, 5f \n" |
| 1775 | " ldr r2, [r1] \n" |
| 1776 | " add r1, r1, r2 @ &cpu_port \n" |
| 1777 | " add ip, r1, %[sizeof_cpu_port] \n" |
| 1778 | |
| 1779 | /* Loop over the cpu_port array looking for a matching MPIDR */ |
| 1780 | "1: ldr r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n" |
| 1781 | " cmp r2, r0 @ compare MPIDR \n" |
| 1782 | " bne 2f \n" |
| 1783 | |
| 1784 | /* Found a match, now test port validity */ |
| 1785 | " ldr r3, [r1, %[offsetof_cpu_port_port]] \n" |
| 1786 | " tst r3, #"__stringify(PORT_VALID)" \n" |
| 1787 | " bne 3f \n" |
| 1788 | |
| 1789 | /* no match, loop with the next cpu_port entry */ |
| 1790 | "2: add r1, r1, %[sizeof_struct_cpu_port] \n" |
| 1791 | " cmp r1, ip @ done? \n" |
| 1792 | " blo 1b \n" |
| 1793 | |
| 1794 | /* CCI port not found -- cheaply try to stall this CPU */ |
| 1795 | "cci_port_not_found: \n" |
| 1796 | " wfi \n" |
| 1797 | " wfe \n" |
| 1798 | " b cci_port_not_found \n" |
| 1799 | |
| 1800 | /* Use matched port index to look up the corresponding ports entry */ |
| 1801 | "3: bic r3, r3, #"__stringify(PORT_VALID)" \n" |
| 1802 | " adr r0, 6f \n" |
| 1803 | " ldmia r0, {r1, r2} \n" |
| 1804 | " sub r1, r1, r0 @ virt - phys \n" |
| 1805 | " ldr r0, [r0, r2] @ *(&ports) \n" |
| 1806 | " mov r2, %[sizeof_struct_ace_port] \n" |
| 1807 | " mla r0, r2, r3, r0 @ &ports[index] \n" |
| 1808 | " sub r0, r0, r1 @ virt_to_phys() \n" |
| 1809 | |
| 1810 | /* Enable the CCI port */ |
| 1811 | " ldr r0, [r0, %[offsetof_port_phys]] \n" |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1812 | " mov r3, %[cci_enable_req]\n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1813 | " str r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n" |
| 1814 | |
| 1815 | /* poll the status reg for completion */ |
| 1816 | " adr r1, 7f \n" |
| 1817 | " ldr r0, [r1] \n" |
| 1818 | " ldr r0, [r0, r1] @ cci_ctrl_base \n" |
| 1819 | "4: ldr r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n" |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1820 | " tst r1, %[cci_control_status_bits] \n" |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1821 | " bne 4b \n" |
| 1822 | |
| 1823 | " mov r0, #0 \n" |
| 1824 | " bx lr \n" |
| 1825 | |
| 1826 | " .align 2 \n" |
| 1827 | "5: .word cpu_port - . \n" |
| 1828 | "6: .word . \n" |
| 1829 | " .word ports - 6b \n" |
| 1830 | "7: .word cci_ctrl_phys - . \n" |
| 1831 | : : |
| 1832 | [sizeof_cpu_port] "i" (sizeof(cpu_port)), |
Victor Kamensky | fdb07ae | 2013-10-15 21:50:34 -0700 | [diff] [blame] | 1833 | [cci_enable_req] "i" cpu_to_le32(CCI_ENABLE_REQ), |
| 1834 | [cci_control_status_bits] "i" cpu_to_le32(1), |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1835 | #ifndef __ARMEB__ |
| 1836 | [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)), |
| 1837 | #else |
| 1838 | [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4), |
| 1839 | #endif |
| 1840 | [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)), |
| 1841 | [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)), |
| 1842 | [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)), |
| 1843 | [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) ); |
| 1844 | |
| 1845 | unreachable(); |
| 1846 | } |
| 1847 | |
| 1848 | /** |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1849 | * __cci_control_port_by_device() - function to control a CCI port by device |
| 1850 | * reference |
| 1851 | * |
| 1852 | * @dn: device node pointer of the device whose CCI port should be |
| 1853 | * controlled |
| 1854 | * @enable: if true enables the port, if false disables it |
| 1855 | * |
| 1856 | * Return: |
| 1857 | * 0 on success |
| 1858 | * -ENODEV on port look-up failure |
| 1859 | */ |
| 1860 | int notrace __cci_control_port_by_device(struct device_node *dn, bool enable) |
| 1861 | { |
| 1862 | int port; |
| 1863 | |
| 1864 | if (!dn) |
| 1865 | return -ENODEV; |
| 1866 | |
| 1867 | port = __cci_ace_get_port(dn, ACE_LITE_PORT); |
| 1868 | if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n", |
| 1869 | dn->full_name)) |
| 1870 | return -ENODEV; |
| 1871 | cci_port_control(port, enable); |
| 1872 | return 0; |
| 1873 | } |
| 1874 | EXPORT_SYMBOL_GPL(__cci_control_port_by_device); |
| 1875 | |
| 1876 | /** |
| 1877 | * __cci_control_port_by_index() - function to control a CCI port by port index |
| 1878 | * |
| 1879 | * @port: port index previously retrieved with cci_ace_get_port() |
| 1880 | * @enable: if true enables the port, if false disables it |
| 1881 | * |
| 1882 | * Return: |
| 1883 | * 0 on success |
| 1884 | * -ENODEV on port index out of range |
| 1885 | * -EPERM if operation carried out on an ACE PORT |
| 1886 | */ |
| 1887 | int notrace __cci_control_port_by_index(u32 port, bool enable) |
| 1888 | { |
| 1889 | if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT) |
| 1890 | return -ENODEV; |
| 1891 | /* |
| 1892 | * CCI control for ports connected to CPUS is extremely fragile |
| 1893 | * and must be made to go through a specific and controlled |
| 1894 | * interface (ie cci_disable_port_by_cpu(); control by general purpose |
| 1895 | * indexing is therefore disabled for ACE ports. |
| 1896 | */ |
| 1897 | if (ports[port].type == ACE_PORT) |
| 1898 | return -EPERM; |
| 1899 | |
| 1900 | cci_port_control(port, enable); |
| 1901 | return 0; |
| 1902 | } |
| 1903 | EXPORT_SYMBOL_GPL(__cci_control_port_by_index); |
| 1904 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1905 | static const struct of_device_id arm_cci_ctrl_if_matches[] = { |
| 1906 | {.compatible = "arm,cci-400-ctrl-if", }, |
| 1907 | {}, |
| 1908 | }; |
| 1909 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1910 | static int cci_probe_ports(struct device_node *np) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1911 | { |
| 1912 | struct cci_nb_ports const *cci_config; |
| 1913 | int ret, i, nb_ace = 0, nb_ace_lite = 0; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1914 | struct device_node *cp; |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1915 | struct resource res; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1916 | const char *match_str; |
| 1917 | bool is_ace; |
| 1918 | |
Abhilash Kesavan | 896ddd6 | 2015-01-10 08:41:35 +0530 | [diff] [blame] | 1919 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1920 | cci_config = of_match_node(arm_cci_matches, np)->data; |
| 1921 | if (!cci_config) |
| 1922 | return -ENODEV; |
| 1923 | |
| 1924 | nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite; |
| 1925 | |
Lorenzo Pieralisi | 7c76203 | 2014-01-27 10:50:37 +0000 | [diff] [blame] | 1926 | ports = kcalloc(nb_cci_ports, sizeof(*ports), GFP_KERNEL); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1927 | if (!ports) |
| 1928 | return -ENOMEM; |
| 1929 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1930 | for_each_child_of_node(np, cp) { |
| 1931 | if (!of_match_node(arm_cci_ctrl_if_matches, cp)) |
| 1932 | continue; |
| 1933 | |
| 1934 | i = nb_ace + nb_ace_lite; |
| 1935 | |
| 1936 | if (i >= nb_cci_ports) |
| 1937 | break; |
| 1938 | |
| 1939 | if (of_property_read_string(cp, "interface-type", |
| 1940 | &match_str)) { |
| 1941 | WARN(1, "node %s missing interface-type property\n", |
| 1942 | cp->full_name); |
| 1943 | continue; |
| 1944 | } |
| 1945 | is_ace = strcmp(match_str, "ace") == 0; |
| 1946 | if (!is_ace && strcmp(match_str, "ace-lite")) { |
| 1947 | WARN(1, "node %s containing invalid interface-type property, skipping it\n", |
| 1948 | cp->full_name); |
| 1949 | continue; |
| 1950 | } |
| 1951 | |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1952 | ret = of_address_to_resource(cp, 0, &res); |
| 1953 | if (!ret) { |
| 1954 | ports[i].base = ioremap(res.start, resource_size(&res)); |
| 1955 | ports[i].phys = res.start; |
| 1956 | } |
| 1957 | if (ret || !ports[i].base) { |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1958 | WARN(1, "unable to ioremap CCI port %d\n", i); |
| 1959 | continue; |
| 1960 | } |
| 1961 | |
| 1962 | if (is_ace) { |
| 1963 | if (WARN_ON(nb_ace >= cci_config->nb_ace)) |
| 1964 | continue; |
| 1965 | ports[i].type = ACE_PORT; |
| 1966 | ++nb_ace; |
| 1967 | } else { |
| 1968 | if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite)) |
| 1969 | continue; |
| 1970 | ports[i].type = ACE_LITE_PORT; |
| 1971 | ++nb_ace_lite; |
| 1972 | } |
| 1973 | ports[i].dn = cp; |
| 1974 | } |
| 1975 | |
| 1976 | /* initialize a stashed array of ACE ports to speed-up look-up */ |
| 1977 | cci_ace_init_ports(); |
| 1978 | |
| 1979 | /* |
| 1980 | * Multi-cluster systems may need this data when non-coherent, during |
| 1981 | * cluster power-up/power-down. Make sure it reaches main memory. |
| 1982 | */ |
| 1983 | sync_cache_w(&cci_ctrl_base); |
Nicolas Pitre | 62158f8 | 2013-05-21 23:34:41 -0400 | [diff] [blame] | 1984 | sync_cache_w(&cci_ctrl_phys); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1985 | sync_cache_w(&ports); |
| 1986 | sync_cache_w(&cpu_port); |
| 1987 | __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports); |
| 1988 | pr_info("ARM CCI driver probed\n"); |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1989 | |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1990 | return 0; |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1991 | } |
Suzuki K. Poulose | ee8e5d5 | 2015-03-18 12:24:41 +0000 | [diff] [blame] | 1992 | #else /* !CONFIG_ARM_CCI400_PORT_CTRL */ |
| 1993 | static inline int cci_probe_ports(struct device_node *np) |
| 1994 | { |
| 1995 | return 0; |
| 1996 | } |
| 1997 | #endif /* CONFIG_ARM_CCI400_PORT_CTRL */ |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 1998 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 1999 | static int cci_probe(void) |
| 2000 | { |
| 2001 | int ret; |
| 2002 | struct device_node *np; |
| 2003 | struct resource res; |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 2004 | |
Suzuki K. Poulose | f6b9e83 | 2015-03-18 12:24:38 +0000 | [diff] [blame] | 2005 | np = of_find_matching_node(NULL, arm_cci_matches); |
| 2006 | if(!np || !of_device_is_available(np)) |
| 2007 | return -ENODEV; |
| 2008 | |
| 2009 | ret = of_address_to_resource(np, 0, &res); |
| 2010 | if (!ret) { |
| 2011 | cci_ctrl_base = ioremap(res.start, resource_size(&res)); |
| 2012 | cci_ctrl_phys = res.start; |
| 2013 | } |
| 2014 | if (ret || !cci_ctrl_base) { |
| 2015 | WARN(1, "unable to ioremap CCI ctrl\n"); |
| 2016 | return -ENXIO; |
| 2017 | } |
| 2018 | |
| 2019 | return cci_probe_ports(np); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 2020 | } |
| 2021 | |
| 2022 | static int cci_init_status = -EAGAIN; |
| 2023 | static DEFINE_MUTEX(cci_probing); |
| 2024 | |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 2025 | static int cci_init(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 2026 | { |
| 2027 | if (cci_init_status != -EAGAIN) |
| 2028 | return cci_init_status; |
| 2029 | |
| 2030 | mutex_lock(&cci_probing); |
| 2031 | if (cci_init_status == -EAGAIN) |
| 2032 | cci_init_status = cci_probe(); |
| 2033 | mutex_unlock(&cci_probing); |
| 2034 | return cci_init_status; |
| 2035 | } |
| 2036 | |
| 2037 | /* |
| 2038 | * To sort out early init calls ordering a helper function is provided to |
| 2039 | * check if the CCI driver has beed initialized. Function check if the driver |
| 2040 | * has been initialized, if not it calls the init function that probes |
| 2041 | * the driver and updates the return value. |
| 2042 | */ |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 2043 | bool cci_probed(void) |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 2044 | { |
| 2045 | return cci_init() == 0; |
| 2046 | } |
| 2047 | EXPORT_SYMBOL_GPL(cci_probed); |
| 2048 | |
| 2049 | early_initcall(cci_init); |
Punit Agrawal | b91c8f2 | 2013-08-22 14:41:51 +0100 | [diff] [blame] | 2050 | core_initcall(cci_platform_init); |
Lorenzo Pieralisi | ed69bdd | 2012-07-13 15:55:52 +0100 | [diff] [blame] | 2051 | MODULE_LICENSE("GPL"); |
| 2052 | MODULE_DESCRIPTION("ARM CCI support"); |