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gerrit-public.fairphone.software / kernel / msm-4.19 / 608308682addfdc7b8e2aee88f0e028331d88e4d / . / arch / arm / boot / dts / spear1340.dtsi
blob: e71df0f2cb52d579bcfef4d114cba5d6e5acddfb [file] [log] [blame]
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]1/*
2 * DTS file for all SPEAr1340 SoCs
3 *
Viresh Kumar10d89352012-06-20 12:53:02 -0700[diff] [blame]4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear13xx.dtsi"
15
16/ {
17 compatible = "st,spear1340";
18
19 ahb {
Shiraz Hashim7cef07d2012-09-03 11:46:58 +0530[diff] [blame]20
21 spics: spics@e0700000{
22 compatible = "st,spear-spics-gpio";
23 reg = <0xe0700000 0x1000>;
24 st-spics,peripcfg-reg = <0x42c>;
25 st-spics,sw-enable-bit = <21>;
26 st-spics,cs-value-bit = <20>;
27 st-spics,cs-enable-mask = <3>;
28 st-spics,cs-enable-shift = <18>;
29 gpio-controller;
30 #gpio-cells = <2>;
31 status = "disabled";
32 };
33
Pratyush Anand549f3ae2014-04-14 15:27:36 +0530[diff] [blame]34 miphy0: miphy@eb800000 {
35 compatible = "st,spear1340-miphy";
36 reg = <0xeb800000 0x4000>;
37 misc = <&misc>;
38 #phy-cells = <1>;
39 status = "disabled";
40 };
41
42 ahci0: ahci@b1000000 {
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]43 compatible = "snps,spear-ahci";
44 reg = <0xb1000000 0x10000>;
45 interrupts = <0 72 0x4>;
Pratyush Anand549f3ae2014-04-14 15:27:36 +0530[diff] [blame]46 phys = <&miphy0 0>;
47 phy-names = "sata-phy";
48 status = "disabled";
49 };
50
51 pcie0: pcie@b1000000 {
52 compatible = "st,spear1340-pcie", "snps,dw-pcie";
53 reg = <0xb1000000 0x4000>;
54 interrupts = <0 68 0x4>;
55 interrupt-map-mask = <0 0 0 0>;
56 interrupt-map = <0x0 0 &gic 0 68 0x4>;
57 num-lanes = <1>;
58 phys = <&miphy0 1>;
59 phy-names = "pcie-phy";
60 #address-cells = <3>;
61 #size-cells = <2>;
62 device_type = "pci";
63 ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */
64 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */
65 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]66 status = "disabled";
67 };
68
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]69 i2s-play@b2400000 {
70 compatible = "snps,designware-i2s";
71 reg = <0xb2400000 0x10000>;
72 interrupt-names = "play_irq";
73 interrupts = <0 98 0x4
74 0 99 0x4>;
75 play;
76 channel = <8>;
77 status = "disabled";
78 };
79
80 i2s-rec@b2000000 {
81 compatible = "snps,designware-i2s";
82 reg = <0xb2000000 0x10000>;
83 interrupt-names = "record_irq";
84 interrupts = <0 100 0x4
85 0 101 0x4>;
86 record;
87 channel = <8>;
88 status = "disabled";
89 };
90
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]91 pinmux: pinmux@e0700000 {
92 compatible = "st,spear1340-pinmux";
93 reg = <0xe0700000 0x1000>;
Haojian Zhuang86853c82013-02-17 19:42:47 +0800[diff] [blame]94 #gpio-range-cells = <3>;
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]95 };
96
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]97 pwm: pwm@e0180000 {
98 compatible ="st,spear13xx-pwm";
99 reg = <0xe0180000 0x1000>;
100 #pwm-cells = <2>;
101 status = "disabled";
102 };
103
104 spdif-in@d0100000 {
105 compatible = "st,spdif-in";
106 reg = < 0xd0100000 0x20000
107 0xd0110000 0x10000 >;
108 interrupts = <0 84 0x4>;
109 status = "disabled";
110 };
111
112 spdif-out@d0000000 {
113 compatible = "st,spdif-out";
114 reg = <0xd0000000 0x20000>;
115 interrupts = <0 85 0x4>;
116 status = "disabled";
117 };
118
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]119 spi1: spi@5d400000 {
120 compatible = "arm,pl022", "arm,primecell";
121 reg = <0x5d400000 0x1000>;
Shiraz Hashim8113ba92012-11-10 17:31:01 +0530[diff] [blame]122 #address-cells = <1>;
123 #size-cells = <0>;
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]124 interrupts = <0 99 0x4>;
125 status = "disabled";
126 };
127
128 apb {
129 i2c1: i2c@b4000000 {
130 #address-cells = <1>;
131 #size-cells = <0>;
132 compatible = "snps,designware-i2c";
133 reg = <0xb4000000 0x1000>;
134 interrupts = <0 104 0x4>;
Vipul Kumar Samarf631b9842012-07-05 11:51:47 +0800[diff] [blame]135 write-16bit;
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]136 status = "disabled";
137 };
138
139 serial@b4100000 {
140 compatible = "arm,pl011", "arm,primecell";
141 reg = <0xb4100000 0x1000>;
142 interrupts = <0 105 0x4>;
143 status = "disabled";
Arnd Bergmann6e8887f62013-01-28 21:48:47 +0000[diff] [blame]144 dmas = <&dwdma0 0x600 0 0 1>, /* 0xC << 11 */
145 <&dwdma0 0x680 0 1 0>; /* 0xD << 7 */
146 dma-names = "tx", "rx";
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]147 };
148
149 thermal@e07008c4 {
150 st,thermal-flags = <0x2a00>;
151 };
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]152
153 gpiopinctrl: gpio@e2800000 {
154 compatible = "st,spear-plgpio";
155 reg = <0xe2800000 0x1000>;
156 interrupts = <0 107 0x4>;
157 #interrupt-cells = <1>;
158 interrupt-controller;
159 gpio-controller;
160 #gpio-cells = <2>;
Haojian Zhuang86853c82013-02-17 19:42:47 +0800[diff] [blame]161 gpio-ranges = <&pinmux 0 0 252>;
Viresh Kumar4ddb1c22012-10-27 15:21:39 +0530[diff] [blame]162 status = "disabled";
163
164 st-plgpio,ngpio = <250>;
165 st-plgpio,wdata-reg = <0x40>;
166 st-plgpio,dir-reg = <0x00>;
167 st-plgpio,ie-reg = <0x80>;
168 st-plgpio,rdata-reg = <0x20>;
169 st-plgpio,mis-reg = <0xa0>;
170 st-plgpio,eit-reg = <0x60>;
171 };
Viresh Kumar07658d92012-04-16 23:57:51 +0530[diff] [blame]172 };
173 };
174};