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Marc Zyngier5c1ce6f2013-04-08 17:17:03 +01001/*
2 * Copyright (C) 2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#ifndef __ASM_ESR_H
19#define __ASM_ESR_H
20
Catalin Marinas91413002014-04-06 23:04:12 +010021#define ESR_EL1_WRITE (1 << 6)
22#define ESR_EL1_CM (1 << 8)
23#define ESR_EL1_IL (1 << 25)
Marc Zyngier5c1ce6f2013-04-08 17:17:03 +010024
Catalin Marinas91413002014-04-06 23:04:12 +010025#define ESR_EL1_EC_SHIFT (26)
Marc Zyngier5c1ce6f2013-04-08 17:17:03 +010026#define ESR_EL1_EC_UNKNOWN (0x00)
27#define ESR_EL1_EC_WFI (0x01)
28#define ESR_EL1_EC_CP15_32 (0x03)
29#define ESR_EL1_EC_CP15_64 (0x04)
30#define ESR_EL1_EC_CP14_MR (0x05)
31#define ESR_EL1_EC_CP14_LS (0x06)
32#define ESR_EL1_EC_FP_ASIMD (0x07)
33#define ESR_EL1_EC_CP10_ID (0x08)
34#define ESR_EL1_EC_CP14_64 (0x0C)
35#define ESR_EL1_EC_ILL_ISS (0x0E)
36#define ESR_EL1_EC_SVC32 (0x11)
37#define ESR_EL1_EC_SVC64 (0x15)
38#define ESR_EL1_EC_SYS64 (0x18)
39#define ESR_EL1_EC_IABT_EL0 (0x20)
40#define ESR_EL1_EC_IABT_EL1 (0x21)
41#define ESR_EL1_EC_PC_ALIGN (0x22)
42#define ESR_EL1_EC_DABT_EL0 (0x24)
43#define ESR_EL1_EC_DABT_EL1 (0x25)
44#define ESR_EL1_EC_SP_ALIGN (0x26)
45#define ESR_EL1_EC_FP_EXC32 (0x28)
46#define ESR_EL1_EC_FP_EXC64 (0x2C)
Mark Rutlandbfb67a52014-02-05 10:24:12 +000047#define ESR_EL1_EC_SERROR (0x2F)
Marc Zyngier5c1ce6f2013-04-08 17:17:03 +010048#define ESR_EL1_EC_BREAKPT_EL0 (0x30)
49#define ESR_EL1_EC_BREAKPT_EL1 (0x31)
50#define ESR_EL1_EC_SOFTSTP_EL0 (0x32)
51#define ESR_EL1_EC_SOFTSTP_EL1 (0x33)
52#define ESR_EL1_EC_WATCHPT_EL0 (0x34)
53#define ESR_EL1_EC_WATCHPT_EL1 (0x35)
54#define ESR_EL1_EC_BKPT32 (0x38)
55#define ESR_EL1_EC_BRK64 (0x3C)
56
Mark Rutlandcf99a482014-11-24 12:03:32 +000057#define ESR_ELx_EC_UNKNOWN (0x00)
58#define ESR_ELx_EC_WFx (0x01)
59/* Unallocated EC: 0x02 */
60#define ESR_ELx_EC_CP15_32 (0x03)
61#define ESR_ELx_EC_CP15_64 (0x04)
62#define ESR_ELx_EC_CP14_MR (0x05)
63#define ESR_ELx_EC_CP14_LS (0x06)
64#define ESR_ELx_EC_FP_ASIMD (0x07)
65#define ESR_ELx_EC_CP10_ID (0x08)
66/* Unallocated EC: 0x09 - 0x0B */
67#define ESR_ELx_EC_CP14_64 (0x0C)
68/* Unallocated EC: 0x0d */
69#define ESR_ELx_EC_ILL (0x0E)
70/* Unallocated EC: 0x0F - 0x10 */
71#define ESR_ELx_EC_SVC32 (0x11)
72#define ESR_ELx_EC_HVC32 (0x12)
73#define ESR_ELx_EC_SMC32 (0x13)
74/* Unallocated EC: 0x14 */
75#define ESR_ELx_EC_SVC64 (0x15)
76#define ESR_ELx_EC_HVC64 (0x16)
77#define ESR_ELx_EC_SMC64 (0x17)
78#define ESR_ELx_EC_SYS64 (0x18)
79/* Unallocated EC: 0x19 - 0x1E */
80#define ESR_ELx_EC_IMP_DEF (0x1f)
81#define ESR_ELx_EC_IABT_LOW (0x20)
82#define ESR_ELx_EC_IABT_CUR (0x21)
83#define ESR_ELx_EC_PC_ALIGN (0x22)
84/* Unallocated EC: 0x23 */
85#define ESR_ELx_EC_DABT_LOW (0x24)
86#define ESR_ELx_EC_DABT_CUR (0x25)
87#define ESR_ELx_EC_SP_ALIGN (0x26)
88/* Unallocated EC: 0x27 */
89#define ESR_ELx_EC_FP_EXC32 (0x28)
90/* Unallocated EC: 0x29 - 0x2B */
91#define ESR_ELx_EC_FP_EXC64 (0x2C)
92/* Unallocated EC: 0x2D - 0x2E */
93#define ESR_ELx_EC_SERROR (0x2F)
94#define ESR_ELx_EC_BREAKPT_LOW (0x30)
95#define ESR_ELx_EC_BREAKPT_CUR (0x31)
96#define ESR_ELx_EC_SOFTSTP_LOW (0x32)
97#define ESR_ELx_EC_SOFTSTP_CUR (0x33)
98#define ESR_ELx_EC_WATCHPT_LOW (0x34)
99#define ESR_ELx_EC_WATCHPT_CUR (0x35)
100/* Unallocated EC: 0x36 - 0x37 */
101#define ESR_ELx_EC_BKPT32 (0x38)
102/* Unallocated EC: 0x39 */
103#define ESR_ELx_EC_VECTOR32 (0x3A)
104/* Unallocted EC: 0x3B */
105#define ESR_ELx_EC_BRK64 (0x3C)
106/* Unallocated EC: 0x3D - 0x3F */
107#define ESR_ELx_EC_MAX (0x3F)
108
109#define ESR_ELx_EC_SHIFT (26)
110#define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
111
112#define ESR_ELx_IL (UL(1) << 25)
113#define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
114#define ESR_ELx_ISV (UL(1) << 24)
115#define ESR_ELx_SAS_SHIFT (22)
116#define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
117#define ESR_ELx_SSE (UL(1) << 21)
118#define ESR_ELx_SRT_SHIFT (16)
119#define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
120#define ESR_ELx_SF (UL(1) << 15)
121#define ESR_ELx_AR (UL(1) << 14)
122#define ESR_ELx_EA (UL(1) << 9)
123#define ESR_ELx_CM (UL(1) << 8)
124#define ESR_ELx_S1PTW (UL(1) << 7)
125#define ESR_ELx_WNR (UL(1) << 6)
126#define ESR_ELx_FSC (0x3F)
127#define ESR_ELx_FSC_TYPE (0x3C)
128#define ESR_ELx_FSC_EXTABT (0x10)
129#define ESR_ELx_FSC_FAULT (0x04)
130#define ESR_ELx_FSC_PERM (0x0C)
131#define ESR_ELx_CV (UL(1) << 24)
132#define ESR_ELx_COND_SHIFT (20)
133#define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
134#define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
135
Mark Rutland60a1f022014-11-18 12:16:30 +0000136#ifndef __ASSEMBLY__
137#include <asm/types.h>
138
139const char *esr_get_class_string(u32 esr);
140#endif /* __ASSEMBLY */
141
Marc Zyngier5c1ce6f2013-04-08 17:17:03 +0100142#endif /* __ASM_ESR_H */