blob: 441caf1a497d752fad226ed737a992d4addddede [file] [log] [blame]
Roland Dreier225c7b12007-05-08 18:00:38 -07001/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
39
Arun Sharma600634972011-07-26 16:09:06 -070040#include <linux/atomic.h>
Roland Dreier225c7b12007-05-08 18:00:38 -070041
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +000042#define MAX_MSIX_P_PORT 17
43#define MAX_MSIX 64
44#define MSIX_LEGACY_SZ 4
45#define MIN_MSIX_P_PORT 5
46
Roland Dreier225c7b12007-05-08 18:00:38 -070047enum {
48 MLX4_FLAG_MSI_X = 1 << 0,
Roland Dreier5ae2a7a2007-06-18 08:15:02 -070049 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
Jack Morgenstein623ed842011-12-13 04:10:33 +000050 MLX4_FLAG_MASTER = 1 << 2,
51 MLX4_FLAG_SLAVE = 1 << 3,
52 MLX4_FLAG_SRIOV = 1 << 4,
Roland Dreier225c7b12007-05-08 18:00:38 -070053};
54
55enum {
56 MLX4_MAX_PORTS = 2
57};
58
Jack Morgenstein396f2fe2012-06-19 11:21:42 +030059/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
60 * These qkeys must not be allowed for general use. This is a 64k range,
61 * and to test for violation, we use the mask (protect against future chg).
62 */
63#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
64#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
65
Roland Dreier225c7b12007-05-08 18:00:38 -070066enum {
Jack Morgensteincd9281d2007-09-18 09:14:18 +020067 MLX4_BOARD_ID_LEN = 64
68};
69
70enum {
Jack Morgenstein623ed842011-12-13 04:10:33 +000071 MLX4_MAX_NUM_PF = 16,
72 MLX4_MAX_NUM_VF = 64,
73 MLX4_MFUNC_MAX = 80,
Marcel Apfelbaum3fc929e2012-05-30 09:14:51 +000074 MLX4_MAX_EQ_NUM = 1024,
Jack Morgenstein623ed842011-12-13 04:10:33 +000075 MLX4_MFUNC_EQ_NUM = 4,
76 MLX4_MFUNC_MAX_EQES = 8,
77 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
78};
79
80enum {
Or Gerlitz52eafc62011-06-15 14:41:42 +000081 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
82 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
83 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
Sean Hefty012a8ff2011-06-02 09:01:33 -070084 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
Or Gerlitz52eafc62011-06-15 14:41:42 +000085 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
86 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
87 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
88 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
89 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
90 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
91 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
92 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
93 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
94 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
95 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
96 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
Or Gerlitzccf86322011-07-07 19:19:29 +000097 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
98 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
Yevgeny Petrilinf3a9d1f2011-10-18 01:50:42 +000099 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
Oren Duer559a9f12011-11-26 19:55:15 +0000100 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
101 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
Or Gerlitzccf86322011-07-07 19:19:29 +0000102 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
103 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
Or Gerlitzf2a3f6a2011-06-15 14:47:14 +0000104 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
Yevgeny Petrilin58a60162011-12-19 04:00:26 +0000105 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300106 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
107 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
Roland Dreier225c7b12007-05-08 18:00:38 -0700108};
109
Shlomo Pongratzb3416f42012-04-29 17:04:25 +0300110enum {
111 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
112 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
113 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2
114};
115
Marcel Apfelbaum97285b72011-10-24 11:02:34 +0200116#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
117
118enum {
Roland Dreier95d04f02008-07-23 08:12:26 -0700119 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
120 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
121 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
122 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
123 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
124};
125
Roland Dreier225c7b12007-05-08 18:00:38 -0700126enum mlx4_event {
127 MLX4_EVENT_TYPE_COMP = 0x00,
128 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
129 MLX4_EVENT_TYPE_COMM_EST = 0x02,
130 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
131 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
132 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
133 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
134 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
135 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
136 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
137 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
138 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
139 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
140 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
141 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
142 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
143 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
Jack Morgenstein623ed842011-12-13 04:10:33 +0000144 MLX4_EVENT_TYPE_CMD = 0x0a,
145 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
146 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
Jack Morgenstein5984be92012-03-06 15:50:49 +0200147 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
Jack Morgenstein623ed842011-12-13 04:10:33 +0000148 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300149 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
Jack Morgenstein623ed842011-12-13 04:10:33 +0000150 MLX4_EVENT_TYPE_NONE = 0xff,
Roland Dreier225c7b12007-05-08 18:00:38 -0700151};
152
153enum {
154 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
155 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
156};
157
158enum {
Jack Morgenstein5984be92012-03-06 15:50:49 +0200159 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
160};
161
162enum {
Roland Dreier225c7b12007-05-08 18:00:38 -0700163 MLX4_PERM_LOCAL_READ = 1 << 10,
164 MLX4_PERM_LOCAL_WRITE = 1 << 11,
165 MLX4_PERM_REMOTE_READ = 1 << 12,
166 MLX4_PERM_REMOTE_WRITE = 1 << 13,
167 MLX4_PERM_ATOMIC = 1 << 14
168};
169
170enum {
171 MLX4_OPCODE_NOP = 0x00,
172 MLX4_OPCODE_SEND_INVAL = 0x01,
173 MLX4_OPCODE_RDMA_WRITE = 0x08,
174 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
175 MLX4_OPCODE_SEND = 0x0a,
176 MLX4_OPCODE_SEND_IMM = 0x0b,
177 MLX4_OPCODE_LSO = 0x0e,
178 MLX4_OPCODE_RDMA_READ = 0x10,
179 MLX4_OPCODE_ATOMIC_CS = 0x11,
180 MLX4_OPCODE_ATOMIC_FA = 0x12,
Vladimir Sokolovsky6fa8f712010-04-14 17:23:39 +0300181 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
182 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
Roland Dreier225c7b12007-05-08 18:00:38 -0700183 MLX4_OPCODE_BIND_MW = 0x18,
184 MLX4_OPCODE_FMR = 0x19,
185 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
186 MLX4_OPCODE_CONFIG_CMD = 0x1f,
187
188 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
189 MLX4_RECV_OPCODE_SEND = 0x01,
190 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
191 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
192
193 MLX4_CQE_OPCODE_ERROR = 0x1e,
194 MLX4_CQE_OPCODE_RESIZE = 0x16,
195};
196
197enum {
198 MLX4_STAT_RATE_OFFSET = 5
199};
200
Aleksey Seninda995a82010-12-02 11:44:49 +0000201enum mlx4_protocol {
Yevgeny Petrilin03455842011-03-22 22:38:17 +0000202 MLX4_PROT_IB_IPV6 = 0,
203 MLX4_PROT_ETH,
204 MLX4_PROT_IB_IPV4,
205 MLX4_PROT_FCOE
Aleksey Seninda995a82010-12-02 11:44:49 +0000206};
207
Vladimir Sokolovsky29bdc882008-09-15 14:25:23 -0700208enum {
209 MLX4_MTT_FLAG_PRESENT = 1
210};
211
Yevgeny Petrilin93fc9e12008-10-22 10:25:29 -0700212enum mlx4_qp_region {
213 MLX4_QP_REGION_FW = 0,
214 MLX4_QP_REGION_ETH_ADDR,
215 MLX4_QP_REGION_FC_ADDR,
216 MLX4_QP_REGION_FC_EXCH,
217 MLX4_NUM_QP_REGION
218};
219
Yevgeny Petrilin7ff93f82008-10-22 15:38:42 -0700220enum mlx4_port_type {
Jack Morgenstein623ed842011-12-13 04:10:33 +0000221 MLX4_PORT_TYPE_NONE = 0,
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700222 MLX4_PORT_TYPE_IB = 1,
223 MLX4_PORT_TYPE_ETH = 2,
224 MLX4_PORT_TYPE_AUTO = 3
Yevgeny Petrilin7ff93f82008-10-22 15:38:42 -0700225};
226
Yevgeny Petrilin2a2336f2008-10-22 11:44:46 -0700227enum mlx4_special_vlan_idx {
228 MLX4_NO_VLAN_IDX = 0,
229 MLX4_VLAN_MISS_IDX,
230 MLX4_VLAN_REGULAR
231};
232
Yevgeny Petrilin03455842011-03-22 22:38:17 +0000233enum mlx4_steer_type {
234 MLX4_MC_STEER = 0,
235 MLX4_UC_STEER,
236 MLX4_NUM_STEERS
237};
238
Yevgeny Petrilin93fc9e12008-10-22 10:25:29 -0700239enum {
240 MLX4_NUM_FEXCH = 64 * 1024,
241};
242
Eli Cohen5a0fd092010-10-07 16:24:16 +0200243enum {
244 MLX4_MAX_FAST_REG_PAGES = 511,
245};
246
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300247enum {
248 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
249 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
250 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
251};
252
253/* Port mgmt change event handling */
254enum {
255 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
256 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
257 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
258 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
259 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
260};
261
262#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
263 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
264
Jack Morgensteinea54b102008-01-28 10:40:59 +0200265static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
266{
267 return (major << 32) | (minor << 16) | subminor;
268}
269
Marcel Apfelbaum3fc929e2012-05-30 09:14:51 +0000270struct mlx4_phys_caps {
Jack Morgenstein66349612012-06-19 11:21:44 +0300271 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
272 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
Marcel Apfelbaum3fc929e2012-05-30 09:14:51 +0000273 u32 num_phys_eqs;
274};
275
Roland Dreier225c7b12007-05-08 18:00:38 -0700276struct mlx4_caps {
277 u64 fw_ver;
Jack Morgenstein623ed842011-12-13 04:10:33 +0000278 u32 function;
Roland Dreier225c7b12007-05-08 18:00:38 -0700279 int num_ports;
Roland Dreier5ae2a7a2007-06-18 08:15:02 -0700280 int vl_cap[MLX4_MAX_PORTS + 1];
Yevgeny Petrilinb79acb42008-10-22 10:56:48 -0700281 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
Jack Morgenstein9a5aa622008-11-28 21:29:46 -0800282 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
Yevgeny Petrilinb79acb42008-10-22 10:56:48 -0700283 u64 def_mac[MLX4_MAX_PORTS + 1];
284 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
Roland Dreier5ae2a7a2007-06-18 08:15:02 -0700285 int gid_table_len[MLX4_MAX_PORTS + 1];
286 int pkey_table_len[MLX4_MAX_PORTS + 1];
Yevgeny Petrilin76995172010-08-24 03:46:23 +0000287 int trans_type[MLX4_MAX_PORTS + 1];
288 int vendor_oui[MLX4_MAX_PORTS + 1];
289 int wavelength[MLX4_MAX_PORTS + 1];
290 u64 trans_code[MLX4_MAX_PORTS + 1];
Roland Dreier225c7b12007-05-08 18:00:38 -0700291 int local_ca_ack_delay;
292 int num_uars;
Jack Morgensteinf5311ac2011-12-13 04:12:13 +0000293 u32 uar_page_size;
Roland Dreier225c7b12007-05-08 18:00:38 -0700294 int bf_reg_size;
295 int bf_regs_per_page;
296 int max_sq_sg;
297 int max_rq_sg;
298 int num_qps;
299 int max_wqes;
300 int max_sq_desc_sz;
301 int max_rq_desc_sz;
302 int max_qp_init_rdma;
303 int max_qp_dest_rdma;
Roland Dreier225c7b12007-05-08 18:00:38 -0700304 int sqp_start;
Jack Morgenstein396f2fe2012-06-19 11:21:42 +0300305 u32 base_sqpn;
306 u32 base_tunnel_sqpn;
Roland Dreier225c7b12007-05-08 18:00:38 -0700307 int num_srqs;
308 int max_srq_wqes;
309 int max_srq_sge;
310 int reserved_srqs;
311 int num_cqs;
312 int max_cqes;
313 int reserved_cqs;
314 int num_eqs;
315 int reserved_eqs;
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800316 int num_comp_vectors;
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +0000317 int comp_pool;
Roland Dreier225c7b12007-05-08 18:00:38 -0700318 int num_mpts;
Eli Cohena5bbe892012-02-09 18:10:06 +0200319 int max_fmr_maps;
Marcel Apfelbaum2b8fb282011-12-13 04:16:56 +0000320 int num_mtts;
Roland Dreier225c7b12007-05-08 18:00:38 -0700321 int fmr_reserved_mtts;
322 int reserved_mtts;
323 int reserved_mrws;
324 int reserved_uars;
325 int num_mgms;
326 int num_amgms;
327 int reserved_mcgs;
328 int num_qp_per_mgm;
329 int num_pds;
330 int reserved_pds;
Sean Hefty012a8ff2011-06-02 09:01:33 -0700331 int max_xrcds;
332 int reserved_xrcds;
Roland Dreier225c7b12007-05-08 18:00:38 -0700333 int mtt_entry_sz;
Dotan Barak149983af2007-06-26 15:55:28 +0300334 u32 max_msg_sz;
Roland Dreier225c7b12007-05-08 18:00:38 -0700335 u32 page_size_cap;
Or Gerlitz52eafc62011-06-15 14:41:42 +0000336 u64 flags;
Shlomo Pongratzb3416f42012-04-29 17:04:25 +0300337 u64 flags2;
Roland Dreier95d04f02008-07-23 08:12:26 -0700338 u32 bmme_flags;
339 u32 reserved_lkey;
Roland Dreier225c7b12007-05-08 18:00:38 -0700340 u16 stat_rate_support;
Roland Dreier5ae2a7a2007-06-18 08:15:02 -0700341 u8 port_width_cap[MLX4_MAX_PORTS + 1];
Eli Cohenb832be12008-04-16 21:09:27 -0700342 int max_gso_sz;
Shlomo Pongratzb3416f42012-04-29 17:04:25 +0300343 int max_rss_tbl_sz;
Yevgeny Petrilin93fc9e12008-10-22 10:25:29 -0700344 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
345 int reserved_qps;
346 int reserved_qps_base[MLX4_NUM_QP_REGION];
347 int log_num_macs;
348 int log_num_vlans;
349 int log_num_prios;
Yevgeny Petrilin7ff93f82008-10-22 15:38:42 -0700350 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
351 u8 supported_type[MLX4_MAX_PORTS + 1];
Yevgeny Petrilin8d0fc7b2011-12-19 04:00:34 +0000352 u8 suggested_type[MLX4_MAX_PORTS + 1];
353 u8 default_sense[MLX4_MAX_PORTS + 1];
Jack Morgenstein65dab252011-12-13 04:10:41 +0000354 u32 port_mask[MLX4_MAX_PORTS + 1];
Yevgeny Petrilin27bf91d2009-03-18 19:45:11 -0700355 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
Or Gerlitzf2a3f6a2011-06-15 14:47:14 +0000356 u32 max_counters;
Or Gerlitz096335b2012-01-11 19:02:17 +0200357 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
Roland Dreier225c7b12007-05-08 18:00:38 -0700358};
359
360struct mlx4_buf_list {
361 void *buf;
362 dma_addr_t map;
363};
364
365struct mlx4_buf {
Roland Dreierb57aacf2008-02-06 21:17:59 -0800366 struct mlx4_buf_list direct;
367 struct mlx4_buf_list *page_list;
Roland Dreier225c7b12007-05-08 18:00:38 -0700368 int nbufs;
369 int npages;
370 int page_shift;
371};
372
373struct mlx4_mtt {
Marcel Apfelbaum2b8fb282011-12-13 04:16:56 +0000374 u32 offset;
Roland Dreier225c7b12007-05-08 18:00:38 -0700375 int order;
376 int page_shift;
377};
378
Yevgeny Petrilin62968832008-04-23 11:55:45 -0700379enum {
380 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
381};
382
383struct mlx4_db_pgdir {
384 struct list_head list;
385 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
386 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
387 unsigned long *bits[2];
388 __be32 *db_page;
389 dma_addr_t db_dma;
390};
391
392struct mlx4_ib_user_db_page;
393
394struct mlx4_db {
395 __be32 *db;
396 union {
397 struct mlx4_db_pgdir *pgdir;
398 struct mlx4_ib_user_db_page *user_page;
399 } u;
400 dma_addr_t dma;
401 int index;
402 int order;
403};
404
Yevgeny Petrilin38ae6a52008-04-25 14:27:08 -0700405struct mlx4_hwq_resources {
406 struct mlx4_db db;
407 struct mlx4_mtt mtt;
408 struct mlx4_buf buf;
409};
410
Roland Dreier225c7b12007-05-08 18:00:38 -0700411struct mlx4_mr {
412 struct mlx4_mtt mtt;
413 u64 iova;
414 u64 size;
415 u32 key;
416 u32 pd;
417 u32 access;
418 int enabled;
419};
420
Jack Morgenstein8ad11fb2007-08-01 12:29:05 +0300421struct mlx4_fmr {
422 struct mlx4_mr mr;
423 struct mlx4_mpt_entry *mpt;
424 __be64 *mtts;
425 dma_addr_t dma_handle;
426 int max_pages;
427 int max_maps;
428 int maps;
429 u8 page_shift;
430};
431
Roland Dreier225c7b12007-05-08 18:00:38 -0700432struct mlx4_uar {
433 unsigned long pfn;
434 int index;
Eli Cohenc1b43dc2011-03-22 22:38:41 +0000435 struct list_head bf_list;
436 unsigned free_bf_bmap;
437 void __iomem *map;
438 void __iomem *bf_map;
439};
440
441struct mlx4_bf {
442 unsigned long offset;
443 int buf_size;
444 struct mlx4_uar *uar;
445 void __iomem *reg;
Roland Dreier225c7b12007-05-08 18:00:38 -0700446};
447
448struct mlx4_cq {
449 void (*comp) (struct mlx4_cq *);
450 void (*event) (struct mlx4_cq *, enum mlx4_event);
451
452 struct mlx4_uar *uar;
453
454 u32 cons_index;
455
456 __be32 *set_ci_db;
457 __be32 *arm_db;
458 int arm_sn;
459
460 int cqn;
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800461 unsigned vector;
Roland Dreier225c7b12007-05-08 18:00:38 -0700462
463 atomic_t refcount;
464 struct completion free;
465};
466
467struct mlx4_qp {
468 void (*event) (struct mlx4_qp *, enum mlx4_event);
469
470 int qpn;
471
472 atomic_t refcount;
473 struct completion free;
474};
475
476struct mlx4_srq {
477 void (*event) (struct mlx4_srq *, enum mlx4_event);
478
479 int srqn;
480 int max;
481 int max_gs;
482 int wqe_shift;
483
484 atomic_t refcount;
485 struct completion free;
486};
487
488struct mlx4_av {
489 __be32 port_pd;
490 u8 reserved1;
491 u8 g_slid;
492 __be16 dlid;
493 u8 reserved2;
494 u8 gid_index;
495 u8 stat_rate;
496 u8 hop_limit;
497 __be32 sl_tclass_flowlabel;
498 u8 dgid[16];
499};
500
Eli Cohenfa417f72010-10-24 21:08:52 -0700501struct mlx4_eth_av {
502 __be32 port_pd;
503 u8 reserved1;
504 u8 smac_idx;
505 u16 reserved2;
506 u8 reserved3;
507 u8 gid_index;
508 u8 stat_rate;
509 u8 hop_limit;
510 __be32 sl_tclass_flowlabel;
511 u8 dgid[16];
512 u32 reserved4[2];
513 __be16 vlan;
514 u8 mac[6];
515};
516
517union mlx4_ext_av {
518 struct mlx4_av ib;
519 struct mlx4_eth_av eth;
520};
521
Or Gerlitzf2a3f6a2011-06-15 14:47:14 +0000522struct mlx4_counter {
523 u8 reserved1[3];
524 u8 counter_mode;
525 __be32 num_ifc;
526 u32 reserved2[2];
527 __be64 rx_frames;
528 __be64 rx_bytes;
529 __be64 tx_frames;
530 __be64 tx_bytes;
531};
532
Roland Dreier225c7b12007-05-08 18:00:38 -0700533struct mlx4_dev {
534 struct pci_dev *pdev;
535 unsigned long flags;
Jack Morgenstein623ed842011-12-13 04:10:33 +0000536 unsigned long num_slaves;
Roland Dreier225c7b12007-05-08 18:00:38 -0700537 struct mlx4_caps caps;
Marcel Apfelbaum3fc929e2012-05-30 09:14:51 +0000538 struct mlx4_phys_caps phys_caps;
Roland Dreier225c7b12007-05-08 18:00:38 -0700539 struct radix_tree_root qp_table_tree;
Yevgeny Petrilin725c8992011-03-22 22:38:07 +0000540 u8 rev_id;
Jack Morgensteincd9281d2007-09-18 09:14:18 +0200541 char board_id[MLX4_BOARD_ID_LEN];
Jack Morgensteinab9c17a2011-12-13 04:18:30 +0000542 int num_vfs;
Roland Dreier225c7b12007-05-08 18:00:38 -0700543};
544
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300545struct mlx4_eqe {
546 u8 reserved1;
547 u8 type;
548 u8 reserved2;
549 u8 subtype;
550 union {
551 u32 raw[6];
552 struct {
553 __be32 cqn;
554 } __packed comp;
555 struct {
556 u16 reserved1;
557 __be16 token;
558 u32 reserved2;
559 u8 reserved3[3];
560 u8 status;
561 __be64 out_param;
562 } __packed cmd;
563 struct {
564 __be32 qpn;
565 } __packed qp;
566 struct {
567 __be32 srqn;
568 } __packed srq;
569 struct {
570 __be32 cqn;
571 u32 reserved1;
572 u8 reserved2[3];
573 u8 syndrome;
574 } __packed cq_err;
575 struct {
576 u32 reserved1[2];
577 __be32 port;
578 } __packed port_change;
579 struct {
580 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
581 u32 reserved;
582 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
583 } __packed comm_channel_arm;
584 struct {
585 u8 port;
586 u8 reserved[3];
587 __be64 mac;
588 } __packed mac_update;
589 struct {
590 __be32 slave_id;
591 } __packed flr_event;
592 struct {
593 __be16 current_temperature;
594 __be16 warning_threshold;
595 } __packed warming;
596 struct {
597 u8 reserved[3];
598 u8 port;
599 union {
600 struct {
601 __be16 mstr_sm_lid;
602 __be16 port_lid;
603 __be32 changed_attr;
604 u8 reserved[3];
605 u8 mstr_sm_sl;
606 __be64 gid_prefix;
607 } __packed port_info;
608 struct {
609 __be32 block_ptr;
610 __be32 tbl_entries_mask;
611 } __packed tbl_change_info;
612 } params;
613 } __packed port_mgmt_change;
614 } event;
615 u8 slave_id;
616 u8 reserved3[2];
617 u8 owner;
618} __packed;
619
Roland Dreier225c7b12007-05-08 18:00:38 -0700620struct mlx4_init_port_param {
621 int set_guid0;
622 int set_node_guid;
623 int set_si_guid;
624 u16 mtu;
625 int port_width_cap;
626 u16 vl_cap;
627 u16 max_gid;
628 u16 max_pkey;
629 u64 guid0;
630 u64 node_guid;
631 u64 si_guid;
632};
633
Yevgeny Petrilin7ff93f82008-10-22 15:38:42 -0700634#define mlx4_foreach_port(port, dev, type) \
635 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
Jack Morgenstein65dab252011-12-13 04:10:41 +0000636 if ((type) == (dev)->caps.port_mask[(port)])
Yevgeny Petrilin7ff93f82008-10-22 15:38:42 -0700637
Jack Morgenstein65dab252011-12-13 04:10:41 +0000638#define mlx4_foreach_ib_transport_port(port, dev) \
639 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
640 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
641 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
Eli Cohenfa417f72010-10-24 21:08:52 -0700642
Jack Morgenstein752a50c2012-06-19 11:21:33 +0300643#define MLX4_INVALID_SLAVE_ID 0xFF
644
Jack Morgenstein00f5ce92012-06-19 11:21:40 +0300645void handle_port_mgmt_change_event(struct work_struct *work);
646
Jack Morgenstein2aca1172012-06-19 11:21:41 +0300647static inline int mlx4_master_func_num(struct mlx4_dev *dev)
648{
649 return dev->caps.function;
650}
651
Jack Morgenstein623ed842011-12-13 04:10:33 +0000652static inline int mlx4_is_master(struct mlx4_dev *dev)
653{
654 return dev->flags & MLX4_FLAG_MASTER;
655}
656
657static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
658{
659 return (qpn < dev->caps.sqp_start + 8);
660}
661
662static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
663{
664 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
665}
666
667static inline int mlx4_is_slave(struct mlx4_dev *dev)
668{
669 return dev->flags & MLX4_FLAG_SLAVE;
670}
Eli Cohenfa417f72010-10-24 21:08:52 -0700671
Roland Dreier225c7b12007-05-08 18:00:38 -0700672int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
673 struct mlx4_buf *buf);
674void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
Roland Dreier1c69fc22008-02-06 21:07:54 -0800675static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
676{
Jack Morgenstein313abe52008-01-28 10:40:51 +0200677 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
Roland Dreierb57aacf2008-02-06 21:17:59 -0800678 return buf->direct.buf + offset;
Roland Dreier1c69fc22008-02-06 21:07:54 -0800679 else
Roland Dreierb57aacf2008-02-06 21:17:59 -0800680 return buf->page_list[offset >> PAGE_SHIFT].buf +
Roland Dreier1c69fc22008-02-06 21:07:54 -0800681 (offset & (PAGE_SIZE - 1));
682}
Roland Dreier225c7b12007-05-08 18:00:38 -0700683
684int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
685void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
Sean Hefty012a8ff2011-06-02 09:01:33 -0700686int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
687void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
Roland Dreier225c7b12007-05-08 18:00:38 -0700688
689int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
690void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
Eli Cohenc1b43dc2011-03-22 22:38:41 +0000691int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
692void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
Roland Dreier225c7b12007-05-08 18:00:38 -0700693
694int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
695 struct mlx4_mtt *mtt);
696void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
697u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
698
699int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
700 int npages, int page_shift, struct mlx4_mr *mr);
701void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
702int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
703int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
704 int start_index, int npages, u64 *page_list);
705int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
706 struct mlx4_buf *buf);
707
Yevgeny Petrilin62968832008-04-23 11:55:45 -0700708int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
709void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
710
Yevgeny Petrilin38ae6a52008-04-25 14:27:08 -0700711int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
712 int size, int max_direct);
713void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
714 int size);
715
Roland Dreier225c7b12007-05-08 18:00:38 -0700716int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
Yevgeny Petriline463c7b2008-04-29 13:46:50 -0700717 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
Yevgeny Petrilinb8dd7862008-12-22 07:15:03 -0800718 unsigned vector, int collapsed);
Roland Dreier225c7b12007-05-08 18:00:38 -0700719void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
720
Yevgeny Petrilina3cdcbf2008-10-10 12:01:37 -0700721int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
722void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
723
724int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
Roland Dreier225c7b12007-05-08 18:00:38 -0700725void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
726
Sean Hefty18abd5e2011-06-02 10:43:26 -0700727int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
728 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
Roland Dreier225c7b12007-05-08 18:00:38 -0700729void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
730int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
Jack Morgenstein65541cb2007-06-21 13:03:11 +0300731int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
Roland Dreier225c7b12007-05-08 18:00:38 -0700732
Roland Dreier5ae2a7a2007-06-18 08:15:02 -0700733int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
Roland Dreier225c7b12007-05-08 18:00:38 -0700734int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
735
Eugenia Emantayevffe455a2011-12-13 04:16:21 +0000736int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
737 int block_mcast_loopback, enum mlx4_protocol prot);
738int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
739 enum mlx4_protocol prot);
Ron Livne521e5752008-07-14 23:48:48 -0700740int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
Aleksey Seninda995a82010-12-02 11:44:49 +0000741 int block_mcast_loopback, enum mlx4_protocol protocol);
742int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
743 enum mlx4_protocol protocol);
Yevgeny Petrilin16792002011-03-22 22:38:31 +0000744int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
745int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
746int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
747int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
748int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
Roland Dreier225c7b12007-05-08 18:00:38 -0700749
Eugenia Emantayevffe455a2011-12-13 04:16:21 +0000750int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
751void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
752int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
753int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
754void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
Eugenia Emantayev93ece0c2012-01-19 09:45:05 +0000755void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
Yevgeny Petrilin9a9a2322012-03-06 04:04:47 +0000756int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
757 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
758int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
759 u8 promisc);
Amir Vadaie5395e92012-04-04 21:33:25 +0000760int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
761int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
762 u8 *pg, u16 *ratelimit);
Eli Cohen4c3eb3c2010-08-26 17:19:22 +0300763int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
Yevgeny Petrilin2a2336f2008-10-22 11:44:46 -0700764int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
765void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
766
Jack Morgenstein8ad11fb2007-08-01 12:29:05 +0300767int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
768 int npages, u64 iova, u32 *lkey, u32 *rkey);
769int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
770 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
771int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
772void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
773 u32 *lkey, u32 *rkey);
774int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
775int mlx4_SYNC_TPT(struct mlx4_dev *dev);
Yevgeny Petriline7c1c2c42010-08-24 03:46:18 +0000776int mlx4_test_interrupts(struct mlx4_dev *dev);
Yevgeny Petrilin0b7ca5a2011-03-22 22:37:47 +0000777int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
778void mlx4_release_eq(struct mlx4_dev *dev, int vec);
Jack Morgenstein8ad11fb2007-08-01 12:29:05 +0300779
Yevgeny Petrilin14c07b12011-03-22 22:37:59 +0000780int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
781int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
782
Or Gerlitzf2a3f6a2011-06-15 14:47:14 +0000783int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
784void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
785
Jack Morgenstein396f2fe2012-06-19 11:21:42 +0300786int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
787
Roland Dreier225c7b12007-05-08 18:00:38 -0700788#endif /* MLX4_DEVICE_H */