| Krzysztof Kozlowski | 4f0d20e | 2015-12-11 15:05:56 +0900 | [diff] [blame] | 1 | /* |
| 2 | * SAMSUNG EXYNOS5420 SoC cpu device tree source |
| 3 | * |
| 4 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
| 5 | * http://www.samsung.com |
| 6 | * |
| 7 | * This file provides desired ordering for Exynos5420 and Exynos5800 |
| 8 | * boards: CPU[0123] being the A15. |
| 9 | * |
| 10 | * The Exynos5420, 5422 and 5800 actually share the same CPU configuration |
| 11 | * but particular boards choose different booting order. |
| 12 | * |
| 13 | * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422 |
| 14 | * booting cluster (big or LITTLE) is chosen by IROM code by reading |
| 15 | * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting |
| 16 | * from the LITTLE: Cortex-A7. |
| 17 | * |
| 18 | * This program is free software; you can redistribute it and/or modify |
| 19 | * it under the terms of the GNU General Public License version 2 as |
| 20 | * published by the Free Software Foundation. |
| 21 | */ |
| 22 | |
| 23 | / { |
| 24 | cpus { |
| 25 | #address-cells = <1>; |
| 26 | #size-cells = <0>; |
| 27 | |
| 28 | cpu0: cpu@0 { |
| 29 | device_type = "cpu"; |
| 30 | compatible = "arm,cortex-a15"; |
| 31 | reg = <0x0>; |
| 32 | clock-frequency = <1800000000>; |
| 33 | cci-control-port = <&cci_control1>; |
| 34 | }; |
| 35 | |
| 36 | cpu1: cpu@1 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a15"; |
| 39 | reg = <0x1>; |
| 40 | clock-frequency = <1800000000>; |
| 41 | cci-control-port = <&cci_control1>; |
| 42 | }; |
| 43 | |
| 44 | cpu2: cpu@2 { |
| 45 | device_type = "cpu"; |
| 46 | compatible = "arm,cortex-a15"; |
| 47 | reg = <0x2>; |
| 48 | clock-frequency = <1800000000>; |
| 49 | cci-control-port = <&cci_control1>; |
| 50 | }; |
| 51 | |
| 52 | cpu3: cpu@3 { |
| 53 | device_type = "cpu"; |
| 54 | compatible = "arm,cortex-a15"; |
| 55 | reg = <0x3>; |
| 56 | clock-frequency = <1800000000>; |
| 57 | cci-control-port = <&cci_control1>; |
| 58 | }; |
| 59 | |
| 60 | cpu4: cpu@100 { |
| 61 | device_type = "cpu"; |
| 62 | compatible = "arm,cortex-a7"; |
| 63 | reg = <0x100>; |
| 64 | clock-frequency = <1000000000>; |
| 65 | cci-control-port = <&cci_control0>; |
| 66 | }; |
| 67 | |
| 68 | cpu5: cpu@101 { |
| 69 | device_type = "cpu"; |
| 70 | compatible = "arm,cortex-a7"; |
| 71 | reg = <0x101>; |
| 72 | clock-frequency = <1000000000>; |
| 73 | cci-control-port = <&cci_control0>; |
| 74 | }; |
| 75 | |
| 76 | cpu6: cpu@102 { |
| 77 | device_type = "cpu"; |
| 78 | compatible = "arm,cortex-a7"; |
| 79 | reg = <0x102>; |
| 80 | clock-frequency = <1000000000>; |
| 81 | cci-control-port = <&cci_control0>; |
| 82 | }; |
| 83 | |
| 84 | cpu7: cpu@103 { |
| 85 | device_type = "cpu"; |
| 86 | compatible = "arm,cortex-a7"; |
| 87 | reg = <0x103>; |
| 88 | clock-frequency = <1000000000>; |
| 89 | cci-control-port = <&cci_control0>; |
| 90 | }; |
| 91 | }; |
| 92 | }; |