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Thomas Mair82041c02012-05-18 14:47:40 -03001/*
2 * Realtek RTL2832 DVB-T demodulator driver
3 *
4 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
Antti Palosaari75c24002014-12-16 13:54:23 -03005 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
Thomas Mair82041c02012-05-18 14:47:40 -03006 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#ifndef RTL2832_PRIV_H
23#define RTL2832_PRIV_H
24
Antti Palosaarid1016582014-12-14 04:45:57 -030025#include <linux/regmap.h>
Antti Palosaarif7caf932014-12-14 10:05:49 -030026#include <linux/math64.h>
Antti Palosaaricd559e02014-12-16 13:37:18 -030027#include <linux/bitops.h>
28
29#include "dvb_frontend.h"
30#include "dvb_math.h"
31#include "rtl2832.h"
Thomas Mair82041c02012-05-18 14:47:40 -030032
Antti Palosaari038c6f22014-12-13 00:37:43 -030033struct rtl2832_dev {
Antti Palosaarie1174d72014-12-13 05:26:27 -030034 struct rtl2832_platform_data *pdata;
Antti Palosaaric2c83862014-12-02 10:55:17 -030035 struct i2c_client *client;
Antti Palosaarib410dae2014-12-18 07:22:46 -030036 struct mutex regmap_mutex;
37 struct regmap_config regmap_config;
Antti Palosaarid1016582014-12-14 04:45:57 -030038 struct regmap *regmap;
Antti Palosaari0ea872d2013-12-03 18:19:39 -030039 struct i2c_adapter *i2c_adapter_tuner;
Thomas Mair82041c02012-05-18 14:47:40 -030040 struct dvb_frontend fe;
Antti Palosaari19d273d2014-12-14 06:55:43 -030041 struct delayed_work stat_work;
42 fe_status_t fe_status;
Antti Palosaari084330b2014-12-14 10:10:22 -030043 u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
Antti Palosaari6b4fd012014-12-14 09:59:20 -030044 u64 post_bit_error;
45 u64 post_bit_count;
Thomas Mair82041c02012-05-18 14:47:40 -030046 bool sleeping;
Antti Palosaari92d20d92014-02-08 03:50:04 -030047 struct delayed_work i2c_gate_work;
Antti Palosaari4b01e012014-12-14 14:07:35 -030048 unsigned long filters; /* PID filter */
Thomas Mair82041c02012-05-18 14:47:40 -030049};
50
51struct rtl2832_reg_entry {
Antti Palosaarieec21be2014-12-15 01:17:25 -030052 u16 start_address;
Thomas Mair82041c02012-05-18 14:47:40 -030053 u8 msb;
54 u8 lsb;
55};
56
57struct rtl2832_reg_value {
58 int reg;
59 u32 value;
60};
61
Thomas Mair82041c02012-05-18 14:47:40 -030062/* Demod register bit names */
63enum DVBT_REG_BIT_NAME {
64 DVBT_SOFT_RST,
65 DVBT_IIC_REPEAT,
66 DVBT_TR_WAIT_MIN_8K,
67 DVBT_RSD_BER_FAIL_VAL,
68 DVBT_EN_BK_TRK,
69 DVBT_REG_PI,
70 DVBT_REG_PFREQ_1_0,
71 DVBT_PD_DA8,
72 DVBT_LOCK_TH,
73 DVBT_BER_PASS_SCAL,
74 DVBT_CE_FFSM_BYPASS,
75 DVBT_ALPHAIIR_N,
76 DVBT_ALPHAIIR_DIF,
77 DVBT_EN_TRK_SPAN,
78 DVBT_LOCK_TH_LEN,
79 DVBT_CCI_THRE,
80 DVBT_CCI_MON_SCAL,
81 DVBT_CCI_M0,
82 DVBT_CCI_M1,
83 DVBT_CCI_M2,
84 DVBT_CCI_M3,
85 DVBT_SPEC_INIT_0,
86 DVBT_SPEC_INIT_1,
87 DVBT_SPEC_INIT_2,
88 DVBT_AD_EN_REG,
89 DVBT_AD_EN_REG1,
90 DVBT_EN_BBIN,
91 DVBT_MGD_THD0,
92 DVBT_MGD_THD1,
93 DVBT_MGD_THD2,
94 DVBT_MGD_THD3,
95 DVBT_MGD_THD4,
96 DVBT_MGD_THD5,
97 DVBT_MGD_THD6,
98 DVBT_MGD_THD7,
99 DVBT_EN_CACQ_NOTCH,
100 DVBT_AD_AV_REF,
101 DVBT_PIP_ON,
102 DVBT_SCALE1_B92,
103 DVBT_SCALE1_B93,
104 DVBT_SCALE1_BA7,
105 DVBT_SCALE1_BA9,
106 DVBT_SCALE1_BAA,
107 DVBT_SCALE1_BAB,
108 DVBT_SCALE1_BAC,
109 DVBT_SCALE1_BB0,
110 DVBT_SCALE1_BB1,
111 DVBT_KB_P1,
112 DVBT_KB_P2,
113 DVBT_KB_P3,
114 DVBT_OPT_ADC_IQ,
115 DVBT_AD_AVI,
116 DVBT_AD_AVQ,
117 DVBT_K1_CR_STEP12,
118 DVBT_TRK_KS_P2,
119 DVBT_TRK_KS_I2,
120 DVBT_TR_THD_SET2,
121 DVBT_TRK_KC_P2,
122 DVBT_TRK_KC_I2,
123 DVBT_CR_THD_SET2,
124 DVBT_PSET_IFFREQ,
125 DVBT_SPEC_INV,
126 DVBT_BW_INDEX,
127 DVBT_RSAMP_RATIO,
128 DVBT_CFREQ_OFF_RATIO,
129 DVBT_FSM_STAGE,
130 DVBT_RX_CONSTEL,
131 DVBT_RX_HIER,
132 DVBT_RX_C_RATE_LP,
133 DVBT_RX_C_RATE_HP,
134 DVBT_GI_IDX,
135 DVBT_FFT_MODE_IDX,
136 DVBT_RSD_BER_EST,
137 DVBT_CE_EST_EVM,
138 DVBT_RF_AGC_VAL,
139 DVBT_IF_AGC_VAL,
140 DVBT_DAGC_VAL,
141 DVBT_SFREQ_OFF,
142 DVBT_CFREQ_OFF,
143 DVBT_POLAR_RF_AGC,
144 DVBT_POLAR_IF_AGC,
145 DVBT_AAGC_HOLD,
146 DVBT_EN_RF_AGC,
147 DVBT_EN_IF_AGC,
148 DVBT_IF_AGC_MIN,
149 DVBT_IF_AGC_MAX,
150 DVBT_RF_AGC_MIN,
151 DVBT_RF_AGC_MAX,
152 DVBT_IF_AGC_MAN,
153 DVBT_IF_AGC_MAN_VAL,
154 DVBT_RF_AGC_MAN,
155 DVBT_RF_AGC_MAN_VAL,
156 DVBT_DAGC_TRG_VAL,
157 DVBT_AGC_TARG_VAL,
158 DVBT_LOOP_GAIN_3_0,
159 DVBT_LOOP_GAIN_4,
160 DVBT_VTOP,
161 DVBT_KRF,
162 DVBT_AGC_TARG_VAL_0,
163 DVBT_AGC_TARG_VAL_8_1,
164 DVBT_AAGC_LOOP_GAIN,
165 DVBT_LOOP_GAIN2_3_0,
166 DVBT_LOOP_GAIN2_4,
167 DVBT_LOOP_GAIN3,
168 DVBT_VTOP1,
169 DVBT_VTOP2,
170 DVBT_VTOP3,
171 DVBT_KRF1,
172 DVBT_KRF2,
173 DVBT_KRF3,
174 DVBT_KRF4,
175 DVBT_EN_GI_PGA,
176 DVBT_THD_LOCK_UP,
177 DVBT_THD_LOCK_DW,
178 DVBT_THD_UP1,
179 DVBT_THD_DW1,
180 DVBT_INTER_CNT_LEN,
181 DVBT_GI_PGA_STATE,
182 DVBT_EN_AGC_PGA,
183 DVBT_CKOUTPAR,
184 DVBT_CKOUT_PWR,
185 DVBT_SYNC_DUR,
186 DVBT_ERR_DUR,
187 DVBT_SYNC_LVL,
188 DVBT_ERR_LVL,
189 DVBT_VAL_LVL,
190 DVBT_SERIAL,
191 DVBT_SER_LSB,
192 DVBT_CDIV_PH0,
193 DVBT_CDIV_PH1,
194 DVBT_MPEG_IO_OPT_2_2,
195 DVBT_MPEG_IO_OPT_1_0,
196 DVBT_CKOUTPAR_PIP,
197 DVBT_CKOUT_PWR_PIP,
198 DVBT_SYNC_LVL_PIP,
199 DVBT_ERR_LVL_PIP,
200 DVBT_VAL_LVL_PIP,
201 DVBT_CKOUTPAR_PID,
202 DVBT_CKOUT_PWR_PID,
203 DVBT_SYNC_LVL_PID,
204 DVBT_ERR_LVL_PID,
205 DVBT_VAL_LVL_PID,
206 DVBT_SM_PASS,
207 DVBT_UPDATE_REG_2,
208 DVBT_BTHD_P3,
209 DVBT_BTHD_D3,
210 DVBT_FUNC4_REG0,
211 DVBT_FUNC4_REG1,
212 DVBT_FUNC4_REG2,
213 DVBT_FUNC4_REG3,
214 DVBT_FUNC4_REG4,
215 DVBT_FUNC4_REG5,
216 DVBT_FUNC4_REG6,
217 DVBT_FUNC4_REG7,
218 DVBT_FUNC4_REG8,
219 DVBT_FUNC4_REG9,
220 DVBT_FUNC4_REG10,
221 DVBT_FUNC5_REG0,
222 DVBT_FUNC5_REG1,
223 DVBT_FUNC5_REG2,
224 DVBT_FUNC5_REG3,
225 DVBT_FUNC5_REG4,
226 DVBT_FUNC5_REG5,
227 DVBT_FUNC5_REG6,
228 DVBT_FUNC5_REG7,
229 DVBT_FUNC5_REG8,
230 DVBT_FUNC5_REG9,
231 DVBT_FUNC5_REG10,
232 DVBT_FUNC5_REG11,
233 DVBT_FUNC5_REG12,
234 DVBT_FUNC5_REG13,
235 DVBT_FUNC5_REG14,
236 DVBT_FUNC5_REG15,
237 DVBT_FUNC5_REG16,
238 DVBT_FUNC5_REG17,
239 DVBT_FUNC5_REG18,
240 DVBT_AD7_SETTING,
241 DVBT_RSSI_R,
242 DVBT_ACI_DET_IND,
243 DVBT_REG_MON,
244 DVBT_REG_MONSEL,
245 DVBT_REG_GPE,
246 DVBT_REG_GPO,
247 DVBT_REG_4MSEL,
248 DVBT_TEST_REG_1,
249 DVBT_TEST_REG_2,
250 DVBT_TEST_REG_3,
251 DVBT_TEST_REG_4,
252 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
253};
254
Antti Palosaari5db41872012-09-11 22:27:08 -0300255static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
256 {DVBT_DAGC_TRG_VAL, 0x39},
257 {DVBT_AGC_TARG_VAL_0, 0x0},
258 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
259 {DVBT_AAGC_LOOP_GAIN, 0x16},
260 {DVBT_LOOP_GAIN2_3_0, 0x6},
261 {DVBT_LOOP_GAIN2_4, 0x1},
262 {DVBT_LOOP_GAIN3, 0x16},
263 {DVBT_VTOP1, 0x35},
264 {DVBT_VTOP2, 0x21},
265 {DVBT_VTOP3, 0x21},
266 {DVBT_KRF1, 0x0},
267 {DVBT_KRF2, 0x40},
268 {DVBT_KRF3, 0x10},
269 {DVBT_KRF4, 0x10},
270 {DVBT_IF_AGC_MIN, 0x80},
271 {DVBT_IF_AGC_MAX, 0x7f},
272 {DVBT_RF_AGC_MIN, 0x9c},
273 {DVBT_RF_AGC_MAX, 0x7f},
274 {DVBT_POLAR_RF_AGC, 0x0},
275 {DVBT_POLAR_IF_AGC, 0x0},
276 {DVBT_AD7_SETTING, 0xe9f4},
277 {DVBT_OPT_ADC_IQ, 0x1},
278 {DVBT_AD_AVI, 0x0},
279 {DVBT_AD_AVQ, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300280 {DVBT_SPEC_INV, 0x0},
Antti Palosaari5db41872012-09-11 22:27:08 -0300281};
282
Antti Palosaari832cc7c2012-09-11 22:27:04 -0300283static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
284 {DVBT_DAGC_TRG_VAL, 0x5a},
285 {DVBT_AGC_TARG_VAL_0, 0x0},
286 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
287 {DVBT_AAGC_LOOP_GAIN, 0x16},
288 {DVBT_LOOP_GAIN2_3_0, 0x6},
289 {DVBT_LOOP_GAIN2_4, 0x1},
290 {DVBT_LOOP_GAIN3, 0x16},
291 {DVBT_VTOP1, 0x35},
292 {DVBT_VTOP2, 0x21},
293 {DVBT_VTOP3, 0x21},
294 {DVBT_KRF1, 0x0},
295 {DVBT_KRF2, 0x40},
296 {DVBT_KRF3, 0x10},
297 {DVBT_KRF4, 0x10},
298 {DVBT_IF_AGC_MIN, 0x80},
299 {DVBT_IF_AGC_MAX, 0x7f},
300 {DVBT_RF_AGC_MIN, 0x80},
301 {DVBT_RF_AGC_MAX, 0x7f},
302 {DVBT_POLAR_RF_AGC, 0x0},
303 {DVBT_POLAR_IF_AGC, 0x0},
304 {DVBT_AD7_SETTING, 0xe9bf},
305 {DVBT_EN_GI_PGA, 0x0},
306 {DVBT_THD_LOCK_UP, 0x0},
307 {DVBT_THD_LOCK_DW, 0x0},
308 {DVBT_THD_UP1, 0x11},
309 {DVBT_THD_DW1, 0xef},
310 {DVBT_INTER_CNT_LEN, 0xc},
311 {DVBT_GI_PGA_STATE, 0x0},
312 {DVBT_EN_AGC_PGA, 0x1},
313 {DVBT_IF_AGC_MAN, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300314 {DVBT_SPEC_INV, 0x0},
Antti Palosaari832cc7c2012-09-11 22:27:04 -0300315};
316
Antti Palosaari7e688de2012-09-17 17:53:04 -0300317static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
318 {DVBT_DAGC_TRG_VAL, 0x5a},
319 {DVBT_AGC_TARG_VAL_0, 0x0},
320 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
321 {DVBT_AAGC_LOOP_GAIN, 0x18},
322 {DVBT_LOOP_GAIN2_3_0, 0x8},
323 {DVBT_LOOP_GAIN2_4, 0x1},
324 {DVBT_LOOP_GAIN3, 0x18},
325 {DVBT_VTOP1, 0x35},
326 {DVBT_VTOP2, 0x21},
327 {DVBT_VTOP3, 0x21},
328 {DVBT_KRF1, 0x0},
329 {DVBT_KRF2, 0x40},
330 {DVBT_KRF3, 0x10},
331 {DVBT_KRF4, 0x10},
332 {DVBT_IF_AGC_MIN, 0x80},
333 {DVBT_IF_AGC_MAX, 0x7f},
334 {DVBT_RF_AGC_MIN, 0x80},
335 {DVBT_RF_AGC_MAX, 0x7f},
336 {DVBT_POLAR_RF_AGC, 0x0},
337 {DVBT_POLAR_IF_AGC, 0x0},
338 {DVBT_AD7_SETTING, 0xe9d4},
339 {DVBT_EN_GI_PGA, 0x0},
340 {DVBT_THD_LOCK_UP, 0x0},
341 {DVBT_THD_LOCK_DW, 0x0},
342 {DVBT_THD_UP1, 0x14},
343 {DVBT_THD_DW1, 0xec},
344 {DVBT_INTER_CNT_LEN, 0xc},
345 {DVBT_GI_PGA_STATE, 0x0},
346 {DVBT_EN_AGC_PGA, 0x1},
347 {DVBT_REG_GPE, 0x1},
348 {DVBT_REG_GPO, 0x1},
349 {DVBT_REG_MONSEL, 0x1},
350 {DVBT_REG_MON, 0x1},
351 {DVBT_REG_4MSEL, 0x0},
Antti Palosaari3ca24182013-10-13 00:06:44 -0300352 {DVBT_SPEC_INV, 0x0},
Mauro Carvalho Chehabfa4bfd22013-04-09 18:19:50 -0300353};
354
355static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
Antti Palosaari3ca24182013-10-13 00:06:44 -0300356 {DVBT_DAGC_TRG_VAL, 0x39},
357 {DVBT_AGC_TARG_VAL_0, 0x0},
358 {DVBT_AGC_TARG_VAL_8_1, 0x40},
359 {DVBT_AAGC_LOOP_GAIN, 0x16},
360 {DVBT_LOOP_GAIN2_3_0, 0x8},
361 {DVBT_LOOP_GAIN2_4, 0x1},
362 {DVBT_LOOP_GAIN3, 0x18},
363 {DVBT_VTOP1, 0x35},
364 {DVBT_VTOP2, 0x21},
365 {DVBT_VTOP3, 0x21},
366 {DVBT_KRF1, 0x0},
367 {DVBT_KRF2, 0x40},
368 {DVBT_KRF3, 0x10},
369 {DVBT_KRF4, 0x10},
370 {DVBT_IF_AGC_MIN, 0x80},
371 {DVBT_IF_AGC_MAX, 0x7f},
372 {DVBT_RF_AGC_MIN, 0x80},
373 {DVBT_RF_AGC_MAX, 0x7f},
374 {DVBT_POLAR_RF_AGC, 0x0},
375 {DVBT_POLAR_IF_AGC, 0x0},
376 {DVBT_AD7_SETTING, 0xe9f4},
377 {DVBT_SPEC_INV, 0x1},
Antti Palosaari7e688de2012-09-17 17:53:04 -0300378};
379
Olli Salonen699dcff2015-05-05 13:54:19 -0300380static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
381 {DVBT_DAGC_TRG_VAL, 0x39},
382 {DVBT_AGC_TARG_VAL_0, 0x0},
383 {DVBT_AGC_TARG_VAL_8_1, 0x40},
384 {DVBT_AAGC_LOOP_GAIN, 0x16},
385 {DVBT_LOOP_GAIN2_3_0, 0x8},
386 {DVBT_LOOP_GAIN2_4, 0x1},
387 {DVBT_LOOP_GAIN3, 0x18},
388 {DVBT_VTOP1, 0x35},
389 {DVBT_VTOP2, 0x21},
390 {DVBT_VTOP3, 0x21},
391 {DVBT_KRF1, 0x0},
392 {DVBT_KRF2, 0x40},
393 {DVBT_KRF3, 0x10},
394 {DVBT_KRF4, 0x10},
395 {DVBT_IF_AGC_MIN, 0x80},
396 {DVBT_IF_AGC_MAX, 0x7f},
397 {DVBT_RF_AGC_MIN, 0x80},
398 {DVBT_RF_AGC_MAX, 0x7f},
399 {DVBT_POLAR_RF_AGC, 0x0},
400 {DVBT_POLAR_IF_AGC, 0x0},
401 {DVBT_AD7_SETTING, 0xe9f4},
402 {DVBT_SPEC_INV, 0x0},
403};
404
Thomas Mair82041c02012-05-18 14:47:40 -0300405#endif /* RTL2832_PRIV_H */