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gerrit-public.fairphone.software / kernel / msm-4.19 / 6e0fc46dc2152d3e2d25a5d5b640ae3586c247c6 / . / include / linux / stmmac.h
blob: eead8ab93c0a36e402741ee767d3c3bc70128964 [file] [log] [blame]
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]1/*******************************************************************************
2
3 Header file for stmmac platform data
4
5 Copyright (C) 2009 STMicroelectronics Ltd
6
7 This program is free software; you can redistribute it and/or modify it
8 under the terms and conditions of the GNU General Public License,
9 version 2, as published by the Free Software Foundation.
10
11 This program is distributed in the hope it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 more details.
15
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc.,
18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19
20 The full GNU General Public License is included in this distribution in
21 the file called "COPYING".
22
23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
24*******************************************************************************/
25
26#ifndef __STMMAC_PLATFORM_DATA
27#define __STMMAC_PLATFORM_DATA
28
Viresh KUMAR57a503c2011-05-02 18:36:45 +0000[diff] [blame]29#include <linux/platform_device.h>
30
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000[diff] [blame]31#define STMMAC_RX_COE_NONE 0
32#define STMMAC_RX_COE_TYPE1 1
33#define STMMAC_RX_COE_TYPE2 2
34
Deepak SIKRIfaeae3f2012-04-04 04:33:22 +0000[diff] [blame]35/* Define the macros for CSR clock range parameters to be passed by
36 * platform code.
37 * This could also be configured at run time using CPU freq framework. */
38
39/* MDC Clock Selection define*/
Giuseppe CAVALLARO18f05d62012-04-04 04:33:26 +0000[diff] [blame]40#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
41#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
42#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
43#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
44#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
45#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
Deepak SIKRIfaeae3f2012-04-04 04:33:22 +0000[diff] [blame]46
Giuseppe CAVALLARO18f05d62012-04-04 04:33:26 +0000[diff] [blame]47/* The MDC clock could be set higher than the IEEE 802.3
Deepak SIKRIfaeae3f2012-04-04 04:33:22 +0000[diff] [blame]48 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
49 * of value different than the above defined values. The resultant MDIO
50 * clock frequency of 12.5 MHz is applicable for the interfacing chips
51 * supporting higher MDC clocks.
52 * The MDC clock selection macros need to be defined for MDC clock rate
53 * of 12.5 MHz, corresponding to the following selection.
Giuseppe CAVALLARO18f05d62012-04-04 04:33:26 +0000[diff] [blame]54 */
55#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
56#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
57#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
58#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
59#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
60#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
61#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
62#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
Deepak SIKRIfaeae3f2012-04-04 04:33:22 +0000[diff] [blame]63
Masanari Iida02582e92012-08-22 19:11:26 +0900[diff] [blame]64/* AXI DMA Burst length supported */
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame]65#define DMA_AXI_BLEN_4 (1 << 1)
66#define DMA_AXI_BLEN_8 (1 << 2)
67#define DMA_AXI_BLEN_16 (1 << 3)
68#define DMA_AXI_BLEN_32 (1 << 4)
69#define DMA_AXI_BLEN_64 (1 << 5)
70#define DMA_AXI_BLEN_128 (1 << 6)
71#define DMA_AXI_BLEN_256 (1 << 7)
72#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
73 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
74 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)
75
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]76/* Platfrom data for platform device structure's platform_data field */
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]77
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]78struct stmmac_mdio_bus_data {
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]79 int (*phy_reset)(void *priv);
80 unsigned int phy_mask;
81 int *irqs;
82 int probed_phy_irq;
Srinivas Kandagatla0e076472013-07-04 10:35:48 +0100[diff] [blame]83#ifdef CONFIG_OF
84 int reset_gpio, active_low;
85 u32 delays[3];
86#endif
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]87};
88
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame]89struct stmmac_dma_cfg {
90 int pbl;
91 int fixed_burst;
Giuseppe CAVALLAROb9cde0a2012-05-13 22:18:42 +0000[diff] [blame]92 int mixed_burst;
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame]93 int burst_len;
94};
95
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]96struct plat_stmmacenet_data {
Srinivas Kandagatlaf142af22012-04-04 04:33:19 +0000[diff] [blame]97 char *phy_bus_name;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]98 int bus_id;
Giuseppe CAVALLARO36bcfe72011-07-20 00:05:23 +0000[diff] [blame]99 int phy_addr;
100 int interface;
101 struct stmmac_mdio_bus_data *mdio_bus_data;
Mathieu Olivari5790cf32015-05-27 11:02:47 -0700[diff] [blame]102 struct device_node *phy_node;
Deepak SIKRI8327eb62012-04-04 04:33:23 +0000[diff] [blame]103 struct stmmac_dma_cfg *dma_cfg;
Giuseppe CAVALLAROdfb8fb92010-09-17 03:23:39 +0000[diff] [blame]104 int clk_csr;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]105 int has_gmac;
Giuseppe CAVALLAROe326e852010-04-13 20:21:14 +0000[diff] [blame]106 int enh_desc;
Giuseppe CAVALLAROebbb2932010-09-17 03:23:40 +0000[diff] [blame]107 int tx_coe;
Deepak SIKRI55f9a4d2012-04-04 04:33:20 +0000[diff] [blame]108 int rx_coe;
Giuseppe CAVALLAROebbb2932010-09-17 03:23:40 +0000[diff] [blame]109 int bugged_jumbo;
Giuseppe Cavallaro543876c2010-09-24 21:27:41 -0700[diff] [blame]110 int pmt;
Srinivas Kandagatla61b80132011-07-17 20:54:09 +0000[diff] [blame]111 int force_sf_dma_mode;
Sonic Zhange2a240c2013-08-28 18:55:39 +0800[diff] [blame]112 int force_thresh_dma_mode;
Giuseppe CAVALLARO62a2ab92012-11-25 23:10:43 +0000[diff] [blame]113 int riwt_off;
Srinivas Kandagatla9cbadf02014-01-16 10:51:43 +0000[diff] [blame]114 int max_speed;
Vince Bridgers2618abb2014-01-20 05:39:01 -0600[diff] [blame]115 int maxmtu;
Vince Bridgers3b57de92014-07-31 15:49:17 -0500[diff] [blame]116 int multicast_filter_bins;
117 int unicast_filter_entries;
Vince Bridgerse7877f52015-04-15 11:17:40 -0500[diff] [blame]118 int tx_fifo_size;
119 int rx_fifo_size;
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]120 void (*fix_mac_speed)(void *priv, unsigned int speed);
Giuseppe CAVALLAROad01b7d2010-08-23 20:40:42 +0000[diff] [blame]121 void (*bus_setup)(void __iomem *ioaddr);
Chen-Yu Tsai938dfda2014-01-17 21:24:42 +0800[diff] [blame]122 int (*init)(struct platform_device *pdev, void *priv);
123 void (*exit)(struct platform_device *pdev, void *priv);
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]124 void *bsp_priv;
125};
Giuseppe CAVALLARO3c9732c2010-01-06 23:07:13 +0000[diff] [blame]126#endif