Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Broadcom Starfighter 2 DSA switch driver |
| 3 | * |
| 4 | * Copyright (C) 2014, Broadcom Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | #include <linux/list.h> |
| 13 | #include <linux/module.h> |
| 14 | #include <linux/netdevice.h> |
| 15 | #include <linux/interrupt.h> |
| 16 | #include <linux/platform_device.h> |
| 17 | #include <linux/of.h> |
| 18 | #include <linux/phy.h> |
| 19 | #include <linux/phy_fixed.h> |
| 20 | #include <linux/mii.h> |
| 21 | #include <linux/of.h> |
| 22 | #include <linux/of_irq.h> |
| 23 | #include <linux/of_address.h> |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 24 | #include <linux/of_net.h> |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 25 | #include <linux/of_mdio.h> |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 26 | #include <net/dsa.h> |
Florian Fainelli | 96e65d7 | 2014-09-18 17:31:25 -0700 | [diff] [blame] | 27 | #include <linux/ethtool.h> |
Florian Fainelli | 12f460f | 2015-02-24 13:15:34 -0800 | [diff] [blame] | 28 | #include <linux/if_bridge.h> |
Florian Fainelli | aafc66f | 2015-06-10 18:08:01 -0700 | [diff] [blame] | 29 | #include <linux/brcmphy.h> |
Florian Fainelli | 680060d | 2015-10-23 11:38:07 -0700 | [diff] [blame] | 30 | #include <linux/etherdevice.h> |
| 31 | #include <net/switchdev.h> |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 32 | #include <linux/platform_data/b53.h> |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 33 | |
| 34 | #include "bcm_sf2.h" |
| 35 | #include "bcm_sf2_regs.h" |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 36 | #include "b53/b53_priv.h" |
| 37 | #include "b53/b53_regs.h" |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 38 | |
Andrew Lunn | 7b31436 | 2016-08-22 16:01:01 +0200 | [diff] [blame] | 39 | static enum dsa_tag_protocol bcm_sf2_sw_get_tag_protocol(struct dsa_switch *ds) |
| 40 | { |
| 41 | return DSA_TAG_PROTO_BRCM; |
| 42 | } |
| 43 | |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 44 | static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port) |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 45 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 46 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 47 | unsigned int i; |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 48 | u32 reg; |
| 49 | |
| 50 | /* Enable the IMP Port to be in the same VLAN as the other ports |
| 51 | * on a per-port basis such that we only have Port i and IMP in |
| 52 | * the same VLAN. |
| 53 | */ |
| 54 | for (i = 0; i < priv->hw_params.num_ports; i++) { |
Andrew Lunn | 74c3e2a | 2016-04-13 02:40:44 +0200 | [diff] [blame] | 55 | if (!((1 << i) & ds->enabled_port_mask)) |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 56 | continue; |
| 57 | |
| 58 | reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i)); |
| 59 | reg |= (1 << cpu_port); |
| 60 | core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i)); |
| 61 | } |
| 62 | } |
| 63 | |
Florian Fainelli | ebb2ac4 | 2017-01-20 12:36:31 -0800 | [diff] [blame] | 64 | static void bcm_sf2_brcm_hdr_setup(struct bcm_sf2_priv *priv, int port) |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 65 | { |
Florian Fainelli | ebb2ac4 | 2017-01-20 12:36:31 -0800 | [diff] [blame] | 66 | u32 reg, val; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 67 | |
| 68 | /* Resolve which bit controls the Broadcom tag */ |
| 69 | switch (port) { |
| 70 | case 8: |
| 71 | val = BRCM_HDR_EN_P8; |
| 72 | break; |
| 73 | case 7: |
| 74 | val = BRCM_HDR_EN_P7; |
| 75 | break; |
| 76 | case 5: |
| 77 | val = BRCM_HDR_EN_P5; |
| 78 | break; |
| 79 | default: |
| 80 | val = 0; |
| 81 | break; |
| 82 | } |
| 83 | |
| 84 | /* Enable Broadcom tags for IMP port */ |
| 85 | reg = core_readl(priv, CORE_BRCM_HDR_CTRL); |
| 86 | reg |= val; |
| 87 | core_writel(priv, reg, CORE_BRCM_HDR_CTRL); |
| 88 | |
| 89 | /* Enable reception Broadcom tag for CPU TX (switch RX) to |
| 90 | * allow us to tag outgoing frames |
| 91 | */ |
| 92 | reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS); |
| 93 | reg &= ~(1 << port); |
| 94 | core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS); |
| 95 | |
| 96 | /* Enable transmission of Broadcom tags from the switch (CPU RX) to |
| 97 | * allow delivering frames to the per-port net_devices |
| 98 | */ |
| 99 | reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS); |
| 100 | reg &= ~(1 << port); |
| 101 | core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS); |
Florian Fainelli | ebb2ac4 | 2017-01-20 12:36:31 -0800 | [diff] [blame] | 102 | } |
| 103 | |
| 104 | static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port) |
| 105 | { |
| 106 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
| 107 | u32 reg, offset; |
| 108 | |
| 109 | if (priv->type == BCM7445_DEVICE_ID) |
| 110 | offset = CORE_STS_OVERRIDE_IMP; |
| 111 | else |
| 112 | offset = CORE_STS_OVERRIDE_IMP2; |
| 113 | |
| 114 | /* Enable the port memories */ |
| 115 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); |
| 116 | reg &= ~P_TXQ_PSM_VDD(port); |
| 117 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); |
| 118 | |
| 119 | /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */ |
| 120 | reg = core_readl(priv, CORE_IMP_CTL); |
| 121 | reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN); |
| 122 | reg &= ~(RX_DIS | TX_DIS); |
| 123 | core_writel(priv, reg, CORE_IMP_CTL); |
| 124 | |
| 125 | /* Enable forwarding */ |
| 126 | core_writel(priv, SW_FWDG_EN, CORE_SWMODE); |
| 127 | |
| 128 | /* Enable IMP port in dumb mode */ |
| 129 | reg = core_readl(priv, CORE_SWITCH_CTRL); |
| 130 | reg |= MII_DUMB_FWDG_EN; |
| 131 | core_writel(priv, reg, CORE_SWITCH_CTRL); |
| 132 | |
| 133 | bcm_sf2_brcm_hdr_setup(priv, port); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 134 | |
| 135 | /* Force link status for IMP port */ |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 136 | reg = core_readl(priv, offset); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 137 | reg |= (MII_SW_OR | LINK_STS); |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 138 | core_writel(priv, reg, offset); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 139 | } |
| 140 | |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 141 | static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable) |
| 142 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 143 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 144 | u32 reg; |
| 145 | |
| 146 | reg = core_readl(priv, CORE_EEE_EN_CTRL); |
| 147 | if (enable) |
| 148 | reg |= 1 << port; |
| 149 | else |
| 150 | reg &= ~(1 << port); |
| 151 | core_writel(priv, reg, CORE_EEE_EN_CTRL); |
| 152 | } |
| 153 | |
Florian Fainelli | b083668 | 2015-02-05 11:40:41 -0800 | [diff] [blame] | 154 | static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable) |
| 155 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 156 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | b083668 | 2015-02-05 11:40:41 -0800 | [diff] [blame] | 157 | u32 reg; |
| 158 | |
Florian Fainelli | 9af197a | 2015-02-05 11:40:42 -0800 | [diff] [blame] | 159 | reg = reg_readl(priv, REG_SPHY_CNTRL); |
| 160 | if (enable) { |
| 161 | reg |= PHY_RESET; |
| 162 | reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS); |
| 163 | reg_writel(priv, reg, REG_SPHY_CNTRL); |
| 164 | udelay(21); |
| 165 | reg = reg_readl(priv, REG_SPHY_CNTRL); |
| 166 | reg &= ~PHY_RESET; |
| 167 | } else { |
| 168 | reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET; |
| 169 | reg_writel(priv, reg, REG_SPHY_CNTRL); |
| 170 | mdelay(1); |
| 171 | reg |= CK25_DIS; |
| 172 | } |
| 173 | reg_writel(priv, reg, REG_SPHY_CNTRL); |
Florian Fainelli | b083668 | 2015-02-05 11:40:41 -0800 | [diff] [blame] | 174 | |
Florian Fainelli | 9af197a | 2015-02-05 11:40:42 -0800 | [diff] [blame] | 175 | /* Use PHY-driven LED signaling */ |
| 176 | if (!enable) { |
| 177 | reg = reg_readl(priv, REG_LED_CNTRL(0)); |
| 178 | reg |= SPDLNK_SRC_SEL; |
| 179 | reg_writel(priv, reg, REG_LED_CNTRL(0)); |
| 180 | } |
Florian Fainelli | b083668 | 2015-02-05 11:40:41 -0800 | [diff] [blame] | 181 | } |
| 182 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 183 | static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv, |
| 184 | int port) |
| 185 | { |
| 186 | unsigned int off; |
| 187 | |
| 188 | switch (port) { |
| 189 | case 7: |
| 190 | off = P7_IRQ_OFF; |
| 191 | break; |
| 192 | case 0: |
| 193 | /* Port 0 interrupts are located on the first bank */ |
| 194 | intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF)); |
| 195 | return; |
| 196 | default: |
| 197 | off = P_IRQ_OFF(port); |
| 198 | break; |
| 199 | } |
| 200 | |
| 201 | intrl2_1_mask_clear(priv, P_IRQ_MASK(off)); |
| 202 | } |
| 203 | |
| 204 | static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv, |
| 205 | int port) |
| 206 | { |
| 207 | unsigned int off; |
| 208 | |
| 209 | switch (port) { |
| 210 | case 7: |
| 211 | off = P7_IRQ_OFF; |
| 212 | break; |
| 213 | case 0: |
| 214 | /* Port 0 interrupts are located on the first bank */ |
| 215 | intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF)); |
| 216 | intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR); |
| 217 | return; |
| 218 | default: |
| 219 | off = P_IRQ_OFF(port); |
| 220 | break; |
| 221 | } |
| 222 | |
| 223 | intrl2_1_mask_set(priv, P_IRQ_MASK(off)); |
| 224 | intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR); |
| 225 | } |
| 226 | |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 227 | static int bcm_sf2_port_setup(struct dsa_switch *ds, int port, |
| 228 | struct phy_device *phy) |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 229 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 230 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 231 | s8 cpu_port = ds->dst[ds->index].cpu_port; |
Florian Fainelli | e1b9147 | 2017-01-30 09:48:41 -0800 | [diff] [blame] | 232 | unsigned int i; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 233 | u32 reg; |
| 234 | |
| 235 | /* Clear the memory power down */ |
| 236 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); |
| 237 | reg &= ~P_TXQ_PSM_VDD(port); |
| 238 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); |
| 239 | |
Florian Fainelli | 64ff2ae | 2017-01-20 12:36:32 -0800 | [diff] [blame] | 240 | /* Enable Broadcom tags for that port if requested */ |
| 241 | if (priv->brcm_tag_mask & BIT(port)) |
| 242 | bcm_sf2_brcm_hdr_setup(priv, port); |
| 243 | |
Florian Fainelli | e1b9147 | 2017-01-30 09:48:41 -0800 | [diff] [blame] | 244 | /* Configure Traffic Class to QoS mapping, allow each priority to map |
| 245 | * to a different queue number |
| 246 | */ |
| 247 | reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port)); |
| 248 | for (i = 0; i < 8; i++) |
| 249 | reg |= i << (PRT_TO_QID_SHIFT * i); |
| 250 | core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port)); |
| 251 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 252 | /* Clear the Rx and Tx disable bits and set to no spanning tree */ |
| 253 | core_writel(priv, 0, CORE_G_PCTL_PORT(port)); |
| 254 | |
Florian Fainelli | 9af197a | 2015-02-05 11:40:42 -0800 | [diff] [blame] | 255 | /* Re-enable the GPHY and re-apply workarounds */ |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 256 | if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) { |
Florian Fainelli | 9af197a | 2015-02-05 11:40:42 -0800 | [diff] [blame] | 257 | bcm_sf2_gphy_enable_set(ds, true); |
| 258 | if (phy) { |
| 259 | /* if phy_stop() has been called before, phy |
| 260 | * will be in halted state, and phy_start() |
| 261 | * will call resume. |
| 262 | * |
| 263 | * the resume path does not configure back |
| 264 | * autoneg settings, and since we hard reset |
| 265 | * the phy manually here, we need to reset the |
| 266 | * state machine also. |
| 267 | */ |
| 268 | phy->state = PHY_READY; |
| 269 | phy_init_hw(phy); |
| 270 | } |
| 271 | } |
| 272 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 273 | /* Enable MoCA port interrupts to get notified */ |
| 274 | if (port == priv->moca_port) |
| 275 | bcm_sf2_port_intr_enable(priv, port); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 276 | |
Florian Fainelli | 12f460f | 2015-02-24 13:15:34 -0800 | [diff] [blame] | 277 | /* Set this port, and only this one to be in the default VLAN, |
| 278 | * if member of a bridge, restore its membership prior to |
| 279 | * bringing down this port. |
| 280 | */ |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 281 | reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port)); |
| 282 | reg &= ~PORT_VLAN_CTRL_MASK; |
| 283 | reg |= (1 << port); |
Florian Fainelli | 0215492 | 2016-09-10 12:39:03 -0700 | [diff] [blame] | 284 | reg |= priv->dev->ports[port].vlan_ctl_mask; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 285 | core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port)); |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 286 | |
| 287 | bcm_sf2_imp_vlan_setup(ds, cpu_port); |
| 288 | |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 289 | /* If EEE was enabled, restore it */ |
| 290 | if (priv->port_sts[port].eee.eee_enabled) |
| 291 | bcm_sf2_eee_enable_set(ds, port, true); |
| 292 | |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 293 | return 0; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 294 | } |
| 295 | |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 296 | static void bcm_sf2_port_disable(struct dsa_switch *ds, int port, |
| 297 | struct phy_device *phy) |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 298 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 299 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 300 | u32 off, reg; |
| 301 | |
Florian Fainelli | 96e65d7 | 2014-09-18 17:31:25 -0700 | [diff] [blame] | 302 | if (priv->wol_ports_mask & (1 << port)) |
| 303 | return; |
| 304 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 305 | if (port == priv->moca_port) |
| 306 | bcm_sf2_port_intr_disable(priv, port); |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 307 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 308 | if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) |
Florian Fainelli | 9af197a | 2015-02-05 11:40:42 -0800 | [diff] [blame] | 309 | bcm_sf2_gphy_enable_set(ds, false); |
| 310 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 311 | if (dsa_is_cpu_port(ds, port)) |
| 312 | off = CORE_IMP_CTL; |
| 313 | else |
| 314 | off = CORE_G_PCTL_PORT(port); |
| 315 | |
| 316 | reg = core_readl(priv, off); |
| 317 | reg |= RX_DIS | TX_DIS; |
| 318 | core_writel(priv, reg, off); |
| 319 | |
| 320 | /* Power down the port memory */ |
| 321 | reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL); |
| 322 | reg |= P_TXQ_PSM_VDD(port); |
| 323 | core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL); |
| 324 | } |
| 325 | |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 326 | /* Returns 0 if EEE was not enabled, or 1 otherwise |
| 327 | */ |
| 328 | static int bcm_sf2_eee_init(struct dsa_switch *ds, int port, |
| 329 | struct phy_device *phy) |
| 330 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 331 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 332 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
| 333 | int ret; |
| 334 | |
| 335 | p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full); |
| 336 | |
| 337 | ret = phy_init_eee(phy, 0); |
| 338 | if (ret) |
| 339 | return 0; |
| 340 | |
| 341 | bcm_sf2_eee_enable_set(ds, port, true); |
| 342 | |
| 343 | return 1; |
| 344 | } |
| 345 | |
| 346 | static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port, |
| 347 | struct ethtool_eee *e) |
| 348 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 349 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 350 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
| 351 | u32 reg; |
| 352 | |
| 353 | reg = core_readl(priv, CORE_EEE_LPI_INDICATE); |
| 354 | e->eee_enabled = p->eee_enabled; |
| 355 | e->eee_active = !!(reg & (1 << port)); |
| 356 | |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port, |
| 361 | struct phy_device *phydev, |
| 362 | struct ethtool_eee *e) |
| 363 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 364 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 450b05c | 2014-09-24 17:05:22 -0700 | [diff] [blame] | 365 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
| 366 | |
| 367 | p->eee_enabled = e->eee_enabled; |
| 368 | |
| 369 | if (!p->eee_enabled) { |
| 370 | bcm_sf2_eee_enable_set(ds, port, false); |
| 371 | } else { |
| 372 | p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); |
| 373 | if (!p->eee_enabled) |
| 374 | return -EOPNOTSUPP; |
| 375 | } |
| 376 | |
| 377 | return 0; |
| 378 | } |
| 379 | |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 380 | static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr, |
| 381 | int regnum, u16 val) |
| 382 | { |
| 383 | int ret = 0; |
| 384 | u32 reg; |
| 385 | |
| 386 | reg = reg_readl(priv, REG_SWITCH_CNTRL); |
| 387 | reg |= MDIO_MASTER_SEL; |
| 388 | reg_writel(priv, reg, REG_SWITCH_CNTRL); |
| 389 | |
| 390 | /* Page << 8 | offset */ |
| 391 | reg = 0x70; |
| 392 | reg <<= 2; |
| 393 | core_writel(priv, addr, reg); |
| 394 | |
| 395 | /* Page << 8 | offset */ |
| 396 | reg = 0x80 << 8 | regnum << 1; |
| 397 | reg <<= 2; |
| 398 | |
| 399 | if (op) |
| 400 | ret = core_readl(priv, reg); |
| 401 | else |
| 402 | core_writel(priv, val, reg); |
| 403 | |
| 404 | reg = reg_readl(priv, REG_SWITCH_CNTRL); |
| 405 | reg &= ~MDIO_MASTER_SEL; |
| 406 | reg_writel(priv, reg, REG_SWITCH_CNTRL); |
| 407 | |
| 408 | return ret & 0xffff; |
| 409 | } |
| 410 | |
| 411 | static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum) |
| 412 | { |
| 413 | struct bcm_sf2_priv *priv = bus->priv; |
| 414 | |
| 415 | /* Intercept reads from Broadcom pseudo-PHY address, else, send |
| 416 | * them to our master MDIO bus controller |
| 417 | */ |
| 418 | if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) |
| 419 | return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0); |
| 420 | else |
Florian Fainelli | 2cfe8f8 | 2017-01-07 21:01:57 -0800 | [diff] [blame] | 421 | return mdiobus_read_nested(priv->master_mii_bus, addr, regnum); |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 422 | } |
| 423 | |
| 424 | static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum, |
| 425 | u16 val) |
| 426 | { |
| 427 | struct bcm_sf2_priv *priv = bus->priv; |
| 428 | |
| 429 | /* Intercept writes to the Broadcom pseudo-PHY address, else, |
| 430 | * send them to our master MDIO bus controller |
| 431 | */ |
| 432 | if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr)) |
| 433 | bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val); |
| 434 | else |
Florian Fainelli | 2cfe8f8 | 2017-01-07 21:01:57 -0800 | [diff] [blame] | 435 | mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val); |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 436 | |
| 437 | return 0; |
| 438 | } |
| 439 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 440 | static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id) |
| 441 | { |
| 442 | struct bcm_sf2_priv *priv = dev_id; |
| 443 | |
| 444 | priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) & |
| 445 | ~priv->irq0_mask; |
| 446 | intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); |
| 447 | |
| 448 | return IRQ_HANDLED; |
| 449 | } |
| 450 | |
| 451 | static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id) |
| 452 | { |
| 453 | struct bcm_sf2_priv *priv = dev_id; |
| 454 | |
| 455 | priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) & |
| 456 | ~priv->irq1_mask; |
| 457 | intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); |
| 458 | |
| 459 | if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) |
| 460 | priv->port_sts[7].link = 1; |
| 461 | if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) |
| 462 | priv->port_sts[7].link = 0; |
| 463 | |
| 464 | return IRQ_HANDLED; |
| 465 | } |
| 466 | |
Florian Fainelli | 33f8461 | 2014-11-25 18:08:49 -0800 | [diff] [blame] | 467 | static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv) |
| 468 | { |
| 469 | unsigned int timeout = 1000; |
| 470 | u32 reg; |
| 471 | |
| 472 | reg = core_readl(priv, CORE_WATCHDOG_CTRL); |
| 473 | reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET; |
| 474 | core_writel(priv, reg, CORE_WATCHDOG_CTRL); |
| 475 | |
| 476 | do { |
| 477 | reg = core_readl(priv, CORE_WATCHDOG_CTRL); |
| 478 | if (!(reg & SOFTWARE_RESET)) |
| 479 | break; |
| 480 | |
| 481 | usleep_range(1000, 2000); |
| 482 | } while (timeout-- > 0); |
| 483 | |
| 484 | if (timeout == 0) |
| 485 | return -ETIMEDOUT; |
| 486 | |
| 487 | return 0; |
| 488 | } |
| 489 | |
Florian Fainelli | 691c9a8 | 2015-01-20 16:42:00 -0800 | [diff] [blame] | 490 | static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv) |
| 491 | { |
Florian Fainelli | f01d598 | 2016-08-25 15:23:41 -0700 | [diff] [blame] | 492 | intrl2_0_mask_set(priv, 0xffffffff); |
Florian Fainelli | 691c9a8 | 2015-01-20 16:42:00 -0800 | [diff] [blame] | 493 | intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); |
Florian Fainelli | f01d598 | 2016-08-25 15:23:41 -0700 | [diff] [blame] | 494 | intrl2_1_mask_set(priv, 0xffffffff); |
Florian Fainelli | 691c9a8 | 2015-01-20 16:42:00 -0800 | [diff] [blame] | 495 | intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR); |
Florian Fainelli | 691c9a8 | 2015-01-20 16:42:00 -0800 | [diff] [blame] | 496 | } |
| 497 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 498 | static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv, |
| 499 | struct device_node *dn) |
| 500 | { |
| 501 | struct device_node *port; |
| 502 | const char *phy_mode_str; |
| 503 | int mode; |
| 504 | unsigned int port_num; |
| 505 | int ret; |
| 506 | |
| 507 | priv->moca_port = -1; |
| 508 | |
| 509 | for_each_available_child_of_node(dn, port) { |
| 510 | if (of_property_read_u32(port, "reg", &port_num)) |
| 511 | continue; |
| 512 | |
| 513 | /* Internal PHYs get assigned a specific 'phy-mode' property |
| 514 | * value: "internal" to help flag them before MDIO probing |
| 515 | * has completed, since they might be turned off at that |
| 516 | * time |
| 517 | */ |
| 518 | mode = of_get_phy_mode(port); |
| 519 | if (mode < 0) { |
| 520 | ret = of_property_read_string(port, "phy-mode", |
| 521 | &phy_mode_str); |
| 522 | if (ret < 0) |
| 523 | continue; |
| 524 | |
| 525 | if (!strcasecmp(phy_mode_str, "internal")) |
| 526 | priv->int_phy_mask |= 1 << port_num; |
| 527 | } |
| 528 | |
| 529 | if (mode == PHY_INTERFACE_MODE_MOCA) |
| 530 | priv->moca_port = port_num; |
Florian Fainelli | 64ff2ae | 2017-01-20 12:36:32 -0800 | [diff] [blame] | 531 | |
| 532 | if (of_property_read_bool(port, "brcm,use-bcm-hdr")) |
| 533 | priv->brcm_tag_mask |= 1 << port_num; |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 534 | } |
| 535 | } |
| 536 | |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 537 | static int bcm_sf2_mdio_register(struct dsa_switch *ds) |
| 538 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 539 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 461cd1b0 | 2016-06-07 16:32:43 -0700 | [diff] [blame] | 540 | struct device_node *dn; |
| 541 | static int index; |
| 542 | int err; |
| 543 | |
| 544 | /* Find our integrated MDIO bus node */ |
| 545 | dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio"); |
| 546 | priv->master_mii_bus = of_mdio_find_bus(dn); |
| 547 | if (!priv->master_mii_bus) |
| 548 | return -EPROBE_DEFER; |
| 549 | |
| 550 | get_device(&priv->master_mii_bus->dev); |
| 551 | priv->master_mii_dn = dn; |
| 552 | |
| 553 | priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev); |
| 554 | if (!priv->slave_mii_bus) |
| 555 | return -ENOMEM; |
| 556 | |
| 557 | priv->slave_mii_bus->priv = priv; |
| 558 | priv->slave_mii_bus->name = "sf2 slave mii"; |
| 559 | priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read; |
| 560 | priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write; |
| 561 | snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d", |
| 562 | index++); |
| 563 | priv->slave_mii_bus->dev.of_node = dn; |
| 564 | |
| 565 | /* Include the pseudo-PHY address to divert reads towards our |
| 566 | * workaround. This is only required for 7445D0, since 7445E0 |
| 567 | * disconnects the internal switch pseudo-PHY such that we can use the |
| 568 | * regular SWITCH_MDIO master controller instead. |
| 569 | * |
| 570 | * Here we flag the pseudo PHY as needing special treatment and would |
| 571 | * otherwise make all other PHY read/writes go to the master MDIO bus |
| 572 | * controller that comes with this switch backed by the "mdio-unimac" |
| 573 | * driver. |
| 574 | */ |
| 575 | if (of_machine_is_compatible("brcm,bcm7445d0")) |
| 576 | priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR); |
| 577 | else |
| 578 | priv->indir_phy_mask = 0; |
| 579 | |
| 580 | ds->phys_mii_mask = priv->indir_phy_mask; |
| 581 | ds->slave_mii_bus = priv->slave_mii_bus; |
| 582 | priv->slave_mii_bus->parent = ds->dev->parent; |
| 583 | priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask; |
| 584 | |
| 585 | if (dn) |
| 586 | err = of_mdiobus_register(priv->slave_mii_bus, dn); |
| 587 | else |
| 588 | err = mdiobus_register(priv->slave_mii_bus); |
| 589 | |
| 590 | if (err) |
| 591 | of_node_put(dn); |
| 592 | |
| 593 | return err; |
| 594 | } |
| 595 | |
| 596 | static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv) |
| 597 | { |
| 598 | mdiobus_unregister(priv->slave_mii_bus); |
| 599 | if (priv->master_mii_dn) |
| 600 | of_node_put(priv->master_mii_dn); |
| 601 | } |
| 602 | |
Florian Fainelli | aa9aef7 | 2014-09-19 13:07:55 -0700 | [diff] [blame] | 603 | static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port) |
| 604 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 605 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | aa9aef7 | 2014-09-19 13:07:55 -0700 | [diff] [blame] | 606 | |
| 607 | /* The BCM7xxx PHY driver expects to find the integrated PHY revision |
| 608 | * in bits 15:8 and the patch level in bits 7:0 which is exactly what |
| 609 | * the REG_PHY_REVISION register layout is. |
| 610 | */ |
| 611 | |
| 612 | return priv->hw_params.gphy_rev; |
| 613 | } |
| 614 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 615 | static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port, |
| 616 | struct phy_device *phydev) |
| 617 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 618 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 76da870 | 2016-11-22 11:40:58 -0800 | [diff] [blame] | 619 | struct ethtool_eee *p = &priv->port_sts[port].eee; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 620 | u32 id_mode_dis = 0, port_mode; |
| 621 | const char *str = NULL; |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 622 | u32 reg, offset; |
| 623 | |
| 624 | if (priv->type == BCM7445_DEVICE_ID) |
| 625 | offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); |
| 626 | else |
| 627 | offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 628 | |
| 629 | switch (phydev->interface) { |
| 630 | case PHY_INTERFACE_MODE_RGMII: |
| 631 | str = "RGMII (no delay)"; |
| 632 | id_mode_dis = 1; |
| 633 | case PHY_INTERFACE_MODE_RGMII_TXID: |
| 634 | if (!str) |
| 635 | str = "RGMII (TX delay)"; |
| 636 | port_mode = EXT_GPHY; |
| 637 | break; |
| 638 | case PHY_INTERFACE_MODE_MII: |
| 639 | str = "MII"; |
| 640 | port_mode = EXT_EPHY; |
| 641 | break; |
| 642 | case PHY_INTERFACE_MODE_REVMII: |
| 643 | str = "Reverse MII"; |
| 644 | port_mode = EXT_REVMII; |
| 645 | break; |
| 646 | default: |
Florian Fainelli | 7de1557 | 2014-09-24 17:05:19 -0700 | [diff] [blame] | 647 | /* All other PHYs: internal and MoCA */ |
| 648 | goto force_link; |
| 649 | } |
| 650 | |
| 651 | /* If the link is down, just disable the interface to conserve power */ |
| 652 | if (!phydev->link) { |
| 653 | reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); |
| 654 | reg &= ~RGMII_MODE_EN; |
| 655 | reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 656 | goto force_link; |
| 657 | } |
| 658 | |
| 659 | /* Clear id_mode_dis bit, and the existing port mode, but |
| 660 | * make sure we enable the RGMII block for data to pass |
| 661 | */ |
| 662 | reg = reg_readl(priv, REG_RGMII_CNTRL_P(port)); |
| 663 | reg &= ~ID_MODE_DIS; |
| 664 | reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT); |
| 665 | reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN); |
| 666 | |
| 667 | reg |= port_mode | RGMII_MODE_EN; |
| 668 | if (id_mode_dis) |
| 669 | reg |= ID_MODE_DIS; |
| 670 | |
| 671 | if (phydev->pause) { |
| 672 | if (phydev->asym_pause) |
| 673 | reg |= TX_PAUSE_EN; |
| 674 | reg |= RX_PAUSE_EN; |
| 675 | } |
| 676 | |
| 677 | reg_writel(priv, reg, REG_RGMII_CNTRL_P(port)); |
| 678 | |
| 679 | pr_info("Port %d configured for %s\n", port, str); |
| 680 | |
| 681 | force_link: |
| 682 | /* Force link settings detected from the PHY */ |
| 683 | reg = SW_OVERRIDE; |
| 684 | switch (phydev->speed) { |
| 685 | case SPEED_1000: |
| 686 | reg |= SPDSTS_1000 << SPEED_SHIFT; |
| 687 | break; |
| 688 | case SPEED_100: |
| 689 | reg |= SPDSTS_100 << SPEED_SHIFT; |
| 690 | break; |
| 691 | } |
| 692 | |
| 693 | if (phydev->link) |
| 694 | reg |= LINK_STS; |
| 695 | if (phydev->duplex == DUPLEX_FULL) |
| 696 | reg |= DUPLX_MODE; |
| 697 | |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 698 | core_writel(priv, reg, offset); |
Florian Fainelli | 76da870 | 2016-11-22 11:40:58 -0800 | [diff] [blame] | 699 | |
| 700 | if (!phydev->is_pseudo_fixed_link) |
| 701 | p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 702 | } |
| 703 | |
| 704 | static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port, |
| 705 | struct fixed_phy_status *status) |
| 706 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 707 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 708 | u32 duplex, pause, offset; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 709 | u32 reg; |
| 710 | |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 711 | if (priv->type == BCM7445_DEVICE_ID) |
| 712 | offset = CORE_STS_OVERRIDE_GMIIP_PORT(port); |
| 713 | else |
| 714 | offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port); |
| 715 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 716 | duplex = core_readl(priv, CORE_DUPSTS); |
| 717 | pause = core_readl(priv, CORE_PAUSESTS); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 718 | |
| 719 | status->link = 0; |
| 720 | |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 721 | /* MoCA port is special as we do not get link status from CORE_LNKSTS, |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 722 | * which means that we need to force the link at the port override |
| 723 | * level to get the data to flow. We do use what the interrupt handler |
| 724 | * did determine before. |
Florian Fainelli | 7855f67 | 2014-12-11 18:12:42 -0800 | [diff] [blame] | 725 | * |
| 726 | * For the other ports, we just force the link status, since this is |
| 727 | * a fixed PHY device. |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 728 | */ |
Florian Fainelli | 8b7c94e | 2015-10-23 12:11:08 -0700 | [diff] [blame] | 729 | if (port == priv->moca_port) { |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 730 | status->link = priv->port_sts[port].link; |
Florian Fainelli | 4ab7f91 | 2015-05-15 12:38:01 -0700 | [diff] [blame] | 731 | /* For MoCA interfaces, also force a link down notification |
| 732 | * since some version of the user-space daemon (mocad) use |
| 733 | * cmd->autoneg to force the link, which messes up the PHY |
| 734 | * state machine and make it go in PHY_FORCING state instead. |
| 735 | */ |
| 736 | if (!status->link) |
Andrew Lunn | c8b0980 | 2016-06-04 21:16:57 +0200 | [diff] [blame] | 737 | netif_carrier_off(ds->ports[port].netdev); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 738 | status->duplex = 1; |
| 739 | } else { |
Florian Fainelli | 7855f67 | 2014-12-11 18:12:42 -0800 | [diff] [blame] | 740 | status->link = 1; |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 741 | status->duplex = !!(duplex & (1 << port)); |
| 742 | } |
| 743 | |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 744 | reg = core_readl(priv, offset); |
Florian Fainelli | 7855f67 | 2014-12-11 18:12:42 -0800 | [diff] [blame] | 745 | reg |= SW_OVERRIDE; |
| 746 | if (status->link) |
| 747 | reg |= LINK_STS; |
| 748 | else |
| 749 | reg &= ~LINK_STS; |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 750 | core_writel(priv, reg, offset); |
Florian Fainelli | 7855f67 | 2014-12-11 18:12:42 -0800 | [diff] [blame] | 751 | |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 752 | if ((pause & (1 << port)) && |
| 753 | (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) { |
| 754 | status->asym_pause = 1; |
| 755 | status->pause = 1; |
| 756 | } |
| 757 | |
| 758 | if (pause & (1 << port)) |
| 759 | status->pause = 1; |
| 760 | } |
| 761 | |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 762 | static int bcm_sf2_sw_suspend(struct dsa_switch *ds) |
| 763 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 764 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 765 | unsigned int port; |
| 766 | |
Florian Fainelli | 691c9a8 | 2015-01-20 16:42:00 -0800 | [diff] [blame] | 767 | bcm_sf2_intr_disable(priv); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 768 | |
| 769 | /* Disable all ports physically present including the IMP |
| 770 | * port, the other ones have already been disabled during |
| 771 | * bcm_sf2_sw_setup |
| 772 | */ |
| 773 | for (port = 0; port < DSA_MAX_PORTS; port++) { |
Andrew Lunn | 74c3e2a | 2016-04-13 02:40:44 +0200 | [diff] [blame] | 774 | if ((1 << port) & ds->enabled_port_mask || |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 775 | dsa_is_cpu_port(ds, port)) |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 776 | bcm_sf2_port_disable(ds, port, NULL); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 777 | } |
| 778 | |
| 779 | return 0; |
| 780 | } |
| 781 | |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 782 | static int bcm_sf2_sw_resume(struct dsa_switch *ds) |
| 783 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 784 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 785 | unsigned int port; |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 786 | int ret; |
| 787 | |
| 788 | ret = bcm_sf2_sw_rst(priv); |
| 789 | if (ret) { |
| 790 | pr_err("%s: failed to software reset switch\n", __func__); |
| 791 | return ret; |
| 792 | } |
| 793 | |
Florian Fainelli | b083668 | 2015-02-05 11:40:41 -0800 | [diff] [blame] | 794 | if (priv->hw_params.num_gphy == 1) |
| 795 | bcm_sf2_gphy_enable_set(ds, true); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 796 | |
| 797 | for (port = 0; port < DSA_MAX_PORTS; port++) { |
Andrew Lunn | 74c3e2a | 2016-04-13 02:40:44 +0200 | [diff] [blame] | 798 | if ((1 << port) & ds->enabled_port_mask) |
Florian Fainelli | b6d045d | 2014-09-24 17:05:20 -0700 | [diff] [blame] | 799 | bcm_sf2_port_setup(ds, port, NULL); |
Florian Fainelli | 8cfa949 | 2014-09-18 17:31:23 -0700 | [diff] [blame] | 800 | else if (dsa_is_cpu_port(ds, port)) |
| 801 | bcm_sf2_imp_setup(ds, port); |
| 802 | } |
| 803 | |
| 804 | return 0; |
| 805 | } |
| 806 | |
Florian Fainelli | 96e65d7 | 2014-09-18 17:31:25 -0700 | [diff] [blame] | 807 | static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port, |
| 808 | struct ethtool_wolinfo *wol) |
| 809 | { |
| 810 | struct net_device *p = ds->dst[ds->index].master_netdev; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 811 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 96e65d7 | 2014-09-18 17:31:25 -0700 | [diff] [blame] | 812 | struct ethtool_wolinfo pwol; |
| 813 | |
| 814 | /* Get the parent device WoL settings */ |
| 815 | p->ethtool_ops->get_wol(p, &pwol); |
| 816 | |
| 817 | /* Advertise the parent device supported settings */ |
| 818 | wol->supported = pwol.supported; |
| 819 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
| 820 | |
| 821 | if (pwol.wolopts & WAKE_MAGICSECURE) |
| 822 | memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass)); |
| 823 | |
| 824 | if (priv->wol_ports_mask & (1 << port)) |
| 825 | wol->wolopts = pwol.wolopts; |
| 826 | else |
| 827 | wol->wolopts = 0; |
| 828 | } |
| 829 | |
| 830 | static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port, |
| 831 | struct ethtool_wolinfo *wol) |
| 832 | { |
| 833 | struct net_device *p = ds->dst[ds->index].master_netdev; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 834 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 96e65d7 | 2014-09-18 17:31:25 -0700 | [diff] [blame] | 835 | s8 cpu_port = ds->dst[ds->index].cpu_port; |
| 836 | struct ethtool_wolinfo pwol; |
| 837 | |
| 838 | p->ethtool_ops->get_wol(p, &pwol); |
| 839 | if (wol->wolopts & ~pwol.supported) |
| 840 | return -EINVAL; |
| 841 | |
| 842 | if (wol->wolopts) |
| 843 | priv->wol_ports_mask |= (1 << port); |
| 844 | else |
| 845 | priv->wol_ports_mask &= ~(1 << port); |
| 846 | |
| 847 | /* If we have at least one port enabled, make sure the CPU port |
| 848 | * is also enabled. If the CPU port is the last one enabled, we disable |
| 849 | * it since this configuration does not make sense. |
| 850 | */ |
| 851 | if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port)) |
| 852 | priv->wol_ports_mask |= (1 << cpu_port); |
| 853 | else |
| 854 | priv->wol_ports_mask &= ~(1 << cpu_port); |
| 855 | |
| 856 | return p->ethtool_ops->set_wol(p, wol); |
| 857 | } |
| 858 | |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 859 | static int bcm_sf2_vlan_op_wait(struct bcm_sf2_priv *priv) |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 860 | { |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 861 | unsigned int timeout = 10; |
| 862 | u32 reg; |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 863 | |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 864 | do { |
| 865 | reg = core_readl(priv, CORE_ARLA_VTBL_RWCTRL); |
| 866 | if (!(reg & ARLA_VTBL_STDN)) |
| 867 | return 0; |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 868 | |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 869 | usleep_range(1000, 2000); |
| 870 | } while (timeout--); |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 871 | |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 872 | return -ETIMEDOUT; |
| 873 | } |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 874 | |
Florian Fainelli | de0b9d3 | 2016-08-26 12:18:34 -0700 | [diff] [blame] | 875 | static int bcm_sf2_vlan_op(struct bcm_sf2_priv *priv, u8 op) |
| 876 | { |
| 877 | core_writel(priv, ARLA_VTBL_STDN | op, CORE_ARLA_VTBL_RWCTRL); |
| 878 | |
| 879 | return bcm_sf2_vlan_op_wait(priv); |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 880 | } |
| 881 | |
| 882 | static void bcm_sf2_sw_configure_vlan(struct dsa_switch *ds) |
| 883 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 884 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 9c57a77 | 2016-06-09 17:42:08 -0700 | [diff] [blame] | 885 | unsigned int port; |
| 886 | |
| 887 | /* Clear all VLANs */ |
| 888 | bcm_sf2_vlan_op(priv, ARLA_VTBL_CMD_CLEAR); |
| 889 | |
| 890 | for (port = 0; port < priv->hw_params.num_ports; port++) { |
| 891 | if (!((1 << port) & ds->enabled_port_mask)) |
| 892 | continue; |
| 893 | |
| 894 | core_writel(priv, 1, CORE_DEFAULT_1Q_TAG_P(port)); |
| 895 | } |
| 896 | } |
| 897 | |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 898 | static int bcm_sf2_sw_setup(struct dsa_switch *ds) |
| 899 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 900 | struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 901 | unsigned int port; |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 902 | |
| 903 | /* Enable all valid ports and disable those unused */ |
| 904 | for (port = 0; port < priv->hw_params.num_ports; port++) { |
| 905 | /* IMP port receives special treatment */ |
| 906 | if ((1 << port) & ds->enabled_port_mask) |
| 907 | bcm_sf2_port_setup(ds, port, NULL); |
| 908 | else if (dsa_is_cpu_port(ds, port)) |
| 909 | bcm_sf2_imp_setup(ds, port); |
| 910 | else |
| 911 | bcm_sf2_port_disable(ds, port, NULL); |
| 912 | } |
| 913 | |
| 914 | bcm_sf2_sw_configure_vlan(ds); |
| 915 | |
| 916 | return 0; |
| 917 | } |
| 918 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 919 | /* The SWITCH_CORE register space is managed by b53 but operates on a page + |
| 920 | * register basis so we need to translate that into an address that the |
| 921 | * bus-glue understands. |
| 922 | */ |
| 923 | #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2) |
| 924 | |
| 925 | static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg, |
| 926 | u8 *val) |
| 927 | { |
| 928 | struct bcm_sf2_priv *priv = dev->priv; |
| 929 | |
| 930 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); |
| 931 | |
| 932 | return 0; |
| 933 | } |
| 934 | |
| 935 | static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg, |
| 936 | u16 *val) |
| 937 | { |
| 938 | struct bcm_sf2_priv *priv = dev->priv; |
| 939 | |
| 940 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); |
| 941 | |
| 942 | return 0; |
| 943 | } |
| 944 | |
| 945 | static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg, |
| 946 | u32 *val) |
| 947 | { |
| 948 | struct bcm_sf2_priv *priv = dev->priv; |
| 949 | |
| 950 | *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg)); |
| 951 | |
| 952 | return 0; |
| 953 | } |
| 954 | |
| 955 | static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg, |
| 956 | u64 *val) |
| 957 | { |
| 958 | struct bcm_sf2_priv *priv = dev->priv; |
| 959 | |
| 960 | *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg)); |
| 961 | |
| 962 | return 0; |
| 963 | } |
| 964 | |
| 965 | static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg, |
| 966 | u8 value) |
| 967 | { |
| 968 | struct bcm_sf2_priv *priv = dev->priv; |
| 969 | |
| 970 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); |
| 971 | |
| 972 | return 0; |
| 973 | } |
| 974 | |
| 975 | static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg, |
| 976 | u16 value) |
| 977 | { |
| 978 | struct bcm_sf2_priv *priv = dev->priv; |
| 979 | |
| 980 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); |
| 981 | |
| 982 | return 0; |
| 983 | } |
| 984 | |
| 985 | static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg, |
| 986 | u32 value) |
| 987 | { |
| 988 | struct bcm_sf2_priv *priv = dev->priv; |
| 989 | |
| 990 | core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); |
| 991 | |
| 992 | return 0; |
| 993 | } |
| 994 | |
| 995 | static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg, |
| 996 | u64 value) |
| 997 | { |
| 998 | struct bcm_sf2_priv *priv = dev->priv; |
| 999 | |
| 1000 | core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg)); |
| 1001 | |
| 1002 | return 0; |
| 1003 | } |
| 1004 | |
Wei Yongjun | 0e26e5b | 2016-09-15 02:24:13 +0000 | [diff] [blame] | 1005 | static struct b53_io_ops bcm_sf2_io_ops = { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1006 | .read8 = bcm_sf2_core_read8, |
| 1007 | .read16 = bcm_sf2_core_read16, |
| 1008 | .read32 = bcm_sf2_core_read32, |
| 1009 | .read48 = bcm_sf2_core_read64, |
| 1010 | .read64 = bcm_sf2_core_read64, |
| 1011 | .write8 = bcm_sf2_core_write8, |
| 1012 | .write16 = bcm_sf2_core_write16, |
| 1013 | .write32 = bcm_sf2_core_write32, |
| 1014 | .write48 = bcm_sf2_core_write64, |
| 1015 | .write64 = bcm_sf2_core_write64, |
| 1016 | }; |
| 1017 | |
Florian Fainelli | a82f67a | 2017-01-08 14:52:08 -0800 | [diff] [blame] | 1018 | static const struct dsa_switch_ops bcm_sf2_ops = { |
Florian Fainelli | 73095cb | 2017-01-08 14:52:06 -0800 | [diff] [blame] | 1019 | .get_tag_protocol = bcm_sf2_sw_get_tag_protocol, |
| 1020 | .setup = bcm_sf2_sw_setup, |
| 1021 | .get_strings = b53_get_strings, |
| 1022 | .get_ethtool_stats = b53_get_ethtool_stats, |
| 1023 | .get_sset_count = b53_get_sset_count, |
| 1024 | .get_phy_flags = bcm_sf2_sw_get_phy_flags, |
| 1025 | .adjust_link = bcm_sf2_sw_adjust_link, |
| 1026 | .fixed_link_update = bcm_sf2_sw_fixed_link_update, |
| 1027 | .suspend = bcm_sf2_sw_suspend, |
| 1028 | .resume = bcm_sf2_sw_resume, |
| 1029 | .get_wol = bcm_sf2_sw_get_wol, |
| 1030 | .set_wol = bcm_sf2_sw_set_wol, |
| 1031 | .port_enable = bcm_sf2_port_setup, |
| 1032 | .port_disable = bcm_sf2_port_disable, |
| 1033 | .get_eee = bcm_sf2_sw_get_eee, |
| 1034 | .set_eee = bcm_sf2_sw_set_eee, |
| 1035 | .port_bridge_join = b53_br_join, |
| 1036 | .port_bridge_leave = b53_br_leave, |
| 1037 | .port_stp_state_set = b53_br_set_stp_state, |
| 1038 | .port_fast_age = b53_br_fast_age, |
| 1039 | .port_vlan_filtering = b53_vlan_filtering, |
| 1040 | .port_vlan_prepare = b53_vlan_prepare, |
| 1041 | .port_vlan_add = b53_vlan_add, |
| 1042 | .port_vlan_del = b53_vlan_del, |
| 1043 | .port_vlan_dump = b53_vlan_dump, |
| 1044 | .port_fdb_prepare = b53_fdb_prepare, |
| 1045 | .port_fdb_dump = b53_fdb_dump, |
| 1046 | .port_fdb_add = b53_fdb_add, |
| 1047 | .port_fdb_del = b53_fdb_del, |
Florian Fainelli | 7318166 | 2017-01-30 09:48:43 -0800 | [diff] [blame^] | 1048 | .get_rxnfc = bcm_sf2_get_rxnfc, |
| 1049 | .set_rxnfc = bcm_sf2_set_rxnfc, |
Florian Fainelli | 73095cb | 2017-01-08 14:52:06 -0800 | [diff] [blame] | 1050 | }; |
| 1051 | |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1052 | struct bcm_sf2_of_data { |
| 1053 | u32 type; |
| 1054 | const u16 *reg_offsets; |
| 1055 | unsigned int core_reg_align; |
| 1056 | }; |
| 1057 | |
| 1058 | /* Register offsets for the SWITCH_REG_* block */ |
| 1059 | static const u16 bcm_sf2_7445_reg_offsets[] = { |
| 1060 | [REG_SWITCH_CNTRL] = 0x00, |
| 1061 | [REG_SWITCH_STATUS] = 0x04, |
| 1062 | [REG_DIR_DATA_WRITE] = 0x08, |
| 1063 | [REG_DIR_DATA_READ] = 0x0C, |
| 1064 | [REG_SWITCH_REVISION] = 0x18, |
| 1065 | [REG_PHY_REVISION] = 0x1C, |
| 1066 | [REG_SPHY_CNTRL] = 0x2C, |
| 1067 | [REG_RGMII_0_CNTRL] = 0x34, |
| 1068 | [REG_RGMII_1_CNTRL] = 0x40, |
| 1069 | [REG_RGMII_2_CNTRL] = 0x4c, |
| 1070 | [REG_LED_0_CNTRL] = 0x90, |
| 1071 | [REG_LED_1_CNTRL] = 0x94, |
| 1072 | [REG_LED_2_CNTRL] = 0x98, |
| 1073 | }; |
| 1074 | |
| 1075 | static const struct bcm_sf2_of_data bcm_sf2_7445_data = { |
| 1076 | .type = BCM7445_DEVICE_ID, |
| 1077 | .core_reg_align = 0, |
| 1078 | .reg_offsets = bcm_sf2_7445_reg_offsets, |
| 1079 | }; |
| 1080 | |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 1081 | static const u16 bcm_sf2_7278_reg_offsets[] = { |
| 1082 | [REG_SWITCH_CNTRL] = 0x00, |
| 1083 | [REG_SWITCH_STATUS] = 0x04, |
| 1084 | [REG_DIR_DATA_WRITE] = 0x08, |
| 1085 | [REG_DIR_DATA_READ] = 0x0c, |
| 1086 | [REG_SWITCH_REVISION] = 0x10, |
| 1087 | [REG_PHY_REVISION] = 0x14, |
| 1088 | [REG_SPHY_CNTRL] = 0x24, |
| 1089 | [REG_RGMII_0_CNTRL] = 0xe0, |
| 1090 | [REG_RGMII_1_CNTRL] = 0xec, |
| 1091 | [REG_RGMII_2_CNTRL] = 0xf8, |
| 1092 | [REG_LED_0_CNTRL] = 0x40, |
| 1093 | [REG_LED_1_CNTRL] = 0x4c, |
| 1094 | [REG_LED_2_CNTRL] = 0x58, |
| 1095 | }; |
| 1096 | |
| 1097 | static const struct bcm_sf2_of_data bcm_sf2_7278_data = { |
| 1098 | .type = BCM7278_DEVICE_ID, |
| 1099 | .core_reg_align = 1, |
| 1100 | .reg_offsets = bcm_sf2_7278_reg_offsets, |
| 1101 | }; |
| 1102 | |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1103 | static const struct of_device_id bcm_sf2_of_match[] = { |
| 1104 | { .compatible = "brcm,bcm7445-switch-v4.0", |
| 1105 | .data = &bcm_sf2_7445_data |
| 1106 | }, |
Florian Fainelli | 0fe9933 | 2017-01-20 12:36:30 -0800 | [diff] [blame] | 1107 | { .compatible = "brcm,bcm7278-switch-v4.0", |
| 1108 | .data = &bcm_sf2_7278_data |
| 1109 | }, |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1110 | { /* sentinel */ }, |
| 1111 | }; |
| 1112 | MODULE_DEVICE_TABLE(of, bcm_sf2_of_match); |
| 1113 | |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1114 | static int bcm_sf2_sw_probe(struct platform_device *pdev) |
| 1115 | { |
| 1116 | const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME; |
| 1117 | struct device_node *dn = pdev->dev.of_node; |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1118 | const struct of_device_id *of_id = NULL; |
| 1119 | const struct bcm_sf2_of_data *data; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1120 | struct b53_platform_data *pdata; |
Florian Fainelli | a4c61b9 | 2017-01-07 21:01:56 -0800 | [diff] [blame] | 1121 | struct dsa_switch_ops *ops; |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1122 | struct bcm_sf2_priv *priv; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1123 | struct b53_device *dev; |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1124 | struct dsa_switch *ds; |
| 1125 | void __iomem **base; |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1126 | struct resource *r; |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1127 | unsigned int i; |
| 1128 | u32 reg, rev; |
| 1129 | int ret; |
| 1130 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1131 | priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
| 1132 | if (!priv) |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1133 | return -ENOMEM; |
| 1134 | |
Florian Fainelli | a4c61b9 | 2017-01-07 21:01:56 -0800 | [diff] [blame] | 1135 | ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL); |
| 1136 | if (!ops) |
| 1137 | return -ENOMEM; |
| 1138 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1139 | dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv); |
| 1140 | if (!dev) |
| 1141 | return -ENOMEM; |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1142 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1143 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 1144 | if (!pdata) |
| 1145 | return -ENOMEM; |
| 1146 | |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1147 | of_id = of_match_node(bcm_sf2_of_match, dn); |
| 1148 | if (!of_id || !of_id->data) |
| 1149 | return -EINVAL; |
| 1150 | |
| 1151 | data = of_id->data; |
| 1152 | |
| 1153 | /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */ |
| 1154 | priv->type = data->type; |
| 1155 | priv->reg_offsets = data->reg_offsets; |
| 1156 | priv->core_reg_align = data->core_reg_align; |
| 1157 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1158 | /* Auto-detection using standard registers will not work, so |
| 1159 | * provide an indication of what kind of device we are for |
| 1160 | * b53_common to work with |
| 1161 | */ |
Florian Fainelli | a78e86e | 2017-01-20 12:36:29 -0800 | [diff] [blame] | 1162 | pdata->chip_id = priv->type; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1163 | dev->pdata = pdata; |
| 1164 | |
| 1165 | priv->dev = dev; |
| 1166 | ds = dev->ds; |
Florian Fainelli | 73095cb | 2017-01-08 14:52:06 -0800 | [diff] [blame] | 1167 | ds->ops = &bcm_sf2_ops; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1168 | |
| 1169 | dev_set_drvdata(&pdev->dev, priv); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1170 | |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1171 | spin_lock_init(&priv->indir_lock); |
| 1172 | mutex_init(&priv->stats_mutex); |
Florian Fainelli | 7318166 | 2017-01-30 09:48:43 -0800 | [diff] [blame^] | 1173 | mutex_init(&priv->cfp.lock); |
| 1174 | |
| 1175 | /* CFP rule #0 cannot be used for specific classifications, flag it as |
| 1176 | * permanently used |
| 1177 | */ |
| 1178 | set_bit(0, priv->cfp.used); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1179 | |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1180 | bcm_sf2_identify_ports(priv, dn->child); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1181 | |
| 1182 | priv->irq0 = irq_of_parse_and_map(dn, 0); |
| 1183 | priv->irq1 = irq_of_parse_and_map(dn, 1); |
| 1184 | |
| 1185 | base = &priv->core; |
| 1186 | for (i = 0; i < BCM_SF2_REGS_NUM; i++) { |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1187 | r = platform_get_resource(pdev, IORESOURCE_MEM, i); |
| 1188 | *base = devm_ioremap_resource(&pdev->dev, r); |
| 1189 | if (IS_ERR(*base)) { |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1190 | pr_err("unable to find register: %s\n", reg_names[i]); |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1191 | return PTR_ERR(*base); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1192 | } |
| 1193 | base++; |
| 1194 | } |
| 1195 | |
| 1196 | ret = bcm_sf2_sw_rst(priv); |
| 1197 | if (ret) { |
| 1198 | pr_err("unable to software reset switch: %d\n", ret); |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1199 | return ret; |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1200 | } |
| 1201 | |
| 1202 | ret = bcm_sf2_mdio_register(ds); |
| 1203 | if (ret) { |
| 1204 | pr_err("failed to register MDIO bus\n"); |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1205 | return ret; |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1206 | } |
| 1207 | |
Florian Fainelli | 7318166 | 2017-01-30 09:48:43 -0800 | [diff] [blame^] | 1208 | ret = bcm_sf2_cfp_rst(priv); |
| 1209 | if (ret) { |
| 1210 | pr_err("failed to reset CFP\n"); |
| 1211 | goto out_mdio; |
| 1212 | } |
| 1213 | |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1214 | /* Disable all interrupts and request them */ |
| 1215 | bcm_sf2_intr_disable(priv); |
| 1216 | |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1217 | ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0, |
| 1218 | "switch_0", priv); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1219 | if (ret < 0) { |
| 1220 | pr_err("failed to request switch_0 IRQ\n"); |
Florian Fainelli | bb9c0fa | 2016-07-29 12:35:57 -0700 | [diff] [blame] | 1221 | goto out_mdio; |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1222 | } |
| 1223 | |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1224 | ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0, |
| 1225 | "switch_1", priv); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1226 | if (ret < 0) { |
| 1227 | pr_err("failed to request switch_1 IRQ\n"); |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1228 | goto out_mdio; |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1229 | } |
| 1230 | |
| 1231 | /* Reset the MIB counters */ |
| 1232 | reg = core_readl(priv, CORE_GMNCFGCFG); |
| 1233 | reg |= RST_MIB_CNT; |
| 1234 | core_writel(priv, reg, CORE_GMNCFGCFG); |
| 1235 | reg &= ~RST_MIB_CNT; |
| 1236 | core_writel(priv, reg, CORE_GMNCFGCFG); |
| 1237 | |
| 1238 | /* Get the maximum number of ports for this switch */ |
| 1239 | priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1; |
| 1240 | if (priv->hw_params.num_ports > DSA_MAX_PORTS) |
| 1241 | priv->hw_params.num_ports = DSA_MAX_PORTS; |
| 1242 | |
| 1243 | /* Assume a single GPHY setup if we can't read that property */ |
| 1244 | if (of_property_read_u32(dn, "brcm,num-gphy", |
| 1245 | &priv->hw_params.num_gphy)) |
| 1246 | priv->hw_params.num_gphy = 1; |
| 1247 | |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1248 | rev = reg_readl(priv, REG_SWITCH_REVISION); |
| 1249 | priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) & |
| 1250 | SWITCH_TOP_REV_MASK; |
| 1251 | priv->hw_params.core_rev = (rev & SF2_REV_MASK); |
| 1252 | |
| 1253 | rev = reg_readl(priv, REG_PHY_REVISION); |
| 1254 | priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK; |
| 1255 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1256 | ret = b53_switch_register(dev); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1257 | if (ret) |
Florian Fainelli | 4bd1167 | 2016-08-18 15:30:15 -0700 | [diff] [blame] | 1258 | goto out_mdio; |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1259 | |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1260 | pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n", |
| 1261 | priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff, |
| 1262 | priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff, |
| 1263 | priv->core, priv->irq0, priv->irq1); |
| 1264 | |
| 1265 | return 0; |
| 1266 | |
Florian Fainelli | bb9c0fa | 2016-07-29 12:35:57 -0700 | [diff] [blame] | 1267 | out_mdio: |
| 1268 | bcm_sf2_mdio_unregister(priv); |
Florian Fainelli | 7fbb1a9 | 2016-06-09 17:42:06 -0700 | [diff] [blame] | 1269 | return ret; |
| 1270 | } |
| 1271 | |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1272 | static int bcm_sf2_sw_remove(struct platform_device *pdev) |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1273 | { |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1274 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1275 | |
| 1276 | /* Disable all ports and interrupts */ |
| 1277 | priv->wol_ports_mask = 0; |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1278 | bcm_sf2_sw_suspend(priv->dev->ds); |
| 1279 | dsa_unregister_switch(priv->dev->ds); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1280 | bcm_sf2_mdio_unregister(priv); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1281 | |
| 1282 | return 0; |
| 1283 | } |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1284 | |
Florian Fainelli | 2399d61 | 2016-10-20 09:32:19 -0700 | [diff] [blame] | 1285 | static void bcm_sf2_sw_shutdown(struct platform_device *pdev) |
| 1286 | { |
| 1287 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
| 1288 | |
| 1289 | /* For a kernel about to be kexec'd we want to keep the GPHY on for a |
| 1290 | * successful MDIO bus scan to occur. If we did turn off the GPHY |
| 1291 | * before (e.g: port_disable), this will also power it back on. |
Florian Fainelli | 4a2947e | 2016-10-21 14:21:56 -0700 | [diff] [blame] | 1292 | * |
| 1293 | * Do not rely on kexec_in_progress, just power the PHY on. |
Florian Fainelli | 2399d61 | 2016-10-20 09:32:19 -0700 | [diff] [blame] | 1294 | */ |
| 1295 | if (priv->hw_params.num_gphy == 1) |
Florian Fainelli | 4a2947e | 2016-10-21 14:21:56 -0700 | [diff] [blame] | 1296 | bcm_sf2_gphy_enable_set(priv->dev->ds, true); |
Florian Fainelli | 2399d61 | 2016-10-20 09:32:19 -0700 | [diff] [blame] | 1297 | } |
| 1298 | |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1299 | #ifdef CONFIG_PM_SLEEP |
| 1300 | static int bcm_sf2_suspend(struct device *dev) |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1301 | { |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1302 | struct platform_device *pdev = to_platform_device(dev); |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1303 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1304 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1305 | return dsa_switch_suspend(priv->dev->ds); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1306 | } |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1307 | |
| 1308 | static int bcm_sf2_resume(struct device *dev) |
| 1309 | { |
| 1310 | struct platform_device *pdev = to_platform_device(dev); |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1311 | struct bcm_sf2_priv *priv = platform_get_drvdata(pdev); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1312 | |
Florian Fainelli | f458995 | 2016-08-26 12:18:33 -0700 | [diff] [blame] | 1313 | return dsa_switch_resume(priv->dev->ds); |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1314 | } |
| 1315 | #endif /* CONFIG_PM_SLEEP */ |
| 1316 | |
| 1317 | static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops, |
| 1318 | bcm_sf2_suspend, bcm_sf2_resume); |
| 1319 | |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1320 | |
| 1321 | static struct platform_driver bcm_sf2_driver = { |
| 1322 | .probe = bcm_sf2_sw_probe, |
| 1323 | .remove = bcm_sf2_sw_remove, |
Florian Fainelli | 2399d61 | 2016-10-20 09:32:19 -0700 | [diff] [blame] | 1324 | .shutdown = bcm_sf2_sw_shutdown, |
Florian Fainelli | d933802 | 2016-08-18 15:30:14 -0700 | [diff] [blame] | 1325 | .driver = { |
| 1326 | .name = "brcm-sf2", |
| 1327 | .of_match_table = bcm_sf2_of_match, |
| 1328 | .pm = &bcm_sf2_pm_ops, |
| 1329 | }, |
| 1330 | }; |
| 1331 | module_platform_driver(bcm_sf2_driver); |
Florian Fainelli | 246d7f7 | 2014-08-27 17:04:56 -0700 | [diff] [blame] | 1332 | |
| 1333 | MODULE_AUTHOR("Broadcom Corporation"); |
| 1334 | MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip"); |
| 1335 | MODULE_LICENSE("GPL"); |
| 1336 | MODULE_ALIAS("platform:brcm-sf2"); |