Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | * Driver for Solarflare Solarstorm network controllers and boards |
| 3 | * Copyright 2005-2006 Fen Systems Ltd. |
| 4 | * Copyright 2005-2008 Solarflare Communications Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published |
| 8 | * by the Free Software Foundation, incorporated herein by reference. |
| 9 | */ |
| 10 | |
| 11 | /* Common definitions for all Efx net driver code */ |
| 12 | |
| 13 | #ifndef EFX_NET_DRIVER_H |
| 14 | #define EFX_NET_DRIVER_H |
| 15 | |
| 16 | #include <linux/version.h> |
| 17 | #include <linux/netdevice.h> |
| 18 | #include <linux/etherdevice.h> |
| 19 | #include <linux/ethtool.h> |
| 20 | #include <linux/if_vlan.h> |
| 21 | #include <linux/timer.h> |
| 22 | #include <linux/mii.h> |
| 23 | #include <linux/list.h> |
| 24 | #include <linux/pci.h> |
| 25 | #include <linux/device.h> |
| 26 | #include <linux/highmem.h> |
| 27 | #include <linux/workqueue.h> |
| 28 | #include <linux/inet_lro.h> |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 29 | #include <linux/i2c.h> |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 30 | |
| 31 | #include "enum.h" |
| 32 | #include "bitfield.h" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 33 | |
| 34 | #define EFX_MAX_LRO_DESCRIPTORS 8 |
| 35 | #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS |
| 36 | |
| 37 | /************************************************************************** |
| 38 | * |
| 39 | * Build definitions |
| 40 | * |
| 41 | **************************************************************************/ |
| 42 | #ifndef EFX_DRIVER_NAME |
| 43 | #define EFX_DRIVER_NAME "sfc" |
| 44 | #endif |
Ben Hutchings | 8757a5f | 2008-05-16 21:21:06 +0100 | [diff] [blame] | 45 | #define EFX_DRIVER_VERSION "2.2" |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 46 | |
| 47 | #ifdef EFX_ENABLE_DEBUG |
| 48 | #define EFX_BUG_ON_PARANOID(x) BUG_ON(x) |
| 49 | #define EFX_WARN_ON_PARANOID(x) WARN_ON(x) |
| 50 | #else |
| 51 | #define EFX_BUG_ON_PARANOID(x) do {} while (0) |
| 52 | #define EFX_WARN_ON_PARANOID(x) do {} while (0) |
| 53 | #endif |
| 54 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 55 | /* Un-rate-limited logging */ |
| 56 | #define EFX_ERR(efx, fmt, args...) \ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 57 | dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 58 | |
| 59 | #define EFX_INFO(efx, fmt, args...) \ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 60 | dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 61 | |
| 62 | #ifdef EFX_ENABLE_DEBUG |
| 63 | #define EFX_LOG(efx, fmt, args...) \ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 64 | dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 65 | #else |
| 66 | #define EFX_LOG(efx, fmt, args...) \ |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 67 | dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 68 | #endif |
| 69 | |
| 70 | #define EFX_TRACE(efx, fmt, args...) do {} while (0) |
| 71 | |
| 72 | #define EFX_REGDUMP(efx, fmt, args...) do {} while (0) |
| 73 | |
| 74 | /* Rate-limited logging */ |
| 75 | #define EFX_ERR_RL(efx, fmt, args...) \ |
| 76 | do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0) |
| 77 | |
| 78 | #define EFX_INFO_RL(efx, fmt, args...) \ |
| 79 | do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0) |
| 80 | |
| 81 | #define EFX_LOG_RL(efx, fmt, args...) \ |
| 82 | do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0) |
| 83 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 84 | /************************************************************************** |
| 85 | * |
| 86 | * Efx data structures |
| 87 | * |
| 88 | **************************************************************************/ |
| 89 | |
| 90 | #define EFX_MAX_CHANNELS 32 |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 91 | #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS |
| 92 | |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 93 | #define EFX_TX_QUEUE_OFFLOAD_CSUM 0 |
| 94 | #define EFX_TX_QUEUE_NO_CSUM 1 |
| 95 | #define EFX_TX_QUEUE_COUNT 2 |
| 96 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 97 | /** |
| 98 | * struct efx_special_buffer - An Efx special buffer |
| 99 | * @addr: CPU base address of the buffer |
| 100 | * @dma_addr: DMA base address of the buffer |
| 101 | * @len: Buffer length, in bytes |
| 102 | * @index: Buffer index within controller;s buffer table |
| 103 | * @entries: Number of buffer table entries |
| 104 | * |
| 105 | * Special buffers are used for the event queues and the TX and RX |
| 106 | * descriptor queues for each channel. They are *not* used for the |
| 107 | * actual transmit and receive buffers. |
| 108 | * |
| 109 | * Note that for Falcon, TX and RX descriptor queues live in host memory. |
| 110 | * Allocation and freeing procedures must take this into account. |
| 111 | */ |
| 112 | struct efx_special_buffer { |
| 113 | void *addr; |
| 114 | dma_addr_t dma_addr; |
| 115 | unsigned int len; |
| 116 | int index; |
| 117 | int entries; |
| 118 | }; |
| 119 | |
| 120 | /** |
| 121 | * struct efx_tx_buffer - An Efx TX buffer |
| 122 | * @skb: The associated socket buffer. |
| 123 | * Set only on the final fragment of a packet; %NULL for all other |
| 124 | * fragments. When this fragment completes, then we can free this |
| 125 | * skb. |
Ben Hutchings | b9b39b6 | 2008-05-07 12:51:12 +0100 | [diff] [blame] | 126 | * @tsoh: The associated TSO header structure, or %NULL if this |
| 127 | * buffer is not a TSO header. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 128 | * @dma_addr: DMA address of the fragment. |
| 129 | * @len: Length of this fragment. |
| 130 | * This field is zero when the queue slot is empty. |
| 131 | * @continuation: True if this fragment is not the end of a packet. |
| 132 | * @unmap_single: True if pci_unmap_single should be used. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 133 | * @unmap_len: Length of this fragment to unmap |
| 134 | */ |
| 135 | struct efx_tx_buffer { |
| 136 | const struct sk_buff *skb; |
Ben Hutchings | b9b39b6 | 2008-05-07 12:51:12 +0100 | [diff] [blame] | 137 | struct efx_tso_header *tsoh; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 138 | dma_addr_t dma_addr; |
| 139 | unsigned short len; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 140 | bool continuation; |
| 141 | bool unmap_single; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 142 | unsigned short unmap_len; |
| 143 | }; |
| 144 | |
| 145 | /** |
| 146 | * struct efx_tx_queue - An Efx TX queue |
| 147 | * |
| 148 | * This is a ring buffer of TX fragments. |
| 149 | * Since the TX completion path always executes on the same |
| 150 | * CPU and the xmit path can operate on different CPUs, |
| 151 | * performance is increased by ensuring that the completion |
| 152 | * path and the xmit path operate on different cache lines. |
| 153 | * This is particularly important if the xmit path is always |
| 154 | * executing on one CPU which is different from the completion |
| 155 | * path. There is also a cache line for members which are |
| 156 | * read but not written on the fast path. |
| 157 | * |
| 158 | * @efx: The associated Efx NIC |
| 159 | * @queue: DMA queue number |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 160 | * @channel: The associated channel |
| 161 | * @buffer: The software buffer ring |
| 162 | * @txd: The hardware descriptor ring |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 163 | * @flushed: Used when handling queue flushing |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 164 | * @read_count: Current read pointer. |
| 165 | * This is the number of buffers that have been removed from both rings. |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 166 | * @stopped: Stopped count. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 167 | * Set if this TX queue is currently stopping its port. |
| 168 | * @insert_count: Current insert pointer |
| 169 | * This is the number of buffers that have been added to the |
| 170 | * software ring. |
| 171 | * @write_count: Current write pointer |
| 172 | * This is the number of buffers that have been added to the |
| 173 | * hardware ring. |
| 174 | * @old_read_count: The value of read_count when last checked. |
| 175 | * This is here for performance reasons. The xmit path will |
| 176 | * only get the up-to-date value of read_count if this |
| 177 | * variable indicates that the queue is full. This is to |
| 178 | * avoid cache-line ping-pong between the xmit path and the |
| 179 | * completion path. |
Ben Hutchings | b9b39b6 | 2008-05-07 12:51:12 +0100 | [diff] [blame] | 180 | * @tso_headers_free: A list of TSO headers allocated for this TX queue |
| 181 | * that are not in use, and so available for new TSO sends. The list |
| 182 | * is protected by the TX queue lock. |
| 183 | * @tso_bursts: Number of times TSO xmit invoked by kernel |
| 184 | * @tso_long_headers: Number of packets with headers too long for standard |
| 185 | * blocks |
| 186 | * @tso_packets: Number of packets via the TSO xmit path |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 187 | */ |
| 188 | struct efx_tx_queue { |
| 189 | /* Members which don't change on the fast path */ |
| 190 | struct efx_nic *efx ____cacheline_aligned_in_smp; |
| 191 | int queue; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 192 | struct efx_channel *channel; |
| 193 | struct efx_nic *nic; |
| 194 | struct efx_tx_buffer *buffer; |
| 195 | struct efx_special_buffer txd; |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 196 | bool flushed; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 197 | |
| 198 | /* Members used mainly on the completion path */ |
| 199 | unsigned int read_count ____cacheline_aligned_in_smp; |
| 200 | int stopped; |
| 201 | |
| 202 | /* Members used only on the xmit path */ |
| 203 | unsigned int insert_count ____cacheline_aligned_in_smp; |
| 204 | unsigned int write_count; |
| 205 | unsigned int old_read_count; |
Ben Hutchings | b9b39b6 | 2008-05-07 12:51:12 +0100 | [diff] [blame] | 206 | struct efx_tso_header *tso_headers_free; |
| 207 | unsigned int tso_bursts; |
| 208 | unsigned int tso_long_headers; |
| 209 | unsigned int tso_packets; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 210 | }; |
| 211 | |
| 212 | /** |
| 213 | * struct efx_rx_buffer - An Efx RX data buffer |
| 214 | * @dma_addr: DMA base address of the buffer |
| 215 | * @skb: The associated socket buffer, if any. |
| 216 | * If both this and page are %NULL, the buffer slot is currently free. |
| 217 | * @page: The associated page buffer, if any. |
| 218 | * If both this and skb are %NULL, the buffer slot is currently free. |
| 219 | * @data: Pointer to ethernet header |
| 220 | * @len: Buffer length, in bytes. |
| 221 | * @unmap_addr: DMA address to unmap |
| 222 | */ |
| 223 | struct efx_rx_buffer { |
| 224 | dma_addr_t dma_addr; |
| 225 | struct sk_buff *skb; |
| 226 | struct page *page; |
| 227 | char *data; |
| 228 | unsigned int len; |
| 229 | dma_addr_t unmap_addr; |
| 230 | }; |
| 231 | |
| 232 | /** |
| 233 | * struct efx_rx_queue - An Efx RX queue |
| 234 | * @efx: The associated Efx NIC |
| 235 | * @queue: DMA queue number |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 236 | * @channel: The associated channel |
| 237 | * @buffer: The software buffer ring |
| 238 | * @rxd: The hardware descriptor ring |
| 239 | * @added_count: Number of buffers added to the receive queue. |
| 240 | * @notified_count: Number of buffers given to NIC (<= @added_count). |
| 241 | * @removed_count: Number of buffers removed from the receive queue. |
| 242 | * @add_lock: Receive queue descriptor add spin lock. |
| 243 | * This lock must be held in order to add buffers to the RX |
| 244 | * descriptor ring (rxd and buffer) and to update added_count (but |
| 245 | * not removed_count). |
| 246 | * @max_fill: RX descriptor maximum fill level (<= ring size) |
| 247 | * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill |
| 248 | * (<= @max_fill) |
| 249 | * @fast_fill_limit: The level to which a fast fill will fill |
| 250 | * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill) |
| 251 | * @min_fill: RX descriptor minimum non-zero fill level. |
| 252 | * This records the minimum fill level observed when a ring |
| 253 | * refill was triggered. |
| 254 | * @min_overfill: RX descriptor minimum overflow fill level. |
| 255 | * This records the minimum fill level at which RX queue |
| 256 | * overflow was observed. It should never be set. |
| 257 | * @alloc_page_count: RX allocation strategy counter. |
| 258 | * @alloc_skb_count: RX allocation strategy counter. |
| 259 | * @work: Descriptor push work thread |
| 260 | * @buf_page: Page for next RX buffer. |
| 261 | * We can use a single page for multiple RX buffers. This tracks |
| 262 | * the remaining space in the allocation. |
| 263 | * @buf_dma_addr: Page's DMA address. |
| 264 | * @buf_data: Page's host address. |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 265 | * @flushed: Use when handling queue flushing |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 266 | */ |
| 267 | struct efx_rx_queue { |
| 268 | struct efx_nic *efx; |
| 269 | int queue; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 270 | struct efx_channel *channel; |
| 271 | struct efx_rx_buffer *buffer; |
| 272 | struct efx_special_buffer rxd; |
| 273 | |
| 274 | int added_count; |
| 275 | int notified_count; |
| 276 | int removed_count; |
| 277 | spinlock_t add_lock; |
| 278 | unsigned int max_fill; |
| 279 | unsigned int fast_fill_trigger; |
| 280 | unsigned int fast_fill_limit; |
| 281 | unsigned int min_fill; |
| 282 | unsigned int min_overfill; |
| 283 | unsigned int alloc_page_count; |
| 284 | unsigned int alloc_skb_count; |
| 285 | struct delayed_work work; |
| 286 | unsigned int slow_fill_count; |
| 287 | |
| 288 | struct page *buf_page; |
| 289 | dma_addr_t buf_dma_addr; |
| 290 | char *buf_data; |
Ben Hutchings | 6bc5d3a | 2008-09-01 12:49:37 +0100 | [diff] [blame] | 291 | bool flushed; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 292 | }; |
| 293 | |
| 294 | /** |
| 295 | * struct efx_buffer - An Efx general-purpose buffer |
| 296 | * @addr: host base address of the buffer |
| 297 | * @dma_addr: DMA base address of the buffer |
| 298 | * @len: Buffer length, in bytes |
| 299 | * |
| 300 | * Falcon uses these buffers for its interrupt status registers and |
| 301 | * MAC stats dumps. |
| 302 | */ |
| 303 | struct efx_buffer { |
| 304 | void *addr; |
| 305 | dma_addr_t dma_addr; |
| 306 | unsigned int len; |
| 307 | }; |
| 308 | |
| 309 | |
| 310 | /* Flags for channel->used_flags */ |
| 311 | #define EFX_USED_BY_RX 1 |
| 312 | #define EFX_USED_BY_TX 2 |
| 313 | #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX) |
| 314 | |
| 315 | enum efx_rx_alloc_method { |
| 316 | RX_ALLOC_METHOD_AUTO = 0, |
| 317 | RX_ALLOC_METHOD_SKB = 1, |
| 318 | RX_ALLOC_METHOD_PAGE = 2, |
| 319 | }; |
| 320 | |
| 321 | /** |
| 322 | * struct efx_channel - An Efx channel |
| 323 | * |
| 324 | * A channel comprises an event queue, at least one TX queue, at least |
| 325 | * one RX queue, and an associated tasklet for processing the event |
| 326 | * queue. |
| 327 | * |
| 328 | * @efx: Associated Efx NIC |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 329 | * @channel: Channel instance number |
| 330 | * @used_flags: Channel is used by net driver |
| 331 | * @enabled: Channel enabled indicator |
| 332 | * @irq: IRQ number (MSI and MSI-X only) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 333 | * @irq_moderation: IRQ moderation value (in us) |
| 334 | * @napi_dev: Net device used with NAPI |
| 335 | * @napi_str: NAPI control structure |
| 336 | * @reset_work: Scheduled reset work thread |
| 337 | * @work_pending: Is work pending via NAPI? |
| 338 | * @eventq: Event queue buffer |
| 339 | * @eventq_read_ptr: Event queue read pointer |
| 340 | * @last_eventq_read_ptr: Last event queue read pointer value. |
| 341 | * @eventq_magic: Event queue magic value for driver-generated test events |
| 342 | * @lro_mgr: LRO state |
| 343 | * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors |
| 344 | * and diagnostic counters |
| 345 | * @rx_alloc_push_pages: RX allocation method currently in use for pushing |
| 346 | * descriptors |
| 347 | * @rx_alloc_pop_pages: RX allocation method currently in use for popping |
| 348 | * descriptors |
| 349 | * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors |
| 350 | * @n_rx_ip_frag_err: Count of RX IP fragment errors |
| 351 | * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors |
| 352 | * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors |
| 353 | * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors |
| 354 | * @n_rx_overlength: Count of RX_OVERLENGTH errors |
| 355 | * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun |
| 356 | */ |
| 357 | struct efx_channel { |
| 358 | struct efx_nic *efx; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 359 | int channel; |
| 360 | int used_flags; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 361 | bool enabled; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 362 | int irq; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 363 | unsigned int irq_moderation; |
| 364 | struct net_device *napi_dev; |
| 365 | struct napi_struct napi_str; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 366 | bool work_pending; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 367 | struct efx_special_buffer eventq; |
| 368 | unsigned int eventq_read_ptr; |
| 369 | unsigned int last_eventq_read_ptr; |
| 370 | unsigned int eventq_magic; |
| 371 | |
| 372 | struct net_lro_mgr lro_mgr; |
| 373 | int rx_alloc_level; |
| 374 | int rx_alloc_push_pages; |
| 375 | int rx_alloc_pop_pages; |
| 376 | |
| 377 | unsigned n_rx_tobe_disc; |
| 378 | unsigned n_rx_ip_frag_err; |
| 379 | unsigned n_rx_ip_hdr_chksum_err; |
| 380 | unsigned n_rx_tcp_udp_chksum_err; |
| 381 | unsigned n_rx_frm_trunc; |
| 382 | unsigned n_rx_overlength; |
| 383 | unsigned n_skbuff_leaks; |
| 384 | |
| 385 | /* Used to pipeline received packets in order to optimise memory |
| 386 | * access with prefetches. |
| 387 | */ |
| 388 | struct efx_rx_buffer *rx_pkt; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 389 | bool rx_pkt_csummed; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 390 | |
| 391 | }; |
| 392 | |
| 393 | /** |
| 394 | * struct efx_blinker - S/W LED blinking context |
| 395 | * @led_num: LED ID (board-specific meaning) |
| 396 | * @state: Current state - on or off |
| 397 | * @resubmit: Timer resubmission flag |
| 398 | * @timer: Control timer for blinking |
| 399 | */ |
| 400 | struct efx_blinker { |
| 401 | int led_num; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 402 | bool state; |
| 403 | bool resubmit; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 404 | struct timer_list timer; |
| 405 | }; |
| 406 | |
| 407 | |
| 408 | /** |
| 409 | * struct efx_board - board information |
| 410 | * @type: Board model type |
| 411 | * @major: Major rev. ('A', 'B' ...) |
| 412 | * @minor: Minor rev. (0, 1, ...) |
| 413 | * @init: Initialisation function |
| 414 | * @init_leds: Sets up board LEDs |
| 415 | * @set_fault_led: Turns the fault LED on or off |
| 416 | * @blink: Starts/stops blinking |
Ben Hutchings | 3e133c4 | 2008-11-04 20:34:56 +0000 | [diff] [blame] | 417 | * @monitor: Board-specific health check function |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 418 | * @fini: Cleanup function |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 419 | * @blinker: used to blink LEDs in software |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 420 | * @hwmon_client: I2C client for hardware monitor |
| 421 | * @ioexp_client: I2C client for power/port control |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 422 | */ |
| 423 | struct efx_board { |
| 424 | int type; |
| 425 | int major; |
| 426 | int minor; |
| 427 | int (*init) (struct efx_nic *nic); |
| 428 | /* As the LEDs are typically attached to the PHY, LEDs |
| 429 | * have a separate init callback that happens later than |
| 430 | * board init. */ |
| 431 | int (*init_leds)(struct efx_nic *efx); |
Ben Hutchings | 3e133c4 | 2008-11-04 20:34:56 +0000 | [diff] [blame] | 432 | int (*monitor) (struct efx_nic *nic); |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 433 | void (*set_fault_led) (struct efx_nic *efx, bool state); |
| 434 | void (*blink) (struct efx_nic *efx, bool start); |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 435 | void (*fini) (struct efx_nic *nic); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 436 | struct efx_blinker blinker; |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 437 | struct i2c_client *hwmon_client, *ioexp_client; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 438 | }; |
| 439 | |
Ben Hutchings | 3273c2e | 2008-05-07 13:36:19 +0100 | [diff] [blame] | 440 | #define STRING_TABLE_LOOKUP(val, member) \ |
| 441 | member ## _names[val] |
| 442 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 443 | enum efx_int_mode { |
| 444 | /* Be careful if altering to correct macro below */ |
| 445 | EFX_INT_MODE_MSIX = 0, |
| 446 | EFX_INT_MODE_MSI = 1, |
| 447 | EFX_INT_MODE_LEGACY = 2, |
| 448 | EFX_INT_MODE_MAX /* Insert any new items before this */ |
| 449 | }; |
| 450 | #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI) |
| 451 | |
| 452 | enum phy_type { |
| 453 | PHY_TYPE_NONE = 0, |
| 454 | PHY_TYPE_CX4_RTMR = 1, |
| 455 | PHY_TYPE_1G_ALASKA = 2, |
| 456 | PHY_TYPE_10XPRESS = 3, |
| 457 | PHY_TYPE_XFP = 4, |
| 458 | PHY_TYPE_PM8358 = 6, |
| 459 | PHY_TYPE_MAX /* Insert any new items before this */ |
| 460 | }; |
| 461 | |
| 462 | #define PHY_ADDR_INVALID 0xff |
| 463 | |
| 464 | enum nic_state { |
| 465 | STATE_INIT = 0, |
| 466 | STATE_RUNNING = 1, |
| 467 | STATE_FINI = 2, |
Ben Hutchings | 3c78708 | 2008-09-01 12:49:08 +0100 | [diff] [blame] | 468 | STATE_DISABLED = 3, |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 469 | STATE_MAX, |
| 470 | }; |
| 471 | |
| 472 | /* |
| 473 | * Alignment of page-allocated RX buffers |
| 474 | * |
| 475 | * Controls the number of bytes inserted at the start of an RX buffer. |
| 476 | * This is the equivalent of NET_IP_ALIGN [which controls the alignment |
| 477 | * of the skb->head for hardware DMA]. |
| 478 | */ |
Ben Hutchings | 13e9ab1 | 2008-09-01 12:50:28 +0100 | [diff] [blame] | 479 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 480 | #define EFX_PAGE_IP_ALIGN 0 |
| 481 | #else |
| 482 | #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN |
| 483 | #endif |
| 484 | |
| 485 | /* |
| 486 | * Alignment of the skb->head which wraps a page-allocated RX buffer |
| 487 | * |
| 488 | * The skb allocated to wrap an rx_buffer can have this alignment. Since |
| 489 | * the data is memcpy'd from the rx_buf, it does not need to be equal to |
| 490 | * EFX_PAGE_IP_ALIGN. |
| 491 | */ |
| 492 | #define EFX_PAGE_SKB_ALIGN 2 |
| 493 | |
| 494 | /* Forward declaration */ |
| 495 | struct efx_nic; |
| 496 | |
| 497 | /* Pseudo bit-mask flow control field */ |
| 498 | enum efx_fc_type { |
| 499 | EFX_FC_RX = 1, |
| 500 | EFX_FC_TX = 2, |
| 501 | EFX_FC_AUTO = 4, |
| 502 | }; |
| 503 | |
| 504 | /** |
| 505 | * struct efx_phy_operations - Efx PHY operations table |
| 506 | * @init: Initialise PHY |
| 507 | * @fini: Shut down PHY |
| 508 | * @reconfigure: Reconfigure PHY (e.g. for new link parameters) |
| 509 | * @clear_interrupt: Clear down interrupt |
| 510 | * @blink: Blink LEDs |
| 511 | * @check_hw: Check hardware |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 512 | * @mmds: MMD presence mask |
Ben Hutchings | 3273c2e | 2008-05-07 13:36:19 +0100 | [diff] [blame] | 513 | * @loopbacks: Supported loopback modes mask |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 514 | */ |
| 515 | struct efx_phy_operations { |
| 516 | int (*init) (struct efx_nic *efx); |
| 517 | void (*fini) (struct efx_nic *efx); |
| 518 | void (*reconfigure) (struct efx_nic *efx); |
| 519 | void (*clear_interrupt) (struct efx_nic *efx); |
| 520 | int (*check_hw) (struct efx_nic *efx); |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 521 | int (*test) (struct efx_nic *efx); |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 522 | int mmds; |
Ben Hutchings | 3273c2e | 2008-05-07 13:36:19 +0100 | [diff] [blame] | 523 | unsigned loopbacks; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 524 | }; |
| 525 | |
Ben Hutchings | f8b87c1 | 2008-09-01 12:48:17 +0100 | [diff] [blame] | 526 | /** |
| 527 | * @enum efx_phy_mode - PHY operating mode flags |
| 528 | * @PHY_MODE_NORMAL: on and should pass traffic |
| 529 | * @PHY_MODE_TX_DISABLED: on with TX disabled |
Ben Hutchings | 3e133c4 | 2008-11-04 20:34:56 +0000 | [diff] [blame] | 530 | * @PHY_MODE_LOW_POWER: set to low power through MDIO |
| 531 | * @PHY_MODE_OFF: switched off through external control |
Ben Hutchings | f8b87c1 | 2008-09-01 12:48:17 +0100 | [diff] [blame] | 532 | * @PHY_MODE_SPECIAL: on but will not pass traffic |
| 533 | */ |
| 534 | enum efx_phy_mode { |
| 535 | PHY_MODE_NORMAL = 0, |
| 536 | PHY_MODE_TX_DISABLED = 1, |
Ben Hutchings | 3e133c4 | 2008-11-04 20:34:56 +0000 | [diff] [blame] | 537 | PHY_MODE_LOW_POWER = 2, |
| 538 | PHY_MODE_OFF = 4, |
Ben Hutchings | f8b87c1 | 2008-09-01 12:48:17 +0100 | [diff] [blame] | 539 | PHY_MODE_SPECIAL = 8, |
| 540 | }; |
| 541 | |
| 542 | static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode) |
| 543 | { |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 544 | return !!(mode & ~PHY_MODE_TX_DISABLED); |
Ben Hutchings | f8b87c1 | 2008-09-01 12:48:17 +0100 | [diff] [blame] | 545 | } |
| 546 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 547 | /* |
| 548 | * Efx extended statistics |
| 549 | * |
| 550 | * Not all statistics are provided by all supported MACs. The purpose |
| 551 | * is this structure is to contain the raw statistics provided by each |
| 552 | * MAC. |
| 553 | */ |
| 554 | struct efx_mac_stats { |
| 555 | u64 tx_bytes; |
| 556 | u64 tx_good_bytes; |
| 557 | u64 tx_bad_bytes; |
| 558 | unsigned long tx_packets; |
| 559 | unsigned long tx_bad; |
| 560 | unsigned long tx_pause; |
| 561 | unsigned long tx_control; |
| 562 | unsigned long tx_unicast; |
| 563 | unsigned long tx_multicast; |
| 564 | unsigned long tx_broadcast; |
| 565 | unsigned long tx_lt64; |
| 566 | unsigned long tx_64; |
| 567 | unsigned long tx_65_to_127; |
| 568 | unsigned long tx_128_to_255; |
| 569 | unsigned long tx_256_to_511; |
| 570 | unsigned long tx_512_to_1023; |
| 571 | unsigned long tx_1024_to_15xx; |
| 572 | unsigned long tx_15xx_to_jumbo; |
| 573 | unsigned long tx_gtjumbo; |
| 574 | unsigned long tx_collision; |
| 575 | unsigned long tx_single_collision; |
| 576 | unsigned long tx_multiple_collision; |
| 577 | unsigned long tx_excessive_collision; |
| 578 | unsigned long tx_deferred; |
| 579 | unsigned long tx_late_collision; |
| 580 | unsigned long tx_excessive_deferred; |
| 581 | unsigned long tx_non_tcpudp; |
| 582 | unsigned long tx_mac_src_error; |
| 583 | unsigned long tx_ip_src_error; |
| 584 | u64 rx_bytes; |
| 585 | u64 rx_good_bytes; |
| 586 | u64 rx_bad_bytes; |
| 587 | unsigned long rx_packets; |
| 588 | unsigned long rx_good; |
| 589 | unsigned long rx_bad; |
| 590 | unsigned long rx_pause; |
| 591 | unsigned long rx_control; |
| 592 | unsigned long rx_unicast; |
| 593 | unsigned long rx_multicast; |
| 594 | unsigned long rx_broadcast; |
| 595 | unsigned long rx_lt64; |
| 596 | unsigned long rx_64; |
| 597 | unsigned long rx_65_to_127; |
| 598 | unsigned long rx_128_to_255; |
| 599 | unsigned long rx_256_to_511; |
| 600 | unsigned long rx_512_to_1023; |
| 601 | unsigned long rx_1024_to_15xx; |
| 602 | unsigned long rx_15xx_to_jumbo; |
| 603 | unsigned long rx_gtjumbo; |
| 604 | unsigned long rx_bad_lt64; |
| 605 | unsigned long rx_bad_64_to_15xx; |
| 606 | unsigned long rx_bad_15xx_to_jumbo; |
| 607 | unsigned long rx_bad_gtjumbo; |
| 608 | unsigned long rx_overflow; |
| 609 | unsigned long rx_missed; |
| 610 | unsigned long rx_false_carrier; |
| 611 | unsigned long rx_symbol_error; |
| 612 | unsigned long rx_align_error; |
| 613 | unsigned long rx_length_error; |
| 614 | unsigned long rx_internal_error; |
| 615 | unsigned long rx_good_lt64; |
| 616 | }; |
| 617 | |
| 618 | /* Number of bits used in a multicast filter hash address */ |
| 619 | #define EFX_MCAST_HASH_BITS 8 |
| 620 | |
| 621 | /* Number of (single-bit) entries in a multicast filter hash */ |
| 622 | #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS) |
| 623 | |
| 624 | /* An Efx multicast filter hash */ |
| 625 | union efx_multicast_hash { |
| 626 | u8 byte[EFX_MCAST_HASH_ENTRIES / 8]; |
| 627 | efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8]; |
| 628 | }; |
| 629 | |
| 630 | /** |
| 631 | * struct efx_nic - an Efx NIC |
| 632 | * @name: Device name (net device name or bus id before net device registered) |
| 633 | * @pci_dev: The PCI device |
| 634 | * @type: Controller type attributes |
| 635 | * @legacy_irq: IRQ number |
Ben Hutchings | 8d9853d | 2008-07-18 19:01:20 +0100 | [diff] [blame] | 636 | * @workqueue: Workqueue for port reconfigures and the HW monitor. |
| 637 | * Work items do not hold and must not acquire RTNL. |
| 638 | * @reset_workqueue: Workqueue for resets. Work item will acquire RTNL. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 639 | * @reset_work: Scheduled reset workitem |
| 640 | * @monitor_work: Hardware monitor workitem |
| 641 | * @membase_phys: Memory BAR value as physical address |
| 642 | * @membase: Memory BAR value |
| 643 | * @biu_lock: BIU (bus interface unit) lock |
| 644 | * @interrupt_mode: Interrupt mode |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 645 | * @i2c_adap: I2C adapter |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 646 | * @board_info: Board-level information |
| 647 | * @state: Device state flag. Serialised by the rtnl_lock. |
| 648 | * @reset_pending: Pending reset method (normally RESET_TYPE_NONE) |
| 649 | * @tx_queue: TX DMA queues |
| 650 | * @rx_queue: RX DMA queues |
| 651 | * @channel: Channels |
Ben Hutchings | 8831da7 | 2008-09-01 12:47:48 +0100 | [diff] [blame] | 652 | * @n_rx_queues: Number of RX queues |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 653 | * @rx_buffer_len: RX buffer length |
| 654 | * @rx_buffer_order: Order (log2) of number of pages for each RX buffer |
| 655 | * @irq_status: Interrupt status buffer |
| 656 | * @last_irq_cpu: Last CPU to handle interrupt. |
| 657 | * This register is written with the SMP processor ID whenever an |
| 658 | * interrupt is handled. It is used by falcon_test_interrupt() |
| 659 | * to verify that an interrupt has occurred. |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 660 | * @spi_flash: SPI flash device |
| 661 | * This field will be %NULL if no flash device is present. |
| 662 | * @spi_eeprom: SPI EEPROM device |
| 663 | * This field will be %NULL if no EEPROM device is present. |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 664 | * @spi_lock: SPI bus lock |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 665 | * @n_rx_nodesc_drop_cnt: RX no descriptor drop count |
| 666 | * @nic_data: Hardware dependant state |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 667 | * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode, |
| 668 | * @port_inhibited, efx_monitor() and efx_reconfigure_port() |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 669 | * @port_enabled: Port enabled indicator. |
| 670 | * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and |
| 671 | * efx_reconfigure_work with kernel interfaces. Safe to read under any |
| 672 | * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must |
| 673 | * be held to modify it. |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 674 | * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 675 | * @port_initialized: Port initialized? |
| 676 | * @net_dev: Operating system network device. Consider holding the rtnl lock |
| 677 | * @rx_checksum_enabled: RX checksumming enabled |
| 678 | * @netif_stop_count: Port stop count |
| 679 | * @netif_stop_lock: Port stop lock |
| 680 | * @mac_stats: MAC statistics. These include all statistics the MACs |
| 681 | * can provide. Generic code converts these into a standard |
| 682 | * &struct net_device_stats. |
| 683 | * @stats_buffer: DMA buffer for statistics |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 684 | * @stats_lock: Statistics update lock. Serialises statistics fetches |
| 685 | * @stats_enabled: Temporarily disable statistics fetches. |
| 686 | * Serialised by @stats_lock |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 687 | * @mac_address: Permanent MAC address |
| 688 | * @phy_type: PHY type |
| 689 | * @phy_lock: PHY access lock |
| 690 | * @phy_op: PHY interface |
| 691 | * @phy_data: PHY private data (including PHY-specific stats) |
| 692 | * @mii: PHY interface |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 693 | * @phy_mode: PHY operating mode. Serialised by @mac_lock. |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 694 | * @link_up: Link status |
| 695 | * @link_options: Link options (MII/GMII format) |
| 696 | * @n_link_state_changes: Number of times the link has changed state |
| 697 | * @promiscuous: Promiscuous flag. Protected by netif_tx_lock. |
| 698 | * @multicast_hash: Multicast hash table |
| 699 | * @flow_control: Flow control flags - separate RX/TX so can't use link_options |
| 700 | * @reconfigure_work: work item for dealing with PHY events |
Ben Hutchings | 3273c2e | 2008-05-07 13:36:19 +0100 | [diff] [blame] | 701 | * @loopback_mode: Loopback status |
| 702 | * @loopback_modes: Supported loopback mode bitmask |
| 703 | * @loopback_selftest: Offline self-test private state |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 704 | * |
| 705 | * The @priv field of the corresponding &struct net_device points to |
| 706 | * this. |
| 707 | */ |
| 708 | struct efx_nic { |
| 709 | char name[IFNAMSIZ]; |
| 710 | struct pci_dev *pci_dev; |
| 711 | const struct efx_nic_type *type; |
| 712 | int legacy_irq; |
| 713 | struct workqueue_struct *workqueue; |
Ben Hutchings | 8d9853d | 2008-07-18 19:01:20 +0100 | [diff] [blame] | 714 | struct workqueue_struct *reset_workqueue; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 715 | struct work_struct reset_work; |
| 716 | struct delayed_work monitor_work; |
Ben Hutchings | 086ea35 | 2008-05-16 21:17:06 +0100 | [diff] [blame] | 717 | resource_size_t membase_phys; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 718 | void __iomem *membase; |
| 719 | spinlock_t biu_lock; |
| 720 | enum efx_int_mode interrupt_mode; |
| 721 | |
Ben Hutchings | 37b5a60 | 2008-05-30 22:27:04 +0100 | [diff] [blame] | 722 | struct i2c_adapter i2c_adap; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 723 | struct efx_board board_info; |
| 724 | |
| 725 | enum nic_state state; |
| 726 | enum reset_type reset_pending; |
| 727 | |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 728 | struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT]; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 729 | struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES]; |
| 730 | struct efx_channel channel[EFX_MAX_CHANNELS]; |
| 731 | |
Ben Hutchings | 8831da7 | 2008-09-01 12:47:48 +0100 | [diff] [blame] | 732 | int n_rx_queues; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 733 | unsigned int rx_buffer_len; |
| 734 | unsigned int rx_buffer_order; |
| 735 | |
| 736 | struct efx_buffer irq_status; |
| 737 | volatile signed int last_irq_cpu; |
| 738 | |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 739 | struct efx_spi_device *spi_flash; |
| 740 | struct efx_spi_device *spi_eeprom; |
Ben Hutchings | f415072 | 2008-11-04 20:34:28 +0000 | [diff] [blame] | 741 | struct mutex spi_lock; |
Ben Hutchings | 4a5b504 | 2008-09-01 12:47:16 +0100 | [diff] [blame] | 742 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 743 | unsigned n_rx_nodesc_drop_cnt; |
| 744 | |
Ben Hutchings | 5daab96 | 2008-05-16 21:19:43 +0100 | [diff] [blame] | 745 | struct falcon_nic_data *nic_data; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 746 | |
| 747 | struct mutex mac_lock; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 748 | bool port_enabled; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 749 | bool port_inhibited; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 750 | |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 751 | bool port_initialized; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 752 | struct net_device *net_dev; |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 753 | bool rx_checksum_enabled; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 754 | |
| 755 | atomic_t netif_stop_count; |
| 756 | spinlock_t netif_stop_lock; |
| 757 | |
| 758 | struct efx_mac_stats mac_stats; |
| 759 | struct efx_buffer stats_buffer; |
| 760 | spinlock_t stats_lock; |
Ben Hutchings | 8c8661e | 2008-09-01 12:49:02 +0100 | [diff] [blame] | 761 | bool stats_enabled; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 762 | |
| 763 | unsigned char mac_address[ETH_ALEN]; |
| 764 | |
| 765 | enum phy_type phy_type; |
| 766 | spinlock_t phy_lock; |
| 767 | struct efx_phy_operations *phy_op; |
| 768 | void *phy_data; |
| 769 | struct mii_if_info mii; |
Ben Hutchings | f8b87c1 | 2008-09-01 12:48:17 +0100 | [diff] [blame] | 770 | enum efx_phy_mode phy_mode; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 771 | |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 772 | bool link_up; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 773 | unsigned int link_options; |
| 774 | unsigned int n_link_state_changes; |
| 775 | |
Ben Hutchings | dc8cfa5 | 2008-09-01 12:46:50 +0100 | [diff] [blame] | 776 | bool promiscuous; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 777 | union efx_multicast_hash multicast_hash; |
| 778 | enum efx_fc_type flow_control; |
| 779 | struct work_struct reconfigure_work; |
| 780 | |
| 781 | atomic_t rx_reset; |
Ben Hutchings | 3273c2e | 2008-05-07 13:36:19 +0100 | [diff] [blame] | 782 | enum efx_loopback_mode loopback_mode; |
| 783 | unsigned int loopback_modes; |
| 784 | |
| 785 | void *loopback_selftest; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 786 | }; |
| 787 | |
Ben Hutchings | 5566861 | 2008-05-16 21:16:10 +0100 | [diff] [blame] | 788 | static inline int efx_dev_registered(struct efx_nic *efx) |
| 789 | { |
| 790 | return efx->net_dev->reg_state == NETREG_REGISTERED; |
| 791 | } |
| 792 | |
| 793 | /* Net device name, for inclusion in log messages if it has been registered. |
| 794 | * Use efx->name not efx->net_dev->name so that races with (un)registration |
| 795 | * are harmless. |
| 796 | */ |
| 797 | static inline const char *efx_dev_name(struct efx_nic *efx) |
| 798 | { |
| 799 | return efx_dev_registered(efx) ? efx->name : ""; |
| 800 | } |
| 801 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 802 | /** |
| 803 | * struct efx_nic_type - Efx device type definition |
| 804 | * @mem_bar: Memory BAR number |
| 805 | * @mem_map_size: Memory BAR mapped size |
| 806 | * @txd_ptr_tbl_base: TX descriptor ring base address |
| 807 | * @rxd_ptr_tbl_base: RX descriptor ring base address |
| 808 | * @buf_tbl_base: Buffer table base address |
| 809 | * @evq_ptr_tbl_base: Event queue pointer table base address |
| 810 | * @evq_rptr_tbl_base: Event queue read-pointer table base address |
| 811 | * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1) |
| 812 | * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1) |
| 813 | * @evq_size: Event queue size (must be a power of two) |
| 814 | * @max_dma_mask: Maximum possible DMA mask |
| 815 | * @tx_dma_mask: TX DMA mask |
| 816 | * @bug5391_mask: Address mask for bug 5391 workaround |
| 817 | * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes) |
| 818 | * @rx_xon_thresh: RX FIFO XON watermark (bytes) |
| 819 | * @rx_buffer_padding: Padding added to each RX buffer |
| 820 | * @max_interrupt_mode: Highest capability interrupt mode supported |
| 821 | * from &enum efx_init_mode. |
| 822 | * @phys_addr_channels: Number of channels with physically addressed |
| 823 | * descriptors |
| 824 | */ |
| 825 | struct efx_nic_type { |
| 826 | unsigned int mem_bar; |
| 827 | unsigned int mem_map_size; |
| 828 | unsigned int txd_ptr_tbl_base; |
| 829 | unsigned int rxd_ptr_tbl_base; |
| 830 | unsigned int buf_tbl_base; |
| 831 | unsigned int evq_ptr_tbl_base; |
| 832 | unsigned int evq_rptr_tbl_base; |
| 833 | |
| 834 | unsigned int txd_ring_mask; |
| 835 | unsigned int rxd_ring_mask; |
| 836 | unsigned int evq_size; |
Ben Hutchings | 9bbd7d9 | 2008-05-16 21:18:48 +0100 | [diff] [blame] | 837 | u64 max_dma_mask; |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 838 | unsigned int tx_dma_mask; |
| 839 | unsigned bug5391_mask; |
| 840 | |
| 841 | int rx_xoff_thresh; |
| 842 | int rx_xon_thresh; |
| 843 | unsigned int rx_buffer_padding; |
| 844 | unsigned int max_interrupt_mode; |
| 845 | unsigned int phys_addr_channels; |
| 846 | }; |
| 847 | |
| 848 | /************************************************************************** |
| 849 | * |
| 850 | * Prototypes and inline functions |
| 851 | * |
| 852 | *************************************************************************/ |
| 853 | |
| 854 | /* Iterate over all used channels */ |
| 855 | #define efx_for_each_channel(_channel, _efx) \ |
| 856 | for (_channel = &_efx->channel[0]; \ |
| 857 | _channel < &_efx->channel[EFX_MAX_CHANNELS]; \ |
| 858 | _channel++) \ |
| 859 | if (!_channel->used_flags) \ |
| 860 | continue; \ |
| 861 | else |
| 862 | |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 863 | /* Iterate over all used TX queues */ |
| 864 | #define efx_for_each_tx_queue(_tx_queue, _efx) \ |
| 865 | for (_tx_queue = &_efx->tx_queue[0]; \ |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 866 | _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \ |
| 867 | _tx_queue++) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 868 | |
| 869 | /* Iterate over all TX queues belonging to a channel */ |
| 870 | #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \ |
| 871 | for (_tx_queue = &_channel->efx->tx_queue[0]; \ |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 872 | _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 873 | _tx_queue++) \ |
Ben Hutchings | 60ac106 | 2008-09-01 12:44:59 +0100 | [diff] [blame] | 874 | if (_tx_queue->channel != _channel) \ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 875 | continue; \ |
| 876 | else |
| 877 | |
| 878 | /* Iterate over all used RX queues */ |
| 879 | #define efx_for_each_rx_queue(_rx_queue, _efx) \ |
| 880 | for (_rx_queue = &_efx->rx_queue[0]; \ |
Ben Hutchings | 8831da7 | 2008-09-01 12:47:48 +0100 | [diff] [blame] | 881 | _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \ |
| 882 | _rx_queue++) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 883 | |
| 884 | /* Iterate over all RX queues belonging to a channel */ |
| 885 | #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \ |
Ben Hutchings | a258902 | 2008-09-01 12:47:57 +0100 | [diff] [blame] | 886 | for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \ |
| 887 | _rx_queue; \ |
| 888 | _rx_queue = NULL) \ |
Ben Hutchings | 8831da7 | 2008-09-01 12:47:48 +0100 | [diff] [blame] | 889 | if (_rx_queue->channel != _channel) \ |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 890 | continue; \ |
| 891 | else |
| 892 | |
| 893 | /* Returns a pointer to the specified receive buffer in the RX |
| 894 | * descriptor queue. |
| 895 | */ |
| 896 | static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue, |
| 897 | unsigned int index) |
| 898 | { |
| 899 | return (&rx_queue->buffer[index]); |
| 900 | } |
| 901 | |
| 902 | /* Set bit in a little-endian bitfield */ |
Ben Hutchings | 18c2fc0 | 2008-09-01 12:43:39 +0100 | [diff] [blame] | 903 | static inline void set_bit_le(unsigned nr, unsigned char *addr) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 904 | { |
| 905 | addr[nr / 8] |= (1 << (nr % 8)); |
| 906 | } |
| 907 | |
| 908 | /* Clear bit in a little-endian bitfield */ |
Ben Hutchings | 18c2fc0 | 2008-09-01 12:43:39 +0100 | [diff] [blame] | 909 | static inline void clear_bit_le(unsigned nr, unsigned char *addr) |
Ben Hutchings | 8ceee66 | 2008-04-27 12:55:59 +0100 | [diff] [blame] | 910 | { |
| 911 | addr[nr / 8] &= ~(1 << (nr % 8)); |
| 912 | } |
| 913 | |
| 914 | |
| 915 | /** |
| 916 | * EFX_MAX_FRAME_LEN - calculate maximum frame length |
| 917 | * |
| 918 | * This calculates the maximum frame length that will be used for a |
| 919 | * given MTU. The frame length will be equal to the MTU plus a |
| 920 | * constant amount of header space and padding. This is the quantity |
| 921 | * that the net driver will program into the MAC as the maximum frame |
| 922 | * length. |
| 923 | * |
| 924 | * The 10G MAC used in Falcon requires 8-byte alignment on the frame |
| 925 | * length, so we round up to the nearest 8. |
| 926 | */ |
| 927 | #define EFX_MAX_FRAME_LEN(mtu) \ |
| 928 | ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7) |
| 929 | |
| 930 | |
| 931 | #endif /* EFX_NET_DRIVER_H */ |