Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 2 | * arch/powerpc/sysdev/dart_iommu.c |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 3 | * |
Olof Johansson | 91f1448 | 2005-11-21 02:12:32 -0600 | [diff] [blame] | 4 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 5 | * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>, |
| 6 | * IBM Corporation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * Based on pSeries_iommu.c: |
| 9 | * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation |
Olof Johansson | 91f1448 | 2005-11-21 02:12:32 -0600 | [diff] [blame] | 10 | * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 11 | * |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 12 | * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 13 | * |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 14 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 15 | * This program is free software; you can redistribute it and/or modify |
| 16 | * it under the terms of the GNU General Public License as published by |
| 17 | * the Free Software Foundation; either version 2 of the License, or |
| 18 | * (at your option) any later version. |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 19 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 24 | * |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 28 | */ |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | #include <linux/init.h> |
| 31 | #include <linux/types.h> |
| 32 | #include <linux/slab.h> |
| 33 | #include <linux/mm.h> |
| 34 | #include <linux/spinlock.h> |
| 35 | #include <linux/string.h> |
| 36 | #include <linux/pci.h> |
| 37 | #include <linux/dma-mapping.h> |
| 38 | #include <linux/vmalloc.h> |
Johannes Berg | 7e11580 | 2007-05-03 22:28:32 +1000 | [diff] [blame] | 39 | #include <linux/suspend.h> |
David S. Miller | d9b2b2a | 2008-02-13 16:56:49 -0800 | [diff] [blame] | 40 | #include <linux/lmb.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 41 | #include <asm/io.h> |
| 42 | #include <asm/prom.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | #include <asm/iommu.h> |
| 44 | #include <asm/pci-bridge.h> |
| 45 | #include <asm/machdep.h> |
| 46 | #include <asm/abs_addr.h> |
| 47 | #include <asm/cacheflush.h> |
Stephen Rothwell | d387899 | 2005-09-28 02:50:25 +1000 | [diff] [blame] | 48 | #include <asm/ppc-pci.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 49 | |
David Gibson | 9933f29 | 2005-11-02 15:13:20 +1100 | [diff] [blame] | 50 | #include "dart.h" |
| 51 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | /* Physical base address and size of the DART table */ |
| 53 | unsigned long dart_tablebase; /* exported to htab_initialize */ |
| 54 | static unsigned long dart_tablesize; |
| 55 | |
| 56 | /* Virtual base address of the DART table */ |
| 57 | static u32 *dart_vbase; |
Johannes Berg | 7e11580 | 2007-05-03 22:28:32 +1000 | [diff] [blame] | 58 | #ifdef CONFIG_PM |
| 59 | static u32 *dart_copy; |
| 60 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 61 | |
| 62 | /* Mapped base address for the dart */ |
Al Viro | 6fa2ffe | 2006-02-01 07:28:02 -0500 | [diff] [blame] | 63 | static unsigned int __iomem *dart; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 64 | |
| 65 | /* Dummy val that entries are set to when unused */ |
| 66 | static unsigned int dart_emptyval; |
| 67 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 68 | static struct iommu_table iommu_table_dart; |
| 69 | static int iommu_table_dart_inited; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 70 | static int dart_dirty; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 71 | static int dart_is_u4; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 72 | |
| 73 | #define DBG(...) |
| 74 | |
| 75 | static inline void dart_tlb_invalidate_all(void) |
| 76 | { |
| 77 | unsigned long l = 0; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 78 | unsigned int reg, inv_bit; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 79 | unsigned long limit; |
| 80 | |
| 81 | DBG("dart: flush\n"); |
| 82 | |
| 83 | /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the |
| 84 | * control register and wait for it to clear. |
| 85 | * |
| 86 | * Gotcha: Sometimes, the DART won't detect that the bit gets |
| 87 | * set. If so, clear it and set it again. |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 88 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | |
| 90 | limit = 0; |
| 91 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 92 | inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 93 | retry: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 94 | l = 0; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 95 | reg = DART_IN(DART_CNTL); |
| 96 | reg |= inv_bit; |
| 97 | DART_OUT(DART_CNTL, reg); |
| 98 | |
| 99 | while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | l++; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 101 | if (l == (1L << limit)) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 102 | if (limit < 4) { |
| 103 | limit++; |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 104 | reg = DART_IN(DART_CNTL); |
| 105 | reg &= ~inv_bit; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 106 | DART_OUT(DART_CNTL, reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 107 | goto retry; |
| 108 | } else |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 109 | panic("DART: TLB did not flush after waiting a long " |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 110 | "time. Buggy U3 ?"); |
| 111 | } |
| 112 | } |
| 113 | |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 114 | static inline void dart_tlb_invalidate_one(unsigned long bus_rpn) |
| 115 | { |
| 116 | unsigned int reg; |
| 117 | unsigned int l, limit; |
| 118 | |
| 119 | reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE | |
| 120 | (bus_rpn & DART_CNTL_U4_IONE_MASK); |
| 121 | DART_OUT(DART_CNTL, reg); |
| 122 | |
| 123 | limit = 0; |
| 124 | wait_more: |
| 125 | l = 0; |
| 126 | while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) { |
| 127 | rmb(); |
| 128 | l++; |
| 129 | } |
| 130 | |
| 131 | if (l == (1L << limit)) { |
| 132 | if (limit < 4) { |
| 133 | limit++; |
| 134 | goto wait_more; |
| 135 | } else |
| 136 | panic("DART: TLB did not flush after waiting a long " |
| 137 | "time. Buggy U4 ?"); |
| 138 | } |
| 139 | } |
| 140 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 141 | static void dart_flush(struct iommu_table *tbl) |
| 142 | { |
Benjamin Herrenschmidt | eeac5c1 | 2006-09-13 22:12:52 +1000 | [diff] [blame] | 143 | mb(); |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 144 | if (dart_dirty) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 145 | dart_tlb_invalidate_all(); |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 146 | dart_dirty = 0; |
| 147 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 148 | } |
| 149 | |
Robert Jennings | 6490c49 | 2008-07-24 04:31:16 +1000 | [diff] [blame] | 150 | static int dart_build(struct iommu_table *tbl, long index, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 151 | long npages, unsigned long uaddr, |
Mark Nelson | 4f3dd8a | 2008-07-16 05:51:47 +1000 | [diff] [blame] | 152 | enum dma_data_direction direction, |
| 153 | struct dma_attrs *attrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | { |
| 155 | unsigned int *dp; |
| 156 | unsigned int rpn; |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 157 | long l; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 158 | |
| 159 | DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr); |
| 160 | |
| 161 | dp = ((unsigned int*)tbl->it_base) + index; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 162 | |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 163 | /* On U3, all memory is contiguous, so we can move this |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 164 | * out of the loop. |
| 165 | */ |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 166 | l = npages; |
| 167 | while (l--) { |
Olof Johansson | d0035c62 | 2005-09-20 13:46:44 +1000 | [diff] [blame] | 168 | rpn = virt_to_abs(uaddr) >> DART_PAGE_SHIFT; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | |
| 170 | *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK); |
| 171 | |
Olof Johansson | d0035c62 | 2005-09-20 13:46:44 +1000 | [diff] [blame] | 172 | uaddr += DART_PAGE_SIZE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 173 | } |
| 174 | |
Benjamin Herrenschmidt | eeac5c1 | 2006-09-13 22:12:52 +1000 | [diff] [blame] | 175 | /* make sure all updates have reached memory */ |
| 176 | mb(); |
| 177 | in_be32((unsigned __iomem *)dp); |
| 178 | mb(); |
| 179 | |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 180 | if (dart_is_u4) { |
| 181 | rpn = index; |
Olof Johansson | feb76c7 | 2006-06-28 02:50:36 -0700 | [diff] [blame] | 182 | while (npages--) |
| 183 | dart_tlb_invalidate_one(rpn++); |
| 184 | } else { |
| 185 | dart_dirty = 1; |
| 186 | } |
Robert Jennings | 6490c49 | 2008-07-24 04:31:16 +1000 | [diff] [blame] | 187 | return 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | |
| 191 | static void dart_free(struct iommu_table *tbl, long index, long npages) |
| 192 | { |
| 193 | unsigned int *dp; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 194 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 195 | /* We don't worry about flushing the TLB cache. The only drawback of |
| 196 | * not doing it is that we won't catch buggy device drivers doing |
| 197 | * bad DMAs, but then no 32-bit architecture ever does either. |
| 198 | */ |
| 199 | |
| 200 | DBG("dart: free at: %lx, %lx\n", index, npages); |
| 201 | |
| 202 | dp = ((unsigned int *)tbl->it_base) + index; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 203 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 204 | while (npages--) |
| 205 | *(dp++) = dart_emptyval; |
| 206 | } |
| 207 | |
| 208 | |
Stephen Rothwell | 109b60f | 2007-08-15 20:54:32 +1000 | [diff] [blame] | 209 | static int __init dart_init(struct device_node *dart_node) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 210 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 211 | unsigned int i; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 212 | unsigned long tmp, base, size; |
| 213 | struct resource r; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 214 | |
| 215 | if (dart_tablebase == 0 || dart_tablesize == 0) { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 216 | printk(KERN_INFO "DART: table not allocated, using " |
| 217 | "direct DMA\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 218 | return -ENODEV; |
| 219 | } |
| 220 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 221 | if (of_address_to_resource(dart_node, 0, &r)) |
| 222 | panic("DART: can't get register base ! "); |
| 223 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 224 | /* Make sure nothing from the DART range remains in the CPU cache |
| 225 | * from a previous mapping that existed before the kernel took |
| 226 | * over |
| 227 | */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 228 | flush_dcache_phys_range(dart_tablebase, |
| 229 | dart_tablebase + dart_tablesize); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 230 | |
| 231 | /* Allocate a spare page to map all invalid DART pages. We need to do |
| 232 | * that to work around what looks like a problem with the HT bridge |
| 233 | * prefetching into invalid pages and corrupting data |
| 234 | */ |
Olof Johansson | d0035c62 | 2005-09-20 13:46:44 +1000 | [diff] [blame] | 235 | tmp = lmb_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 236 | dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) & |
| 237 | DARTMAP_RPNMASK); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 238 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 239 | /* Map in DART registers */ |
| 240 | dart = ioremap(r.start, r.end - r.start + 1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 241 | if (dart == NULL) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 242 | panic("DART: Cannot map registers!"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 244 | /* Map in DART table */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 245 | dart_vbase = ioremap(virt_to_abs(dart_tablebase), dart_tablesize); |
| 246 | |
| 247 | /* Fill initial table */ |
| 248 | for (i = 0; i < dart_tablesize/4; i++) |
| 249 | dart_vbase[i] = dart_emptyval; |
| 250 | |
| 251 | /* Initialize DART with table base and enable it. */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 252 | base = dart_tablebase >> DART_PAGE_SHIFT; |
| 253 | size = dart_tablesize >> DART_PAGE_SHIFT; |
| 254 | if (dart_is_u4) { |
Benjamin Herrenschmidt | 56c8eae | 2005-12-19 16:49:07 +1100 | [diff] [blame] | 255 | size &= DART_SIZE_U4_SIZE_MASK; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 256 | DART_OUT(DART_BASE_U4, base); |
| 257 | DART_OUT(DART_SIZE_U4, size); |
| 258 | DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE); |
| 259 | } else { |
Benjamin Herrenschmidt | 56c8eae | 2005-12-19 16:49:07 +1100 | [diff] [blame] | 260 | size &= DART_CNTL_U3_SIZE_MASK; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 261 | DART_OUT(DART_CNTL, |
| 262 | DART_CNTL_U3_ENABLE | |
| 263 | (base << DART_CNTL_U3_BASE_SHIFT) | |
| 264 | (size << DART_CNTL_U3_SIZE_SHIFT)); |
| 265 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | |
| 267 | /* Invalidate DART to get rid of possible stale TLBs */ |
| 268 | dart_tlb_invalidate_all(); |
| 269 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 270 | printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n", |
| 271 | dart_is_u4 ? "U4" : "U3"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | |
| 273 | return 0; |
| 274 | } |
| 275 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 276 | static void iommu_table_dart_setup(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 277 | { |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 278 | iommu_table_dart.it_busno = 0; |
| 279 | iommu_table_dart.it_offset = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 280 | /* it_size is in number of entries */ |
Linas Vepstas | 5d2efba | 2006-10-30 16:15:59 +1100 | [diff] [blame] | 281 | iommu_table_dart.it_size = dart_tablesize / sizeof(u32); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 282 | |
| 283 | /* Initialize the common IOMMU code */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 284 | iommu_table_dart.it_base = (unsigned long)dart_vbase; |
| 285 | iommu_table_dart.it_index = 0; |
| 286 | iommu_table_dart.it_blocksize = 1; |
Anton Blanchard | ca1588e | 2006-06-10 20:58:08 +1000 | [diff] [blame] | 287 | iommu_init_table(&iommu_table_dart, -1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 288 | |
| 289 | /* Reserve the last page of the DART to avoid possible prefetch |
| 290 | * past the DART mapped area |
| 291 | */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 292 | set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | } |
| 294 | |
Benjamin Herrenschmidt | 12d04ee | 2006-11-11 17:25:02 +1100 | [diff] [blame] | 295 | static void pci_dma_dev_setup_dart(struct pci_dev *dev) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 297 | /* We only have one iommu table on the mac for now, which makes |
| 298 | * things simple. Setup all PCI devices to point to this table |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | */ |
Becky Bruce | 738ef42 | 2009-09-21 08:26:35 +0000 | [diff] [blame] | 300 | set_iommu_table_base(&dev->dev, &iommu_table_dart); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 301 | } |
| 302 | |
Benjamin Herrenschmidt | 12d04ee | 2006-11-11 17:25:02 +1100 | [diff] [blame] | 303 | static void pci_dma_bus_setup_dart(struct pci_bus *bus) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 304 | { |
| 305 | struct device_node *dn; |
| 306 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 307 | if (!iommu_table_dart_inited) { |
| 308 | iommu_table_dart_inited = 1; |
| 309 | iommu_table_dart_setup(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 310 | } |
| 311 | |
| 312 | dn = pci_bus_to_OF_node(bus); |
| 313 | |
| 314 | if (dn) |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 315 | PCI_DN(dn)->iommu_table = &iommu_table_dart; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 316 | } |
| 317 | |
Stephen Rothwell | 109b60f | 2007-08-15 20:54:32 +1000 | [diff] [blame] | 318 | void __init iommu_init_early_dart(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 319 | { |
| 320 | struct device_node *dn; |
| 321 | |
| 322 | /* Find the DART in the device-tree */ |
| 323 | dn = of_find_compatible_node(NULL, "dart", "u3-dart"); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 324 | if (dn == NULL) { |
| 325 | dn = of_find_compatible_node(NULL, "dart", "u4-dart"); |
| 326 | if (dn == NULL) |
| 327 | goto bail; |
| 328 | dart_is_u4 = 1; |
| 329 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 330 | |
| 331 | /* Setup low level TCE operations for the core IOMMU code */ |
| 332 | ppc_md.tce_build = dart_build; |
| 333 | ppc_md.tce_free = dart_free; |
| 334 | ppc_md.tce_flush = dart_flush; |
| 335 | |
| 336 | /* Initialize the DART HW */ |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 337 | if (dart_init(dn) == 0) { |
Benjamin Herrenschmidt | 12d04ee | 2006-11-11 17:25:02 +1100 | [diff] [blame] | 338 | ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_dart; |
| 339 | ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_dart; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 340 | |
| 341 | /* Setup pci_dma ops */ |
Stephen Rothwell | 9874777 | 2007-03-04 16:58:39 +1100 | [diff] [blame] | 342 | set_pci_dma_ops(&dma_iommu_ops); |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 343 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 344 | } |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 345 | |
| 346 | bail: |
| 347 | /* If init failed, use direct iommu and null setup functions */ |
Benjamin Herrenschmidt | 12d04ee | 2006-11-11 17:25:02 +1100 | [diff] [blame] | 348 | ppc_md.pci_dma_dev_setup = NULL; |
| 349 | ppc_md.pci_dma_bus_setup = NULL; |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 350 | |
| 351 | /* Setup pci_dma ops */ |
Stephen Rothwell | 9874777 | 2007-03-04 16:58:39 +1100 | [diff] [blame] | 352 | set_pci_dma_ops(&dma_direct_ops); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 353 | } |
| 354 | |
Johannes Berg | 7e11580 | 2007-05-03 22:28:32 +1000 | [diff] [blame] | 355 | #ifdef CONFIG_PM |
| 356 | static void iommu_dart_save(void) |
| 357 | { |
| 358 | memcpy(dart_copy, dart_vbase, 2*1024*1024); |
| 359 | } |
| 360 | |
| 361 | static void iommu_dart_restore(void) |
| 362 | { |
| 363 | memcpy(dart_vbase, dart_copy, 2*1024*1024); |
| 364 | dart_tlb_invalidate_all(); |
| 365 | } |
| 366 | |
| 367 | static int __init iommu_init_late_dart(void) |
| 368 | { |
| 369 | unsigned long tbasepfn; |
| 370 | struct page *p; |
| 371 | |
| 372 | /* if no dart table exists then we won't need to save it |
| 373 | * and the area has also not been reserved */ |
| 374 | if (!dart_tablebase) |
| 375 | return 0; |
| 376 | |
| 377 | tbasepfn = __pa(dart_tablebase) >> PAGE_SHIFT; |
| 378 | register_nosave_region_late(tbasepfn, |
| 379 | tbasepfn + ((1<<24) >> PAGE_SHIFT)); |
| 380 | |
| 381 | /* For suspend we need to copy the dart contents because |
| 382 | * it is not part of the regular mapping (see above) and |
| 383 | * thus not saved automatically. The memory for this copy |
| 384 | * must be allocated early because we need 2 MB. */ |
| 385 | p = alloc_pages(GFP_KERNEL, 21 - PAGE_SHIFT); |
| 386 | BUG_ON(!p); |
| 387 | dart_copy = page_address(p); |
| 388 | |
| 389 | ppc_md.iommu_save = iommu_dart_save; |
| 390 | ppc_md.iommu_restore = iommu_dart_restore; |
| 391 | |
| 392 | return 0; |
| 393 | } |
| 394 | |
| 395 | late_initcall(iommu_init_late_dart); |
| 396 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 398 | void __init alloc_dart_table(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 399 | { |
Olof Johansson | 2889773 | 2006-04-12 21:52:33 -0500 | [diff] [blame] | 400 | /* Only reserve DART space if machine has more than 1GB of RAM |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | * or if requested with iommu=on on cmdline. |
Olof Johansson | 2889773 | 2006-04-12 21:52:33 -0500 | [diff] [blame] | 402 | * |
| 403 | * 1GB of RAM is picked as limit because some default devices |
| 404 | * (i.e. Airport Extreme) have 30 bit address range limits. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 405 | */ |
Olof Johansson | 2889773 | 2006-04-12 21:52:33 -0500 | [diff] [blame] | 406 | |
| 407 | if (iommu_is_off) |
| 408 | return; |
| 409 | |
| 410 | if (!iommu_force_on && lmb_end_of_DRAM() <= 0x40000000ull) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 411 | return; |
| 412 | |
| 413 | /* 512 pages (2MB) is max DART tablesize. */ |
| 414 | dart_tablesize = 1UL << 21; |
| 415 | /* 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we |
| 416 | * will blow up an entire large page anyway in the kernel mapping |
| 417 | */ |
| 418 | dart_tablebase = (unsigned long) |
| 419 | abs_to_virt(lmb_alloc_base(1UL<<24, 1UL<<24, 0x80000000L)); |
| 420 | |
Benjamin Herrenschmidt | 1beb6a7 | 2005-12-14 13:10:10 +1100 | [diff] [blame] | 421 | printk(KERN_INFO "DART table allocated at: %lx\n", dart_tablebase); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 422 | } |