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gerrit-public.fairphone.software / kernel / msm-4.19 / 77aff8c76425c8f49b50d0b9009915066739e7d2 / . / arch / arm / boot / dts / keystone-k2l.dtsi
blob: 148650406cf701cd7ffc5ac92d9054d606e97bfd [file] [log] [blame]
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]1/*
2 * Copyright 2014 Texas Instruments, Inc.
3 *
4 * Keystone 2 Lamarr SoC specific device tree
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
Suman Anna2ae4dad2017-01-19 09:44:11 -0800[diff] [blame]11#include <dt-bindings/reset/ti-syscon.h>
12
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]13/ {
Nishanth Menon91dca0f2015-10-03 17:02:56 -0700[diff] [blame]14 compatible = "ti,k2l", "ti,keystone";
15 model = "Texas Instruments Keystone 2 Lamarr SoC";
16
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 interrupt-parent = <&gic>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a15";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a15";
31 device_type = "cpu";
32 reg = <1>;
33 };
34 };
35
36 soc {
Nishanth Menon5edafc22016-03-22 09:06:22 -0700[diff] [blame]37 /include/ "keystone-k2l-clocks.dtsi"
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]38
39 uart2: serial@02348400 {
David Lechner1dd55812017-01-06 11:07:01 -0800[diff] [blame]40 compatible = "ti,da830-uart", "ns16550a";
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]41 current-speed = <115200>;
42 reg-shift = <2>;
43 reg-io-width = <4>;
44 reg = <0x02348400 0x100>;
45 clocks = <&clkuart2>;
46 interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>;
47 };
48
49 uart3: serial@02348800 {
David Lechner1dd55812017-01-06 11:07:01 -0800[diff] [blame]50 compatible = "ti,da830-uart", "ns16550a";
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]51 current-speed = <115200>;
52 reg-shift = <2>;
53 reg-io-width = <4>;
54 reg = <0x02348800 0x100>;
55 clocks = <&clkuart3>;
56 interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
57 };
Grygorii Strashkoa3d3ee32014-09-22 15:19:27 -0400[diff] [blame]58
Keerthya6bada62016-06-08 16:06:44 -0700[diff] [blame]59 k2l_pmx: pinmux@02620690 {
60 compatible = "pinctrl-single";
61 reg = <0x02620690 0xc>;
62 #address-cells = <1>;
63 #size-cells = <0>;
Tony Lindgrenbe76fd32016-11-07 08:27:49 -0700[diff] [blame]64 #pinctrl-cells = <2>;
Keerthya6bada62016-06-08 16:06:44 -0700[diff] [blame]65 pinctrl-single,bit-per-mux;
66 pinctrl-single,register-width = <32>;
67 pinctrl-single,function-mask = <0x1>;
68 status = "disabled";
69
70 uart3_emifa_pins: pinmux_uart3_emifa_pins {
71 pinctrl-single,bits = <
72 /* UART3_EMIFA_SEL */
73 0x0 0x0 0xc0
74 >;
75 };
76
77 uart2_emifa_pins: pinmux_uart2_emifa_pins {
78 pinctrl-single,bits = <
79 /* UART2_EMIFA_SEL */
80 0x0 0x0 0x30
81 >;
82 };
83
84 uart01_spi2_pins: pinmux_uart01_spi2_pins {
85 pinctrl-single,bits = <
86 /* UART01_SPI2_SEL */
87 0x0 0x0 0x4
88 >;
89 };
90
91 dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
92 pinctrl-single,bits = <
93 /* DFESYNC_RP1_SEL */
94 0x0 0x0 0x2
95 >;
96 };
97
98 avsif_pins: pinmux_avsif_pins {
99 pinctrl-single,bits = <
100 /* AVSIF_SEL */
101 0x0 0x0 0x1
102 >;
103 };
104
105 gpio_emu_pins: pinmux_gpio_emu_pins {
106 pinctrl-single,bits = <
107 /*
108 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
109 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
110 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
111 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
112 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
113 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
114 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
115 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
116 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
117 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
118 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
119 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
120 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
121 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
122 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
123 */
124 0x4 0x0000 0xFFFE0000
125 >;
126 };
127
128 gpio_timio_pins: pinmux_gpio_timio_pins {
129 pinctrl-single,bits = <
130 /*
131 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
132 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
133 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
134 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
135 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
136 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
137 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
138 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
139 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
140 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
141 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
142 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
143 */
144 0x4 0x0 0xFFF0
145 >;
146 };
147
148 gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
149 pinctrl-single,bits = <
150 /*
151 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
152 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
153 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
154 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
155 */
156 0x4 0x0 0xF
157 >;
158 };
159
160 gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
161 pinctrl-single,bits = <
162 /*
163 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
164 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
165 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
166 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
167 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
168 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
169 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
170 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
171 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
172 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
173 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
174 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
175 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
176 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
177 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
178 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
179 */
180 0x8 0x0 0xFFFF0000
181 >;
182 };
183
184 gpio_emifa_pins: pinmux_gpio_emifa_pins {
185 pinctrl-single,bits = <
186 /*
187 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
188 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
189 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
190 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
191 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
192 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
193 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
194 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
195 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
196 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
197 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
198 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
199 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
200 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
201 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
202 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
203 */
204 0x8 0x0 0xFFFF
205 >;
206 };
207 };
208
Suman Annad29db5a2017-01-07 12:33:08 -0800[diff] [blame]209 msm_ram: msmram@0c000000 {
210 compatible = "mmio-sram";
211 reg = <0x0c000000 0x200000>;
212 ranges = <0x0 0x0c000000 0x200000>;
213 #address-cells = <1>;
214 #size-cells = <1>;
Suman Anna82d76b62017-01-07 12:33:08 -0800[diff] [blame]215
216 sram-bm@1f8000 {
217 reg = <0x001f8000 0x8000>;
218 };
Suman Annad29db5a2017-01-07 12:33:08 -0800[diff] [blame]219 };
220
Suman Anna2ae4dad2017-01-19 09:44:11 -0800[diff] [blame]221 psc: power-sleep-controller@02350000 {
222 pscrst: reset-controller {
223 compatible = "ti,k2l-pscrst", "ti,syscon-reset";
224 #reset-cells = <1>;
225
226 ti,reset-bits = <
227 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */
228 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */
229 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */
230 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */
231 >;
232 };
233 };
234
Murali Karicheri791229f2017-03-29 16:02:18 +0530[diff] [blame]235 osr: sram@70000000 {
236 compatible = "mmio-sram";
237 reg = <0x70000000 0x10000>;
238 #address-cells = <1>;
239 #size-cells = <1>;
240 clocks = <&clkosr>;
241 };
242
Grygorii Strashkoa3d3ee32014-09-22 15:19:27 -0400[diff] [blame]243 dspgpio0: keystone_dsp_gpio@02620240 {
244 compatible = "ti,keystone-dsp-gpio";
245 gpio-controller;
246 #gpio-cells = <2>;
247 gpio,syscon-dev = <&devctrl 0x240>;
248 };
249
250 dspgpio1: keystone_dsp_gpio@2620244 {
251 compatible = "ti,keystone-dsp-gpio";
252 gpio-controller;
253 #gpio-cells = <2>;
254 gpio,syscon-dev = <&devctrl 0x244>;
255 };
256
257 dspgpio2: keystone_dsp_gpio@2620248 {
258 compatible = "ti,keystone-dsp-gpio";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio,syscon-dev = <&devctrl 0x248>;
262 };
263
264 dspgpio3: keystone_dsp_gpio@262024c {
265 compatible = "ti,keystone-dsp-gpio";
266 gpio-controller;
267 #gpio-cells = <2>;
268 gpio,syscon-dev = <&devctrl 0x24c>;
269 };
Murali Karicheri85ad3de2015-08-09 20:06:27 -0700[diff] [blame]270
271 mdio: mdio@26200f00 {
272 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
273 #address-cells = <1>;
274 #size-cells = <0>;
275 reg = <0x26200f00 0x100>;
276 status = "disabled";
277 clocks = <&clkcpgmac>;
278 clock-names = "fck";
279 bus_freq = <2500000>;
280 };
Nishanth Menon5edafc22016-03-22 09:06:22 -0700[diff] [blame]281 /include/ "keystone-k2l-netcp.dtsi"
Murali Karicherifc1c72e2014-02-24 10:56:48 -0500[diff] [blame]282 };
283};
Karicheri Muralidharan48443f02014-09-22 15:19:27 -0400[diff] [blame]284
285&spi0 {
286 ti,davinci-spi-num-cs = <5>;
287};
288
289&spi1 {
290 ti,davinci-spi-num-cs = <3>;
291};
292
293&spi2 {
294 ti,davinci-spi-num-cs = <5>;
295 /* Pin muxed. Enabled and configured by Bootloader */
296 status = "disabled";
297};