blob: 32f4d564494a9f48cfebd328e61d3c281387d252 [file] [log] [blame]
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001/*
2 * xHCI host controller driver
3 *
4 * Copyright (C) 2008 Intel Corp.
5 *
6 * Author: Sarah Sharp
7 * Some code borrowed from the Linux EHCI driver.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23/*
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
29 *
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
41 *
42 * Cycle bit rules:
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
47 *
48 * Producer rules:
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
52 * cycle state).
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
56 *
57 * Consumer rules:
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
65 */
66
Sarah Sharp8a96c052009-04-27 19:59:19 -070067#include <linux/scatterlist.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090068#include <linux/slab.h>
Sarah Sharp7f84eef2009-04-27 19:53:56 -070069#include "xhci.h"
Xenia Ragiadakou3a7fa5b2013-07-31 07:35:27 +030070#include "xhci-trace.h"
Sarah Sharp7f84eef2009-04-27 19:53:56 -070071
72/*
73 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 * address of the TRB.
75 */
Sarah Sharp23e3be12009-04-29 19:05:20 -070076dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
Sarah Sharp7f84eef2009-04-27 19:53:56 -070077 union xhci_trb *trb)
78{
Sarah Sharp6071d832009-05-14 11:44:14 -070079 unsigned long segment_offset;
Sarah Sharp7f84eef2009-04-27 19:53:56 -070080
Sarah Sharp6071d832009-05-14 11:44:14 -070081 if (!seg || !trb || trb < seg->trbs)
Sarah Sharp7f84eef2009-04-27 19:53:56 -070082 return 0;
Sarah Sharp6071d832009-05-14 11:44:14 -070083 /* offset in TRBs */
84 segment_offset = trb - seg->trbs;
Mathias Nyman78950862015-08-03 16:07:48 +030085 if (segment_offset >= TRBS_PER_SEGMENT)
Sarah Sharp7f84eef2009-04-27 19:53:56 -070086 return 0;
Sarah Sharp6071d832009-05-14 11:44:14 -070087 return seg->dma + (segment_offset * sizeof(*trb));
Sarah Sharp7f84eef2009-04-27 19:53:56 -070088}
89
90/* Does this link TRB point to the first segment in a ring,
91 * or was the previous TRB the last TRB on the last segment in the ERST?
92 */
Dmitry Torokhov575688e2011-03-20 02:15:16 -070093static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -070094 struct xhci_segment *seg, union xhci_trb *trb)
95{
96 if (ring == xhci->event_ring)
97 return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
98 (seg->next == xhci->event_ring->first_seg);
99 else
Matt Evans28ccd292011-03-29 13:40:46 +1100100 return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700101}
102
103/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
104 * segment? I.e. would the updated event TRB pointer step off the end of the
105 * event seg?
106 */
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700107static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700108 struct xhci_segment *seg, union xhci_trb *trb)
109{
110 if (ring == xhci->event_ring)
111 return trb == &seg->trbs[TRBS_PER_SEGMENT];
112 else
Matt Evansf5960b62011-06-01 10:22:55 +1000113 return TRB_TYPE_LINK_LE32(trb->link.control);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700114}
115
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700116static int enqueue_is_link_trb(struct xhci_ring *ring)
John Youn6c12db92010-05-10 15:33:00 -0700117{
118 struct xhci_link_trb *link = &ring->enqueue->link;
Matt Evansf5960b62011-06-01 10:22:55 +1000119 return TRB_TYPE_LINK_LE32(link->control);
John Youn6c12db92010-05-10 15:33:00 -0700120}
121
Sarah Sharpae636742009-04-29 19:02:31 -0700122/* Updates trb to point to the next TRB in the ring, and updates seg if the next
123 * TRB is in a new segment. This does not skip over link TRBs, and it does not
124 * effect the ring dequeue or enqueue pointers.
125 */
126static void next_trb(struct xhci_hcd *xhci,
127 struct xhci_ring *ring,
128 struct xhci_segment **seg,
129 union xhci_trb **trb)
130{
131 if (last_trb(xhci, ring, *seg, *trb)) {
132 *seg = (*seg)->next;
133 *trb = ((*seg)->trbs);
134 } else {
John Youna1669b22010-08-09 13:56:11 -0700135 (*trb)++;
Sarah Sharpae636742009-04-29 19:02:31 -0700136 }
137}
138
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700139/*
140 * See Cycle bit rules. SW is the consumer for the event ring only.
141 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
142 */
Andiry Xu3b72fca2012-03-05 17:49:32 +0800143static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700144{
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700145 ring->deq_updates++;
Andiry Xub008df62012-03-05 17:49:34 +0800146
Sarah Sharp50d0206f2012-07-26 12:03:59 -0700147 /*
148 * If this is not event ring, and the dequeue pointer
149 * is not on a link TRB, there is one more usable TRB
150 */
Andiry Xub008df62012-03-05 17:49:34 +0800151 if (ring->type != TYPE_EVENT &&
152 !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
153 ring->num_trbs_free++;
Andiry Xub008df62012-03-05 17:49:34 +0800154
Sarah Sharp50d0206f2012-07-26 12:03:59 -0700155 do {
156 /*
157 * Update the dequeue pointer further if that was a link TRB or
158 * we're at the end of an event ring segment (which doesn't have
159 * link TRBS)
160 */
161 if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
162 if (ring->type == TYPE_EVENT &&
163 last_trb_on_last_seg(xhci, ring,
164 ring->deq_seg, ring->dequeue)) {
Dan Williams4e341812013-10-07 11:58:34 -0700165 ring->cycle_state ^= 1;
Sarah Sharp50d0206f2012-07-26 12:03:59 -0700166 }
167 ring->deq_seg = ring->deq_seg->next;
168 ring->dequeue = ring->deq_seg->trbs;
169 } else {
170 ring->dequeue++;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700171 }
Sarah Sharp50d0206f2012-07-26 12:03:59 -0700172 } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700173}
174
175/*
176 * See Cycle bit rules. SW is the consumer for the event ring only.
177 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
178 *
179 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
180 * chain bit is set), then set the chain bit in all the following link TRBs.
181 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
182 * have their chain bit cleared (so that each Link TRB is a separate TD).
183 *
184 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
Sarah Sharpb0567b32009-08-07 14:04:36 -0700185 * set, but other sections talk about dealing with the chain bit set. This was
186 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
187 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700188 *
189 * @more_trbs_coming: Will you enqueue more TRBs before calling
190 * prepare_transfer()?
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700191 */
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700192static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
Andiry Xu3b72fca2012-03-05 17:49:32 +0800193 bool more_trbs_coming)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700194{
195 u32 chain;
196 union xhci_trb *next;
197
Matt Evans28ccd292011-03-29 13:40:46 +1100198 chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
Andiry Xub008df62012-03-05 17:49:34 +0800199 /* If this is not event ring, there is one less usable TRB */
200 if (ring->type != TYPE_EVENT &&
201 !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
202 ring->num_trbs_free--;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700203 next = ++(ring->enqueue);
204
205 ring->enq_updates++;
206 /* Update the dequeue pointer further if that was a link TRB or we're at
207 * the end of an event ring segment (which doesn't have link TRBS)
208 */
209 while (last_trb(xhci, ring, ring->enq_seg, next)) {
Andiry Xu3b72fca2012-03-05 17:49:32 +0800210 if (ring->type != TYPE_EVENT) {
211 /*
212 * If the caller doesn't plan on enqueueing more
213 * TDs before ringing the doorbell, then we
214 * don't want to give the link TRB to the
215 * hardware just yet. We'll give the link TRB
216 * back in prepare_ring() just before we enqueue
217 * the TD at the top of the ring.
218 */
219 if (!chain && !more_trbs_coming)
220 break;
Sarah Sharp6cc30d82010-06-10 12:25:28 -0700221
Andiry Xu3b72fca2012-03-05 17:49:32 +0800222 /* If we're not dealing with 0.95 hardware or
223 * isoc rings on AMD 0.96 host,
224 * carry over the chain bit of the previous TRB
225 * (which may mean the chain bit is cleared).
226 */
227 if (!(ring->type == TYPE_ISOC &&
228 (xhci->quirks & XHCI_AMD_0x96_HOST))
Andiry Xu7e393a82011-09-23 14:19:54 -0700229 && !xhci_link_trb_quirk(xhci)) {
Andiry Xu3b72fca2012-03-05 17:49:32 +0800230 next->link.control &=
231 cpu_to_le32(~TRB_CHAIN);
232 next->link.control |=
233 cpu_to_le32(chain);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700234 }
Andiry Xu3b72fca2012-03-05 17:49:32 +0800235 /* Give this link TRB to the hardware */
236 wmb();
237 next->link.control ^= cpu_to_le32(TRB_CYCLE);
238
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700239 /* Toggle the cycle bit after the last ring segment. */
240 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
Lin Wange5401bf2015-03-17 18:32:21 +0200241 ring->cycle_state ^= 1;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700242 }
243 }
244 ring->enq_seg = ring->enq_seg->next;
245 ring->enqueue = ring->enq_seg->trbs;
246 next = ring->enqueue;
247 }
248}
249
250/*
Andiry Xu085deb12012-03-05 17:49:40 +0800251 * Check to see if there's room to enqueue num_trbs on the ring and make sure
252 * enqueue pointer will not advance into dequeue segment. See rules above.
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700253 */
Andiry Xub008df62012-03-05 17:49:34 +0800254static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700255 unsigned int num_trbs)
256{
Andiry Xu085deb12012-03-05 17:49:40 +0800257 int num_trbs_in_deq_seg;
Andiry Xub008df62012-03-05 17:49:34 +0800258
Andiry Xu085deb12012-03-05 17:49:40 +0800259 if (ring->num_trbs_free < num_trbs)
260 return 0;
261
262 if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
263 num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
264 if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
265 return 0;
266 }
267
268 return 1;
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700269}
270
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700271/* Ring the host controller doorbell after placing a command on the ring */
Sarah Sharp23e3be12009-04-29 19:05:20 -0700272void xhci_ring_cmd_db(struct xhci_hcd *xhci)
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700273{
Elric Fuc181bc52012-06-27 16:30:57 +0800274 if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
275 return;
276
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700277 xhci_dbg(xhci, "// Ding dong!\n");
Xenia Ragiadakou204b7792013-11-15 05:34:07 +0200278 writel(DB_VALUE_HOST, &xhci->dba->doorbell[0]);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700279 /* Flush PCI posted writes */
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +0200280 readl(&xhci->dba->doorbell[0]);
Sarah Sharp7f84eef2009-04-27 19:53:56 -0700281}
282
Elric Fub92cc662012-06-27 16:31:12 +0800283static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
284{
285 u64 temp_64;
286 int ret;
287
288 xhci_dbg(xhci, "Abort command ring\n");
289
Sarah Sharpf7b2e402014-01-30 13:27:49 -0800290 temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
Elric Fub92cc662012-06-27 16:31:12 +0800291 xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
Sarah Sharp477632d2014-01-29 14:02:00 -0800292 xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
293 &xhci->op_regs->cmd_ring);
Elric Fub92cc662012-06-27 16:31:12 +0800294
295 /* Section 4.6.1.2 of xHCI 1.0 spec says software should
296 * time the completion od all xHCI commands, including
297 * the Command Abort operation. If software doesn't see
298 * CRR negated in a timely manner (e.g. longer than 5
299 * seconds), then it should assume that the there are
300 * larger problems with the xHC and assert HCRST.
301 */
Lin Wangdc0b1772015-01-09 16:06:28 +0200302 ret = xhci_handshake(&xhci->op_regs->cmd_ring,
Elric Fub92cc662012-06-27 16:31:12 +0800303 CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
304 if (ret < 0) {
305 xhci_err(xhci, "Stopped the command ring failed, "
306 "maybe the host is dead\n");
307 xhci->xhc_state |= XHCI_STATE_DYING;
308 xhci_quiesce(xhci);
309 xhci_halt(xhci);
310 return -ESHUTDOWN;
311 }
312
313 return 0;
314}
315
Andiry Xube88fe42010-10-14 07:22:57 -0700316void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
Sarah Sharpae636742009-04-29 19:02:31 -0700317 unsigned int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700318 unsigned int ep_index,
319 unsigned int stream_id)
Sarah Sharpae636742009-04-29 19:02:31 -0700320{
Matt Evans28ccd292011-03-29 13:40:46 +1100321 __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
Matthew Wilcox50d646762010-12-15 14:18:11 -0500322 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
323 unsigned int ep_state = ep->ep_state;
Sarah Sharpae636742009-04-29 19:02:31 -0700324
Sarah Sharpae636742009-04-29 19:02:31 -0700325 /* Don't ring the doorbell for this endpoint if there are pending
Matthew Wilcox50d646762010-12-15 14:18:11 -0500326 * cancellations because we don't want to interrupt processing.
Sarah Sharp8df75f42010-04-02 15:34:16 -0700327 * We don't want to restart any stream rings if there's a set dequeue
328 * pointer command pending because the device can choose to start any
329 * stream once the endpoint is on the HW schedule.
Sarah Sharpae636742009-04-29 19:02:31 -0700330 */
Matthew Wilcox50d646762010-12-15 14:18:11 -0500331 if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
332 (ep_state & EP_HALTED))
333 return;
Xenia Ragiadakou204b7792013-11-15 05:34:07 +0200334 writel(DB_VALUE(ep_index, stream_id), db_addr);
Matthew Wilcox50d646762010-12-15 14:18:11 -0500335 /* The CPU has better things to do at this point than wait for a
336 * write-posting flush. It'll get there soon enough.
337 */
Sarah Sharpae636742009-04-29 19:02:31 -0700338}
339
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700340/* Ring the doorbell for any rings with pending URBs */
341static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
342 unsigned int slot_id,
343 unsigned int ep_index)
344{
345 unsigned int stream_id;
346 struct xhci_virt_ep *ep;
347
348 ep = &xhci->devs[slot_id]->eps[ep_index];
349
350 /* A ring has pending URBs if its TD list is not empty */
351 if (!(ep->ep_state & EP_HAS_STREAMS)) {
Oleksij Rempeld66eaf92013-07-21 15:36:19 +0200352 if (ep->ring && !(list_empty(&ep->ring->td_list)))
Andiry Xube88fe42010-10-14 07:22:57 -0700353 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700354 return;
355 }
356
357 for (stream_id = 1; stream_id < ep->stream_info->num_streams;
358 stream_id++) {
359 struct xhci_stream_info *stream_info = ep->stream_info;
360 if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
Andiry Xube88fe42010-10-14 07:22:57 -0700361 xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
362 stream_id);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700363 }
364}
365
Sarah Sharp021bff92010-07-29 22:12:20 -0700366static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
367 unsigned int slot_id, unsigned int ep_index,
368 unsigned int stream_id)
369{
370 struct xhci_virt_ep *ep;
371
372 ep = &xhci->devs[slot_id]->eps[ep_index];
373 /* Common case: no streams */
374 if (!(ep->ep_state & EP_HAS_STREAMS))
375 return ep->ring;
376
377 if (stream_id == 0) {
378 xhci_warn(xhci,
379 "WARN: Slot ID %u, ep index %u has streams, "
380 "but URB has no stream ID.\n",
381 slot_id, ep_index);
382 return NULL;
383 }
384
385 if (stream_id < ep->stream_info->num_streams)
386 return ep->stream_info->stream_rings[stream_id];
387
388 xhci_warn(xhci,
389 "WARN: Slot ID %u, ep index %u has "
390 "stream IDs 1 to %u allocated, "
391 "but stream ID %u is requested.\n",
392 slot_id, ep_index,
393 ep->stream_info->num_streams - 1,
394 stream_id);
395 return NULL;
396}
397
398/* Get the right ring for the given URB.
399 * If the endpoint supports streams, boundary check the URB's stream ID.
400 * If the endpoint doesn't support streams, return the singular endpoint ring.
401 */
402static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
403 struct urb *urb)
404{
405 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
406 xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
407}
408
Sarah Sharpae636742009-04-29 19:02:31 -0700409/*
410 * Move the xHC's endpoint ring dequeue pointer past cur_td.
411 * Record the new state of the xHC's endpoint ring dequeue segment,
412 * dequeue pointer, and new consumer cycle state in state.
413 * Update our internal representation of the ring's dequeue pointer.
414 *
415 * We do this in three jumps:
416 * - First we update our new ring state to be the same as when the xHC stopped.
417 * - Then we traverse the ring to find the segment that contains
418 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
419 * any link TRBs with the toggle cycle bit set.
420 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
421 * if we've moved it past a link TRB with the toggle cycle bit set.
Matt Evans28ccd292011-03-29 13:40:46 +1100422 *
423 * Some of the uses of xhci_generic_trb are grotty, but if they're done
424 * with correct __le32 accesses they should work fine. Only users of this are
425 * in here.
Sarah Sharpae636742009-04-29 19:02:31 -0700426 */
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700427void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
Sarah Sharpae636742009-04-29 19:02:31 -0700428 unsigned int slot_id, unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700429 unsigned int stream_id, struct xhci_td *cur_td,
430 struct xhci_dequeue_state *state)
Sarah Sharpae636742009-04-29 19:02:31 -0700431{
432 struct xhci_virt_device *dev = xhci->devs[slot_id];
Hans de Goedec4bedb72013-10-04 00:29:47 +0200433 struct xhci_virt_ep *ep = &dev->eps[ep_index];
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700434 struct xhci_ring *ep_ring;
Mathias Nyman365038d2014-08-19 15:17:58 +0300435 struct xhci_segment *new_seg;
436 union xhci_trb *new_deq;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700437 dma_addr_t addr;
Julius Werner1f81b6d2014-04-25 19:20:13 +0300438 u64 hw_dequeue;
Mathias Nyman365038d2014-08-19 15:17:58 +0300439 bool cycle_found = false;
440 bool td_last_trb_found = false;
Sarah Sharpae636742009-04-29 19:02:31 -0700441
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700442 ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
443 ep_index, stream_id);
444 if (!ep_ring) {
445 xhci_warn(xhci, "WARN can't find new dequeue state "
446 "for invalid stream ID %u.\n",
447 stream_id);
448 return;
449 }
Paul Zimmerman68e41c52011-02-12 14:06:06 -0800450
Sarah Sharpae636742009-04-29 19:02:31 -0700451 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300452 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
453 "Finding endpoint context");
Hans de Goedec4bedb72013-10-04 00:29:47 +0200454 /* 4.6.9 the css flag is written to the stream context for streams */
455 if (ep->ep_state & EP_HAS_STREAMS) {
456 struct xhci_stream_ctx *ctx =
457 &ep->stream_info->stream_ctx_array[stream_id];
Julius Werner1f81b6d2014-04-25 19:20:13 +0300458 hw_dequeue = le64_to_cpu(ctx->stream_ring);
Hans de Goedec4bedb72013-10-04 00:29:47 +0200459 } else {
460 struct xhci_ep_ctx *ep_ctx
461 = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
Julius Werner1f81b6d2014-04-25 19:20:13 +0300462 hw_dequeue = le64_to_cpu(ep_ctx->deq);
Hans de Goedec4bedb72013-10-04 00:29:47 +0200463 }
Sarah Sharpae636742009-04-29 19:02:31 -0700464
Mathias Nyman365038d2014-08-19 15:17:58 +0300465 new_seg = ep_ring->deq_seg;
466 new_deq = ep_ring->dequeue;
467 state->new_cycle_state = hw_dequeue & 0x1;
468
469 /*
470 * We want to find the pointer, segment and cycle state of the new trb
471 * (the one after current TD's last_trb). We know the cycle state at
472 * hw_dequeue, so walk the ring until both hw_dequeue and last_trb are
473 * found.
474 */
475 do {
476 if (!cycle_found && xhci_trb_virt_to_dma(new_seg, new_deq)
477 == (dma_addr_t)(hw_dequeue & ~0xf)) {
478 cycle_found = true;
479 if (td_last_trb_found)
480 break;
481 }
482 if (new_deq == cur_td->last_trb)
483 td_last_trb_found = true;
484
485 if (cycle_found &&
486 TRB_TYPE_LINK_LE32(new_deq->generic.field[3]) &&
487 new_deq->generic.field[3] & cpu_to_le32(LINK_TOGGLE))
488 state->new_cycle_state ^= 0x1;
489
490 next_trb(xhci, ep_ring, &new_seg, &new_deq);
491
492 /* Search wrapped around, bail out */
493 if (new_deq == ep->ring->dequeue) {
494 xhci_err(xhci, "Error: Failed finding new dequeue state\n");
495 state->new_deq_seg = NULL;
496 state->new_deq_ptr = NULL;
Julius Werner1f81b6d2014-04-25 19:20:13 +0300497 return;
498 }
Julius Werner1f81b6d2014-04-25 19:20:13 +0300499
Mathias Nyman365038d2014-08-19 15:17:58 +0300500 } while (!cycle_found || !td_last_trb_found);
Sarah Sharpae636742009-04-29 19:02:31 -0700501
Mathias Nyman365038d2014-08-19 15:17:58 +0300502 state->new_deq_seg = new_seg;
503 state->new_deq_ptr = new_deq;
Sarah Sharpae636742009-04-29 19:02:31 -0700504
Julius Werner1f81b6d2014-04-25 19:20:13 +0300505 /* Don't update the ring cycle state for the producer (us). */
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300506 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
507 "Cycle state = 0x%x", state->new_cycle_state);
Sarah Sharp01a1fdb2011-02-23 18:12:29 -0800508
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300509 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
510 "New dequeue segment = %p (virtual)",
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700511 state->new_deq_seg);
512 addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300513 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
514 "New dequeue pointer = 0x%llx (DMA)",
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700515 (unsigned long long) addr);
Sarah Sharpae636742009-04-29 19:02:31 -0700516}
517
Sarah Sharp522989a2011-07-29 12:44:32 -0700518/* flip_cycle means flip the cycle bit of all but the first and last TRB.
519 * (The last TRB actually points to the ring enqueue pointer, which is not part
520 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
521 */
Sarah Sharp23e3be12009-04-29 19:05:20 -0700522static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
Sarah Sharp522989a2011-07-29 12:44:32 -0700523 struct xhci_td *cur_td, bool flip_cycle)
Sarah Sharpae636742009-04-29 19:02:31 -0700524{
525 struct xhci_segment *cur_seg;
526 union xhci_trb *cur_trb;
527
528 for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
529 true;
530 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +1000531 if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
Sarah Sharpae636742009-04-29 19:02:31 -0700532 /* Unchain any chained Link TRBs, but
533 * leave the pointers intact.
534 */
Matt Evans28ccd292011-03-29 13:40:46 +1100535 cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
Sarah Sharp522989a2011-07-29 12:44:32 -0700536 /* Flip the cycle bit (link TRBs can't be the first
537 * or last TRB).
538 */
539 if (flip_cycle)
540 cur_trb->generic.field[3] ^=
541 cpu_to_le32(TRB_CYCLE);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300542 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
543 "Cancel (unchain) link TRB");
544 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
545 "Address = %p (0x%llx dma); "
546 "in seg %p (0x%llx dma)",
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700547 cur_trb,
Sarah Sharp23e3be12009-04-29 19:05:20 -0700548 (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -0700549 cur_seg,
550 (unsigned long long)cur_seg->dma);
Sarah Sharpae636742009-04-29 19:02:31 -0700551 } else {
552 cur_trb->generic.field[0] = 0;
553 cur_trb->generic.field[1] = 0;
554 cur_trb->generic.field[2] = 0;
555 /* Preserve only the cycle bit of this TRB */
Matt Evans28ccd292011-03-29 13:40:46 +1100556 cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
Sarah Sharp522989a2011-07-29 12:44:32 -0700557 /* Flip the cycle bit except on the first or last TRB */
558 if (flip_cycle && cur_trb != cur_td->first_trb &&
559 cur_trb != cur_td->last_trb)
560 cur_trb->generic.field[3] ^=
561 cpu_to_le32(TRB_CYCLE);
Matt Evans28ccd292011-03-29 13:40:46 +1100562 cur_trb->generic.field[3] |= cpu_to_le32(
563 TRB_TYPE(TRB_TR_NOOP));
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300564 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
565 "TRB to noop at offset 0x%llx",
Sarah Sharp79688ac2011-12-19 16:56:04 -0800566 (unsigned long long)
567 xhci_trb_virt_to_dma(cur_seg, cur_trb));
Sarah Sharpae636742009-04-29 19:02:31 -0700568 }
569 if (cur_trb == cur_td->last_trb)
570 break;
571 }
572}
573
Dmitry Torokhov575688e2011-03-20 02:15:16 -0700574static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700575 struct xhci_virt_ep *ep)
576{
577 ep->ep_state &= ~EP_HALT_PENDING;
578 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
579 * timer is running on another CPU, we don't decrement stop_cmds_pending
580 * (since we didn't successfully stop the watchdog timer).
581 */
582 if (del_timer(&ep->stop_cmd_timer))
583 ep->stop_cmds_pending--;
584}
585
586/* Must be called with xhci->lock held in interrupt context */
587static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
Xenia Ragiadakou07a37e92013-09-09 13:29:45 +0300588 struct xhci_td *cur_td, int status)
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700589{
Sarah Sharp214f76f2010-10-26 11:22:02 -0700590 struct usb_hcd *hcd;
Andiry Xu8e51adc2010-07-22 15:23:31 -0700591 struct urb *urb;
592 struct urb_priv *urb_priv;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700593
Andiry Xu8e51adc2010-07-22 15:23:31 -0700594 urb = cur_td->urb;
595 urb_priv = urb->hcpriv;
596 urb_priv->td_cnt++;
Sarah Sharp214f76f2010-10-26 11:22:02 -0700597 hcd = bus_to_hcd(urb->dev->bus);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700598
Andiry Xu8e51adc2010-07-22 15:23:31 -0700599 /* Only giveback urb when this is the last td in urb */
600 if (urb_priv->td_cnt == urb_priv->length) {
Andiry Xuc41136b2011-03-22 17:08:14 +0800601 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
602 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
603 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
604 if (xhci->quirks & XHCI_AMD_PLL_FIX)
605 usb_amd_quirk_pll_enable();
606 }
607 }
Andiry Xu8e51adc2010-07-22 15:23:31 -0700608 usb_hcd_unlink_urb_from_ep(hcd, urb);
Andiry Xu8e51adc2010-07-22 15:23:31 -0700609
610 spin_unlock(&xhci->lock);
611 usb_hcd_giveback_urb(hcd, urb, status);
Lin Wang4daf9df2015-01-09 16:06:31 +0200612 xhci_urb_free_priv(urb_priv);
Andiry Xu8e51adc2010-07-22 15:23:31 -0700613 spin_lock(&xhci->lock);
Andiry Xu8e51adc2010-07-22 15:23:31 -0700614 }
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700615}
616
Sarah Sharpae636742009-04-29 19:02:31 -0700617/*
618 * When we get a command completion for a Stop Endpoint Command, we need to
619 * unlink any cancelled TDs from the ring. There are two ways to do that:
620 *
621 * 1. If the HW was in the middle of processing the TD that needs to be
622 * cancelled, then we must move the ring's dequeue pointer past the last TRB
623 * in the TD with a Set Dequeue Pointer Command.
624 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
625 * bit cleared) so that the HW will skip over them.
626 */
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +0300627static void xhci_handle_cmd_stop_ep(struct xhci_hcd *xhci, int slot_id,
Andiry Xube88fe42010-10-14 07:22:57 -0700628 union xhci_trb *trb, struct xhci_event_cmd *event)
Sarah Sharpae636742009-04-29 19:02:31 -0700629{
Sarah Sharpae636742009-04-29 19:02:31 -0700630 unsigned int ep_index;
631 struct xhci_ring *ep_ring;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700632 struct xhci_virt_ep *ep;
Sarah Sharpae636742009-04-29 19:02:31 -0700633 struct list_head *entry;
Randy Dunlap326b4812010-04-19 08:53:50 -0700634 struct xhci_td *cur_td = NULL;
Sarah Sharpae636742009-04-29 19:02:31 -0700635 struct xhci_td *last_unlinked_td;
636
Sarah Sharpc92bcfa2009-07-27 12:05:21 -0700637 struct xhci_dequeue_state deq_state;
Sarah Sharpae636742009-04-29 19:02:31 -0700638
Xenia Ragiadakoubc752bd2013-09-09 13:29:59 +0300639 if (unlikely(TRB_TO_SUSPEND_PORT(le32_to_cpu(trb->generic.field[3])))) {
Mathias Nyman9ea18332014-05-08 19:26:02 +0300640 if (!xhci->devs[slot_id])
Andiry Xube88fe42010-10-14 07:22:57 -0700641 xhci_warn(xhci, "Stop endpoint command "
642 "completion for disabled slot %u\n",
643 slot_id);
644 return;
645 }
646
Sarah Sharpae636742009-04-29 19:02:31 -0700647 memset(&deq_state, 0, sizeof(deq_state));
Matt Evans28ccd292011-03-29 13:40:46 +1100648 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700649 ep = &xhci->devs[slot_id]->eps[ep_index];
Sarah Sharpae636742009-04-29 19:02:31 -0700650
Sarah Sharp678539c2009-10-27 10:55:52 -0700651 if (list_empty(&ep->cancelled_td_list)) {
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700652 xhci_stop_watchdog_timer_in_irq(xhci, ep);
Sarah Sharp0714a572011-05-24 11:53:29 -0700653 ep->stopped_td = NULL;
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700654 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -0700655 return;
Sarah Sharp678539c2009-10-27 10:55:52 -0700656 }
Sarah Sharpae636742009-04-29 19:02:31 -0700657
658 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
659 * We have the xHCI lock, so nothing can modify this list until we drop
660 * it. We're also in the event handler, so we can't get re-interrupted
661 * if another Stop Endpoint command completes
662 */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700663 list_for_each(entry, &ep->cancelled_td_list) {
Sarah Sharpae636742009-04-29 19:02:31 -0700664 cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300665 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
666 "Removing canceled TD starting at 0x%llx (dma).",
Sarah Sharp79688ac2011-12-19 16:56:04 -0800667 (unsigned long long)xhci_trb_virt_to_dma(
668 cur_td->start_seg, cur_td->first_trb));
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700669 ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
670 if (!ep_ring) {
671 /* This shouldn't happen unless a driver is mucking
672 * with the stream ID after submission. This will
673 * leave the TD on the hardware ring, and the hardware
674 * will try to execute it, and may access a buffer
675 * that has already been freed. In the best case, the
676 * hardware will execute it, and the event handler will
677 * ignore the completion event for that TD, since it was
678 * removed from the td_list for that endpoint. In
679 * short, don't muck with the stream ID after
680 * submission.
681 */
682 xhci_warn(xhci, "WARN Cancelled URB %p "
683 "has invalid stream ID %u.\n",
684 cur_td->urb,
685 cur_td->urb->stream_id);
686 goto remove_finished_td;
687 }
Sarah Sharpae636742009-04-29 19:02:31 -0700688 /*
689 * If we stopped on the TD we need to cancel, then we have to
690 * move the xHC endpoint ring dequeue pointer past this TD.
691 */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700692 if (cur_td == ep->stopped_td)
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700693 xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
694 cur_td->urb->stream_id,
695 cur_td, &deq_state);
Sarah Sharpae636742009-04-29 19:02:31 -0700696 else
Sarah Sharp522989a2011-07-29 12:44:32 -0700697 td_to_noop(xhci, ep_ring, cur_td, false);
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700698remove_finished_td:
Sarah Sharpae636742009-04-29 19:02:31 -0700699 /*
700 * The event handler won't see a completion for this TD anymore,
701 * so remove it from the endpoint ring's TD list. Keep it in
702 * the cancelled TD list for URB completion later.
703 */
Sarah Sharp585df1d2011-08-02 15:43:40 -0700704 list_del_init(&cur_td->td_list);
Sarah Sharpae636742009-04-29 19:02:31 -0700705 }
706 last_unlinked_td = cur_td;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700707 xhci_stop_watchdog_timer_in_irq(xhci, ep);
Sarah Sharpae636742009-04-29 19:02:31 -0700708
709 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
710 if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
Hans de Goede1e3452e2014-08-20 16:41:52 +0300711 xhci_queue_new_dequeue_state(xhci, slot_id, ep_index,
712 ep->stopped_td->urb->stream_id, &deq_state);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -0700713 xhci_ring_cmd_db(xhci);
Sarah Sharpae636742009-04-29 19:02:31 -0700714 } else {
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700715 /* Otherwise ring the doorbell(s) to restart queued transfers */
716 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -0700717 }
Florian Wolter526867c2013-08-14 10:33:16 +0200718
Mathias Nymand97b4f82014-11-27 18:19:16 +0200719 ep->stopped_td = NULL;
Sarah Sharpae636742009-04-29 19:02:31 -0700720
721 /*
722 * Drop the lock and complete the URBs in the cancelled TD list.
723 * New TDs to be cancelled might be added to the end of the list before
724 * we can complete all the URBs for the TDs we already unlinked.
725 * So stop when we've completed the URB for the last TD we unlinked.
726 */
727 do {
Sarah Sharp63a0d9a2009-09-04 10:53:09 -0700728 cur_td = list_entry(ep->cancelled_td_list.next,
Sarah Sharpae636742009-04-29 19:02:31 -0700729 struct xhci_td, cancelled_td_list);
Sarah Sharp585df1d2011-08-02 15:43:40 -0700730 list_del_init(&cur_td->cancelled_td_list);
Sarah Sharpae636742009-04-29 19:02:31 -0700731
732 /* Clean up the cancelled URB */
Sarah Sharpae636742009-04-29 19:02:31 -0700733 /* Doesn't matter what we pass for status, since the core will
734 * just overwrite it (because the URB has been unlinked).
735 */
Xenia Ragiadakou07a37e92013-09-09 13:29:45 +0300736 xhci_giveback_urb_in_irq(xhci, cur_td, 0);
Sarah Sharpae636742009-04-29 19:02:31 -0700737
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700738 /* Stop processing the cancelled list if the watchdog timer is
739 * running.
740 */
741 if (xhci->xhc_state & XHCI_STATE_DYING)
742 return;
Sarah Sharpae636742009-04-29 19:02:31 -0700743 } while (cur_td != last_unlinked_td);
744
745 /* Return to the event handler with xhci->lock re-acquired */
746}
747
Sarah Sharp50e87252014-02-21 09:27:30 -0800748static void xhci_kill_ring_urbs(struct xhci_hcd *xhci, struct xhci_ring *ring)
749{
750 struct xhci_td *cur_td;
751
752 while (!list_empty(&ring->td_list)) {
753 cur_td = list_first_entry(&ring->td_list,
754 struct xhci_td, td_list);
755 list_del_init(&cur_td->td_list);
756 if (!list_empty(&cur_td->cancelled_td_list))
757 list_del_init(&cur_td->cancelled_td_list);
758 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
759 }
760}
761
762static void xhci_kill_endpoint_urbs(struct xhci_hcd *xhci,
763 int slot_id, int ep_index)
764{
765 struct xhci_td *cur_td;
766 struct xhci_virt_ep *ep;
767 struct xhci_ring *ring;
768
769 ep = &xhci->devs[slot_id]->eps[ep_index];
Sarah Sharp21d0e512014-02-21 14:29:02 -0800770 if ((ep->ep_state & EP_HAS_STREAMS) ||
771 (ep->ep_state & EP_GETTING_NO_STREAMS)) {
772 int stream_id;
773
774 for (stream_id = 0; stream_id < ep->stream_info->num_streams;
775 stream_id++) {
776 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
777 "Killing URBs for slot ID %u, ep index %u, stream %u",
778 slot_id, ep_index, stream_id + 1);
779 xhci_kill_ring_urbs(xhci,
780 ep->stream_info->stream_rings[stream_id]);
781 }
782 } else {
783 ring = ep->ring;
784 if (!ring)
785 return;
786 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
787 "Killing URBs for slot ID %u, ep index %u",
788 slot_id, ep_index);
789 xhci_kill_ring_urbs(xhci, ring);
790 }
Sarah Sharp50e87252014-02-21 09:27:30 -0800791 while (!list_empty(&ep->cancelled_td_list)) {
792 cur_td = list_first_entry(&ep->cancelled_td_list,
793 struct xhci_td, cancelled_td_list);
794 list_del_init(&cur_td->cancelled_td_list);
795 xhci_giveback_urb_in_irq(xhci, cur_td, -ESHUTDOWN);
796 }
797}
798
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700799/* Watchdog timer function for when a stop endpoint command fails to complete.
800 * In this case, we assume the host controller is broken or dying or dead. The
801 * host may still be completing some other events, so we have to be careful to
802 * let the event ring handler and the URB dequeueing/enqueueing functions know
803 * through xhci->state.
804 *
805 * The timer may also fire if the host takes a very long time to respond to the
806 * command, and the stop endpoint command completion handler cannot delete the
807 * timer before the timer function is called. Another endpoint cancellation may
808 * sneak in before the timer function can grab the lock, and that may queue
809 * another stop endpoint command and add the timer back. So we cannot use a
810 * simple flag to say whether there is a pending stop endpoint command for a
811 * particular endpoint.
812 *
813 * Instead we use a combination of that flag and a counter for the number of
814 * pending stop endpoint commands. If the timer is the tail end of the last
815 * stop endpoint command, and the endpoint's command is still pending, we assume
816 * the host is dying.
817 */
818void xhci_stop_endpoint_command_watchdog(unsigned long arg)
819{
820 struct xhci_hcd *xhci;
821 struct xhci_virt_ep *ep;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700822 int ret, i, j;
Don Zickusf43d6232011-10-20 23:52:14 -0400823 unsigned long flags;
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700824
825 ep = (struct xhci_virt_ep *) arg;
826 xhci = ep->xhci;
827
Don Zickusf43d6232011-10-20 23:52:14 -0400828 spin_lock_irqsave(&xhci->lock, flags);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700829
830 ep->stop_cmds_pending--;
831 if (xhci->xhc_state & XHCI_STATE_DYING) {
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300832 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
833 "Stop EP timer ran, but another timer marked "
834 "xHCI as DYING, exiting.");
Don Zickusf43d6232011-10-20 23:52:14 -0400835 spin_unlock_irqrestore(&xhci->lock, flags);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700836 return;
837 }
838 if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300839 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
840 "Stop EP timer ran, but no command pending, "
841 "exiting.");
Don Zickusf43d6232011-10-20 23:52:14 -0400842 spin_unlock_irqrestore(&xhci->lock, flags);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700843 return;
844 }
845
846 xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
847 xhci_warn(xhci, "Assuming host is dying, halting host.\n");
848 /* Oops, HC is dead or dying or at least not responding to the stop
849 * endpoint command.
850 */
851 xhci->xhc_state |= XHCI_STATE_DYING;
852 /* Disable interrupts from the host controller and start halting it */
853 xhci_quiesce(xhci);
Don Zickusf43d6232011-10-20 23:52:14 -0400854 spin_unlock_irqrestore(&xhci->lock, flags);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700855
856 ret = xhci_halt(xhci);
857
Don Zickusf43d6232011-10-20 23:52:14 -0400858 spin_lock_irqsave(&xhci->lock, flags);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700859 if (ret < 0) {
860 /* This is bad; the host is not responding to commands and it's
861 * not allowing itself to be halted. At least interrupts are
Sarah Sharpac04e6f2011-03-11 08:47:33 -0800862 * disabled. If we call usb_hc_died(), it will attempt to
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700863 * disconnect all device drivers under this host. Those
864 * disconnect() methods will wait for all URBs to be unlinked,
865 * so we must complete them.
866 */
867 xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
868 xhci_warn(xhci, "Completing active URBs anyway.\n");
869 /* We could turn all TDs on the rings to no-ops. This won't
870 * help if the host has cached part of the ring, and is slow if
871 * we want to preserve the cycle bit. Skip it and hope the host
872 * doesn't touch the memory.
873 */
874 }
875 for (i = 0; i < MAX_HC_SLOTS; i++) {
876 if (!xhci->devs[i])
877 continue;
Sarah Sharp50e87252014-02-21 09:27:30 -0800878 for (j = 0; j < 31; j++)
879 xhci_kill_endpoint_urbs(xhci, i, j);
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700880 }
Don Zickusf43d6232011-10-20 23:52:14 -0400881 spin_unlock_irqrestore(&xhci->lock, flags);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300882 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
883 "Calling usb_hc_died()");
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -0800884 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300885 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
886 "xHCI host controller is dead.");
Sarah Sharp6f5165c2009-10-27 10:57:01 -0700887}
888
Andiry Xub008df62012-03-05 17:49:34 +0800889
890static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
891 struct xhci_virt_device *dev,
892 struct xhci_ring *ep_ring,
893 unsigned int ep_index)
894{
895 union xhci_trb *dequeue_temp;
896 int num_trbs_free_temp;
897 bool revert = false;
898
899 num_trbs_free_temp = ep_ring->num_trbs_free;
900 dequeue_temp = ep_ring->dequeue;
901
Sarah Sharp0d9f78a2012-06-21 16:28:30 -0700902 /* If we get two back-to-back stalls, and the first stalled transfer
903 * ends just before a link TRB, the dequeue pointer will be left on
904 * the link TRB by the code in the while loop. So we have to update
905 * the dequeue pointer one segment further, or we'll jump off
906 * the segment into la-la-land.
907 */
908 if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
909 ep_ring->deq_seg = ep_ring->deq_seg->next;
910 ep_ring->dequeue = ep_ring->deq_seg->trbs;
911 }
912
Andiry Xub008df62012-03-05 17:49:34 +0800913 while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
914 /* We have more usable TRBs */
915 ep_ring->num_trbs_free++;
916 ep_ring->dequeue++;
917 if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
918 ep_ring->dequeue)) {
919 if (ep_ring->dequeue ==
920 dev->eps[ep_index].queued_deq_ptr)
921 break;
922 ep_ring->deq_seg = ep_ring->deq_seg->next;
923 ep_ring->dequeue = ep_ring->deq_seg->trbs;
924 }
925 if (ep_ring->dequeue == dequeue_temp) {
926 revert = true;
927 break;
928 }
929 }
930
931 if (revert) {
932 xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
933 ep_ring->num_trbs_free = num_trbs_free_temp;
934 }
935}
936
Sarah Sharpae636742009-04-29 19:02:31 -0700937/*
938 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
939 * we need to clear the set deq pending flag in the endpoint ring state, so that
940 * the TD queueing code can ring the doorbell again. We also need to ring the
941 * endpoint doorbell to restart the ring, but only if there aren't more
942 * cancellations pending.
943 */
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +0300944static void xhci_handle_cmd_set_deq(struct xhci_hcd *xhci, int slot_id,
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +0300945 union xhci_trb *trb, u32 cmd_comp_code)
Sarah Sharpae636742009-04-29 19:02:31 -0700946{
Sarah Sharpae636742009-04-29 19:02:31 -0700947 unsigned int ep_index;
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700948 unsigned int stream_id;
Sarah Sharpae636742009-04-29 19:02:31 -0700949 struct xhci_ring *ep_ring;
950 struct xhci_virt_device *dev;
Hans de Goede9aad95e2013-10-04 00:29:49 +0200951 struct xhci_virt_ep *ep;
John Yound115b042009-07-27 12:05:15 -0700952 struct xhci_ep_ctx *ep_ctx;
953 struct xhci_slot_ctx *slot_ctx;
Sarah Sharpae636742009-04-29 19:02:31 -0700954
Matt Evans28ccd292011-03-29 13:40:46 +1100955 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
956 stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
Sarah Sharpae636742009-04-29 19:02:31 -0700957 dev = xhci->devs[slot_id];
Hans de Goede9aad95e2013-10-04 00:29:49 +0200958 ep = &dev->eps[ep_index];
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700959
960 ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
961 if (!ep_ring) {
Oliver Neukume587b8b2014-01-08 17:13:11 +0100962 xhci_warn(xhci, "WARN Set TR deq ptr command for freed stream ID %u\n",
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700963 stream_id);
964 /* XXX: Harmless??? */
Hans de Goede0d4976e2014-08-20 16:41:55 +0300965 goto cleanup;
Sarah Sharpe9df17e2010-04-02 15:34:43 -0700966 }
967
John Yound115b042009-07-27 12:05:15 -0700968 ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
969 slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
Sarah Sharpae636742009-04-29 19:02:31 -0700970
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +0300971 if (cmd_comp_code != COMP_SUCCESS) {
Sarah Sharpae636742009-04-29 19:02:31 -0700972 unsigned int ep_state;
973 unsigned int slot_state;
974
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +0300975 switch (cmd_comp_code) {
Sarah Sharpae636742009-04-29 19:02:31 -0700976 case COMP_TRB_ERR:
Oliver Neukume587b8b2014-01-08 17:13:11 +0100977 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because of stream ID configuration\n");
Sarah Sharpae636742009-04-29 19:02:31 -0700978 break;
979 case COMP_CTX_STATE:
Oliver Neukume587b8b2014-01-08 17:13:11 +0100980 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due to incorrect slot or ep state.\n");
Matt Evans28ccd292011-03-29 13:40:46 +1100981 ep_state = le32_to_cpu(ep_ctx->ep_info);
Sarah Sharpae636742009-04-29 19:02:31 -0700982 ep_state &= EP_STATE_MASK;
Matt Evans28ccd292011-03-29 13:40:46 +1100983 slot_state = le32_to_cpu(slot_ctx->dev_state);
Sarah Sharpae636742009-04-29 19:02:31 -0700984 slot_state = GET_SLOT_STATE(slot_state);
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +0300985 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
986 "Slot state = %u, EP state = %u",
Sarah Sharpae636742009-04-29 19:02:31 -0700987 slot_state, ep_state);
988 break;
989 case COMP_EBADSLT:
Oliver Neukume587b8b2014-01-08 17:13:11 +0100990 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because slot %u was not enabled.\n",
991 slot_id);
Sarah Sharpae636742009-04-29 19:02:31 -0700992 break;
993 default:
Oliver Neukume587b8b2014-01-08 17:13:11 +0100994 xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown completion code of %u.\n",
995 cmd_comp_code);
Sarah Sharpae636742009-04-29 19:02:31 -0700996 break;
997 }
998 /* OK what do we do now? The endpoint state is hosed, and we
999 * should never get to this point if the synchronization between
1000 * queueing, and endpoint state are correct. This might happen
1001 * if the device gets disconnected after we've finished
1002 * cancelling URBs, which might not be an error...
1003 */
1004 } else {
Hans de Goede9aad95e2013-10-04 00:29:49 +02001005 u64 deq;
1006 /* 4.6.10 deq ptr is written to the stream ctx for streams */
1007 if (ep->ep_state & EP_HAS_STREAMS) {
1008 struct xhci_stream_ctx *ctx =
1009 &ep->stream_info->stream_ctx_array[stream_id];
1010 deq = le64_to_cpu(ctx->stream_ring) & SCTX_DEQ_MASK;
1011 } else {
1012 deq = le64_to_cpu(ep_ctx->deq) & ~EP_CTX_CYCLE_MASK;
1013 }
Xenia Ragiadakouaa50b292013-08-14 06:33:54 +03001014 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
Hans de Goede9aad95e2013-10-04 00:29:49 +02001015 "Successful Set TR Deq Ptr cmd, deq = @%08llx", deq);
1016 if (xhci_trb_virt_to_dma(ep->queued_deq_seg,
1017 ep->queued_deq_ptr) == deq) {
Sarah Sharpbf161e82011-02-23 15:46:42 -08001018 /* Update the ring's dequeue segment and dequeue pointer
1019 * to reflect the new position.
1020 */
Andiry Xub008df62012-03-05 17:49:34 +08001021 update_ring_for_set_deq_completion(xhci, dev,
1022 ep_ring, ep_index);
Sarah Sharpbf161e82011-02-23 15:46:42 -08001023 } else {
Oliver Neukume587b8b2014-01-08 17:13:11 +01001024 xhci_warn(xhci, "Mismatch between completed Set TR Deq Ptr command & xHCI internal state.\n");
Sarah Sharpbf161e82011-02-23 15:46:42 -08001025 xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
Hans de Goede9aad95e2013-10-04 00:29:49 +02001026 ep->queued_deq_seg, ep->queued_deq_ptr);
Sarah Sharpbf161e82011-02-23 15:46:42 -08001027 }
Sarah Sharpae636742009-04-29 19:02:31 -07001028 }
1029
Hans de Goede0d4976e2014-08-20 16:41:55 +03001030cleanup:
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001031 dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
Sarah Sharpbf161e82011-02-23 15:46:42 -08001032 dev->eps[ep_index].queued_deq_seg = NULL;
1033 dev->eps[ep_index].queued_deq_ptr = NULL;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001034 /* Restart any rings with pending URBs */
1035 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
Sarah Sharpae636742009-04-29 19:02:31 -07001036}
1037
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +03001038static void xhci_handle_cmd_reset_ep(struct xhci_hcd *xhci, int slot_id,
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +03001039 union xhci_trb *trb, u32 cmd_comp_code)
Sarah Sharpa1587d92009-07-27 12:03:15 -07001040{
Sarah Sharpa1587d92009-07-27 12:03:15 -07001041 unsigned int ep_index;
1042
Matt Evans28ccd292011-03-29 13:40:46 +11001043 ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
Sarah Sharpa1587d92009-07-27 12:03:15 -07001044 /* This command will only fail if the endpoint wasn't halted,
1045 * but we don't care.
1046 */
Xenia Ragiadakoua0254322013-08-06 07:52:46 +03001047 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +03001048 "Ignoring reset ep completion code of %u", cmd_comp_code);
Sarah Sharpa1587d92009-07-27 12:03:15 -07001049
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001050 /* HW with the reset endpoint quirk needs to have a configure endpoint
1051 * command complete before the endpoint can be used. Queue that here
1052 * because the HW can't handle two commands being queued in a row.
1053 */
1054 if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
Mathias Nymanddba5cd2014-05-08 19:26:00 +03001055 struct xhci_command *command;
1056 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
Hans de Goedea0ee6192014-07-25 22:01:21 +02001057 if (!command) {
1058 xhci_warn(xhci, "WARN Cannot submit cfg ep: ENOMEM\n");
1059 return;
1060 }
Xenia Ragiadakou4bdfe4c2013-08-06 07:52:45 +03001061 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1062 "Queueing configure endpoint command");
Mathias Nymanddba5cd2014-05-08 19:26:00 +03001063 xhci_queue_configure_endpoint(xhci, command,
Sarah Sharp913a8a32009-09-04 10:53:13 -07001064 xhci->devs[slot_id]->in_ctx->dma, slot_id,
1065 false);
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001066 xhci_ring_cmd_db(xhci);
1067 } else {
Mathias Nymanc3492db2014-11-18 11:27:11 +02001068 /* Clear our internal halted state */
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07001069 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
Sarah Sharpac9d8fe2009-08-07 14:04:55 -07001070 }
Sarah Sharpa1587d92009-07-27 12:03:15 -07001071}
Sarah Sharpae636742009-04-29 19:02:31 -07001072
Xenia Ragiadakoub244b432013-09-09 13:29:47 +03001073static void xhci_handle_cmd_enable_slot(struct xhci_hcd *xhci, int slot_id,
1074 u32 cmd_comp_code)
1075{
1076 if (cmd_comp_code == COMP_SUCCESS)
1077 xhci->slot_id = slot_id;
1078 else
1079 xhci->slot_id = 0;
Xenia Ragiadakoub244b432013-09-09 13:29:47 +03001080}
1081
Xenia Ragiadakou6c02dd12013-09-09 13:29:48 +03001082static void xhci_handle_cmd_disable_slot(struct xhci_hcd *xhci, int slot_id)
1083{
1084 struct xhci_virt_device *virt_dev;
1085
1086 virt_dev = xhci->devs[slot_id];
1087 if (!virt_dev)
1088 return;
1089 if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1090 /* Delete default control endpoint resources */
1091 xhci_free_device_endpoint_resources(xhci, virt_dev, true);
1092 xhci_free_virt_device(xhci, slot_id);
1093}
1094
Xenia Ragiadakou6ed46d32013-09-09 13:29:55 +03001095static void xhci_handle_cmd_config_ep(struct xhci_hcd *xhci, int slot_id,
1096 struct xhci_event_cmd *event, u32 cmd_comp_code)
1097{
1098 struct xhci_virt_device *virt_dev;
1099 struct xhci_input_control_ctx *ctrl_ctx;
1100 unsigned int ep_index;
1101 unsigned int ep_state;
1102 u32 add_flags, drop_flags;
1103
Xenia Ragiadakou6ed46d32013-09-09 13:29:55 +03001104 /*
1105 * Configure endpoint commands can come from the USB core
1106 * configuration or alt setting changes, or because the HW
1107 * needed an extra configure endpoint command after a reset
1108 * endpoint command or streams were being configured.
1109 * If the command was for a halted endpoint, the xHCI driver
1110 * is not waiting on the configure endpoint command.
1111 */
Mathias Nyman9ea18332014-05-08 19:26:02 +03001112 virt_dev = xhci->devs[slot_id];
Lin Wang4daf9df2015-01-09 16:06:31 +02001113 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
Xenia Ragiadakou6ed46d32013-09-09 13:29:55 +03001114 if (!ctrl_ctx) {
1115 xhci_warn(xhci, "Could not get input context, bad type.\n");
1116 return;
1117 }
1118
1119 add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1120 drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1121 /* Input ctx add_flags are the endpoint index plus one */
1122 ep_index = xhci_last_valid_endpoint(add_flags) - 1;
1123
1124 /* A usb_set_interface() call directly after clearing a halted
1125 * condition may race on this quirky hardware. Not worth
1126 * worrying about, since this is prototype hardware. Not sure
1127 * if this will work for streams, but streams support was
1128 * untested on this prototype.
1129 */
1130 if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1131 ep_index != (unsigned int) -1 &&
1132 add_flags - SLOT_FLAG == drop_flags) {
1133 ep_state = virt_dev->eps[ep_index].ep_state;
1134 if (!(ep_state & EP_HALTED))
Mathias Nymanddba5cd2014-05-08 19:26:00 +03001135 return;
Xenia Ragiadakou6ed46d32013-09-09 13:29:55 +03001136 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1137 "Completed config ep cmd - "
1138 "last ep index = %d, state = %d",
1139 ep_index, ep_state);
1140 /* Clear internal halted state and restart ring(s) */
1141 virt_dev->eps[ep_index].ep_state &= ~EP_HALTED;
1142 ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1143 return;
1144 }
Xenia Ragiadakou6ed46d32013-09-09 13:29:55 +03001145 return;
1146}
1147
Xenia Ragiadakouf6813212013-09-09 13:29:51 +03001148static void xhci_handle_cmd_reset_dev(struct xhci_hcd *xhci, int slot_id,
1149 struct xhci_event_cmd *event)
1150{
Xenia Ragiadakouf6813212013-09-09 13:29:51 +03001151 xhci_dbg(xhci, "Completed reset device command.\n");
Mathias Nyman9ea18332014-05-08 19:26:02 +03001152 if (!xhci->devs[slot_id])
Xenia Ragiadakouf6813212013-09-09 13:29:51 +03001153 xhci_warn(xhci, "Reset device command completion "
1154 "for disabled slot %u\n", slot_id);
1155}
1156
Xenia Ragiadakou2c070822013-09-09 13:29:52 +03001157static void xhci_handle_cmd_nec_get_fw(struct xhci_hcd *xhci,
1158 struct xhci_event_cmd *event)
1159{
1160 if (!(xhci->quirks & XHCI_NEC_HOST)) {
1161 xhci->error_bitmask |= 1 << 6;
1162 return;
1163 }
1164 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1165 "NEC firmware version %2x.%02x",
1166 NEC_FW_MAJOR(le32_to_cpu(event->status)),
1167 NEC_FW_MINOR(le32_to_cpu(event->status)));
1168}
1169
Mathias Nyman9ea18332014-05-08 19:26:02 +03001170static void xhci_complete_del_and_free_cmd(struct xhci_command *cmd, u32 status)
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001171{
1172 list_del(&cmd->cmd_list);
Mathias Nyman9ea18332014-05-08 19:26:02 +03001173
1174 if (cmd->completion) {
1175 cmd->status = status;
1176 complete(cmd->completion);
1177 } else {
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001178 kfree(cmd);
Mathias Nyman9ea18332014-05-08 19:26:02 +03001179 }
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001180}
1181
1182void xhci_cleanup_command_queue(struct xhci_hcd *xhci)
1183{
1184 struct xhci_command *cur_cmd, *tmp_cmd;
1185 list_for_each_entry_safe(cur_cmd, tmp_cmd, &xhci->cmd_list, cmd_list)
Mathias Nyman9ea18332014-05-08 19:26:02 +03001186 xhci_complete_del_and_free_cmd(cur_cmd, COMP_CMD_ABORT);
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001187}
1188
Mathias Nymanc311e392014-05-08 19:26:03 +03001189/*
1190 * Turn all commands on command ring with status set to "aborted" to no-op trbs.
1191 * If there are other commands waiting then restart the ring and kick the timer.
1192 * This must be called with command ring stopped and xhci->lock held.
1193 */
1194static void xhci_handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1195 struct xhci_command *cur_cmd)
1196{
1197 struct xhci_command *i_cmd, *tmp_cmd;
1198 u32 cycle_state;
1199
1200 /* Turn all aborted commands in list to no-ops, then restart */
1201 list_for_each_entry_safe(i_cmd, tmp_cmd, &xhci->cmd_list,
1202 cmd_list) {
1203
1204 if (i_cmd->status != COMP_CMD_ABORT)
1205 continue;
1206
1207 i_cmd->status = COMP_CMD_STOP;
1208
1209 xhci_dbg(xhci, "Turn aborted command %p to no-op\n",
1210 i_cmd->command_trb);
1211 /* get cycle state from the original cmd trb */
1212 cycle_state = le32_to_cpu(
1213 i_cmd->command_trb->generic.field[3]) & TRB_CYCLE;
1214 /* modify the command trb to no-op command */
1215 i_cmd->command_trb->generic.field[0] = 0;
1216 i_cmd->command_trb->generic.field[1] = 0;
1217 i_cmd->command_trb->generic.field[2] = 0;
1218 i_cmd->command_trb->generic.field[3] = cpu_to_le32(
1219 TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1220
1221 /*
1222 * caller waiting for completion is called when command
1223 * completion event is received for these no-op commands
1224 */
1225 }
1226
1227 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1228
1229 /* ring command ring doorbell to restart the command ring */
1230 if ((xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue) &&
1231 !(xhci->xhc_state & XHCI_STATE_DYING)) {
1232 xhci->current_cmd = cur_cmd;
1233 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1234 xhci_ring_cmd_db(xhci);
1235 }
1236 return;
1237}
1238
1239
1240void xhci_handle_command_timeout(unsigned long data)
1241{
1242 struct xhci_hcd *xhci;
1243 int ret;
1244 unsigned long flags;
1245 u64 hw_ring_state;
1246 struct xhci_command *cur_cmd = NULL;
1247 xhci = (struct xhci_hcd *) data;
1248
1249 /* mark this command to be cancelled */
1250 spin_lock_irqsave(&xhci->lock, flags);
1251 if (xhci->current_cmd) {
1252 cur_cmd = xhci->current_cmd;
1253 cur_cmd->status = COMP_CMD_ABORT;
1254 }
1255
1256
1257 /* Make sure command ring is running before aborting it */
1258 hw_ring_state = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
1259 if ((xhci->cmd_ring_state & CMD_RING_STATE_RUNNING) &&
1260 (hw_ring_state & CMD_RING_RUNNING)) {
1261
1262 spin_unlock_irqrestore(&xhci->lock, flags);
1263 xhci_dbg(xhci, "Command timeout\n");
1264 ret = xhci_abort_cmd_ring(xhci);
1265 if (unlikely(ret == -ESHUTDOWN)) {
1266 xhci_err(xhci, "Abort command ring failed\n");
1267 xhci_cleanup_command_queue(xhci);
1268 usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
1269 xhci_dbg(xhci, "xHCI host controller is dead.\n");
1270 }
1271 return;
1272 }
1273 /* command timeout on stopped ring, ring can't be aborted */
1274 xhci_dbg(xhci, "Command timeout on stopped ring\n");
1275 xhci_handle_stopped_cmd_ring(xhci, xhci->current_cmd);
1276 spin_unlock_irqrestore(&xhci->lock, flags);
1277 return;
1278}
1279
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001280static void handle_cmd_completion(struct xhci_hcd *xhci,
1281 struct xhci_event_cmd *event)
1282{
Matt Evans28ccd292011-03-29 13:40:46 +11001283 int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001284 u64 cmd_dma;
1285 dma_addr_t cmd_dequeue_dma;
Xenia Ragiadakoue7a79a12013-09-09 13:29:56 +03001286 u32 cmd_comp_code;
Xenia Ragiadakou9124b122013-09-09 13:29:57 +03001287 union xhci_trb *cmd_trb;
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001288 struct xhci_command *cmd;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001289 u32 cmd_type;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001290
Matt Evans28ccd292011-03-29 13:40:46 +11001291 cmd_dma = le64_to_cpu(event->cmd_trb);
Xenia Ragiadakou9124b122013-09-09 13:29:57 +03001292 cmd_trb = xhci->cmd_ring->dequeue;
Sarah Sharp23e3be12009-04-29 19:05:20 -07001293 cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
Xenia Ragiadakou9124b122013-09-09 13:29:57 +03001294 cmd_trb);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001295 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1296 if (cmd_dequeue_dma == 0) {
1297 xhci->error_bitmask |= 1 << 4;
1298 return;
1299 }
1300 /* Does the DMA address match our internal dequeue pointer address? */
1301 if (cmd_dma != (u64) cmd_dequeue_dma) {
1302 xhci->error_bitmask |= 1 << 5;
1303 return;
1304 }
Elric Fub63f4052012-06-27 16:55:43 +08001305
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001306 cmd = list_entry(xhci->cmd_list.next, struct xhci_command, cmd_list);
1307
1308 if (cmd->command_trb != xhci->cmd_ring->dequeue) {
1309 xhci_err(xhci,
1310 "Command completion event does not match command\n");
1311 return;
1312 }
Mathias Nymanc311e392014-05-08 19:26:03 +03001313
1314 del_timer(&xhci->cmd_timer);
1315
Xenia Ragiadakou9124b122013-09-09 13:29:57 +03001316 trace_xhci_cmd_completion(cmd_trb, (struct xhci_generic_trb *) event);
Xenia Ragiadakou63a23b9a2013-08-06 07:52:48 +03001317
Xenia Ragiadakoue7a79a12013-09-09 13:29:56 +03001318 cmd_comp_code = GET_COMP_CODE(le32_to_cpu(event->status));
Mathias Nymanc311e392014-05-08 19:26:03 +03001319
1320 /* If CMD ring stopped we own the trbs between enqueue and dequeue */
1321 if (cmd_comp_code == COMP_CMD_STOP) {
1322 xhci_handle_stopped_cmd_ring(xhci, cmd);
1323 return;
1324 }
1325 /*
1326 * Host aborted the command ring, check if the current command was
1327 * supposed to be aborted, otherwise continue normally.
1328 * The command ring is stopped now, but the xHC will issue a Command
1329 * Ring Stopped event which will cause us to restart it.
1330 */
1331 if (cmd_comp_code == COMP_CMD_ABORT) {
1332 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1333 if (cmd->status == COMP_CMD_ABORT)
1334 goto event_handled;
Elric Fub63f4052012-06-27 16:55:43 +08001335 }
1336
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001337 cmd_type = TRB_FIELD_TO_TYPE(le32_to_cpu(cmd_trb->generic.field[3]));
1338 switch (cmd_type) {
1339 case TRB_ENABLE_SLOT:
Xenia Ragiadakoue7a79a12013-09-09 13:29:56 +03001340 xhci_handle_cmd_enable_slot(xhci, slot_id, cmd_comp_code);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001341 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001342 case TRB_DISABLE_SLOT:
Xenia Ragiadakou6c02dd12013-09-09 13:29:48 +03001343 xhci_handle_cmd_disable_slot(xhci, slot_id);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001344 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001345 case TRB_CONFIG_EP:
Mathias Nyman9ea18332014-05-08 19:26:02 +03001346 if (!cmd->completion)
1347 xhci_handle_cmd_config_ep(xhci, slot_id, event,
1348 cmd_comp_code);
Sarah Sharpf94e01862009-04-27 19:58:38 -07001349 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001350 case TRB_EVAL_CONTEXT:
Sarah Sharp2d3f1fa2009-08-07 14:04:49 -07001351 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001352 case TRB_ADDR_DEV:
Sarah Sharp3ffbba92009-04-27 19:57:38 -07001353 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001354 case TRB_STOP_RING:
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +03001355 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1356 le32_to_cpu(cmd_trb->generic.field[3])));
1357 xhci_handle_cmd_stop_ep(xhci, slot_id, cmd_trb, event);
Sarah Sharpae636742009-04-29 19:02:31 -07001358 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001359 case TRB_SET_DEQ:
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +03001360 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1361 le32_to_cpu(cmd_trb->generic.field[3])));
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +03001362 xhci_handle_cmd_set_deq(xhci, slot_id, cmd_trb, cmd_comp_code);
Sarah Sharpae636742009-04-29 19:02:31 -07001363 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001364 case TRB_CMD_NOOP:
Mathias Nymanc311e392014-05-08 19:26:03 +03001365 /* Is this an aborted command turned to NO-OP? */
1366 if (cmd->status == COMP_CMD_STOP)
1367 cmd_comp_code = COMP_CMD_STOP;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001368 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001369 case TRB_RESET_EP:
Xenia Ragiadakoub8200c92013-09-09 13:30:00 +03001370 WARN_ON(slot_id != TRB_TO_SLOT_ID(
1371 le32_to_cpu(cmd_trb->generic.field[3])));
Xenia Ragiadakouc69a0592013-09-09 13:30:01 +03001372 xhci_handle_cmd_reset_ep(xhci, slot_id, cmd_trb, cmd_comp_code);
Sarah Sharpa1587d92009-07-27 12:03:15 -07001373 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001374 case TRB_RESET_DEV:
Mathias Nyman6fcfb0d2014-06-24 17:14:40 +03001375 /* SLOT_ID field in reset device cmd completion event TRB is 0.
1376 * Use the SLOT_ID from the command TRB instead (xhci 4.6.11)
1377 */
1378 slot_id = TRB_TO_SLOT_ID(
1379 le32_to_cpu(cmd_trb->generic.field[3]));
Xenia Ragiadakouf6813212013-09-09 13:29:51 +03001380 xhci_handle_cmd_reset_dev(xhci, slot_id, event);
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08001381 break;
Xenia Ragiadakoub54fc462013-09-09 13:29:58 +03001382 case TRB_NEC_GET_FW:
Xenia Ragiadakou2c070822013-09-09 13:29:52 +03001383 xhci_handle_cmd_nec_get_fw(xhci, event);
Sarah Sharp02386342010-05-24 13:25:28 -07001384 break;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001385 default:
1386 /* Skip over unknown commands on the event ring */
1387 xhci->error_bitmask |= 1 << 6;
1388 break;
1389 }
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001390
Mathias Nymanc311e392014-05-08 19:26:03 +03001391 /* restart timer if this wasn't the last command */
1392 if (cmd->cmd_list.next != &xhci->cmd_list) {
1393 xhci->current_cmd = list_entry(cmd->cmd_list.next,
1394 struct xhci_command, cmd_list);
1395 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
1396 }
1397
1398event_handled:
Mathias Nyman9ea18332014-05-08 19:26:02 +03001399 xhci_complete_del_and_free_cmd(cmd, cmd_comp_code);
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03001400
Andiry Xu3b72fca2012-03-05 17:49:32 +08001401 inc_deq(xhci, xhci->cmd_ring);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07001402}
1403
Sarah Sharp02386342010-05-24 13:25:28 -07001404static void handle_vendor_event(struct xhci_hcd *xhci,
1405 union xhci_trb *event)
1406{
1407 u32 trb_type;
1408
Matt Evans28ccd292011-03-29 13:40:46 +11001409 trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
Sarah Sharp02386342010-05-24 13:25:28 -07001410 xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1411 if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1412 handle_cmd_completion(xhci, &event->event_cmd);
1413}
1414
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001415/* @port_id: the one-based port ID from the hardware (indexed from array of all
1416 * port registers -- USB 3.0 and USB 2.0).
1417 *
1418 * Returns a zero-based port number, which is suitable for indexing into each of
1419 * the split roothubs' port arrays and bus state arrays.
Sarah Sharpd0cd5d42011-11-14 17:51:39 -08001420 * Add one to it in order to call xhci_find_slot_id_by_port.
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001421 */
1422static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1423 struct xhci_hcd *xhci, u32 port_id)
1424{
1425 unsigned int i;
1426 unsigned int num_similar_speed_ports = 0;
1427
1428 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1429 * and usb2_ports are 0-based indexes. Count the number of similar
1430 * speed ports, up to 1 port before this port.
1431 */
1432 for (i = 0; i < (port_id - 1); i++) {
1433 u8 port_speed = xhci->port_array[i];
1434
1435 /*
1436 * Skip ports that don't have known speeds, or have duplicate
1437 * Extended Capabilities port speed entries.
1438 */
Dan Carpenter22e04872011-03-17 22:39:49 +03001439 if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001440 continue;
1441
1442 /*
1443 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1444 * 1.1 ports are under the USB 2.0 hub. If the port speed
1445 * matches the device speed, it's a similar speed port.
1446 */
1447 if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1448 num_similar_speed_ports++;
1449 }
1450 return num_similar_speed_ports;
1451}
1452
Sarah Sharp623bef92011-11-11 14:57:33 -08001453static void handle_device_notification(struct xhci_hcd *xhci,
1454 union xhci_trb *event)
1455{
1456 u32 slot_id;
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001457 struct usb_device *udev;
Sarah Sharp623bef92011-11-11 14:57:33 -08001458
Xenia Ragiadakou7e76ad42013-09-09 21:03:10 +03001459 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->generic.field[3]));
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001460 if (!xhci->devs[slot_id]) {
Sarah Sharp623bef92011-11-11 14:57:33 -08001461 xhci_warn(xhci, "Device Notification event for "
1462 "unused slot %u\n", slot_id);
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001463 return;
1464 }
1465
1466 xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1467 slot_id);
1468 udev = xhci->devs[slot_id]->udev;
1469 if (udev && udev->parent)
1470 usb_wakeup_notification(udev->parent, udev->portnum);
Sarah Sharp623bef92011-11-11 14:57:33 -08001471}
1472
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001473static void handle_port_status(struct xhci_hcd *xhci,
1474 union xhci_trb *event)
1475{
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001476 struct usb_hcd *hcd;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001477 u32 port_id;
Andiry Xu56192532010-10-14 07:23:00 -07001478 u32 temp, temp1;
Sarah Sharp518e8482010-12-15 11:56:29 -08001479 int max_ports;
Andiry Xu56192532010-10-14 07:23:00 -07001480 int slot_id;
Sarah Sharp5308a912010-12-01 11:34:59 -08001481 unsigned int faked_port_index;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001482 u8 major_revision;
Sarah Sharp20b67cf2010-12-15 12:47:14 -08001483 struct xhci_bus_state *bus_state;
Matt Evans28ccd292011-03-29 13:40:46 +11001484 __le32 __iomem **port_array;
Sarah Sharp386139d2011-03-24 08:02:58 -07001485 bool bogus_port_status = false;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001486
1487 /* Port status change events always have a successful completion code */
Matt Evans28ccd292011-03-29 13:40:46 +11001488 if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001489 xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1490 xhci->error_bitmask |= 1 << 8;
1491 }
Matt Evans28ccd292011-03-29 13:40:46 +11001492 port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001493 xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1494
Sarah Sharp518e8482010-12-15 11:56:29 -08001495 max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1496 if ((port_id <= 0) || (port_id > max_ports)) {
Andiry Xu56192532010-10-14 07:23:00 -07001497 xhci_warn(xhci, "Invalid port id %d\n", port_id);
Peter Chen09ce0c02013-03-20 09:30:00 +08001498 inc_deq(xhci, xhci->event_ring);
1499 return;
Andiry Xu56192532010-10-14 07:23:00 -07001500 }
1501
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001502 /* Figure out which usb_hcd this port is attached to:
1503 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1504 */
1505 major_revision = xhci->port_array[port_id - 1];
Peter Chen09ce0c02013-03-20 09:30:00 +08001506
1507 /* Find the right roothub. */
1508 hcd = xhci_to_hcd(xhci);
1509 if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1510 hcd = xhci->shared_hcd;
1511
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001512 if (major_revision == 0) {
1513 xhci_warn(xhci, "Event for port %u not in "
1514 "Extended Capabilities, ignoring.\n",
1515 port_id);
Sarah Sharp386139d2011-03-24 08:02:58 -07001516 bogus_port_status = true;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001517 goto cleanup;
1518 }
Dan Carpenter22e04872011-03-17 22:39:49 +03001519 if (major_revision == DUPLICATE_ENTRY) {
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001520 xhci_warn(xhci, "Event for port %u duplicated in"
1521 "Extended Capabilities, ignoring.\n",
1522 port_id);
Sarah Sharp386139d2011-03-24 08:02:58 -07001523 bogus_port_status = true;
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001524 goto cleanup;
Sarah Sharp5308a912010-12-01 11:34:59 -08001525 }
1526
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001527 /*
1528 * Hardware port IDs reported by a Port Status Change Event include USB
1529 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1530 * resume event, but we first need to translate the hardware port ID
1531 * into the index into the ports on the correct split roothub, and the
1532 * correct bus_state structure.
1533 */
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001534 bus_state = &xhci->bus_state[hcd_index(hcd)];
1535 if (hcd->speed == HCD_USB3)
1536 port_array = xhci->usb3_ports;
1537 else
1538 port_array = xhci->usb2_ports;
1539 /* Find the faked port hub number */
1540 faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1541 port_id);
1542
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +02001543 temp = readl(port_array[faked_port_index]);
Sarah Sharp7111ebc2010-12-14 13:24:55 -08001544 if (hcd->state == HC_STATE_SUSPENDED) {
Andiry Xu56192532010-10-14 07:23:00 -07001545 xhci_dbg(xhci, "resume root hub\n");
1546 usb_hcd_resume_root_hub(hcd);
1547 }
1548
Zhuang Jin Canfac42712015-07-21 17:20:30 +03001549 if (hcd->speed == HCD_USB3 && (temp & PORT_PLS_MASK) == XDEV_INACTIVE)
1550 bus_state->port_remote_wakeup &= ~(1 << faked_port_index);
1551
Andiry Xu56192532010-10-14 07:23:00 -07001552 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1553 xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1554
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +02001555 temp1 = readl(&xhci->op_regs->command);
Andiry Xu56192532010-10-14 07:23:00 -07001556 if (!(temp1 & CMD_RUN)) {
1557 xhci_warn(xhci, "xHC is not running.\n");
1558 goto cleanup;
1559 }
1560
1561 if (DEV_SUPERSPEED(temp)) {
Sarah Sharpd93814c2012-01-24 16:39:02 -08001562 xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001563 /* Set a flag to say the port signaled remote wakeup,
1564 * so we can tell the difference between the end of
1565 * device and host initiated resume.
1566 */
1567 bus_state->port_remote_wakeup |= 1 << faked_port_index;
Sarah Sharpd93814c2012-01-24 16:39:02 -08001568 xhci_test_and_clear_bit(xhci, port_array,
1569 faked_port_index, PORT_PLC);
Andiry Xuc9682df2011-09-23 14:19:48 -07001570 xhci_set_link_state(xhci, port_array, faked_port_index,
1571 XDEV_U0);
Sarah Sharpd93814c2012-01-24 16:39:02 -08001572 /* Need to wait until the next link state change
1573 * indicates the device is actually in U0.
1574 */
1575 bogus_port_status = true;
1576 goto cleanup;
Andiry Xu56192532010-10-14 07:23:00 -07001577 } else {
1578 xhci_dbg(xhci, "resume HS port %d\n", port_id);
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001579 bus_state->resume_done[faked_port_index] = jiffies +
Felipe Balbib9e45182015-02-13 14:39:13 -06001580 msecs_to_jiffies(USB_RESUME_TIMEOUT);
Andiry Xuf370b992012-04-14 02:54:30 +08001581 set_bit(faked_port_index, &bus_state->resuming_ports);
Andiry Xu56192532010-10-14 07:23:00 -07001582 mod_timer(&hcd->rh_timer,
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001583 bus_state->resume_done[faked_port_index]);
Andiry Xu56192532010-10-14 07:23:00 -07001584 /* Do the rest in GetPortStatus */
1585 }
1586 }
1587
Sarah Sharpd93814c2012-01-24 16:39:02 -08001588 if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1589 DEV_SUPERSPEED(temp)) {
1590 xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001591 /* We've just brought the device into U0 through either the
1592 * Resume state after a device remote wakeup, or through the
1593 * U3Exit state after a host-initiated resume. If it's a device
1594 * initiated remote wake, don't pass up the link state change,
1595 * so the roothub behavior is consistent with external
1596 * USB 3.0 hub behavior.
1597 */
Sarah Sharpd93814c2012-01-24 16:39:02 -08001598 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1599 faked_port_index + 1);
1600 if (slot_id && xhci->devs[slot_id])
1601 xhci_ring_device(xhci, slot_id);
Nickolai Zeldovichba7b5c22013-01-07 22:39:31 -05001602 if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
Sarah Sharp4ee823b2011-11-14 18:00:01 -08001603 bus_state->port_remote_wakeup &=
1604 ~(1 << faked_port_index);
1605 xhci_test_and_clear_bit(xhci, port_array,
1606 faked_port_index, PORT_PLC);
1607 usb_wakeup_notification(hcd->self.root_hub,
1608 faked_port_index + 1);
1609 bogus_port_status = true;
1610 goto cleanup;
1611 }
Sarah Sharpd93814c2012-01-24 16:39:02 -08001612 }
1613
Sarah Sharp8b3d4572013-08-20 08:12:12 -07001614 /*
1615 * Check to see if xhci-hub.c is waiting on RExit to U0 transition (or
1616 * RExit to a disconnect state). If so, let the the driver know it's
1617 * out of the RExit state.
1618 */
1619 if (!DEV_SUPERSPEED(temp) &&
1620 test_and_clear_bit(faked_port_index,
1621 &bus_state->rexit_ports)) {
1622 complete(&bus_state->rexit_done[faked_port_index]);
1623 bogus_port_status = true;
1624 goto cleanup;
1625 }
1626
Andiry Xu6fd45622011-09-23 14:19:50 -07001627 if (hcd->speed != HCD_USB3)
1628 xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1629 PORT_PLC);
1630
Andiry Xu56192532010-10-14 07:23:00 -07001631cleanup:
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001632 /* Update event ring dequeue pointer before dropping the lock */
Andiry Xu3b72fca2012-03-05 17:49:32 +08001633 inc_deq(xhci, xhci->event_ring);
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001634
Sarah Sharp386139d2011-03-24 08:02:58 -07001635 /* Don't make the USB core poll the roothub if we got a bad port status
1636 * change event. Besides, at that point we can't tell which roothub
1637 * (USB 2.0 or USB 3.0) to kick.
1638 */
1639 if (bogus_port_status)
1640 return;
1641
Sarah Sharpc52804a2012-11-27 12:30:23 -08001642 /*
1643 * xHCI port-status-change events occur when the "or" of all the
1644 * status-change bits in the portsc register changes from 0 to 1.
1645 * New status changes won't cause an event if any other change
1646 * bits are still set. When an event occurs, switch over to
1647 * polling to avoid losing status changes.
1648 */
1649 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1650 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001651 spin_unlock(&xhci->lock);
1652 /* Pass this up to the core */
Sarah Sharpf6ff0ac2010-12-16 11:21:10 -08001653 usb_hcd_poll_rh_status(hcd);
Sarah Sharp0f2a7932009-04-27 19:57:12 -07001654 spin_lock(&xhci->lock);
1655}
1656
1657/*
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001658 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1659 * at end_trb, which may be in another segment. If the suspect DMA address is a
1660 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1661 * returns 0.
1662 */
Hans de Goedecffb9be2014-08-20 16:41:51 +03001663struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
1664 struct xhci_segment *start_seg,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001665 union xhci_trb *start_trb,
1666 union xhci_trb *end_trb,
Hans de Goedecffb9be2014-08-20 16:41:51 +03001667 dma_addr_t suspect_dma,
1668 bool debug)
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001669{
1670 dma_addr_t start_dma;
1671 dma_addr_t end_seg_dma;
1672 dma_addr_t end_trb_dma;
1673 struct xhci_segment *cur_seg;
1674
Sarah Sharp23e3be12009-04-29 19:05:20 -07001675 start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001676 cur_seg = start_seg;
1677
1678 do {
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001679 if (start_dma == 0)
Randy Dunlap326b4812010-04-19 08:53:50 -07001680 return NULL;
Sarah Sharpae636742009-04-29 19:02:31 -07001681 /* We may get an event for a Link TRB in the middle of a TD */
Sarah Sharp23e3be12009-04-29 19:05:20 -07001682 end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001683 &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001684 /* If the end TRB isn't in this segment, this is set to 0 */
Sarah Sharp23e3be12009-04-29 19:05:20 -07001685 end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001686
Hans de Goedecffb9be2014-08-20 16:41:51 +03001687 if (debug)
1688 xhci_warn(xhci,
1689 "Looking for event-dma %016llx trb-start %016llx trb-end %016llx seg-start %016llx seg-end %016llx\n",
1690 (unsigned long long)suspect_dma,
1691 (unsigned long long)start_dma,
1692 (unsigned long long)end_trb_dma,
1693 (unsigned long long)cur_seg->dma,
1694 (unsigned long long)end_seg_dma);
1695
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001696 if (end_trb_dma > 0) {
1697 /* The end TRB is in this segment, so suspect should be here */
1698 if (start_dma <= end_trb_dma) {
1699 if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1700 return cur_seg;
1701 } else {
1702 /* Case for one segment with
1703 * a TD wrapped around to the top
1704 */
1705 if ((suspect_dma >= start_dma &&
1706 suspect_dma <= end_seg_dma) ||
1707 (suspect_dma >= cur_seg->dma &&
1708 suspect_dma <= end_trb_dma))
1709 return cur_seg;
1710 }
Randy Dunlap326b4812010-04-19 08:53:50 -07001711 return NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001712 } else {
1713 /* Might still be somewhere in this segment */
1714 if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1715 return cur_seg;
1716 }
1717 cur_seg = cur_seg->next;
Sarah Sharp23e3be12009-04-29 19:05:20 -07001718 start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
Sarah Sharp2fa88da2009-11-03 22:02:24 -08001719 } while (cur_seg != start_seg);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001720
Randy Dunlap326b4812010-04-19 08:53:50 -07001721 return NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001722}
1723
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001724static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1725 unsigned int slot_id, unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001726 unsigned int stream_id,
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001727 struct xhci_td *td, union xhci_trb *event_trb)
1728{
1729 struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
Mathias Nymanddba5cd2014-05-08 19:26:00 +03001730 struct xhci_command *command;
1731 command = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
1732 if (!command)
1733 return;
1734
Mathias Nymand0167ad2015-03-10 19:49:00 +02001735 ep->ep_state |= EP_HALTED;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07001736 ep->stopped_stream = stream_id;
Sarah Sharp1624ae12010-05-06 13:40:08 -07001737
Mathias Nymanddba5cd2014-05-08 19:26:00 +03001738 xhci_queue_reset_ep(xhci, command, slot_id, ep_index);
Mathias Nymand97b4f82014-11-27 18:19:16 +02001739 xhci_cleanup_stalled_ring(xhci, ep_index, td);
Sarah Sharp1624ae12010-05-06 13:40:08 -07001740
Sarah Sharp5e5cf6f2010-05-06 13:40:18 -07001741 ep->stopped_stream = 0;
Sarah Sharp1624ae12010-05-06 13:40:08 -07001742
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001743 xhci_ring_cmd_db(xhci);
1744}
1745
1746/* Check if an error has halted the endpoint ring. The class driver will
1747 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1748 * However, a babble and other errors also halt the endpoint ring, and the class
1749 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1750 * Ring Dequeue Pointer command manually.
1751 */
1752static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1753 struct xhci_ep_ctx *ep_ctx,
1754 unsigned int trb_comp_code)
1755{
1756 /* TRB completion codes that may require a manual halt cleanup */
1757 if (trb_comp_code == COMP_TX_ERR ||
1758 trb_comp_code == COMP_BABBLE ||
1759 trb_comp_code == COMP_SPLIT_ERR)
1760 /* The 0.96 spec says a babbling control endpoint
1761 * is not halted. The 0.96 spec says it is. Some HW
1762 * claims to be 0.95 compliant, but it halts the control
1763 * endpoint anyway. Check if a babble halted the
1764 * endpoint.
1765 */
Matt Evansf5960b62011-06-01 10:22:55 +10001766 if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1767 cpu_to_le32(EP_STATE_HALTED))
Sarah Sharpbcef3fd2009-11-11 10:28:44 -08001768 return 1;
1769
1770 return 0;
1771}
1772
Sarah Sharpb45b5062009-12-09 15:59:06 -08001773int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1774{
1775 if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1776 /* Vendor defined "informational" completion code,
1777 * treat as not-an-error.
1778 */
1779 xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1780 trb_comp_code);
1781 xhci_dbg(xhci, "Treating code as success.\n");
1782 return 1;
1783 }
1784 return 0;
1785}
1786
Sarah Sharpd0e96f52009-04-27 19:58:01 -07001787/*
Andiry Xu4422da62010-07-22 15:22:55 -07001788 * Finish the td processing, remove the td from td list;
1789 * Return 1 if the urb can be given back.
1790 */
1791static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1792 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1793 struct xhci_virt_ep *ep, int *status, bool skip)
1794{
1795 struct xhci_virt_device *xdev;
1796 struct xhci_ring *ep_ring;
1797 unsigned int slot_id;
1798 int ep_index;
1799 struct urb *urb = NULL;
1800 struct xhci_ep_ctx *ep_ctx;
1801 int ret = 0;
Andiry Xu8e51adc2010-07-22 15:23:31 -07001802 struct urb_priv *urb_priv;
Andiry Xu4422da62010-07-22 15:22:55 -07001803 u32 trb_comp_code;
1804
Matt Evans28ccd292011-03-29 13:40:46 +11001805 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Andiry Xu4422da62010-07-22 15:22:55 -07001806 xdev = xhci->devs[slot_id];
Matt Evans28ccd292011-03-29 13:40:46 +11001807 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1808 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Andiry Xu4422da62010-07-22 15:22:55 -07001809 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Matt Evans28ccd292011-03-29 13:40:46 +11001810 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu4422da62010-07-22 15:22:55 -07001811
1812 if (skip)
1813 goto td_cleanup;
1814
Mathias Nyman69defe02014-11-27 18:19:14 +02001815 if (trb_comp_code == COMP_STOP_INVAL || trb_comp_code == COMP_STOP) {
Andiry Xu4422da62010-07-22 15:22:55 -07001816 /* The Endpoint Stop Command completion will take care of any
1817 * stopped TDs. A stopped TD may be restarted, so don't update
1818 * the ring dequeue pointer or take this TD off any lists yet.
1819 */
1820 ep->stopped_td = td;
Andiry Xu4422da62010-07-22 15:22:55 -07001821 return 0;
Mathias Nyman69defe02014-11-27 18:19:14 +02001822 }
1823 if (trb_comp_code == COMP_STALL ||
1824 xhci_requires_manual_halt_cleanup(xhci, ep_ctx,
1825 trb_comp_code)) {
1826 /* Issue a reset endpoint command to clear the host side
1827 * halt, followed by a set dequeue command to move the
1828 * dequeue pointer past the TD.
1829 * The class driver clears the device side halt later.
1830 */
1831 xhci_cleanup_halted_endpoint(xhci, slot_id, ep_index,
1832 ep_ring->stream_id, td, event_trb);
Andiry Xu4422da62010-07-22 15:22:55 -07001833 } else {
Mathias Nyman69defe02014-11-27 18:19:14 +02001834 /* Update ring dequeue pointer */
1835 while (ep_ring->dequeue != td->last_trb)
Andiry Xu3b72fca2012-03-05 17:49:32 +08001836 inc_deq(xhci, ep_ring);
Mathias Nyman69defe02014-11-27 18:19:14 +02001837 inc_deq(xhci, ep_ring);
1838 }
Andiry Xu4422da62010-07-22 15:22:55 -07001839
1840td_cleanup:
Mathias Nyman69defe02014-11-27 18:19:14 +02001841 /* Clean up the endpoint's TD list */
1842 urb = td->urb;
1843 urb_priv = urb->hcpriv;
Andiry Xu4422da62010-07-22 15:22:55 -07001844
Mathias Nyman69defe02014-11-27 18:19:14 +02001845 /* Do one last check of the actual transfer length.
1846 * If the host controller said we transferred more data than the buffer
1847 * length, urb->actual_length will be a very big number (since it's
1848 * unsigned). Play it safe and say we didn't transfer anything.
1849 */
1850 if (urb->actual_length > urb->transfer_buffer_length) {
1851 xhci_warn(xhci, "URB transfer length is wrong, xHC issue? req. len = %u, act. len = %u\n",
1852 urb->transfer_buffer_length,
1853 urb->actual_length);
1854 urb->actual_length = 0;
1855 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1856 *status = -EREMOTEIO;
1857 else
1858 *status = 0;
1859 }
1860 list_del_init(&td->td_list);
1861 /* Was this TD slated to be cancelled but completed anyway? */
1862 if (!list_empty(&td->cancelled_td_list))
1863 list_del_init(&td->cancelled_td_list);
Andiry Xu4422da62010-07-22 15:22:55 -07001864
Mathias Nyman69defe02014-11-27 18:19:14 +02001865 urb_priv->td_cnt++;
1866 /* Giveback the urb when all the tds are completed */
1867 if (urb_priv->td_cnt == urb_priv->length) {
1868 ret = 1;
1869 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1870 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1871 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
1872 if (xhci->quirks & XHCI_AMD_PLL_FIX)
1873 usb_amd_quirk_pll_enable();
Andiry Xuc41136b2011-03-22 17:08:14 +08001874 }
1875 }
Andiry Xu4422da62010-07-22 15:22:55 -07001876 }
1877
1878 return ret;
1879}
1880
1881/*
Andiry Xu8af56be2010-07-22 15:23:03 -07001882 * Process control tds, update urb status and actual_length.
1883 */
1884static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1885 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1886 struct xhci_virt_ep *ep, int *status)
1887{
1888 struct xhci_virt_device *xdev;
1889 struct xhci_ring *ep_ring;
1890 unsigned int slot_id;
1891 int ep_index;
1892 struct xhci_ep_ctx *ep_ctx;
1893 u32 trb_comp_code;
1894
Matt Evans28ccd292011-03-29 13:40:46 +11001895 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Andiry Xu8af56be2010-07-22 15:23:03 -07001896 xdev = xhci->devs[slot_id];
Matt Evans28ccd292011-03-29 13:40:46 +11001897 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1898 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Andiry Xu8af56be2010-07-22 15:23:03 -07001899 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Matt Evans28ccd292011-03-29 13:40:46 +11001900 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu8af56be2010-07-22 15:23:03 -07001901
Andiry Xu8af56be2010-07-22 15:23:03 -07001902 switch (trb_comp_code) {
1903 case COMP_SUCCESS:
1904 if (event_trb == ep_ring->dequeue) {
1905 xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
1906 "without IOC set??\n");
1907 *status = -ESHUTDOWN;
1908 } else if (event_trb != td->last_trb) {
1909 xhci_warn(xhci, "WARN: Success on ctrl data TRB "
1910 "without IOC set??\n");
1911 *status = -ESHUTDOWN;
1912 } else {
Andiry Xu8af56be2010-07-22 15:23:03 -07001913 *status = 0;
1914 }
1915 break;
1916 case COMP_SHORT_TX:
Andiry Xu8af56be2010-07-22 15:23:03 -07001917 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1918 *status = -EREMOTEIO;
1919 else
1920 *status = 0;
1921 break;
Sarah Sharp3abeca92011-05-05 19:08:09 -07001922 case COMP_STOP_INVAL:
1923 case COMP_STOP:
1924 return finish_td(xhci, td, event_trb, event, ep, status, false);
Andiry Xu8af56be2010-07-22 15:23:03 -07001925 default:
1926 if (!xhci_requires_manual_halt_cleanup(xhci,
1927 ep_ctx, trb_comp_code))
1928 break;
1929 xhci_dbg(xhci, "TRB error code %u, "
1930 "halted endpoint index = %u\n",
1931 trb_comp_code, ep_index);
1932 /* else fall through */
1933 case COMP_STALL:
1934 /* Did we transfer part of the data (middle) phase? */
1935 if (event_trb != ep_ring->dequeue &&
1936 event_trb != td->last_trb)
1937 td->urb->actual_length =
Vivek Gautam1c11a172013-03-21 12:06:48 +05301938 td->urb->transfer_buffer_length -
1939 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
Mathias Nyman22ae47e2015-05-29 17:01:53 +03001940 else if (!td->urb_length_set)
Andiry Xu8af56be2010-07-22 15:23:03 -07001941 td->urb->actual_length = 0;
1942
Mathias Nyman8e71a3222014-11-18 11:27:12 +02001943 return finish_td(xhci, td, event_trb, event, ep, status, false);
Andiry Xu8af56be2010-07-22 15:23:03 -07001944 }
1945 /*
1946 * Did we transfer any data, despite the errors that might have
1947 * happened? I.e. did we get past the setup stage?
1948 */
1949 if (event_trb != ep_ring->dequeue) {
1950 /* The event was for the status stage */
1951 if (event_trb == td->last_trb) {
Aleksander Morgado45ba2152015-03-06 17:14:21 +02001952 if (td->urb_length_set) {
Andiry Xu8af56be2010-07-22 15:23:03 -07001953 /* Don't overwrite a previously set error code
1954 */
1955 if ((*status == -EINPROGRESS || *status == 0) &&
1956 (td->urb->transfer_flags
1957 & URB_SHORT_NOT_OK))
1958 /* Did we already see a short data
1959 * stage? */
1960 *status = -EREMOTEIO;
1961 } else {
1962 td->urb->actual_length =
1963 td->urb->transfer_buffer_length;
1964 }
1965 } else {
Aleksander Morgado45ba2152015-03-06 17:14:21 +02001966 /*
1967 * Maybe the event was for the data stage? If so, update
1968 * already the actual_length of the URB and flag it as
1969 * set, so that it is not overwritten in the event for
1970 * the last TRB.
1971 */
1972 td->urb_length_set = true;
Sarah Sharp3abeca92011-05-05 19:08:09 -07001973 td->urb->actual_length =
1974 td->urb->transfer_buffer_length -
Vivek Gautam1c11a172013-03-21 12:06:48 +05301975 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
Sarah Sharp3abeca92011-05-05 19:08:09 -07001976 xhci_dbg(xhci, "Waiting for status "
1977 "stage event\n");
1978 return 0;
Andiry Xu8af56be2010-07-22 15:23:03 -07001979 }
1980 }
1981
1982 return finish_td(xhci, td, event_trb, event, ep, status, false);
1983}
1984
1985/*
Andiry Xu04e51902010-07-22 15:23:39 -07001986 * Process isochronous tds, update urb packet status and actual_length.
1987 */
1988static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
1989 union xhci_trb *event_trb, struct xhci_transfer_event *event,
1990 struct xhci_virt_ep *ep, int *status)
1991{
1992 struct xhci_ring *ep_ring;
1993 struct urb_priv *urb_priv;
1994 int idx;
1995 int len = 0;
Andiry Xu04e51902010-07-22 15:23:39 -07001996 union xhci_trb *cur_trb;
1997 struct xhci_segment *cur_seg;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07001998 struct usb_iso_packet_descriptor *frame;
Andiry Xu04e51902010-07-22 15:23:39 -07001999 u32 trb_comp_code;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002000 bool skip_td = false;
Andiry Xu04e51902010-07-22 15:23:39 -07002001
Matt Evans28ccd292011-03-29 13:40:46 +11002002 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2003 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu04e51902010-07-22 15:23:39 -07002004 urb_priv = td->urb->hcpriv;
2005 idx = urb_priv->td_cnt;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002006 frame = &td->urb->iso_frame_desc[idx];
Andiry Xu04e51902010-07-22 15:23:39 -07002007
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002008 /* handle completion code */
2009 switch (trb_comp_code) {
2010 case COMP_SUCCESS:
Vivek Gautam1c11a172013-03-21 12:06:48 +05302011 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
Sarah Sharp1530bbc62012-05-08 09:22:49 -07002012 frame->status = 0;
2013 break;
2014 }
2015 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2016 trb_comp_code = COMP_SHORT_TX;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002017 case COMP_SHORT_TX:
2018 frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2019 -EREMOTEIO : 0;
2020 break;
2021 case COMP_BW_OVER:
2022 frame->status = -ECOMM;
2023 skip_td = true;
2024 break;
2025 case COMP_BUFF_OVER:
2026 case COMP_BABBLE:
2027 frame->status = -EOVERFLOW;
2028 skip_td = true;
2029 break;
Alex Hef6ba6fe2011-06-08 18:34:06 +08002030 case COMP_DEV_ERR:
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002031 case COMP_STALL:
Mathias Nymand104d012015-04-30 17:16:02 +03002032 frame->status = -EPROTO;
2033 skip_td = true;
2034 break;
Hans de Goede9c745992012-04-23 15:06:09 +02002035 case COMP_TX_ERR:
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002036 frame->status = -EPROTO;
Mathias Nymand104d012015-04-30 17:16:02 +03002037 if (event_trb != td->last_trb)
2038 return 0;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002039 skip_td = true;
2040 break;
2041 case COMP_STOP:
2042 case COMP_STOP_INVAL:
2043 break;
2044 default:
2045 frame->status = -1;
2046 break;
Andiry Xu04e51902010-07-22 15:23:39 -07002047 }
2048
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002049 if (trb_comp_code == COMP_SUCCESS || skip_td) {
2050 frame->actual_length = frame->length;
2051 td->urb->actual_length += frame->length;
Andiry Xu04e51902010-07-22 15:23:39 -07002052 } else {
2053 for (cur_trb = ep_ring->dequeue,
2054 cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2055 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +10002056 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2057 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
Matt Evans28ccd292011-03-29 13:40:46 +11002058 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
Andiry Xu04e51902010-07-22 15:23:39 -07002059 }
Matt Evans28ccd292011-03-29 13:40:46 +11002060 len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
Vivek Gautam1c11a172013-03-21 12:06:48 +05302061 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu04e51902010-07-22 15:23:39 -07002062
2063 if (trb_comp_code != COMP_STOP_INVAL) {
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002064 frame->actual_length = len;
Andiry Xu04e51902010-07-22 15:23:39 -07002065 td->urb->actual_length += len;
2066 }
2067 }
2068
Andiry Xu04e51902010-07-22 15:23:39 -07002069 return finish_td(xhci, td, event_trb, event, ep, status, false);
2070}
2071
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002072static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2073 struct xhci_transfer_event *event,
2074 struct xhci_virt_ep *ep, int *status)
2075{
2076 struct xhci_ring *ep_ring;
2077 struct urb_priv *urb_priv;
2078 struct usb_iso_packet_descriptor *frame;
2079 int idx;
2080
Matt Evansf6975312011-06-01 13:01:01 +10002081 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002082 urb_priv = td->urb->hcpriv;
2083 idx = urb_priv->td_cnt;
2084 frame = &td->urb->iso_frame_desc[idx];
2085
Sarah Sharpb3df3f92011-06-15 19:57:46 -07002086 /* The transfer is partly done. */
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002087 frame->status = -EXDEV;
2088
2089 /* calc actual length */
2090 frame->actual_length = 0;
2091
2092 /* Update ring dequeue pointer */
2093 while (ep_ring->dequeue != td->last_trb)
Andiry Xu3b72fca2012-03-05 17:49:32 +08002094 inc_deq(xhci, ep_ring);
2095 inc_deq(xhci, ep_ring);
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002096
2097 return finish_td(xhci, td, NULL, event, ep, status, true);
2098}
2099
Andiry Xu04e51902010-07-22 15:23:39 -07002100/*
Andiry Xu22405ed2010-07-22 15:23:08 -07002101 * Process bulk and interrupt tds, update urb status and actual_length.
2102 */
2103static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2104 union xhci_trb *event_trb, struct xhci_transfer_event *event,
2105 struct xhci_virt_ep *ep, int *status)
2106{
2107 struct xhci_ring *ep_ring;
2108 union xhci_trb *cur_trb;
2109 struct xhci_segment *cur_seg;
2110 u32 trb_comp_code;
2111
Matt Evans28ccd292011-03-29 13:40:46 +11002112 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2113 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07002114
2115 switch (trb_comp_code) {
2116 case COMP_SUCCESS:
2117 /* Double check that the HW transferred everything. */
Sarah Sharp1530bbc62012-05-08 09:22:49 -07002118 if (event_trb != td->last_trb ||
Vivek Gautam1c11a172013-03-21 12:06:48 +05302119 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
Andiry Xu22405ed2010-07-22 15:23:08 -07002120 xhci_warn(xhci, "WARN Successful completion "
2121 "on short TX\n");
2122 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2123 *status = -EREMOTEIO;
2124 else
2125 *status = 0;
Sarah Sharp1530bbc62012-05-08 09:22:49 -07002126 if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2127 trb_comp_code = COMP_SHORT_TX;
Andiry Xu22405ed2010-07-22 15:23:08 -07002128 } else {
Andiry Xu22405ed2010-07-22 15:23:08 -07002129 *status = 0;
2130 }
2131 break;
2132 case COMP_SHORT_TX:
2133 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2134 *status = -EREMOTEIO;
2135 else
2136 *status = 0;
2137 break;
2138 default:
2139 /* Others already handled above */
2140 break;
2141 }
Sarah Sharpf444ff22011-04-05 15:53:47 -07002142 if (trb_comp_code == COMP_SHORT_TX)
2143 xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2144 "%d bytes untransferred\n",
2145 td->urb->ep->desc.bEndpointAddress,
2146 td->urb->transfer_buffer_length,
Vivek Gautam1c11a172013-03-21 12:06:48 +05302147 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
Andiry Xu22405ed2010-07-22 15:23:08 -07002148 /* Fast path - was this the last TRB in the TD for this URB? */
2149 if (event_trb == td->last_trb) {
Vivek Gautam1c11a172013-03-21 12:06:48 +05302150 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
Andiry Xu22405ed2010-07-22 15:23:08 -07002151 td->urb->actual_length =
2152 td->urb->transfer_buffer_length -
Vivek Gautam1c11a172013-03-21 12:06:48 +05302153 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07002154 if (td->urb->transfer_buffer_length <
2155 td->urb->actual_length) {
2156 xhci_warn(xhci, "HC gave bad length "
2157 "of %d bytes left\n",
Vivek Gautam1c11a172013-03-21 12:06:48 +05302158 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
Andiry Xu22405ed2010-07-22 15:23:08 -07002159 td->urb->actual_length = 0;
2160 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2161 *status = -EREMOTEIO;
2162 else
2163 *status = 0;
2164 }
2165 /* Don't overwrite a previously set error code */
2166 if (*status == -EINPROGRESS) {
2167 if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2168 *status = -EREMOTEIO;
2169 else
2170 *status = 0;
2171 }
2172 } else {
2173 td->urb->actual_length =
2174 td->urb->transfer_buffer_length;
2175 /* Ignore a short packet completion if the
2176 * untransferred length was zero.
2177 */
2178 if (*status == -EREMOTEIO)
2179 *status = 0;
2180 }
2181 } else {
2182 /* Slow path - walk the list, starting from the dequeue
2183 * pointer, to get the actual length transferred.
2184 */
2185 td->urb->actual_length = 0;
2186 for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2187 cur_trb != event_trb;
2188 next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
Matt Evansf5960b62011-06-01 10:22:55 +10002189 if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2190 !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
Andiry Xu22405ed2010-07-22 15:23:08 -07002191 td->urb->actual_length +=
Matt Evans28ccd292011-03-29 13:40:46 +11002192 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
Andiry Xu22405ed2010-07-22 15:23:08 -07002193 }
2194 /* If the ring didn't stop on a Link or No-op TRB, add
2195 * in the actual bytes transferred from the Normal TRB
2196 */
2197 if (trb_comp_code != COMP_STOP_INVAL)
2198 td->urb->actual_length +=
Matt Evans28ccd292011-03-29 13:40:46 +11002199 TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
Vivek Gautam1c11a172013-03-21 12:06:48 +05302200 EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
Andiry Xu22405ed2010-07-22 15:23:08 -07002201 }
2202
2203 return finish_td(xhci, td, event_trb, event, ep, status, false);
2204}
2205
2206/*
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002207 * If this function returns an error condition, it means it got a Transfer
2208 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2209 * At this point, the host controller is probably hosed and should be reset.
2210 */
2211static int handle_tx_event(struct xhci_hcd *xhci,
2212 struct xhci_transfer_event *event)
Felipe Balbied384bd2012-08-07 14:10:03 +03002213 __releases(&xhci->lock)
2214 __acquires(&xhci->lock)
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002215{
2216 struct xhci_virt_device *xdev;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07002217 struct xhci_virt_ep *ep;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002218 struct xhci_ring *ep_ring;
Sarah Sharp82d10092009-08-07 14:04:52 -07002219 unsigned int slot_id;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002220 int ep_index;
Randy Dunlap326b4812010-04-19 08:53:50 -07002221 struct xhci_td *td = NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002222 dma_addr_t event_dma;
2223 struct xhci_segment *event_seg;
2224 union xhci_trb *event_trb;
Randy Dunlap326b4812010-04-19 08:53:50 -07002225 struct urb *urb = NULL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002226 int status = -EINPROGRESS;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002227 struct urb_priv *urb_priv;
John Yound115b042009-07-27 12:05:15 -07002228 struct xhci_ep_ctx *ep_ctx;
Andiry Xuc2d7b492011-09-19 16:05:12 -07002229 struct list_head *tmp;
Sarah Sharp66d1eeb2009-08-27 14:35:53 -07002230 u32 trb_comp_code;
Andiry Xu4422da62010-07-22 15:22:55 -07002231 int ret = 0;
Andiry Xuc2d7b492011-09-19 16:05:12 -07002232 int td_num = 0;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002233
Matt Evans28ccd292011-03-29 13:40:46 +11002234 slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
Sarah Sharp82d10092009-08-07 14:04:52 -07002235 xdev = xhci->devs[slot_id];
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002236 if (!xdev) {
2237 xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
Sarah Sharp9258c0b2011-12-01 14:50:30 -08002238 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
Sarah Sharpe910b442012-01-04 16:54:12 -08002239 (unsigned long long) xhci_trb_virt_to_dma(
2240 xhci->event_ring->deq_seg,
Sarah Sharp9258c0b2011-12-01 14:50:30 -08002241 xhci->event_ring->dequeue),
2242 lower_32_bits(le64_to_cpu(event->buffer)),
2243 upper_32_bits(le64_to_cpu(event->buffer)),
2244 le32_to_cpu(event->transfer_len),
2245 le32_to_cpu(event->flags));
2246 xhci_dbg(xhci, "Event ring:\n");
2247 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002248 return -ENODEV;
2249 }
2250
2251 /* Endpoint ID is 1 based, our index is zero based */
Matt Evans28ccd292011-03-29 13:40:46 +11002252 ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07002253 ep = &xdev->eps[ep_index];
Matt Evans28ccd292011-03-29 13:40:46 +11002254 ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
John Yound115b042009-07-27 12:05:15 -07002255 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07002256 if (!ep_ring ||
Matt Evans28ccd292011-03-29 13:40:46 +11002257 (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2258 EP_STATE_DISABLED) {
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002259 xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2260 "or incorrect stream ring\n");
Sarah Sharp9258c0b2011-12-01 14:50:30 -08002261 xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
Sarah Sharpe910b442012-01-04 16:54:12 -08002262 (unsigned long long) xhci_trb_virt_to_dma(
2263 xhci->event_ring->deq_seg,
Sarah Sharp9258c0b2011-12-01 14:50:30 -08002264 xhci->event_ring->dequeue),
2265 lower_32_bits(le64_to_cpu(event->buffer)),
2266 upper_32_bits(le64_to_cpu(event->buffer)),
2267 le32_to_cpu(event->transfer_len),
2268 le32_to_cpu(event->flags));
2269 xhci_dbg(xhci, "Event ring:\n");
2270 xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002271 return -ENODEV;
2272 }
2273
Andiry Xuc2d7b492011-09-19 16:05:12 -07002274 /* Count current td numbers if ep->skip is set */
2275 if (ep->skip) {
2276 list_for_each(tmp, &ep_ring->td_list)
2277 td_num++;
2278 }
2279
Matt Evans28ccd292011-03-29 13:40:46 +11002280 event_dma = le64_to_cpu(event->buffer);
2281 trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
Andiry Xu986a92d2010-07-22 15:23:20 -07002282 /* Look for common error cases */
Sarah Sharp66d1eeb2009-08-27 14:35:53 -07002283 switch (trb_comp_code) {
Sarah Sharpb10de142009-04-27 19:58:50 -07002284 /* Skip codes that require special handling depending on
2285 * transfer type
2286 */
2287 case COMP_SUCCESS:
Vivek Gautam1c11a172013-03-21 12:06:48 +05302288 if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
Sarah Sharp1530bbc62012-05-08 09:22:49 -07002289 break;
2290 if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2291 trb_comp_code = COMP_SHORT_TX;
2292 else
Sarah Sharp8202ce22012-07-25 10:52:45 -07002293 xhci_warn_ratelimited(xhci,
2294 "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
Sarah Sharpb10de142009-04-27 19:58:50 -07002295 case COMP_SHORT_TX:
2296 break;
Sarah Sharpae636742009-04-29 19:02:31 -07002297 case COMP_STOP:
2298 xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2299 break;
2300 case COMP_STOP_INVAL:
2301 xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2302 break;
Sarah Sharpb10de142009-04-27 19:58:50 -07002303 case COMP_STALL:
Sarah Sharp2a9227a2011-10-25 13:55:30 +02002304 xhci_dbg(xhci, "Stalled endpoint\n");
Sarah Sharp63a0d9a2009-09-04 10:53:09 -07002305 ep->ep_state |= EP_HALTED;
Sarah Sharpb10de142009-04-27 19:58:50 -07002306 status = -EPIPE;
2307 break;
2308 case COMP_TRB_ERR:
2309 xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2310 status = -EILSEQ;
2311 break;
Sarah Sharpec74e402009-11-11 10:28:36 -08002312 case COMP_SPLIT_ERR:
Sarah Sharpb10de142009-04-27 19:58:50 -07002313 case COMP_TX_ERR:
Sarah Sharp2a9227a2011-10-25 13:55:30 +02002314 xhci_dbg(xhci, "Transfer error on endpoint\n");
Sarah Sharpb10de142009-04-27 19:58:50 -07002315 status = -EPROTO;
2316 break;
Sarah Sharp4a731432009-07-27 12:04:32 -07002317 case COMP_BABBLE:
Sarah Sharp2a9227a2011-10-25 13:55:30 +02002318 xhci_dbg(xhci, "Babble error on endpoint\n");
Sarah Sharp4a731432009-07-27 12:04:32 -07002319 status = -EOVERFLOW;
2320 break;
Sarah Sharpb10de142009-04-27 19:58:50 -07002321 case COMP_DB_ERR:
2322 xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2323 status = -ENOSR;
2324 break;
Andiry Xu986a92d2010-07-22 15:23:20 -07002325 case COMP_BW_OVER:
2326 xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2327 break;
2328 case COMP_BUFF_OVER:
2329 xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2330 break;
2331 case COMP_UNDERRUN:
2332 /*
2333 * When the Isoch ring is empty, the xHC will generate
2334 * a Ring Overrun Event for IN Isoch endpoint or Ring
2335 * Underrun Event for OUT Isoch endpoint.
2336 */
2337 xhci_dbg(xhci, "underrun event on endpoint\n");
2338 if (!list_empty(&ep_ring->td_list))
2339 xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2340 "still with TDs queued?\n",
Matt Evans28ccd292011-03-29 13:40:46 +11002341 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2342 ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07002343 goto cleanup;
2344 case COMP_OVERRUN:
2345 xhci_dbg(xhci, "overrun event on endpoint\n");
2346 if (!list_empty(&ep_ring->td_list))
2347 xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2348 "still with TDs queued?\n",
Matt Evans28ccd292011-03-29 13:40:46 +11002349 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2350 ep_index);
Andiry Xu986a92d2010-07-22 15:23:20 -07002351 goto cleanup;
Alex Hef6ba6fe2011-06-08 18:34:06 +08002352 case COMP_DEV_ERR:
2353 xhci_warn(xhci, "WARN: detect an incompatible device");
2354 status = -EPROTO;
2355 break;
Andiry Xud18240d2010-07-22 15:23:25 -07002356 case COMP_MISSED_INT:
2357 /*
2358 * When encounter missed service error, one or more isoc tds
2359 * may be missed by xHC.
2360 * Set skip flag of the ep_ring; Complete the missed tds as
2361 * short transfer when process the ep_ring next time.
2362 */
2363 ep->skip = true;
2364 xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2365 goto cleanup;
Sarah Sharpb10de142009-04-27 19:58:50 -07002366 default:
Sarah Sharpb45b5062009-12-09 15:59:06 -08002367 if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
Sarah Sharp5ad6a522009-11-11 10:28:40 -08002368 status = 0;
2369 break;
2370 }
Mathias Nyman86cd7402015-01-09 16:06:32 +02002371 xhci_warn(xhci, "ERROR Unknown event condition %u, HC probably busted\n",
2372 trb_comp_code);
Sarah Sharpb10de142009-04-27 19:58:50 -07002373 goto cleanup;
2374 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002375
Andiry Xud18240d2010-07-22 15:23:25 -07002376 do {
2377 /* This TRB should be in the TD at the head of this ring's
2378 * TD list.
2379 */
2380 if (list_empty(&ep_ring->td_list)) {
Sarah Sharpa83d6752013-03-18 10:19:51 -07002381 /*
2382 * A stopped endpoint may generate an extra completion
2383 * event if the device was suspended. Don't print
2384 * warnings.
2385 */
2386 if (!(trb_comp_code == COMP_STOP ||
2387 trb_comp_code == COMP_STOP_INVAL)) {
2388 xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2389 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2390 ep_index);
2391 xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2392 (le32_to_cpu(event->flags) &
2393 TRB_TYPE_BITMASK)>>10);
2394 xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2395 }
Andiry Xud18240d2010-07-22 15:23:25 -07002396 if (ep->skip) {
2397 ep->skip = false;
2398 xhci_dbg(xhci, "td_list is empty while skip "
2399 "flag set. Clear skip flag.\n");
2400 }
2401 ret = 0;
2402 goto cleanup;
2403 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002404
Andiry Xuc2d7b492011-09-19 16:05:12 -07002405 /* We've skipped all the TDs on the ep ring when ep->skip set */
2406 if (ep->skip && td_num == 0) {
2407 ep->skip = false;
2408 xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2409 "Clear skip flag.\n");
2410 ret = 0;
2411 goto cleanup;
2412 }
2413
Andiry Xud18240d2010-07-22 15:23:25 -07002414 td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
Andiry Xuc2d7b492011-09-19 16:05:12 -07002415 if (ep->skip)
2416 td_num--;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002417
Andiry Xud18240d2010-07-22 15:23:25 -07002418 /* Is this a TRB in the currently executing TD? */
Hans de Goedecffb9be2014-08-20 16:41:51 +03002419 event_seg = trb_in_td(xhci, ep_ring->deq_seg, ep_ring->dequeue,
2420 td->last_trb, event_dma, false);
Alex Hee1cf4862011-06-03 15:58:25 +08002421
2422 /*
2423 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2424 * is not in the current TD pointed by ep_ring->dequeue because
2425 * that the hardware dequeue pointer still at the previous TRB
2426 * of the current TD. The previous TRB maybe a Link TD or the
2427 * last TRB of the previous TD. The command completion handle
2428 * will take care the rest.
2429 */
Hans de Goede9a548862014-08-19 15:17:56 +03002430 if (!event_seg && (trb_comp_code == COMP_STOP ||
2431 trb_comp_code == COMP_STOP_INVAL)) {
Alex Hee1cf4862011-06-03 15:58:25 +08002432 ret = 0;
2433 goto cleanup;
2434 }
2435
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002436 if (!event_seg) {
2437 if (!ep->skip ||
2438 !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
Sarah Sharpad808332011-05-25 10:43:56 -07002439 /* Some host controllers give a spurious
2440 * successful event after a short transfer.
2441 * Ignore it.
2442 */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03002443 if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) &&
Sarah Sharpad808332011-05-25 10:43:56 -07002444 ep_ring->last_td_was_short) {
2445 ep_ring->last_td_was_short = false;
2446 ret = 0;
2447 goto cleanup;
2448 }
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002449 /* HC is busted, give up! */
2450 xhci_err(xhci,
2451 "ERROR Transfer event TRB DMA ptr not "
Hans de Goedecffb9be2014-08-20 16:41:51 +03002452 "part of current TD ep_index %d "
2453 "comp_code %u\n", ep_index,
2454 trb_comp_code);
2455 trb_in_td(xhci, ep_ring->deq_seg,
2456 ep_ring->dequeue, td->last_trb,
2457 event_dma, true);
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002458 return -ESHUTDOWN;
2459 }
2460
2461 ret = skip_isoc_td(xhci, td, event, ep, &status);
2462 goto cleanup;
2463 }
Sarah Sharpad808332011-05-25 10:43:56 -07002464 if (trb_comp_code == COMP_SHORT_TX)
2465 ep_ring->last_td_was_short = true;
2466 else
2467 ep_ring->last_td_was_short = false;
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002468
2469 if (ep->skip) {
Andiry Xud18240d2010-07-22 15:23:25 -07002470 xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2471 ep->skip = false;
2472 }
Andiry Xu986a92d2010-07-22 15:23:20 -07002473
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002474 event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2475 sizeof(*event_trb)];
2476 /*
2477 * No-op TRB should not trigger interrupts.
2478 * If event_trb is a no-op TRB, it means the
2479 * corresponding TD has been cancelled. Just ignore
2480 * the TD.
2481 */
Matt Evansf5960b62011-06-01 10:22:55 +10002482 if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
Dmitry Torokhov926008c2011-03-23 20:47:05 -07002483 xhci_dbg(xhci,
2484 "event_trb is a no-op TRB. Skip it\n");
2485 goto cleanup;
Andiry Xud18240d2010-07-22 15:23:25 -07002486 }
2487
2488 /* Now update the urb's actual_length and give back to
2489 * the core
2490 */
2491 if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2492 ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2493 &status);
Andiry Xu04e51902010-07-22 15:23:39 -07002494 else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2495 ret = process_isoc_td(xhci, td, event_trb, event, ep,
2496 &status);
Andiry Xud18240d2010-07-22 15:23:25 -07002497 else
2498 ret = process_bulk_intr_td(xhci, td, event_trb, event,
2499 ep, &status);
Andiry Xu4422da62010-07-22 15:22:55 -07002500
2501cleanup:
Andiry Xud18240d2010-07-22 15:23:25 -07002502 /*
2503 * Do not update event ring dequeue pointer if ep->skip is set.
2504 * Will roll back to continue process missed tds.
Sarah Sharp82d10092009-08-07 14:04:52 -07002505 */
Andiry Xud18240d2010-07-22 15:23:25 -07002506 if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
Andiry Xu3b72fca2012-03-05 17:49:32 +08002507 inc_deq(xhci, xhci->event_ring);
Andiry Xud18240d2010-07-22 15:23:25 -07002508 }
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002509
Andiry Xud18240d2010-07-22 15:23:25 -07002510 if (ret) {
2511 urb = td->urb;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002512 urb_priv = urb->hcpriv;
Mathias Nyman8e71a3222014-11-18 11:27:12 +02002513
Lin Wang4daf9df2015-01-09 16:06:31 +02002514 xhci_urb_free_priv(urb_priv);
Andiry Xud18240d2010-07-22 15:23:25 -07002515
Sarah Sharp214f76f2010-10-26 11:22:02 -07002516 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
Sarah Sharpf444ff22011-04-05 15:53:47 -07002517 if ((urb->actual_length != urb->transfer_buffer_length &&
2518 (urb->transfer_flags &
2519 URB_SHORT_NOT_OK)) ||
Sarah Sharpfd984d22011-09-02 11:05:56 -07002520 (status != 0 &&
2521 !usb_endpoint_xfer_isoc(&urb->ep->desc)))
Sarah Sharpf444ff22011-04-05 15:53:47 -07002522 xhci_dbg(xhci, "Giveback URB %p, len = %d, "
Alan Stern1949f9e2012-05-07 13:22:52 -04002523 "expected = %d, status = %d\n",
Sarah Sharpf444ff22011-04-05 15:53:47 -07002524 urb, urb->actual_length,
2525 urb->transfer_buffer_length,
2526 status);
Andiry Xud18240d2010-07-22 15:23:25 -07002527 spin_unlock(&xhci->lock);
Sarah Sharpb3df3f92011-06-15 19:57:46 -07002528 /* EHCI, UHCI, and OHCI always unconditionally set the
2529 * urb->status of an isochronous endpoint to 0.
2530 */
2531 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2532 status = 0;
Sarah Sharp214f76f2010-10-26 11:22:02 -07002533 usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
Andiry Xud18240d2010-07-22 15:23:25 -07002534 spin_lock(&xhci->lock);
2535 }
2536
2537 /*
2538 * If ep->skip is set, it means there are missed tds on the
2539 * endpoint ring need to take care of.
2540 * Process them as short transfer until reach the td pointed by
2541 * the event.
2542 */
2543 } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2544
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002545 return 0;
2546}
2547
2548/*
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002549 * This function handles all OS-owned events on the event ring. It may drop
2550 * xhci->lock between event processing (e.g. to pass up port status changes).
Matt Evans9dee9a22011-03-29 13:41:02 +11002551 * Returns >0 for "possibly more events to process" (caller should call again),
2552 * otherwise 0 if done. In future, <0 returns should indicate error code.
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002553 */
Matt Evans9dee9a22011-03-29 13:41:02 +11002554static int xhci_handle_event(struct xhci_hcd *xhci)
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002555{
2556 union xhci_trb *event;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002557 int update_ptrs = 1;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002558 int ret;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002559
2560 if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2561 xhci->error_bitmask |= 1 << 1;
Matt Evans9dee9a22011-03-29 13:41:02 +11002562 return 0;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002563 }
2564
2565 event = xhci->event_ring->dequeue;
2566 /* Does the HC or OS own the TRB? */
Matt Evans28ccd292011-03-29 13:40:46 +11002567 if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2568 xhci->event_ring->cycle_state) {
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002569 xhci->error_bitmask |= 1 << 2;
Matt Evans9dee9a22011-03-29 13:41:02 +11002570 return 0;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002571 }
2572
Matt Evans92a3da42011-03-29 13:40:51 +11002573 /*
2574 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2575 * speculative reads of the event's flags/data below.
2576 */
2577 rmb();
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002578 /* FIXME: Handle more event types. */
Matt Evans28ccd292011-03-29 13:40:46 +11002579 switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002580 case TRB_TYPE(TRB_COMPLETION):
2581 handle_cmd_completion(xhci, &event->event_cmd);
2582 break;
Sarah Sharp0f2a7932009-04-27 19:57:12 -07002583 case TRB_TYPE(TRB_PORT_STATUS):
2584 handle_port_status(xhci, event);
2585 update_ptrs = 0;
2586 break;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002587 case TRB_TYPE(TRB_TRANSFER):
2588 ret = handle_tx_event(xhci, &event->trans_event);
2589 if (ret < 0)
2590 xhci->error_bitmask |= 1 << 9;
2591 else
2592 update_ptrs = 0;
2593 break;
Sarah Sharp623bef92011-11-11 14:57:33 -08002594 case TRB_TYPE(TRB_DEV_NOTE):
2595 handle_device_notification(xhci, event);
2596 break;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002597 default:
Matt Evans28ccd292011-03-29 13:40:46 +11002598 if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2599 TRB_TYPE(48))
Sarah Sharp02386342010-05-24 13:25:28 -07002600 handle_vendor_event(xhci, event);
2601 else
2602 xhci->error_bitmask |= 1 << 3;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002603 }
Sarah Sharp6f5165c2009-10-27 10:57:01 -07002604 /* Any of the above functions may drop and re-acquire the lock, so check
2605 * to make sure a watchdog timer didn't mark the host as non-responsive.
2606 */
2607 if (xhci->xhc_state & XHCI_STATE_DYING) {
2608 xhci_dbg(xhci, "xHCI host dying, returning from "
2609 "event handler.\n");
Matt Evans9dee9a22011-03-29 13:41:02 +11002610 return 0;
Sarah Sharp6f5165c2009-10-27 10:57:01 -07002611 }
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002612
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002613 if (update_ptrs)
2614 /* Update SW event ring dequeue pointer */
Andiry Xu3b72fca2012-03-05 17:49:32 +08002615 inc_deq(xhci, xhci->event_ring);
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002616
Matt Evans9dee9a22011-03-29 13:41:02 +11002617 /* Are there more items on the event ring? Caller will call us again to
2618 * check.
2619 */
2620 return 1;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002621}
Sarah Sharp9032cd52010-07-29 22:12:29 -07002622
2623/*
2624 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2625 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2626 * indicators of an event TRB error, but we check the status *first* to be safe.
2627 */
2628irqreturn_t xhci_irq(struct usb_hcd *hcd)
2629{
2630 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
Sarah Sharpc21599a2010-07-29 22:13:00 -07002631 u32 status;
Sarah Sharpbda53142010-07-29 22:12:38 -07002632 u64 temp_64;
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002633 union xhci_trb *event_ring_deq;
2634 dma_addr_t deq;
Sarah Sharp9032cd52010-07-29 22:12:29 -07002635
2636 spin_lock(&xhci->lock);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002637 /* Check if the xHC generated the interrupt, or the irq is shared */
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +02002638 status = readl(&xhci->op_regs->status);
Sarah Sharpc21599a2010-07-29 22:13:00 -07002639 if (status == 0xffffffff)
Sarah Sharp9032cd52010-07-29 22:12:29 -07002640 goto hw_died;
2641
Sarah Sharpc21599a2010-07-29 22:13:00 -07002642 if (!(status & STS_EINT)) {
Sarah Sharp9032cd52010-07-29 22:12:29 -07002643 spin_unlock(&xhci->lock);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002644 return IRQ_NONE;
2645 }
Sarah Sharp27e0dd42010-07-29 22:12:43 -07002646 if (status & STS_FATAL) {
Sarah Sharp9032cd52010-07-29 22:12:29 -07002647 xhci_warn(xhci, "WARNING: Host System Error\n");
2648 xhci_halt(xhci);
2649hw_died:
Sarah Sharp9032cd52010-07-29 22:12:29 -07002650 spin_unlock(&xhci->lock);
Joe Lawrence948fa132015-04-30 17:16:04 +03002651 return IRQ_HANDLED;
Sarah Sharp9032cd52010-07-29 22:12:29 -07002652 }
2653
Sarah Sharpbda53142010-07-29 22:12:38 -07002654 /*
2655 * Clear the op reg interrupt status first,
2656 * so we can receive interrupts from other MSI-X interrupters.
2657 * Write 1 to clear the interrupt status.
2658 */
Sarah Sharp27e0dd42010-07-29 22:12:43 -07002659 status |= STS_EINT;
Xenia Ragiadakou204b7792013-11-15 05:34:07 +02002660 writel(status, &xhci->op_regs->status);
Sarah Sharpbda53142010-07-29 22:12:38 -07002661 /* FIXME when MSI-X is supported and there are multiple vectors */
2662 /* Clear the MSI-X event interrupt status */
2663
Felipe Balbicd704692012-02-29 16:46:23 +02002664 if (hcd->irq) {
Sarah Sharpc21599a2010-07-29 22:13:00 -07002665 u32 irq_pending;
2666 /* Acknowledge the PCI interrupt */
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +02002667 irq_pending = readl(&xhci->ir_set->irq_pending);
Felipe Balbi4e833c02012-03-15 16:37:08 +02002668 irq_pending |= IMAN_IP;
Xenia Ragiadakou204b7792013-11-15 05:34:07 +02002669 writel(irq_pending, &xhci->ir_set->irq_pending);
Sarah Sharpc21599a2010-07-29 22:13:00 -07002670 }
Sarah Sharpbda53142010-07-29 22:12:38 -07002671
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002672 if (xhci->xhc_state & XHCI_STATE_DYING) {
Sarah Sharpbda53142010-07-29 22:12:38 -07002673 xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2674 "Shouldn't IRQs be disabled?\n");
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002675 /* Clear the event handler busy flag (RW1C);
2676 * the event ring should be empty.
Sarah Sharpbda53142010-07-29 22:12:38 -07002677 */
Sarah Sharpf7b2e402014-01-30 13:27:49 -08002678 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
Sarah Sharp477632d2014-01-29 14:02:00 -08002679 xhci_write_64(xhci, temp_64 | ERST_EHB,
2680 &xhci->ir_set->erst_dequeue);
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002681 spin_unlock(&xhci->lock);
2682
2683 return IRQ_HANDLED;
2684 }
2685
2686 event_ring_deq = xhci->event_ring->dequeue;
2687 /* FIXME this should be a delayed service routine
2688 * that clears the EHB.
2689 */
Matt Evans9dee9a22011-03-29 13:41:02 +11002690 while (xhci_handle_event(xhci) > 0) {}
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002691
Sarah Sharpf7b2e402014-01-30 13:27:49 -08002692 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002693 /* If necessary, update the HW's version of the event ring deq ptr. */
2694 if (event_ring_deq != xhci->event_ring->dequeue) {
2695 deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2696 xhci->event_ring->dequeue);
2697 if (deq == 0)
2698 xhci_warn(xhci, "WARN something wrong with SW event "
2699 "ring dequeue ptr.\n");
2700 /* Update HC event ring dequeue pointer */
2701 temp_64 &= ERST_PTR_MASK;
2702 temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2703 }
Sarah Sharpbda53142010-07-29 22:12:38 -07002704
2705 /* Clear the event handler busy flag (RW1C); event ring is empty. */
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002706 temp_64 |= ERST_EHB;
Sarah Sharp477632d2014-01-29 14:02:00 -08002707 xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
Sarah Sharpc06d68b2010-07-29 22:12:49 -07002708
Sarah Sharp9032cd52010-07-29 22:12:29 -07002709 spin_unlock(&xhci->lock);
2710
2711 return IRQ_HANDLED;
2712}
2713
Alex Shi851ec162013-05-24 10:54:19 +08002714irqreturn_t xhci_msi_irq(int irq, void *hcd)
Sarah Sharp9032cd52010-07-29 22:12:29 -07002715{
Alan Stern968b8222011-11-03 12:03:38 -04002716 return xhci_irq(hcd);
Sarah Sharp9032cd52010-07-29 22:12:29 -07002717}
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002718
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002719/**** Endpoint Ring Operations ****/
2720
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002721/*
2722 * Generic function for queueing a TRB on a ring.
2723 * The caller must have checked to make sure there's room on the ring.
Sarah Sharp6cc30d82010-06-10 12:25:28 -07002724 *
2725 * @more_trbs_coming: Will you enqueue more TRBs before calling
2726 * prepare_transfer()?
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002727 */
2728static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
Andiry Xu3b72fca2012-03-05 17:49:32 +08002729 bool more_trbs_coming,
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002730 u32 field1, u32 field2, u32 field3, u32 field4)
2731{
2732 struct xhci_generic_trb *trb;
2733
2734 trb = &ring->enqueue->generic;
Matt Evans28ccd292011-03-29 13:40:46 +11002735 trb->field[0] = cpu_to_le32(field1);
2736 trb->field[1] = cpu_to_le32(field2);
2737 trb->field[2] = cpu_to_le32(field3);
2738 trb->field[3] = cpu_to_le32(field4);
Andiry Xu3b72fca2012-03-05 17:49:32 +08002739 inc_enq(xhci, ring, more_trbs_coming);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07002740}
2741
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002742/*
2743 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2744 * FIXME allocate segments if the ring is full.
2745 */
2746static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
Andiry Xu3b72fca2012-03-05 17:49:32 +08002747 u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002748{
Andiry Xu8dfec612012-03-05 17:49:37 +08002749 unsigned int num_trbs_needed;
2750
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002751 /* Make sure the endpoint has been added to xHC schedule */
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002752 switch (ep_state) {
2753 case EP_STATE_DISABLED:
2754 /*
2755 * USB core changed config/interfaces without notifying us,
2756 * or hardware is reporting the wrong state.
2757 */
2758 xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2759 return -ENOENT;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002760 case EP_STATE_ERROR:
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07002761 xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002762 /* FIXME event handling code for error needs to clear it */
2763 /* XXX not sure if this should be -ENOENT or not */
2764 return -EINVAL;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07002765 case EP_STATE_HALTED:
2766 xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002767 case EP_STATE_STOPPED:
2768 case EP_STATE_RUNNING:
2769 break;
2770 default:
2771 xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2772 /*
2773 * FIXME issue Configure Endpoint command to try to get the HC
2774 * back into a known state.
2775 */
2776 return -EINVAL;
2777 }
Andiry Xu8dfec612012-03-05 17:49:37 +08002778
2779 while (1) {
Sarah Sharp3d4b81e2014-01-31 11:52:57 -08002780 if (room_on_ring(xhci, ep_ring, num_trbs))
2781 break;
Andiry Xu8dfec612012-03-05 17:49:37 +08002782
2783 if (ep_ring == xhci->cmd_ring) {
2784 xhci_err(xhci, "Do not support expand command ring\n");
2785 return -ENOMEM;
2786 }
2787
Xenia Ragiadakou68ffb012013-08-14 06:33:56 +03002788 xhci_dbg_trace(xhci, trace_xhci_dbg_ring_expansion,
2789 "ERROR no room on ep ring, try ring expansion");
Andiry Xu8dfec612012-03-05 17:49:37 +08002790 num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2791 if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2792 mem_flags)) {
2793 xhci_err(xhci, "Ring expansion failed\n");
2794 return -ENOMEM;
2795 }
Peter Senna Tschudin261fa122012-09-12 19:03:17 +02002796 }
John Youn6c12db92010-05-10 15:33:00 -07002797
2798 if (enqueue_is_link_trb(ep_ring)) {
2799 struct xhci_ring *ring = ep_ring;
2800 union xhci_trb *next;
John Youn6c12db92010-05-10 15:33:00 -07002801
John Youn6c12db92010-05-10 15:33:00 -07002802 next = ring->enqueue;
2803
2804 while (last_trb(xhci, ring, ring->enq_seg, next)) {
Andiry Xu7e393a82011-09-23 14:19:54 -07002805 /* If we're not dealing with 0.95 hardware or isoc rings
2806 * on AMD 0.96 host, clear the chain bit.
John Youn6c12db92010-05-10 15:33:00 -07002807 */
Andiry Xu3b72fca2012-03-05 17:49:32 +08002808 if (!xhci_link_trb_quirk(xhci) &&
2809 !(ring->type == TYPE_ISOC &&
2810 (xhci->quirks & XHCI_AMD_0x96_HOST)))
Matt Evans28ccd292011-03-29 13:40:46 +11002811 next->link.control &= cpu_to_le32(~TRB_CHAIN);
John Youn6c12db92010-05-10 15:33:00 -07002812 else
Matt Evans28ccd292011-03-29 13:40:46 +11002813 next->link.control |= cpu_to_le32(TRB_CHAIN);
John Youn6c12db92010-05-10 15:33:00 -07002814
2815 wmb();
Matt Evansf5960b62011-06-01 10:22:55 +10002816 next->link.control ^= cpu_to_le32(TRB_CYCLE);
John Youn6c12db92010-05-10 15:33:00 -07002817
2818 /* Toggle the cycle bit after the last ring segment. */
2819 if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
Lin Wange5401bf2015-03-17 18:32:21 +02002820 ring->cycle_state ^= 1;
John Youn6c12db92010-05-10 15:33:00 -07002821 }
2822 ring->enq_seg = ring->enq_seg->next;
2823 ring->enqueue = ring->enq_seg->trbs;
2824 next = ring->enqueue;
2825 }
2826 }
2827
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002828 return 0;
2829}
2830
Sarah Sharp23e3be12009-04-29 19:05:20 -07002831static int prepare_transfer(struct xhci_hcd *xhci,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002832 struct xhci_virt_device *xdev,
2833 unsigned int ep_index,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002834 unsigned int stream_id,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002835 unsigned int num_trbs,
2836 struct urb *urb,
Andiry Xu8e51adc2010-07-22 15:23:31 -07002837 unsigned int td_index,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002838 gfp_t mem_flags)
2839{
2840 int ret;
Andiry Xu8e51adc2010-07-22 15:23:31 -07002841 struct urb_priv *urb_priv;
2842 struct xhci_td *td;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002843 struct xhci_ring *ep_ring;
John Yound115b042009-07-27 12:05:15 -07002844 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002845
2846 ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2847 if (!ep_ring) {
2848 xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2849 stream_id);
2850 return -EINVAL;
2851 }
2852
2853 ret = prepare_ring(xhci, ep_ring,
Matt Evans28ccd292011-03-29 13:40:46 +11002854 le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
Andiry Xu3b72fca2012-03-05 17:49:32 +08002855 num_trbs, mem_flags);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002856 if (ret)
2857 return ret;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002858
Andiry Xu8e51adc2010-07-22 15:23:31 -07002859 urb_priv = urb->hcpriv;
2860 td = urb_priv->td[td_index];
2861
2862 INIT_LIST_HEAD(&td->td_list);
2863 INIT_LIST_HEAD(&td->cancelled_td_list);
2864
2865 if (td_index == 0) {
Sarah Sharp214f76f2010-10-26 11:22:02 -07002866 ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
Sarah Sharpd13565c2011-07-22 14:34:34 -07002867 if (unlikely(ret))
Andiry Xu8e51adc2010-07-22 15:23:31 -07002868 return ret;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002869 }
2870
Andiry Xu8e51adc2010-07-22 15:23:31 -07002871 td->urb = urb;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002872 /* Add this TD to the tail of the endpoint ring's TD list */
Andiry Xu8e51adc2010-07-22 15:23:31 -07002873 list_add_tail(&td->td_list, &ep_ring->td_list);
2874 td->start_seg = ep_ring->enq_seg;
2875 td->first_trb = ep_ring->enqueue;
2876
2877 urb_priv->td[td_index] = td;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07002878
2879 return 0;
2880}
2881
Sarah Sharp23e3be12009-04-29 19:05:20 -07002882static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002883{
2884 int num_sgs, num_trbs, running_total, temp, i;
2885 struct scatterlist *sg;
2886
2887 sg = NULL;
Clemens Ladischbc677d52011-12-03 23:41:31 +01002888 num_sgs = urb->num_mapped_sgs;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002889 temp = urb->transfer_buffer_length;
2890
Sarah Sharp8a96c052009-04-27 19:59:19 -07002891 num_trbs = 0;
Matthew Wilcox910f8d02010-05-01 12:20:01 -06002892 for_each_sg(urb->sg, sg, num_sgs, i) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002893 unsigned int len = sg_dma_len(sg);
2894
2895 /* Scatter gather list entries may cross 64KB boundaries */
2896 running_total = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08002897 (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
Paul Zimmerman58077952011-02-12 14:07:20 -08002898 running_total &= TRB_MAX_BUFF_SIZE - 1;
Sarah Sharp8a96c052009-04-27 19:59:19 -07002899 if (running_total != 0)
2900 num_trbs++;
2901
2902 /* How many more 64KB chunks to transfer, how many more TRBs? */
Paul Zimmermanbcd2fde2011-02-12 14:07:57 -08002903 while (running_total < sg_dma_len(sg) && running_total < temp) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07002904 num_trbs++;
2905 running_total += TRB_MAX_BUFF_SIZE;
2906 }
Sarah Sharp8a96c052009-04-27 19:59:19 -07002907 len = min_t(int, len, temp);
2908 temp -= len;
2909 if (temp == 0)
2910 break;
2911 }
Sarah Sharp8a96c052009-04-27 19:59:19 -07002912 return num_trbs;
2913}
2914
Sarah Sharp23e3be12009-04-29 19:05:20 -07002915static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002916{
2917 if (num_trbs != 0)
Paul Zimmermana2490182011-02-12 14:06:44 -08002918 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
Sarah Sharp8a96c052009-04-27 19:59:19 -07002919 "TRBs, %d left\n", __func__,
2920 urb->ep->desc.bEndpointAddress, num_trbs);
2921 if (running_total != urb->transfer_buffer_length)
Paul Zimmermana2490182011-02-12 14:06:44 -08002922 dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
Sarah Sharp8a96c052009-04-27 19:59:19 -07002923 "queued %#x (%d), asked for %#x (%d)\n",
2924 __func__,
2925 urb->ep->desc.bEndpointAddress,
2926 running_total, running_total,
2927 urb->transfer_buffer_length,
2928 urb->transfer_buffer_length);
2929}
2930
Sarah Sharp23e3be12009-04-29 19:05:20 -07002931static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
Sarah Sharpe9df17e2010-04-02 15:34:43 -07002932 unsigned int ep_index, unsigned int stream_id, int start_cycle,
Andiry Xue1eab2e2011-01-04 16:30:39 -08002933 struct xhci_generic_trb *start_trb)
Sarah Sharp8a96c052009-04-27 19:59:19 -07002934{
Sarah Sharp8a96c052009-04-27 19:59:19 -07002935 /*
2936 * Pass all the TRBs to the hardware at once and make sure this write
2937 * isn't reordered.
2938 */
2939 wmb();
Andiry Xu50f7b522010-12-20 15:09:34 +08002940 if (start_cycle)
Matt Evans28ccd292011-03-29 13:40:46 +11002941 start_trb->field[3] |= cpu_to_le32(start_cycle);
Andiry Xu50f7b522010-12-20 15:09:34 +08002942 else
Matt Evans28ccd292011-03-29 13:40:46 +11002943 start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
Andiry Xube88fe42010-10-14 07:22:57 -07002944 xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
Sarah Sharp8a96c052009-04-27 19:59:19 -07002945}
2946
Sarah Sharp624defa2009-09-02 12:14:28 -07002947/*
2948 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2949 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2950 * (comprised of sg list entries) can take several service intervals to
2951 * transmit.
2952 */
2953int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
2954 struct urb *urb, int slot_id, unsigned int ep_index)
2955{
2956 struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
2957 xhci->devs[slot_id]->out_ctx, ep_index);
2958 int xhci_interval;
2959 int ep_interval;
2960
Matt Evans28ccd292011-03-29 13:40:46 +11002961 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
Sarah Sharp624defa2009-09-02 12:14:28 -07002962 ep_interval = urb->interval;
2963 /* Convert to microframes */
2964 if (urb->dev->speed == USB_SPEED_LOW ||
2965 urb->dev->speed == USB_SPEED_FULL)
2966 ep_interval *= 8;
2967 /* FIXME change this to a warning and a suggestion to use the new API
2968 * to set the polling interval (once the API is added).
2969 */
2970 if (xhci_interval != ep_interval) {
Dmitry Kasatkin0730d522013-08-27 17:47:35 +03002971 dev_dbg_ratelimited(&urb->dev->dev,
2972 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
2973 ep_interval, ep_interval == 1 ? "" : "s",
2974 xhci_interval, xhci_interval == 1 ? "" : "s");
Sarah Sharp624defa2009-09-02 12:14:28 -07002975 urb->interval = xhci_interval;
2976 /* Convert back to frames for LS/FS devices */
2977 if (urb->dev->speed == USB_SPEED_LOW ||
2978 urb->dev->speed == USB_SPEED_FULL)
2979 urb->interval /= 8;
2980 }
Dan Carpenter3fc82062012-03-28 10:30:26 +03002981 return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
Sarah Sharp624defa2009-09-02 12:14:28 -07002982}
2983
Sarah Sharp04dd9502009-11-11 10:28:30 -08002984/*
2985 * The TD size is the number of bytes remaining in the TD (including this TRB),
2986 * right shifted by 10.
2987 * It must fit in bits 21:17, so it can't be bigger than 31.
2988 */
2989static u32 xhci_td_remainder(unsigned int remainder)
2990{
2991 u32 max = (1 << (21 - 17 + 1)) - 1;
2992
2993 if ((remainder >> 10) >= max)
2994 return max << 17;
2995 else
2996 return (remainder >> 10) << 17;
2997}
2998
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07002999/*
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003000 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3001 * packets remaining in the TD (*not* including this TRB).
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003002 *
3003 * Total TD packet count = total_packet_count =
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003004 * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003005 *
3006 * Packets transferred up to and including this TRB = packets_transferred =
3007 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3008 *
3009 * TD size = total_packet_count - packets_transferred
3010 *
3011 * It must fit in bits 21:17, so it can't be bigger than 31.
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003012 * The last TRB in a TD must have the TD size set to zero.
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003013 */
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003014static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003015 unsigned int total_packet_count, struct urb *urb,
3016 unsigned int num_trbs_left)
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003017{
3018 int packets_transferred;
3019
Sarah Sharp48df4a62011-08-12 10:23:01 -07003020 /* One TRB with a zero-length data packet. */
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003021 if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
Sarah Sharp48df4a62011-08-12 10:23:01 -07003022 return 0;
3023
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003024 /* All the TRB queueing functions don't count the current TRB in
3025 * running_total.
3026 */
3027 packets_transferred = (running_total + trb_buff_len) /
Sarah Sharpf18f8ed2013-01-11 13:36:35 -08003028 GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003029
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003030 if ((total_packet_count - packets_transferred) > 31)
3031 return 31 << 17;
3032 return (total_packet_count - packets_transferred) << 17;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003033}
3034
Sarah Sharp23e3be12009-04-29 19:05:20 -07003035static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharp8a96c052009-04-27 19:59:19 -07003036 struct urb *urb, int slot_id, unsigned int ep_index)
3037{
3038 struct xhci_ring *ep_ring;
3039 unsigned int num_trbs;
Andiry Xu8e51adc2010-07-22 15:23:31 -07003040 struct urb_priv *urb_priv;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003041 struct xhci_td *td;
3042 struct scatterlist *sg;
3043 int num_sgs;
3044 int trb_buff_len, this_sg_len, running_total;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003045 unsigned int total_packet_count;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003046 bool first_trb;
3047 u64 addr;
Sarah Sharp6cc30d82010-06-10 12:25:28 -07003048 bool more_trbs_coming;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003049
3050 struct xhci_generic_trb *start_trb;
3051 int start_cycle;
3052
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003053 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3054 if (!ep_ring)
3055 return -EINVAL;
3056
Sarah Sharp8a96c052009-04-27 19:59:19 -07003057 num_trbs = count_sg_trbs_needed(xhci, urb);
Clemens Ladischbc677d52011-12-03 23:41:31 +01003058 num_sgs = urb->num_mapped_sgs;
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003059 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07003060 usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharp8a96c052009-04-27 19:59:19 -07003061
Sarah Sharp23e3be12009-04-29 19:05:20 -07003062 trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003063 ep_index, urb->stream_id,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003064 num_trbs, urb, 0, mem_flags);
Sarah Sharp8a96c052009-04-27 19:59:19 -07003065 if (trb_buff_len < 0)
3066 return trb_buff_len;
Andiry Xu8e51adc2010-07-22 15:23:31 -07003067
3068 urb_priv = urb->hcpriv;
3069 td = urb_priv->td[0];
3070
Sarah Sharp8a96c052009-04-27 19:59:19 -07003071 /*
3072 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3073 * until we've finished creating all the other TRBs. The ring's cycle
3074 * state may change as we enqueue the other TRBs, so save it too.
3075 */
3076 start_trb = &ep_ring->enqueue->generic;
3077 start_cycle = ep_ring->cycle_state;
3078
3079 running_total = 0;
3080 /*
3081 * How much data is in the first TRB?
3082 *
3083 * There are three forces at work for TRB buffer pointers and lengths:
3084 * 1. We don't want to walk off the end of this sg-list entry buffer.
3085 * 2. The transfer length that the driver requested may be smaller than
3086 * the amount of memory allocated for this scatter-gather list.
3087 * 3. TRBs buffers can't cross 64KB boundaries.
3088 */
Matthew Wilcox910f8d02010-05-01 12:20:01 -06003089 sg = urb->sg;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003090 addr = (u64) sg_dma_address(sg);
3091 this_sg_len = sg_dma_len(sg);
Paul Zimmermana2490182011-02-12 14:06:44 -08003092 trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
Sarah Sharp8a96c052009-04-27 19:59:19 -07003093 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3094 if (trb_buff_len > urb->transfer_buffer_length)
3095 trb_buff_len = urb->transfer_buffer_length;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003096
3097 first_trb = true;
3098 /* Queue the first TRB, even if it's zero-length */
3099 do {
3100 u32 field = 0;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003101 u32 length_field = 0;
Sarah Sharp04dd9502009-11-11 10:28:30 -08003102 u32 remainder = 0;
Sarah Sharp8a96c052009-04-27 19:59:19 -07003103
3104 /* Don't change the cycle bit of the first TRB until later */
Andiry Xu50f7b522010-12-20 15:09:34 +08003105 if (first_trb) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07003106 first_trb = false;
Andiry Xu50f7b522010-12-20 15:09:34 +08003107 if (start_cycle == 0)
3108 field |= 0x1;
3109 } else
Sarah Sharp8a96c052009-04-27 19:59:19 -07003110 field |= ep_ring->cycle_state;
3111
3112 /* Chain all the TRBs together; clear the chain bit in the last
3113 * TRB to indicate it's the last TRB in the chain.
3114 */
3115 if (num_trbs > 1) {
3116 field |= TRB_CHAIN;
3117 } else {
3118 /* FIXME - add check for ZERO_PACKET flag before this */
3119 td->last_trb = ep_ring->enqueue;
3120 field |= TRB_IOC;
3121 }
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003122
3123 /* Only set interrupt on short packet for IN endpoints */
3124 if (usb_urb_dir_in(urb))
3125 field |= TRB_ISP;
3126
Sarah Sharp8a96c052009-04-27 19:59:19 -07003127 if (TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08003128 (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
Sarah Sharp8a96c052009-04-27 19:59:19 -07003129 xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3130 xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3131 (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3132 (unsigned int) addr + trb_buff_len);
3133 }
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003134
3135 /* Set the TRB length, TD size, and interrupter fields. */
3136 if (xhci->hci_version < 0x100) {
3137 remainder = xhci_td_remainder(
3138 urb->transfer_buffer_length -
3139 running_total);
3140 } else {
3141 remainder = xhci_v1_0_td_remainder(running_total,
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003142 trb_buff_len, total_packet_count, urb,
3143 num_trbs - 1);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003144 }
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003145 length_field = TRB_LEN(trb_buff_len) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08003146 remainder |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003147 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003148
Sarah Sharp6cc30d82010-06-10 12:25:28 -07003149 if (num_trbs > 1)
3150 more_trbs_coming = true;
3151 else
3152 more_trbs_coming = false;
Andiry Xu3b72fca2012-03-05 17:49:32 +08003153 queue_trb(xhci, ep_ring, more_trbs_coming,
Sarah Sharp8e595a52009-07-27 12:03:31 -07003154 lower_32_bits(addr),
3155 upper_32_bits(addr),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003156 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003157 field | TRB_TYPE(TRB_NORMAL));
Sarah Sharp8a96c052009-04-27 19:59:19 -07003158 --num_trbs;
3159 running_total += trb_buff_len;
3160
3161 /* Calculate length for next transfer --
3162 * Are we done queueing all the TRBs for this sg entry?
3163 */
3164 this_sg_len -= trb_buff_len;
3165 if (this_sg_len == 0) {
3166 --num_sgs;
3167 if (num_sgs == 0)
3168 break;
3169 sg = sg_next(sg);
3170 addr = (u64) sg_dma_address(sg);
3171 this_sg_len = sg_dma_len(sg);
3172 } else {
3173 addr += trb_buff_len;
3174 }
3175
3176 trb_buff_len = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08003177 (addr & (TRB_MAX_BUFF_SIZE - 1));
Sarah Sharp8a96c052009-04-27 19:59:19 -07003178 trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3179 if (running_total + trb_buff_len > urb->transfer_buffer_length)
3180 trb_buff_len =
3181 urb->transfer_buffer_length - running_total;
3182 } while (running_total < urb->transfer_buffer_length);
3183
3184 check_trb_math(urb, num_trbs, running_total);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003185 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
Andiry Xue1eab2e2011-01-04 16:30:39 -08003186 start_cycle, start_trb);
Sarah Sharp8a96c052009-04-27 19:59:19 -07003187 return 0;
3188}
3189
Sarah Sharpb10de142009-04-27 19:58:50 -07003190/* This is very similar to what ehci-q.c qtd_fill() does */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003191int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharpb10de142009-04-27 19:58:50 -07003192 struct urb *urb, int slot_id, unsigned int ep_index)
3193{
3194 struct xhci_ring *ep_ring;
Andiry Xu8e51adc2010-07-22 15:23:31 -07003195 struct urb_priv *urb_priv;
Sarah Sharpb10de142009-04-27 19:58:50 -07003196 struct xhci_td *td;
3197 int num_trbs;
3198 struct xhci_generic_trb *start_trb;
3199 bool first_trb;
Sarah Sharp6cc30d82010-06-10 12:25:28 -07003200 bool more_trbs_coming;
Sarah Sharpb10de142009-04-27 19:58:50 -07003201 int start_cycle;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003202 u32 field, length_field;
Sarah Sharpb10de142009-04-27 19:58:50 -07003203
3204 int running_total, trb_buff_len, ret;
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003205 unsigned int total_packet_count;
Sarah Sharpb10de142009-04-27 19:58:50 -07003206 u64 addr;
3207
Alan Sternff9c8952010-04-02 13:27:28 -04003208 if (urb->num_sgs)
Sarah Sharp8a96c052009-04-27 19:59:19 -07003209 return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3210
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003211 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3212 if (!ep_ring)
3213 return -EINVAL;
Sarah Sharpb10de142009-04-27 19:58:50 -07003214
3215 num_trbs = 0;
3216 /* How much data is (potentially) left before the 64KB boundary? */
3217 running_total = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08003218 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
Paul Zimmerman58077952011-02-12 14:07:20 -08003219 running_total &= TRB_MAX_BUFF_SIZE - 1;
Sarah Sharpb10de142009-04-27 19:58:50 -07003220
3221 /* If there's some data on this 64KB chunk, or we have to send a
3222 * zero-length transfer, we need at least one TRB
3223 */
3224 if (running_total != 0 || urb->transfer_buffer_length == 0)
3225 num_trbs++;
3226 /* How many more 64KB chunks to transfer, how many more TRBs? */
3227 while (running_total < urb->transfer_buffer_length) {
3228 num_trbs++;
3229 running_total += TRB_MAX_BUFF_SIZE;
3230 }
3231 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3232
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003233 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3234 ep_index, urb->stream_id,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003235 num_trbs, urb, 0, mem_flags);
Sarah Sharpb10de142009-04-27 19:58:50 -07003236 if (ret < 0)
3237 return ret;
3238
Andiry Xu8e51adc2010-07-22 15:23:31 -07003239 urb_priv = urb->hcpriv;
3240 td = urb_priv->td[0];
3241
Sarah Sharpb10de142009-04-27 19:58:50 -07003242 /*
3243 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3244 * until we've finished creating all the other TRBs. The ring's cycle
3245 * state may change as we enqueue the other TRBs, so save it too.
3246 */
3247 start_trb = &ep_ring->enqueue->generic;
3248 start_cycle = ep_ring->cycle_state;
3249
3250 running_total = 0;
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003251 total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
Kuninori Morimoto29cc8892011-08-23 03:12:03 -07003252 usb_endpoint_maxp(&urb->ep->desc));
Sarah Sharpb10de142009-04-27 19:58:50 -07003253 /* How much data is in the first TRB? */
3254 addr = (u64) urb->transfer_dma;
3255 trb_buff_len = TRB_MAX_BUFF_SIZE -
Paul Zimmermana2490182011-02-12 14:06:44 -08003256 (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3257 if (trb_buff_len > urb->transfer_buffer_length)
Sarah Sharpb10de142009-04-27 19:58:50 -07003258 trb_buff_len = urb->transfer_buffer_length;
3259
3260 first_trb = true;
3261
3262 /* Queue the first TRB, even if it's zero-length */
3263 do {
Sarah Sharp04dd9502009-11-11 10:28:30 -08003264 u32 remainder = 0;
Sarah Sharpb10de142009-04-27 19:58:50 -07003265 field = 0;
3266
3267 /* Don't change the cycle bit of the first TRB until later */
Andiry Xu50f7b522010-12-20 15:09:34 +08003268 if (first_trb) {
Sarah Sharpb10de142009-04-27 19:58:50 -07003269 first_trb = false;
Andiry Xu50f7b522010-12-20 15:09:34 +08003270 if (start_cycle == 0)
3271 field |= 0x1;
3272 } else
Sarah Sharpb10de142009-04-27 19:58:50 -07003273 field |= ep_ring->cycle_state;
3274
3275 /* Chain all the TRBs together; clear the chain bit in the last
3276 * TRB to indicate it's the last TRB in the chain.
3277 */
3278 if (num_trbs > 1) {
3279 field |= TRB_CHAIN;
3280 } else {
3281 /* FIXME - add check for ZERO_PACKET flag before this */
3282 td->last_trb = ep_ring->enqueue;
3283 field |= TRB_IOC;
3284 }
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003285
3286 /* Only set interrupt on short packet for IN endpoints */
3287 if (usb_urb_dir_in(urb))
3288 field |= TRB_ISP;
3289
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003290 /* Set the TRB length, TD size, and interrupter fields. */
3291 if (xhci->hci_version < 0x100) {
3292 remainder = xhci_td_remainder(
3293 urb->transfer_buffer_length -
3294 running_total);
3295 } else {
3296 remainder = xhci_v1_0_td_remainder(running_total,
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003297 trb_buff_len, total_packet_count, urb,
3298 num_trbs - 1);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003299 }
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003300 length_field = TRB_LEN(trb_buff_len) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08003301 remainder |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003302 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003303
Sarah Sharp6cc30d82010-06-10 12:25:28 -07003304 if (num_trbs > 1)
3305 more_trbs_coming = true;
3306 else
3307 more_trbs_coming = false;
Andiry Xu3b72fca2012-03-05 17:49:32 +08003308 queue_trb(xhci, ep_ring, more_trbs_coming,
Sarah Sharp8e595a52009-07-27 12:03:31 -07003309 lower_32_bits(addr),
3310 upper_32_bits(addr),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003311 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003312 field | TRB_TYPE(TRB_NORMAL));
Sarah Sharpb10de142009-04-27 19:58:50 -07003313 --num_trbs;
3314 running_total += trb_buff_len;
3315
3316 /* Calculate length for next transfer */
3317 addr += trb_buff_len;
3318 trb_buff_len = urb->transfer_buffer_length - running_total;
3319 if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3320 trb_buff_len = TRB_MAX_BUFF_SIZE;
3321 } while (running_total < urb->transfer_buffer_length);
3322
Sarah Sharp8a96c052009-04-27 19:59:19 -07003323 check_trb_math(urb, num_trbs, running_total);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003324 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
Andiry Xue1eab2e2011-01-04 16:30:39 -08003325 start_cycle, start_trb);
Sarah Sharpb10de142009-04-27 19:58:50 -07003326 return 0;
3327}
3328
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003329/* Caller must have locked xhci->lock */
Sarah Sharp23e3be12009-04-29 19:05:20 -07003330int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003331 struct urb *urb, int slot_id, unsigned int ep_index)
3332{
3333 struct xhci_ring *ep_ring;
3334 int num_trbs;
3335 int ret;
3336 struct usb_ctrlrequest *setup;
3337 struct xhci_generic_trb *start_trb;
3338 int start_cycle;
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003339 u32 field, length_field;
Andiry Xu8e51adc2010-07-22 15:23:31 -07003340 struct urb_priv *urb_priv;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003341 struct xhci_td *td;
3342
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003343 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3344 if (!ep_ring)
3345 return -EINVAL;
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003346
3347 /*
3348 * Need to copy setup packet into setup TRB, so we can't use the setup
3349 * DMA address.
3350 */
3351 if (!urb->setup_packet)
3352 return -EINVAL;
3353
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003354 /* 1 TRB for setup, 1 for status */
3355 num_trbs = 2;
3356 /*
3357 * Don't need to check if we need additional event data and normal TRBs,
3358 * since data in control transfers will never get bigger than 16MB
3359 * XXX: can we get a buffer that crosses 64KB boundaries?
3360 */
3361 if (urb->transfer_buffer_length > 0)
3362 num_trbs++;
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003363 ret = prepare_transfer(xhci, xhci->devs[slot_id],
3364 ep_index, urb->stream_id,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003365 num_trbs, urb, 0, mem_flags);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003366 if (ret < 0)
3367 return ret;
3368
Andiry Xu8e51adc2010-07-22 15:23:31 -07003369 urb_priv = urb->hcpriv;
3370 td = urb_priv->td[0];
3371
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003372 /*
3373 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3374 * until we've finished creating all the other TRBs. The ring's cycle
3375 * state may change as we enqueue the other TRBs, so save it too.
3376 */
3377 start_trb = &ep_ring->enqueue->generic;
3378 start_cycle = ep_ring->cycle_state;
3379
3380 /* Queue setup TRB - see section 6.4.1.2.1 */
3381 /* FIXME better way to translate setup_packet into two u32 fields? */
3382 setup = (struct usb_ctrlrequest *) urb->setup_packet;
Andiry Xu50f7b522010-12-20 15:09:34 +08003383 field = 0;
3384 field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3385 if (start_cycle == 0)
3386 field |= 0x1;
Andiry Xub83cdc82011-05-05 18:13:56 +08003387
3388 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3389 if (xhci->hci_version == 0x100) {
3390 if (urb->transfer_buffer_length > 0) {
3391 if (setup->bRequestType & USB_DIR_IN)
3392 field |= TRB_TX_TYPE(TRB_DATA_IN);
3393 else
3394 field |= TRB_TX_TYPE(TRB_DATA_OUT);
3395 }
3396 }
3397
Andiry Xu3b72fca2012-03-05 17:49:32 +08003398 queue_trb(xhci, ep_ring, true,
Matt Evans28ccd292011-03-29 13:40:46 +11003399 setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3400 le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3401 TRB_LEN(8) | TRB_INTR_TARGET(0),
3402 /* Immediate data in pointer */
3403 field);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003404
3405 /* If there's data, queue data TRBs */
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003406 /* Only set interrupt on short packet for IN endpoints */
3407 if (usb_urb_dir_in(urb))
3408 field = TRB_ISP | TRB_TYPE(TRB_DATA);
3409 else
3410 field = TRB_TYPE(TRB_DATA);
3411
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003412 length_field = TRB_LEN(urb->transfer_buffer_length) |
Sarah Sharp04dd9502009-11-11 10:28:30 -08003413 xhci_td_remainder(urb->transfer_buffer_length) |
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003414 TRB_INTR_TARGET(0);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003415 if (urb->transfer_buffer_length > 0) {
3416 if (setup->bRequestType & USB_DIR_IN)
3417 field |= TRB_DIR_IN;
Andiry Xu3b72fca2012-03-05 17:49:32 +08003418 queue_trb(xhci, ep_ring, true,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003419 lower_32_bits(urb->transfer_dma),
3420 upper_32_bits(urb->transfer_dma),
Sarah Sharpf9dc68f2009-07-27 12:03:07 -07003421 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003422 field | ep_ring->cycle_state);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003423 }
3424
3425 /* Save the DMA address of the last TRB in the TD */
3426 td->last_trb = ep_ring->enqueue;
3427
3428 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3429 /* If the device sent data, the status stage is an OUT transfer */
3430 if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3431 field = 0;
3432 else
3433 field = TRB_DIR_IN;
Andiry Xu3b72fca2012-03-05 17:49:32 +08003434 queue_trb(xhci, ep_ring, false,
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003435 0,
3436 0,
3437 TRB_INTR_TARGET(0),
3438 /* Event on completion */
3439 field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3440
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003441 giveback_first_trb(xhci, slot_id, ep_index, 0,
Andiry Xue1eab2e2011-01-04 16:30:39 -08003442 start_cycle, start_trb);
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003443 return 0;
3444}
3445
Andiry Xu04e51902010-07-22 15:23:39 -07003446static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3447 struct urb *urb, int i)
3448{
3449 int num_trbs = 0;
Sarah Sharp48df4a62011-08-12 10:23:01 -07003450 u64 addr, td_len;
Andiry Xu04e51902010-07-22 15:23:39 -07003451
3452 addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3453 td_len = urb->iso_frame_desc[i].length;
3454
Sarah Sharp48df4a62011-08-12 10:23:01 -07003455 num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3456 TRB_MAX_BUFF_SIZE);
3457 if (num_trbs == 0)
Andiry Xu04e51902010-07-22 15:23:39 -07003458 num_trbs++;
3459
Andiry Xu04e51902010-07-22 15:23:39 -07003460 return num_trbs;
3461}
3462
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003463/*
3464 * The transfer burst count field of the isochronous TRB defines the number of
3465 * bursts that are required to move all packets in this TD. Only SuperSpeed
3466 * devices can burst up to bMaxBurst number of packets per service interval.
3467 * This field is zero based, meaning a value of zero in the field means one
3468 * burst. Basically, for everything but SuperSpeed devices, this field will be
3469 * zero. Only xHCI 1.0 host controllers support this field.
3470 */
3471static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3472 struct usb_device *udev,
3473 struct urb *urb, unsigned int total_packet_count)
3474{
3475 unsigned int max_burst;
3476
3477 if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3478 return 0;
3479
3480 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
Mathias Nyman3213b152014-06-24 17:14:41 +03003481 return DIV_ROUND_UP(total_packet_count, max_burst + 1) - 1;
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003482}
3483
Sarah Sharpb61d3782011-04-19 17:43:33 -07003484/*
3485 * Returns the number of packets in the last "burst" of packets. This field is
3486 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3487 * the last burst packet count is equal to the total number of packets in the
3488 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3489 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3490 * contain 1 to (bMaxBurst + 1) packets.
3491 */
3492static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3493 struct usb_device *udev,
3494 struct urb *urb, unsigned int total_packet_count)
3495{
3496 unsigned int max_burst;
3497 unsigned int residue;
3498
3499 if (xhci->hci_version < 0x100)
3500 return 0;
3501
3502 switch (udev->speed) {
3503 case USB_SPEED_SUPER:
3504 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3505 max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3506 residue = total_packet_count % (max_burst + 1);
3507 /* If residue is zero, the last burst contains (max_burst + 1)
3508 * number of packets, but the TLBPC field is zero-based.
3509 */
3510 if (residue == 0)
3511 return max_burst;
3512 return residue - 1;
3513 default:
3514 if (total_packet_count == 0)
3515 return 0;
3516 return total_packet_count - 1;
3517 }
3518}
3519
Andiry Xu04e51902010-07-22 15:23:39 -07003520/* This is for isoc transfer */
3521static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3522 struct urb *urb, int slot_id, unsigned int ep_index)
3523{
3524 struct xhci_ring *ep_ring;
3525 struct urb_priv *urb_priv;
3526 struct xhci_td *td;
3527 int num_tds, trbs_per_td;
3528 struct xhci_generic_trb *start_trb;
3529 bool first_trb;
3530 int start_cycle;
3531 u32 field, length_field;
3532 int running_total, trb_buff_len, td_len, td_remain_len, ret;
3533 u64 start_addr, addr;
3534 int i, j;
Andiry Xu47cbf692010-12-20 14:49:48 +08003535 bool more_trbs_coming;
Andiry Xu04e51902010-07-22 15:23:39 -07003536
3537 ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3538
3539 num_tds = urb->number_of_packets;
3540 if (num_tds < 1) {
3541 xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3542 return -EINVAL;
3543 }
3544
Andiry Xu04e51902010-07-22 15:23:39 -07003545 start_addr = (u64) urb->transfer_dma;
3546 start_trb = &ep_ring->enqueue->generic;
3547 start_cycle = ep_ring->cycle_state;
3548
Sarah Sharp522989a2011-07-29 12:44:32 -07003549 urb_priv = urb->hcpriv;
Andiry Xu04e51902010-07-22 15:23:39 -07003550 /* Queue the first TRB, even if it's zero-length */
3551 for (i = 0; i < num_tds; i++) {
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003552 unsigned int total_packet_count;
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003553 unsigned int burst_count;
Sarah Sharpb61d3782011-04-19 17:43:33 -07003554 unsigned int residue;
Andiry Xu04e51902010-07-22 15:23:39 -07003555
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003556 first_trb = true;
Andiry Xu04e51902010-07-22 15:23:39 -07003557 running_total = 0;
3558 addr = start_addr + urb->iso_frame_desc[i].offset;
3559 td_len = urb->iso_frame_desc[i].length;
3560 td_remain_len = td_len;
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003561 total_packet_count = DIV_ROUND_UP(td_len,
Sarah Sharpf18f8ed2013-01-11 13:36:35 -08003562 GET_MAX_PACKET(
3563 usb_endpoint_maxp(&urb->ep->desc)));
Sarah Sharp48df4a62011-08-12 10:23:01 -07003564 /* A zero-length transfer still involves at least one packet. */
3565 if (total_packet_count == 0)
3566 total_packet_count++;
Sarah Sharp5cd43e32011-04-08 09:37:29 -07003567 burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3568 total_packet_count);
Sarah Sharpb61d3782011-04-19 17:43:33 -07003569 residue = xhci_get_last_burst_packet_count(xhci,
3570 urb->dev, urb, total_packet_count);
Andiry Xu04e51902010-07-22 15:23:39 -07003571
3572 trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3573
3574 ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003575 urb->stream_id, trbs_per_td, urb, i, mem_flags);
Sarah Sharp522989a2011-07-29 12:44:32 -07003576 if (ret < 0) {
3577 if (i == 0)
3578 return ret;
3579 goto cleanup;
3580 }
Andiry Xu04e51902010-07-22 15:23:39 -07003581
Andiry Xu04e51902010-07-22 15:23:39 -07003582 td = urb_priv->td[i];
Andiry Xu04e51902010-07-22 15:23:39 -07003583 for (j = 0; j < trbs_per_td; j++) {
3584 u32 remainder = 0;
Sarah Sharp760973d2013-01-11 11:19:07 -08003585 field = 0;
Andiry Xu04e51902010-07-22 15:23:39 -07003586
3587 if (first_trb) {
Sarah Sharp760973d2013-01-11 11:19:07 -08003588 field = TRB_TBC(burst_count) |
3589 TRB_TLBPC(residue);
Andiry Xu04e51902010-07-22 15:23:39 -07003590 /* Queue the isoc TRB */
3591 field |= TRB_TYPE(TRB_ISOC);
3592 /* Assume URB_ISO_ASAP is set */
3593 field |= TRB_SIA;
Andiry Xu50f7b522010-12-20 15:09:34 +08003594 if (i == 0) {
3595 if (start_cycle == 0)
3596 field |= 0x1;
3597 } else
Andiry Xu04e51902010-07-22 15:23:39 -07003598 field |= ep_ring->cycle_state;
3599 first_trb = false;
3600 } else {
3601 /* Queue other normal TRBs */
3602 field |= TRB_TYPE(TRB_NORMAL);
3603 field |= ep_ring->cycle_state;
3604 }
3605
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003606 /* Only set interrupt on short packet for IN EPs */
3607 if (usb_urb_dir_in(urb))
3608 field |= TRB_ISP;
3609
Andiry Xu04e51902010-07-22 15:23:39 -07003610 /* Chain all the TRBs together; clear the chain bit in
3611 * the last TRB to indicate it's the last TRB in the
3612 * chain.
3613 */
3614 if (j < trbs_per_td - 1) {
3615 field |= TRB_CHAIN;
Andiry Xu47cbf692010-12-20 14:49:48 +08003616 more_trbs_coming = true;
Andiry Xu04e51902010-07-22 15:23:39 -07003617 } else {
3618 td->last_trb = ep_ring->enqueue;
3619 field |= TRB_IOC;
Sarah Sharp80fab3b2012-09-19 16:27:26 -07003620 if (xhci->hci_version == 0x100 &&
3621 !(xhci->quirks &
3622 XHCI_AVOID_BEI)) {
Andiry Xuad106f22011-05-05 18:14:02 +08003623 /* Set BEI bit except for the last td */
3624 if (i < num_tds - 1)
3625 field |= TRB_BEI;
3626 }
Andiry Xu47cbf692010-12-20 14:49:48 +08003627 more_trbs_coming = false;
Andiry Xu04e51902010-07-22 15:23:39 -07003628 }
3629
3630 /* Calculate TRB length */
3631 trb_buff_len = TRB_MAX_BUFF_SIZE -
3632 (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3633 if (trb_buff_len > td_remain_len)
3634 trb_buff_len = td_remain_len;
3635
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003636 /* Set the TRB length, TD size, & interrupter fields. */
3637 if (xhci->hci_version < 0x100) {
3638 remainder = xhci_td_remainder(
3639 td_len - running_total);
3640 } else {
3641 remainder = xhci_v1_0_td_remainder(
3642 running_total, trb_buff_len,
Sarah Sharp4525c0a2012-10-25 15:56:40 -07003643 total_packet_count, urb,
3644 (trbs_per_td - j - 1));
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003645 }
Andiry Xu04e51902010-07-22 15:23:39 -07003646 length_field = TRB_LEN(trb_buff_len) |
3647 remainder |
3648 TRB_INTR_TARGET(0);
Sarah Sharp4da6e6f2011-04-01 14:01:30 -07003649
Andiry Xu3b72fca2012-03-05 17:49:32 +08003650 queue_trb(xhci, ep_ring, more_trbs_coming,
Andiry Xu04e51902010-07-22 15:23:39 -07003651 lower_32_bits(addr),
3652 upper_32_bits(addr),
3653 length_field,
Sarah Sharpaf8b9e62011-03-23 16:26:26 -07003654 field);
Andiry Xu04e51902010-07-22 15:23:39 -07003655 running_total += trb_buff_len;
3656
3657 addr += trb_buff_len;
3658 td_remain_len -= trb_buff_len;
3659 }
3660
3661 /* Check TD length */
3662 if (running_total != td_len) {
3663 xhci_err(xhci, "ISOC TD length unmatch\n");
Andiry Xucf840552012-01-18 17:47:12 +08003664 ret = -EINVAL;
3665 goto cleanup;
Andiry Xu04e51902010-07-22 15:23:39 -07003666 }
3667 }
3668
Andiry Xuc41136b2011-03-22 17:08:14 +08003669 if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3670 if (xhci->quirks & XHCI_AMD_PLL_FIX)
3671 usb_amd_quirk_pll_disable();
3672 }
3673 xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3674
Andiry Xue1eab2e2011-01-04 16:30:39 -08003675 giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3676 start_cycle, start_trb);
Andiry Xu04e51902010-07-22 15:23:39 -07003677 return 0;
Sarah Sharp522989a2011-07-29 12:44:32 -07003678cleanup:
3679 /* Clean up a partially enqueued isoc transfer. */
3680
3681 for (i--; i >= 0; i--)
Sarah Sharp585df1d2011-08-02 15:43:40 -07003682 list_del_init(&urb_priv->td[i]->td_list);
Sarah Sharp522989a2011-07-29 12:44:32 -07003683
3684 /* Use the first TD as a temporary variable to turn the TDs we've queued
3685 * into No-ops with a software-owned cycle bit. That way the hardware
3686 * won't accidentally start executing bogus TDs when we partially
3687 * overwrite them. td->first_trb and td->start_seg are already set.
3688 */
3689 urb_priv->td[0]->last_trb = ep_ring->enqueue;
3690 /* Every TRB except the first & last will have its cycle bit flipped. */
3691 td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3692
3693 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3694 ep_ring->enqueue = urb_priv->td[0]->first_trb;
3695 ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3696 ep_ring->cycle_state = start_cycle;
Andiry Xub008df62012-03-05 17:49:34 +08003697 ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
Sarah Sharp522989a2011-07-29 12:44:32 -07003698 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3699 return ret;
Andiry Xu04e51902010-07-22 15:23:39 -07003700}
3701
3702/*
3703 * Check transfer ring to guarantee there is enough room for the urb.
3704 * Update ISO URB start_frame and interval.
3705 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3706 * update the urb->start_frame by now.
3707 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3708 */
3709int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3710 struct urb *urb, int slot_id, unsigned int ep_index)
3711{
3712 struct xhci_virt_device *xdev;
3713 struct xhci_ring *ep_ring;
3714 struct xhci_ep_ctx *ep_ctx;
3715 int start_frame;
3716 int xhci_interval;
3717 int ep_interval;
3718 int num_tds, num_trbs, i;
3719 int ret;
3720
3721 xdev = xhci->devs[slot_id];
3722 ep_ring = xdev->eps[ep_index].ring;
3723 ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3724
3725 num_trbs = 0;
3726 num_tds = urb->number_of_packets;
3727 for (i = 0; i < num_tds; i++)
3728 num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3729
3730 /* Check the ring to guarantee there is enough room for the whole urb.
3731 * Do not insert any td of the urb to the ring if the check failed.
3732 */
Matt Evans28ccd292011-03-29 13:40:46 +11003733 ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003734 num_trbs, mem_flags);
Andiry Xu04e51902010-07-22 15:23:39 -07003735 if (ret)
3736 return ret;
3737
Xenia Ragiadakoub0ba9722013-11-15 05:34:06 +02003738 start_frame = readl(&xhci->run_regs->microframe_index);
Andiry Xu04e51902010-07-22 15:23:39 -07003739 start_frame &= 0x3fff;
3740
3741 urb->start_frame = start_frame;
3742 if (urb->dev->speed == USB_SPEED_LOW ||
3743 urb->dev->speed == USB_SPEED_FULL)
3744 urb->start_frame >>= 3;
3745
Matt Evans28ccd292011-03-29 13:40:46 +11003746 xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
Andiry Xu04e51902010-07-22 15:23:39 -07003747 ep_interval = urb->interval;
3748 /* Convert to microframes */
3749 if (urb->dev->speed == USB_SPEED_LOW ||
3750 urb->dev->speed == USB_SPEED_FULL)
3751 ep_interval *= 8;
3752 /* FIXME change this to a warning and a suggestion to use the new API
3753 * to set the polling interval (once the API is added).
3754 */
3755 if (xhci_interval != ep_interval) {
Dmitry Kasatkin0730d522013-08-27 17:47:35 +03003756 dev_dbg_ratelimited(&urb->dev->dev,
3757 "Driver uses different interval (%d microframe%s) than xHCI (%d microframe%s)\n",
3758 ep_interval, ep_interval == 1 ? "" : "s",
3759 xhci_interval, xhci_interval == 1 ? "" : "s");
Andiry Xu04e51902010-07-22 15:23:39 -07003760 urb->interval = xhci_interval;
3761 /* Convert back to frames for LS/FS devices */
3762 if (urb->dev->speed == USB_SPEED_LOW ||
3763 urb->dev->speed == USB_SPEED_FULL)
3764 urb->interval /= 8;
3765 }
Andiry Xub008df62012-03-05 17:49:34 +08003766 ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3767
Dan Carpenter3fc82062012-03-28 10:30:26 +03003768 return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
Andiry Xu04e51902010-07-22 15:23:39 -07003769}
3770
Sarah Sharpd0e96f52009-04-27 19:58:01 -07003771/**** Command Ring Operations ****/
3772
Sarah Sharp913a8a32009-09-04 10:53:13 -07003773/* Generic function for queueing a command TRB on the command ring.
3774 * Check to make sure there's room on the command ring for one command TRB.
3775 * Also check that there's room reserved for commands that must not fail.
3776 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3777 * then only check for the number of reserved spots.
3778 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3779 * because the command event handler may want to resubmit a failed command.
3780 */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003781static int queue_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
3782 u32 field1, u32 field2,
3783 u32 field3, u32 field4, bool command_must_succeed)
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003784{
Sarah Sharp913a8a32009-09-04 10:53:13 -07003785 int reserved_trbs = xhci->cmd_ring_reserved_trbs;
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003786 int ret;
Roger Quadrosad6b1d92015-05-29 17:01:49 +03003787
3788 if (xhci->xhc_state) {
3789 xhci_dbg(xhci, "xHCI dying or halted, can't queue_command\n");
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03003790 return -ESHUTDOWN;
Roger Quadrosad6b1d92015-05-29 17:01:49 +03003791 }
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003792
Sarah Sharp913a8a32009-09-04 10:53:13 -07003793 if (!command_must_succeed)
3794 reserved_trbs++;
3795
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003796 ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
Andiry Xu3b72fca2012-03-05 17:49:32 +08003797 reserved_trbs, GFP_ATOMIC);
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003798 if (ret < 0) {
3799 xhci_err(xhci, "ERR: No room for command on command ring\n");
Sarah Sharp913a8a32009-09-04 10:53:13 -07003800 if (command_must_succeed)
3801 xhci_err(xhci, "ERR: Reserved TRB counting for "
3802 "unfailable commands failed.\n");
Sarah Sharpd1dc9082010-07-09 17:08:38 +02003803 return ret;
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003804 }
Mathias Nymanc9aa1a22014-05-08 19:26:01 +03003805
3806 cmd->command_trb = xhci->cmd_ring->enqueue;
3807 list_add_tail(&cmd->cmd_list, &xhci->cmd_list);
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003808
Mathias Nymanc311e392014-05-08 19:26:03 +03003809 /* if there are no other commands queued we start the timeout timer */
3810 if (xhci->cmd_list.next == &cmd->cmd_list &&
3811 !timer_pending(&xhci->cmd_timer)) {
3812 xhci->current_cmd = cmd;
3813 mod_timer(&xhci->cmd_timer, jiffies + XHCI_CMD_DEFAULT_TIMEOUT);
3814 }
3815
Andiry Xu3b72fca2012-03-05 17:49:32 +08003816 queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3817 field4 | xhci->cmd_ring->cycle_state);
Sarah Sharp7f84eef2009-04-27 19:53:56 -07003818 return 0;
3819}
3820
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003821/* Queue a slot enable or disable request on the command ring */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003822int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
3823 u32 trb_type, u32 slot_id)
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003824{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003825 return queue_command(xhci, cmd, 0, 0, 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003826 TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003827}
3828
3829/* Queue an address device command TRB */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003830int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3831 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev setup)
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003832{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003833 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
Sarah Sharp8e595a52009-07-27 12:03:31 -07003834 upper_32_bits(in_ctx_ptr), 0,
Dan Williams48fc7db2013-12-05 17:07:27 -08003835 TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id)
3836 | (setup == SETUP_CONTEXT_ONLY ? TRB_BSR : 0), false);
Sarah Sharp3ffbba92009-04-27 19:57:38 -07003837}
Sarah Sharpf94e01862009-04-27 19:58:38 -07003838
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003839int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
Sarah Sharp02386342010-05-24 13:25:28 -07003840 u32 field1, u32 field2, u32 field3, u32 field4)
3841{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003842 return queue_command(xhci, cmd, field1, field2, field3, field4, false);
Sarah Sharp02386342010-05-24 13:25:28 -07003843}
3844
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08003845/* Queue a reset device command TRB */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003846int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
3847 u32 slot_id)
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08003848{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003849 return queue_command(xhci, cmd, 0, 0, 0,
Sarah Sharp2a8f82c2009-12-09 15:59:13 -08003850 TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3851 false);
3852}
3853
Sarah Sharpf94e01862009-04-27 19:58:38 -07003854/* Queue a configure endpoint command TRB */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003855int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
3856 struct xhci_command *cmd, dma_addr_t in_ctx_ptr,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003857 u32 slot_id, bool command_must_succeed)
Sarah Sharpf94e01862009-04-27 19:58:38 -07003858{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003859 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
Sarah Sharp8e595a52009-07-27 12:03:31 -07003860 upper_32_bits(in_ctx_ptr), 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003861 TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3862 command_must_succeed);
Sarah Sharpf94e01862009-04-27 19:58:38 -07003863}
Sarah Sharpae636742009-04-29 19:02:31 -07003864
Sarah Sharpf2217e82009-08-07 14:04:43 -07003865/* Queue an evaluate context command TRB */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003866int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
3867 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed)
Sarah Sharpf2217e82009-08-07 14:04:43 -07003868{
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003869 return queue_command(xhci, cmd, lower_32_bits(in_ctx_ptr),
Sarah Sharpf2217e82009-08-07 14:04:43 -07003870 upper_32_bits(in_ctx_ptr), 0,
Sarah Sharp913a8a32009-09-04 10:53:13 -07003871 TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
Sarah Sharp4b266542012-05-07 15:34:26 -07003872 command_must_succeed);
Sarah Sharpf2217e82009-08-07 14:04:43 -07003873}
3874
Andiry Xube88fe42010-10-14 07:22:57 -07003875/*
3876 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3877 * activity on an endpoint that is about to be suspended.
3878 */
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003879int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
3880 int slot_id, unsigned int ep_index, int suspend)
Sarah Sharpae636742009-04-29 19:02:31 -07003881{
3882 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3883 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3884 u32 type = TRB_TYPE(TRB_STOP_RING);
Andiry Xube88fe42010-10-14 07:22:57 -07003885 u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
Sarah Sharpae636742009-04-29 19:02:31 -07003886
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003887 return queue_command(xhci, cmd, 0, 0, 0,
Andiry Xube88fe42010-10-14 07:22:57 -07003888 trb_slot_id | trb_ep_index | type | trb_suspend, false);
Sarah Sharpae636742009-04-29 19:02:31 -07003889}
3890
Hans de Goeded3a43e62014-08-20 16:41:53 +03003891/* Set Transfer Ring Dequeue Pointer command */
3892void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
3893 unsigned int slot_id, unsigned int ep_index,
3894 unsigned int stream_id,
3895 struct xhci_dequeue_state *deq_state)
Sarah Sharpae636742009-04-29 19:02:31 -07003896{
3897 dma_addr_t addr;
3898 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3899 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
Sarah Sharpe9df17e2010-04-02 15:34:43 -07003900 u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
Hans de Goede95241db2013-10-04 00:29:48 +02003901 u32 trb_sct = 0;
Sarah Sharpae636742009-04-29 19:02:31 -07003902 u32 type = TRB_TYPE(TRB_SET_DEQ);
Sarah Sharpbf161e82011-02-23 15:46:42 -08003903 struct xhci_virt_ep *ep;
Hans de Goede1e3452e2014-08-20 16:41:52 +03003904 struct xhci_command *cmd;
3905 int ret;
Sarah Sharpae636742009-04-29 19:02:31 -07003906
Hans de Goeded3a43e62014-08-20 16:41:53 +03003907 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
3908 "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), new deq ptr = %p (0x%llx dma), new cycle = %u",
3909 deq_state->new_deq_seg,
3910 (unsigned long long)deq_state->new_deq_seg->dma,
3911 deq_state->new_deq_ptr,
3912 (unsigned long long)xhci_trb_virt_to_dma(
3913 deq_state->new_deq_seg, deq_state->new_deq_ptr),
3914 deq_state->new_cycle_state);
3915
3916 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3917 deq_state->new_deq_ptr);
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07003918 if (addr == 0) {
Sarah Sharpae636742009-04-29 19:02:31 -07003919 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
Greg Kroah-Hartman700e2052009-04-29 19:14:08 -07003920 xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
Hans de Goeded3a43e62014-08-20 16:41:53 +03003921 deq_state->new_deq_seg, deq_state->new_deq_ptr);
3922 return;
Sarah Sharpc92bcfa2009-07-27 12:05:21 -07003923 }
Sarah Sharpbf161e82011-02-23 15:46:42 -08003924 ep = &xhci->devs[slot_id]->eps[ep_index];
3925 if ((ep->ep_state & SET_DEQ_PENDING)) {
3926 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3927 xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
Hans de Goeded3a43e62014-08-20 16:41:53 +03003928 return;
Sarah Sharpbf161e82011-02-23 15:46:42 -08003929 }
Hans de Goede1e3452e2014-08-20 16:41:52 +03003930
3931 /* This function gets called from contexts where it cannot sleep */
3932 cmd = xhci_alloc_command(xhci, false, false, GFP_ATOMIC);
3933 if (!cmd) {
3934 xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr: ENOMEM\n");
Hans de Goeded3a43e62014-08-20 16:41:53 +03003935 return;
Hans de Goede1e3452e2014-08-20 16:41:52 +03003936 }
3937
Hans de Goeded3a43e62014-08-20 16:41:53 +03003938 ep->queued_deq_seg = deq_state->new_deq_seg;
3939 ep->queued_deq_ptr = deq_state->new_deq_ptr;
Hans de Goede95241db2013-10-04 00:29:48 +02003940 if (stream_id)
3941 trb_sct = SCT_FOR_TRB(SCT_PRI_TR);
Hans de Goede1e3452e2014-08-20 16:41:52 +03003942 ret = queue_command(xhci, cmd,
Hans de Goeded3a43e62014-08-20 16:41:53 +03003943 lower_32_bits(addr) | trb_sct | deq_state->new_cycle_state,
3944 upper_32_bits(addr), trb_stream_id,
3945 trb_slot_id | trb_ep_index | type, false);
Hans de Goede1e3452e2014-08-20 16:41:52 +03003946 if (ret < 0) {
3947 xhci_free_command(xhci, cmd);
Hans de Goeded3a43e62014-08-20 16:41:53 +03003948 return;
Hans de Goede1e3452e2014-08-20 16:41:52 +03003949 }
3950
Hans de Goeded3a43e62014-08-20 16:41:53 +03003951 /* Stop the TD queueing code from ringing the doorbell until
3952 * this command completes. The HC won't set the dequeue pointer
3953 * if the ring is running, and ringing the doorbell starts the
3954 * ring running.
3955 */
3956 ep->ep_state |= SET_DEQ_PENDING;
Sarah Sharpae636742009-04-29 19:02:31 -07003957}
Sarah Sharpa1587d92009-07-27 12:03:15 -07003958
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003959int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
3960 int slot_id, unsigned int ep_index)
Sarah Sharpa1587d92009-07-27 12:03:15 -07003961{
3962 u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3963 u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3964 u32 type = TRB_TYPE(TRB_RESET_EP);
3965
Mathias Nymanddba5cd2014-05-08 19:26:00 +03003966 return queue_command(xhci, cmd, 0, 0, 0,
3967 trb_slot_id | trb_ep_index | type, false);
Sarah Sharpa1587d92009-07-27 12:03:15 -07003968}