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Emilio López45fb6b62015-09-12 15:26:24 +02001/*
2 * Copyright 2014 Emilio López <emilio@elopez.com.ar>
3 * Copyright 2014 Jon Smirl <jonsmirl@gmail.com>
4 * Copyright 2015 Maxime Ripard <maxime.ripard@free-electrons.com>
Adam Sampson474d1472015-10-27 21:00:45 +00005 * Copyright 2015 Adam Sampson <ats@offog.org>
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08006 * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
Emilio López45fb6b62015-09-12 15:26:24 +02007 *
8 * Based on the Allwinner SDK driver, released under the GPL.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/of.h>
Emilio López45fb6b62015-09-12 15:26:24 +020028#include <linux/of_address.h>
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +080029#include <linux/of_device.h>
30#include <linux/of_platform.h>
Emilio López45fb6b62015-09-12 15:26:24 +020031#include <linux/clk.h>
32#include <linux/regmap.h>
Chen-Yu Tsai9aead152016-11-07 18:06:58 +080033#include <linux/reset.h>
Hans de Goede40592622015-12-11 19:43:57 +010034#include <linux/gpio/consumer.h>
Emilio López45fb6b62015-09-12 15:26:24 +020035
36#include <sound/core.h>
37#include <sound/pcm.h>
38#include <sound/pcm_params.h>
39#include <sound/soc.h>
40#include <sound/tlv.h>
41#include <sound/initval.h>
42#include <sound/dmaengine_pcm.h>
43
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +080044/* Codec DAC digital controls and FIFO registers */
Emilio López45fb6b62015-09-12 15:26:24 +020045#define SUN4I_CODEC_DAC_DPC (0x00)
46#define SUN4I_CODEC_DAC_DPC_EN_DA (31)
47#define SUN4I_CODEC_DAC_DPC_DVOL (12)
48#define SUN4I_CODEC_DAC_FIFOC (0x04)
49#define SUN4I_CODEC_DAC_FIFOC_DAC_FS (29)
50#define SUN4I_CODEC_DAC_FIFOC_FIR_VERSION (28)
51#define SUN4I_CODEC_DAC_FIFOC_SEND_LASAT (26)
52#define SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE (24)
53#define SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT (21)
54#define SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL (8)
55#define SUN4I_CODEC_DAC_FIFOC_MONO_EN (6)
56#define SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS (5)
57#define SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN (4)
58#define SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH (0)
59#define SUN4I_CODEC_DAC_FIFOS (0x08)
60#define SUN4I_CODEC_DAC_TXDATA (0x0c)
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +080061
62/* Codec DAC side analog signal controls */
Emilio López45fb6b62015-09-12 15:26:24 +020063#define SUN4I_CODEC_DAC_ACTL (0x10)
64#define SUN4I_CODEC_DAC_ACTL_DACAENR (31)
65#define SUN4I_CODEC_DAC_ACTL_DACAENL (30)
66#define SUN4I_CODEC_DAC_ACTL_MIXEN (29)
67#define SUN4I_CODEC_DAC_ACTL_LDACLMIXS (15)
68#define SUN4I_CODEC_DAC_ACTL_RDACRMIXS (14)
69#define SUN4I_CODEC_DAC_ACTL_LDACRMIXS (13)
70#define SUN4I_CODEC_DAC_ACTL_DACPAS (8)
71#define SUN4I_CODEC_DAC_ACTL_MIXPAS (7)
72#define SUN4I_CODEC_DAC_ACTL_PA_MUTE (6)
73#define SUN4I_CODEC_DAC_ACTL_PA_VOL (0)
74#define SUN4I_CODEC_DAC_TUNE (0x14)
75#define SUN4I_CODEC_DAC_DEBUG (0x18)
76
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +080077/* Codec ADC digital controls and FIFO registers */
Emilio López45fb6b62015-09-12 15:26:24 +020078#define SUN4I_CODEC_ADC_FIFOC (0x1c)
Maxime Ripard1fb34b42015-11-30 16:37:47 +010079#define SUN4I_CODEC_ADC_FIFOC_ADC_FS (29)
Emilio López45fb6b62015-09-12 15:26:24 +020080#define SUN4I_CODEC_ADC_FIFOC_EN_AD (28)
81#define SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE (24)
82#define SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL (8)
83#define SUN4I_CODEC_ADC_FIFOC_MONO_EN (7)
84#define SUN4I_CODEC_ADC_FIFOC_RX_SAMPLE_BITS (6)
85#define SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN (4)
86#define SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH (0)
87#define SUN4I_CODEC_ADC_FIFOS (0x20)
88#define SUN4I_CODEC_ADC_RXDATA (0x24)
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +080089
90/* Codec ADC side analog signal controls */
Emilio López45fb6b62015-09-12 15:26:24 +020091#define SUN4I_CODEC_ADC_ACTL (0x28)
92#define SUN4I_CODEC_ADC_ACTL_ADC_R_EN (31)
93#define SUN4I_CODEC_ADC_ACTL_ADC_L_EN (30)
94#define SUN4I_CODEC_ADC_ACTL_PREG1EN (29)
95#define SUN4I_CODEC_ADC_ACTL_PREG2EN (28)
96#define SUN4I_CODEC_ADC_ACTL_VMICEN (27)
97#define SUN4I_CODEC_ADC_ACTL_VADCG (20)
98#define SUN4I_CODEC_ADC_ACTL_ADCIS (17)
99#define SUN4I_CODEC_ADC_ACTL_PA_EN (4)
100#define SUN4I_CODEC_ADC_ACTL_DDE (3)
101#define SUN4I_CODEC_ADC_DEBUG (0x2c)
102
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +0800103/* FIFO counters */
Emilio López45fb6b62015-09-12 15:26:24 +0200104#define SUN4I_CODEC_DAC_TXCNT (0x30)
105#define SUN4I_CODEC_ADC_RXCNT (0x34)
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +0800106
107/* Calibration register (sun7i only) */
Danny Milosavljevic4f0c4e92016-09-22 09:13:12 +0200108#define SUN7I_CODEC_AC_DAC_CAL (0x38)
Chen-Yu Tsaibd720ec2016-11-03 15:55:45 +0800109
110/* Microphone controls (sun7i only) */
Danny Milosavljevic4f0c4e92016-09-22 09:13:12 +0200111#define SUN7I_CODEC_AC_MIC_PHONE_CAL (0x3c)
Emilio López45fb6b62015-09-12 15:26:24 +0200112
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800113/*
114 * sun6i specific registers
115 *
116 * sun6i shares the same digital control and FIFO registers as sun4i,
117 * but only the DAC digital controls are at the same offset. The others
118 * have been moved around to accommodate extra analog controls.
119 */
120
121/* Codec DAC digital controls and FIFO registers */
122#define SUN6I_CODEC_ADC_FIFOC (0x10)
123#define SUN6I_CODEC_ADC_FIFOC_EN_AD (28)
124#define SUN6I_CODEC_ADC_FIFOS (0x14)
125#define SUN6I_CODEC_ADC_RXDATA (0x18)
126
127/* Output mixer and gain controls */
128#define SUN6I_CODEC_OM_DACA_CTRL (0x20)
129#define SUN6I_CODEC_OM_DACA_CTRL_DACAREN (31)
130#define SUN6I_CODEC_OM_DACA_CTRL_DACALEN (30)
131#define SUN6I_CODEC_OM_DACA_CTRL_RMIXEN (29)
132#define SUN6I_CODEC_OM_DACA_CTRL_LMIXEN (28)
133#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1 (23)
134#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2 (22)
135#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONE (21)
136#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_PHONEP (20)
137#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR (19)
138#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR (18)
139#define SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL (17)
140#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1 (16)
141#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2 (15)
142#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONE (14)
143#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_PHONEN (13)
144#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL (12)
145#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL (11)
146#define SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR (10)
147#define SUN6I_CODEC_OM_DACA_CTRL_RHPIS (9)
148#define SUN6I_CODEC_OM_DACA_CTRL_LHPIS (8)
149#define SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE (7)
150#define SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE (6)
151#define SUN6I_CODEC_OM_DACA_CTRL_HPVOL (0)
152#define SUN6I_CODEC_OM_PA_CTRL (0x24)
153#define SUN6I_CODEC_OM_PA_CTRL_HPPAEN (31)
154#define SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL (29)
155#define SUN6I_CODEC_OM_PA_CTRL_COMPTEN (28)
156#define SUN6I_CODEC_OM_PA_CTRL_MIC1G (15)
157#define SUN6I_CODEC_OM_PA_CTRL_MIC2G (12)
158#define SUN6I_CODEC_OM_PA_CTRL_LINEING (9)
159#define SUN6I_CODEC_OM_PA_CTRL_PHONEG (6)
160#define SUN6I_CODEC_OM_PA_CTRL_PHONEPG (3)
161#define SUN6I_CODEC_OM_PA_CTRL_PHONENG (0)
162
163/* Microphone, line out and phone out controls */
164#define SUN6I_CODEC_MIC_CTRL (0x28)
165#define SUN6I_CODEC_MIC_CTRL_HBIASEN (31)
166#define SUN6I_CODEC_MIC_CTRL_MBIASEN (30)
167#define SUN6I_CODEC_MIC_CTRL_MIC1AMPEN (28)
168#define SUN6I_CODEC_MIC_CTRL_MIC1BOOST (25)
169#define SUN6I_CODEC_MIC_CTRL_MIC2AMPEN (24)
170#define SUN6I_CODEC_MIC_CTRL_MIC2BOOST (21)
171#define SUN6I_CODEC_MIC_CTRL_MIC2SLT (20)
172#define SUN6I_CODEC_MIC_CTRL_LINEOUTLEN (19)
173#define SUN6I_CODEC_MIC_CTRL_LINEOUTREN (18)
174#define SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC (17)
175#define SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC (16)
176#define SUN6I_CODEC_MIC_CTRL_LINEOUTVC (11)
177#define SUN6I_CODEC_MIC_CTRL_PHONEPREG (8)
178
179/* ADC mixer controls */
180#define SUN6I_CODEC_ADC_ACTL (0x2c)
181#define SUN6I_CODEC_ADC_ACTL_ADCREN (31)
182#define SUN6I_CODEC_ADC_ACTL_ADCLEN (30)
183#define SUN6I_CODEC_ADC_ACTL_ADCRG (27)
184#define SUN6I_CODEC_ADC_ACTL_ADCLG (24)
185#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1 (13)
186#define SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2 (12)
187#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONE (11)
188#define SUN6I_CODEC_ADC_ACTL_RADCMIX_PHONEP (10)
189#define SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR (9)
190#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR (8)
191#define SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL (7)
192#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1 (6)
193#define SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2 (5)
194#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONE (4)
195#define SUN6I_CODEC_ADC_ACTL_LADCMIX_PHONEN (3)
196#define SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL (2)
197#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL (1)
198#define SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR (0)
199
200/* Analog performance tuning controls */
201#define SUN6I_CODEC_ADDA_TUNE (0x30)
202
203/* Calibration controls */
204#define SUN6I_CODEC_CALIBRATION (0x34)
205
206/* FIFO counters */
207#define SUN6I_CODEC_DAC_TXCNT (0x40)
208#define SUN6I_CODEC_ADC_RXCNT (0x44)
209
210/* headset jack detection and button support registers */
211#define SUN6I_CODEC_HMIC_CTL (0x50)
212#define SUN6I_CODEC_HMIC_DATA (0x54)
213
214/* TODO sun6i DAP (Digital Audio Processing) bits */
215
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +0800216/* FIFO counters moved on A23 */
217#define SUN8I_A23_CODEC_DAC_TXCNT (0x1c)
218#define SUN8I_A23_CODEC_ADC_RXCNT (0x20)
219
Chen-Yu Tsai4a15b242016-11-25 20:34:40 +0800220/* TX FIFO moved on H3 */
221#define SUN8I_H3_CODEC_DAC_TXDATA (0x20)
222#define SUN8I_H3_CODEC_DAC_DBG (0x48)
223#define SUN8I_H3_CODEC_ADC_DBG (0x4c)
224
225/* TODO H3 DAP (Digital Audio Processing) bits */
226
Emilio López45fb6b62015-09-12 15:26:24 +0200227struct sun4i_codec {
228 struct device *dev;
229 struct regmap *regmap;
230 struct clk *clk_apb;
231 struct clk *clk_module;
Chen-Yu Tsai9aead152016-11-07 18:06:58 +0800232 struct reset_control *rst;
Hans de Goede40592622015-12-11 19:43:57 +0100233 struct gpio_desc *gpio_pa;
Emilio López45fb6b62015-09-12 15:26:24 +0200234
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800235 /* ADC_FIFOC register is at different offset on different SoCs */
236 struct regmap_field *reg_adc_fifoc;
237
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100238 struct snd_dmaengine_dai_dma_data capture_dma_data;
Emilio López45fb6b62015-09-12 15:26:24 +0200239 struct snd_dmaengine_dai_dma_data playback_dma_data;
240};
241
242static void sun4i_codec_start_playback(struct sun4i_codec *scodec)
243{
Emilio López45fb6b62015-09-12 15:26:24 +0200244 /* Flush TX FIFO */
245 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
246 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
247 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
248
249 /* Enable DAC DRQ */
250 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
251 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
252 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN));
253}
254
255static void sun4i_codec_stop_playback(struct sun4i_codec *scodec)
256{
Emilio López45fb6b62015-09-12 15:26:24 +0200257 /* Disable DAC DRQ */
258 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
259 BIT(SUN4I_CODEC_DAC_FIFOC_DAC_DRQ_EN),
260 0);
261}
262
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100263static void sun4i_codec_start_capture(struct sun4i_codec *scodec)
264{
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100265 /* Enable ADC DRQ */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800266 regmap_field_update_bits(scodec->reg_adc_fifoc,
267 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN),
268 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN));
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100269}
270
271static void sun4i_codec_stop_capture(struct sun4i_codec *scodec)
272{
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100273 /* Disable ADC DRQ */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800274 regmap_field_update_bits(scodec->reg_adc_fifoc,
275 BIT(SUN4I_CODEC_ADC_FIFOC_ADC_DRQ_EN), 0);
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100276}
277
Emilio López45fb6b62015-09-12 15:26:24 +0200278static int sun4i_codec_trigger(struct snd_pcm_substream *substream, int cmd,
279 struct snd_soc_dai *dai)
280{
281 struct snd_soc_pcm_runtime *rtd = substream->private_data;
282 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
283
Emilio López45fb6b62015-09-12 15:26:24 +0200284 switch (cmd) {
285 case SNDRV_PCM_TRIGGER_START:
286 case SNDRV_PCM_TRIGGER_RESUME:
287 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100288 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
289 sun4i_codec_start_playback(scodec);
290 else
291 sun4i_codec_start_capture(scodec);
Emilio López45fb6b62015-09-12 15:26:24 +0200292 break;
293
294 case SNDRV_PCM_TRIGGER_STOP:
295 case SNDRV_PCM_TRIGGER_SUSPEND:
296 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
298 sun4i_codec_stop_playback(scodec);
299 else
300 sun4i_codec_stop_capture(scodec);
Emilio López45fb6b62015-09-12 15:26:24 +0200301 break;
302
303 default:
304 return -EINVAL;
305 }
306
307 return 0;
308}
309
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100310static int sun4i_codec_prepare_capture(struct snd_pcm_substream *substream,
311 struct snd_soc_dai *dai)
312{
313 struct snd_soc_pcm_runtime *rtd = substream->private_data;
314 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
315
316
317 /* Flush RX FIFO */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800318 regmap_field_update_bits(scodec->reg_adc_fifoc,
319 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH),
320 BIT(SUN4I_CODEC_ADC_FIFOC_FIFO_FLUSH));
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100321
322
323 /* Set RX FIFO trigger level */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800324 regmap_field_update_bits(scodec->reg_adc_fifoc,
325 0xf << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL,
326 0x7 << SUN4I_CODEC_ADC_FIFOC_RX_TRIG_LEVEL);
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100327
328 /*
329 * FIXME: Undocumented in the datasheet, but
330 * Allwinner's code mentions that it is related
331 * related to microphone gain
332 */
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800333 if (of_device_is_compatible(scodec->dev->of_node,
334 "allwinner,sun4i-a10-codec") ||
335 of_device_is_compatible(scodec->dev->of_node,
336 "allwinner,sun7i-a20-codec")) {
337 regmap_update_bits(scodec->regmap, SUN4I_CODEC_ADC_ACTL,
338 0x3 << 25,
339 0x1 << 25);
340 }
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100341
342 if (of_device_is_compatible(scodec->dev->of_node,
343 "allwinner,sun7i-a20-codec"))
344 /* FIXME: Undocumented bits */
345 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_TUNE,
346 0x3 << 8,
347 0x1 << 8);
348
349 /* Fill most significant bits with valid data MSB */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800350 regmap_field_update_bits(scodec->reg_adc_fifoc,
351 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE),
352 BIT(SUN4I_CODEC_ADC_FIFOC_RX_FIFO_MODE));
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100353
354 return 0;
355}
356
357static int sun4i_codec_prepare_playback(struct snd_pcm_substream *substream,
358 struct snd_soc_dai *dai)
Emilio López45fb6b62015-09-12 15:26:24 +0200359{
360 struct snd_soc_pcm_runtime *rtd = substream->private_data;
361 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
362 u32 val;
363
Emilio López45fb6b62015-09-12 15:26:24 +0200364 /* Flush the TX FIFO */
365 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
366 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH),
367 BIT(SUN4I_CODEC_DAC_FIFOC_FIFO_FLUSH));
368
369 /* Set TX FIFO Empty Trigger Level */
370 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
371 0x3f << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL,
372 0xf << SUN4I_CODEC_DAC_FIFOC_TX_TRIG_LEVEL);
373
374 if (substream->runtime->rate > 32000)
375 /* Use 64 bits FIR filter */
376 val = 0;
377 else
378 /* Use 32 bits FIR filter */
379 val = BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION);
380
381 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
382 BIT(SUN4I_CODEC_DAC_FIFOC_FIR_VERSION),
383 val);
384
385 /* Send zeros when we have an underrun */
386 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
387 BIT(SUN4I_CODEC_DAC_FIFOC_SEND_LASAT),
388 0);
389
390 return 0;
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100391};
392
393static int sun4i_codec_prepare(struct snd_pcm_substream *substream,
394 struct snd_soc_dai *dai)
395{
396 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
397 return sun4i_codec_prepare_playback(substream, dai);
398
399 return sun4i_codec_prepare_capture(substream, dai);
Emilio López45fb6b62015-09-12 15:26:24 +0200400}
401
402static unsigned long sun4i_codec_get_mod_freq(struct snd_pcm_hw_params *params)
403{
404 unsigned int rate = params_rate(params);
405
406 switch (rate) {
407 case 176400:
408 case 88200:
409 case 44100:
410 case 33075:
411 case 22050:
412 case 14700:
413 case 11025:
414 case 7350:
415 return 22579200;
416
417 case 192000:
418 case 96000:
419 case 48000:
420 case 32000:
421 case 24000:
422 case 16000:
423 case 12000:
424 case 8000:
425 return 24576000;
426
427 default:
428 return 0;
429 }
430}
431
432static int sun4i_codec_get_hw_rate(struct snd_pcm_hw_params *params)
433{
434 unsigned int rate = params_rate(params);
435
436 switch (rate) {
437 case 192000:
438 case 176400:
439 return 6;
440
441 case 96000:
442 case 88200:
443 return 7;
444
445 case 48000:
446 case 44100:
447 return 0;
448
449 case 32000:
450 case 33075:
451 return 1;
452
453 case 24000:
454 case 22050:
455 return 2;
456
457 case 16000:
458 case 14700:
459 return 3;
460
461 case 12000:
462 case 11025:
463 return 4;
464
465 case 8000:
466 case 7350:
467 return 5;
468
469 default:
470 return -EINVAL;
471 }
472}
473
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100474static int sun4i_codec_hw_params_capture(struct sun4i_codec *scodec,
475 struct snd_pcm_hw_params *params,
476 unsigned int hwrate)
Emilio López45fb6b62015-09-12 15:26:24 +0200477{
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100478 /* Set ADC sample rate */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800479 regmap_field_update_bits(scodec->reg_adc_fifoc,
480 7 << SUN4I_CODEC_ADC_FIFOC_ADC_FS,
481 hwrate << SUN4I_CODEC_ADC_FIFOC_ADC_FS);
Emilio López45fb6b62015-09-12 15:26:24 +0200482
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100483 /* Set the number of channels we want to use */
484 if (params_channels(params) == 1)
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800485 regmap_field_update_bits(scodec->reg_adc_fifoc,
486 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
487 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN));
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100488 else
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +0800489 regmap_field_update_bits(scodec->reg_adc_fifoc,
490 BIT(SUN4I_CODEC_ADC_FIFOC_MONO_EN),
491 0);
Emilio López45fb6b62015-09-12 15:26:24 +0200492
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100493 return 0;
494}
Emilio López45fb6b62015-09-12 15:26:24 +0200495
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100496static int sun4i_codec_hw_params_playback(struct sun4i_codec *scodec,
497 struct snd_pcm_hw_params *params,
498 unsigned int hwrate)
499{
500 u32 val;
Emilio López45fb6b62015-09-12 15:26:24 +0200501
502 /* Set DAC sample rate */
503 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
504 7 << SUN4I_CODEC_DAC_FIFOC_DAC_FS,
505 hwrate << SUN4I_CODEC_DAC_FIFOC_DAC_FS);
506
507 /* Set the number of channels we want to use */
508 if (params_channels(params) == 1)
509 val = BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN);
510 else
511 val = 0;
512
513 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
514 BIT(SUN4I_CODEC_DAC_FIFOC_MONO_EN),
515 val);
516
517 /* Set the number of sample bits to either 16 or 24 bits */
518 if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) {
519 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
520 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
521 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS));
522
523 /* Set TX FIFO mode to padding the LSBs with 0 */
524 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
525 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
526 0);
527
528 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
529 } else {
530 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
531 BIT(SUN4I_CODEC_DAC_FIFOC_TX_SAMPLE_BITS),
532 0);
533
534 /* Set TX FIFO mode to repeat the MSB */
535 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
536 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE),
537 BIT(SUN4I_CODEC_DAC_FIFOC_TX_FIFO_MODE));
538
539 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
540 }
541
542 return 0;
543}
544
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100545static int sun4i_codec_hw_params(struct snd_pcm_substream *substream,
546 struct snd_pcm_hw_params *params,
547 struct snd_soc_dai *dai)
548{
549 struct snd_soc_pcm_runtime *rtd = substream->private_data;
550 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
551 unsigned long clk_freq;
Maxime Ripard8400ddf2015-12-01 12:06:47 +0100552 int ret, hwrate;
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100553
554 clk_freq = sun4i_codec_get_mod_freq(params);
555 if (!clk_freq)
556 return -EINVAL;
557
Maxime Ripard8400ddf2015-12-01 12:06:47 +0100558 ret = clk_set_rate(scodec->clk_module, clk_freq);
559 if (ret)
560 return ret;
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100561
562 hwrate = sun4i_codec_get_hw_rate(params);
563 if (hwrate < 0)
564 return hwrate;
565
566 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
567 return sun4i_codec_hw_params_playback(scodec, params,
568 hwrate);
569
570 return sun4i_codec_hw_params_capture(scodec, params,
571 hwrate);
572}
573
Emilio López45fb6b62015-09-12 15:26:24 +0200574static int sun4i_codec_startup(struct snd_pcm_substream *substream,
575 struct snd_soc_dai *dai)
576{
577 struct snd_soc_pcm_runtime *rtd = substream->private_data;
578 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
579
580 /*
581 * Stop issuing DRQ when we have room for less than 16 samples
582 * in our TX FIFO
583 */
584 regmap_update_bits(scodec->regmap, SUN4I_CODEC_DAC_FIFOC,
585 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT,
586 3 << SUN4I_CODEC_DAC_FIFOC_DRQ_CLR_CNT);
587
588 return clk_prepare_enable(scodec->clk_module);
589}
590
591static void sun4i_codec_shutdown(struct snd_pcm_substream *substream,
592 struct snd_soc_dai *dai)
593{
594 struct snd_soc_pcm_runtime *rtd = substream->private_data;
595 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(rtd->card);
596
597 clk_disable_unprepare(scodec->clk_module);
598}
599
600static const struct snd_soc_dai_ops sun4i_codec_dai_ops = {
601 .startup = sun4i_codec_startup,
602 .shutdown = sun4i_codec_shutdown,
603 .trigger = sun4i_codec_trigger,
604 .hw_params = sun4i_codec_hw_params,
605 .prepare = sun4i_codec_prepare,
606};
607
608static struct snd_soc_dai_driver sun4i_codec_dai = {
609 .name = "Codec",
610 .ops = &sun4i_codec_dai_ops,
611 .playback = {
612 .stream_name = "Codec Playback",
613 .channels_min = 1,
614 .channels_max = 2,
615 .rate_min = 8000,
616 .rate_max = 192000,
617 .rates = SNDRV_PCM_RATE_8000_48000 |
618 SNDRV_PCM_RATE_96000 |
Maxime Riparddebb9722015-09-29 21:43:18 +0200619 SNDRV_PCM_RATE_192000,
Emilio López45fb6b62015-09-12 15:26:24 +0200620 .formats = SNDRV_PCM_FMTBIT_S16_LE |
621 SNDRV_PCM_FMTBIT_S32_LE,
622 .sig_bits = 24,
623 },
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100624 .capture = {
625 .stream_name = "Codec Capture",
626 .channels_min = 1,
627 .channels_max = 2,
628 .rate_min = 8000,
629 .rate_max = 192000,
630 .rates = SNDRV_PCM_RATE_8000_48000 |
631 SNDRV_PCM_RATE_96000 |
632 SNDRV_PCM_RATE_192000 |
633 SNDRV_PCM_RATE_KNOT,
634 .formats = SNDRV_PCM_FMTBIT_S16_LE |
635 SNDRV_PCM_FMTBIT_S32_LE,
636 .sig_bits = 24,
637 },
Emilio López45fb6b62015-09-12 15:26:24 +0200638};
639
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800640/*** sun4i Codec ***/
Emilio López45fb6b62015-09-12 15:26:24 +0200641static const struct snd_kcontrol_new sun4i_codec_pa_mute =
642 SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
643 SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
644
645static DECLARE_TLV_DB_SCALE(sun4i_codec_pa_volume_scale, -6300, 100, 1);
646
Danny Milosavljevicc9e902f2016-09-24 22:05:01 +0200647static const struct snd_kcontrol_new sun4i_codec_controls[] = {
Adam Sampson474d1472015-10-27 21:00:45 +0000648 SOC_SINGLE_TLV("Power Amplifier Volume", SUN4I_CODEC_DAC_ACTL,
Emilio López45fb6b62015-09-12 15:26:24 +0200649 SUN4I_CODEC_DAC_ACTL_PA_VOL, 0x3F, 0,
650 sun4i_codec_pa_volume_scale),
651};
652
653static const struct snd_kcontrol_new sun4i_codec_left_mixer_controls[] = {
654 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
655 SUN4I_CODEC_DAC_ACTL_LDACLMIXS, 1, 0),
656};
657
658static const struct snd_kcontrol_new sun4i_codec_right_mixer_controls[] = {
659 SOC_DAPM_SINGLE("Right DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
660 SUN4I_CODEC_DAC_ACTL_RDACRMIXS, 1, 0),
661 SOC_DAPM_SINGLE("Left DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
662 SUN4I_CODEC_DAC_ACTL_LDACRMIXS, 1, 0),
663};
664
665static const struct snd_kcontrol_new sun4i_codec_pa_mixer_controls[] = {
666 SOC_DAPM_SINGLE("DAC Playback Switch", SUN4I_CODEC_DAC_ACTL,
667 SUN4I_CODEC_DAC_ACTL_DACPAS, 1, 0),
668 SOC_DAPM_SINGLE("Mixer Playback Switch", SUN4I_CODEC_DAC_ACTL,
669 SUN4I_CODEC_DAC_ACTL_MIXPAS, 1, 0),
670};
671
Hans de Goedee6415b42015-12-11 19:43:56 +0100672static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100673 /* Digital parts of the ADCs */
674 SND_SOC_DAPM_SUPPLY("ADC", SUN4I_CODEC_ADC_FIFOC,
675 SUN4I_CODEC_ADC_FIFOC_EN_AD, 0,
676 NULL, 0),
677
Emilio López45fb6b62015-09-12 15:26:24 +0200678 /* Digital parts of the DACs */
679 SND_SOC_DAPM_SUPPLY("DAC", SUN4I_CODEC_DAC_DPC,
680 SUN4I_CODEC_DAC_DPC_EN_DA, 0,
681 NULL, 0),
682
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100683 /* Analog parts of the ADCs */
684 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
685 SUN4I_CODEC_ADC_ACTL_ADC_L_EN, 0),
686 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN4I_CODEC_ADC_ACTL,
687 SUN4I_CODEC_ADC_ACTL_ADC_R_EN, 0),
688
Emilio López45fb6b62015-09-12 15:26:24 +0200689 /* Analog parts of the DACs */
690 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
691 SUN4I_CODEC_DAC_ACTL_DACAENL, 0),
692 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback", SUN4I_CODEC_DAC_ACTL,
693 SUN4I_CODEC_DAC_ACTL_DACAENR, 0),
694
695 /* Mixers */
696 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
697 sun4i_codec_left_mixer_controls,
698 ARRAY_SIZE(sun4i_codec_left_mixer_controls)),
699 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
700 sun4i_codec_right_mixer_controls,
701 ARRAY_SIZE(sun4i_codec_right_mixer_controls)),
702
703 /* Global Mixer Enable */
704 SND_SOC_DAPM_SUPPLY("Mixer Enable", SUN4I_CODEC_DAC_ACTL,
705 SUN4I_CODEC_DAC_ACTL_MIXEN, 0, NULL, 0),
706
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100707 /* VMIC */
708 SND_SOC_DAPM_SUPPLY("VMIC", SUN4I_CODEC_ADC_ACTL,
709 SUN4I_CODEC_ADC_ACTL_VMICEN, 0, NULL, 0),
710
711 /* Mic Pre-Amplifiers */
712 SND_SOC_DAPM_PGA("MIC1 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
713 SUN4I_CODEC_ADC_ACTL_PREG1EN, 0, NULL, 0),
714
Adam Sampson474d1472015-10-27 21:00:45 +0000715 /* Power Amplifier */
716 SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
Emilio López45fb6b62015-09-12 15:26:24 +0200717 SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
718 sun4i_codec_pa_mixer_controls,
719 ARRAY_SIZE(sun4i_codec_pa_mixer_controls)),
Adam Sampson474d1472015-10-27 21:00:45 +0000720 SND_SOC_DAPM_SWITCH("Power Amplifier Mute", SND_SOC_NOPM, 0, 0,
Emilio López45fb6b62015-09-12 15:26:24 +0200721 &sun4i_codec_pa_mute),
722
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100723 SND_SOC_DAPM_INPUT("Mic1"),
724
Emilio López45fb6b62015-09-12 15:26:24 +0200725 SND_SOC_DAPM_OUTPUT("HP Right"),
726 SND_SOC_DAPM_OUTPUT("HP Left"),
727};
728
Hans de Goedee6415b42015-12-11 19:43:56 +0100729static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100730 /* Left ADC / DAC Routes */
731 { "Left ADC", NULL, "ADC" },
Emilio López45fb6b62015-09-12 15:26:24 +0200732 { "Left DAC", NULL, "DAC" },
733
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100734 /* Right ADC / DAC Routes */
735 { "Right ADC", NULL, "ADC" },
Emilio López45fb6b62015-09-12 15:26:24 +0200736 { "Right DAC", NULL, "DAC" },
737
738 /* Right Mixer Routes */
739 { "Right Mixer", NULL, "Mixer Enable" },
740 { "Right Mixer", "Left DAC Playback Switch", "Left DAC" },
741 { "Right Mixer", "Right DAC Playback Switch", "Right DAC" },
742
743 /* Left Mixer Routes */
744 { "Left Mixer", NULL, "Mixer Enable" },
745 { "Left Mixer", "Left DAC Playback Switch", "Left DAC" },
746
Adam Sampson474d1472015-10-27 21:00:45 +0000747 /* Power Amplifier Routes */
748 { "Power Amplifier", "Mixer Playback Switch", "Left Mixer" },
749 { "Power Amplifier", "Mixer Playback Switch", "Right Mixer" },
750 { "Power Amplifier", "DAC Playback Switch", "Left DAC" },
751 { "Power Amplifier", "DAC Playback Switch", "Right DAC" },
Emilio López45fb6b62015-09-12 15:26:24 +0200752
Adam Sampson474d1472015-10-27 21:00:45 +0000753 /* Headphone Output Routes */
754 { "Power Amplifier Mute", "Switch", "Power Amplifier" },
755 { "HP Right", NULL, "Power Amplifier Mute" },
756 { "HP Left", NULL, "Power Amplifier Mute" },
Maxime Ripard1fb34b42015-11-30 16:37:47 +0100757
758 /* Mic1 Routes */
759 { "Left ADC", NULL, "MIC1 Pre-Amplifier" },
760 { "Right ADC", NULL, "MIC1 Pre-Amplifier" },
761 { "MIC1 Pre-Amplifier", NULL, "Mic1"},
762 { "Mic1", NULL, "VMIC" },
Emilio López45fb6b62015-09-12 15:26:24 +0200763};
764
765static struct snd_soc_codec_driver sun4i_codec_codec = {
Kuninori Morimoto180f58f2016-08-08 08:46:41 +0000766 .component_driver = {
Danny Milosavljevicc9e902f2016-09-24 22:05:01 +0200767 .controls = sun4i_codec_controls,
768 .num_controls = ARRAY_SIZE(sun4i_codec_controls),
Kuninori Morimoto180f58f2016-08-08 08:46:41 +0000769 .dapm_widgets = sun4i_codec_codec_dapm_widgets,
770 .num_dapm_widgets = ARRAY_SIZE(sun4i_codec_codec_dapm_widgets),
771 .dapm_routes = sun4i_codec_codec_dapm_routes,
772 .num_dapm_routes = ARRAY_SIZE(sun4i_codec_codec_dapm_routes),
773 },
Emilio López45fb6b62015-09-12 15:26:24 +0200774};
775
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800776/*** sun6i Codec ***/
777
778/* mixer controls */
779static const struct snd_kcontrol_new sun6i_codec_mixer_controls[] = {
780 SOC_DAPM_DOUBLE("DAC Playback Switch",
781 SUN6I_CODEC_OM_DACA_CTRL,
782 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACL,
783 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACR, 1, 0),
784 SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
785 SUN6I_CODEC_OM_DACA_CTRL,
786 SUN6I_CODEC_OM_DACA_CTRL_LMIX_DACR,
787 SUN6I_CODEC_OM_DACA_CTRL_RMIX_DACL, 1, 0),
Chen-Yu Tsaidff50512016-11-03 15:55:49 +0800788 SOC_DAPM_DOUBLE("Line In Playback Switch",
789 SUN6I_CODEC_OM_DACA_CTRL,
790 SUN6I_CODEC_OM_DACA_CTRL_LMIX_LINEINL,
791 SUN6I_CODEC_OM_DACA_CTRL_RMIX_LINEINR, 1, 0),
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +0800792 SOC_DAPM_DOUBLE("Mic1 Playback Switch",
793 SUN6I_CODEC_OM_DACA_CTRL,
794 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC1,
795 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC1, 1, 0),
796 SOC_DAPM_DOUBLE("Mic2 Playback Switch",
797 SUN6I_CODEC_OM_DACA_CTRL,
798 SUN6I_CODEC_OM_DACA_CTRL_LMIX_MIC2,
799 SUN6I_CODEC_OM_DACA_CTRL_RMIX_MIC2, 1, 0),
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800800};
801
Chen-Yu Tsai24c99f82016-11-07 18:06:59 +0800802/* ADC mixer controls */
803static const struct snd_kcontrol_new sun6i_codec_adc_mixer_controls[] = {
804 SOC_DAPM_DOUBLE("Mixer Capture Switch",
805 SUN6I_CODEC_ADC_ACTL,
806 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXL,
807 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXR, 1, 0),
808 SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
809 SUN6I_CODEC_ADC_ACTL,
810 SUN6I_CODEC_ADC_ACTL_LADCMIX_OMIXR,
811 SUN6I_CODEC_ADC_ACTL_RADCMIX_OMIXL, 1, 0),
812 SOC_DAPM_DOUBLE("Line In Capture Switch",
813 SUN6I_CODEC_ADC_ACTL,
814 SUN6I_CODEC_ADC_ACTL_LADCMIX_LINEINL,
815 SUN6I_CODEC_ADC_ACTL_RADCMIX_LINEINR, 1, 0),
816 SOC_DAPM_DOUBLE("Mic1 Capture Switch",
817 SUN6I_CODEC_ADC_ACTL,
818 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC1,
819 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC1, 1, 0),
820 SOC_DAPM_DOUBLE("Mic2 Capture Switch",
821 SUN6I_CODEC_ADC_ACTL,
822 SUN6I_CODEC_ADC_ACTL_LADCMIX_MIC2,
823 SUN6I_CODEC_ADC_ACTL_RADCMIX_MIC2, 1, 0),
824};
825
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800826/* headphone controls */
827static const char * const sun6i_codec_hp_src_enum_text[] = {
828 "DAC", "Mixer",
829};
830
831static SOC_ENUM_DOUBLE_DECL(sun6i_codec_hp_src_enum,
832 SUN6I_CODEC_OM_DACA_CTRL,
833 SUN6I_CODEC_OM_DACA_CTRL_LHPIS,
834 SUN6I_CODEC_OM_DACA_CTRL_RHPIS,
835 sun6i_codec_hp_src_enum_text);
836
837static const struct snd_kcontrol_new sun6i_codec_hp_src[] = {
838 SOC_DAPM_ENUM("Headphone Source Playback Route",
839 sun6i_codec_hp_src_enum),
840};
841
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +0800842/* microphone controls */
843static const char * const sun6i_codec_mic2_src_enum_text[] = {
844 "Mic2", "Mic3",
845};
846
847static SOC_ENUM_SINGLE_DECL(sun6i_codec_mic2_src_enum,
848 SUN6I_CODEC_MIC_CTRL,
849 SUN6I_CODEC_MIC_CTRL_MIC2SLT,
850 sun6i_codec_mic2_src_enum_text);
851
852static const struct snd_kcontrol_new sun6i_codec_mic2_src[] = {
853 SOC_DAPM_ENUM("Mic2 Amplifier Source Route",
854 sun6i_codec_mic2_src_enum),
855};
856
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +0800857/* line out controls */
858static const char * const sun6i_codec_lineout_src_enum_text[] = {
859 "Stereo", "Mono Differential",
860};
861
862static SOC_ENUM_DOUBLE_DECL(sun6i_codec_lineout_src_enum,
863 SUN6I_CODEC_MIC_CTRL,
864 SUN6I_CODEC_MIC_CTRL_LINEOUTLSRC,
865 SUN6I_CODEC_MIC_CTRL_LINEOUTRSRC,
866 sun6i_codec_lineout_src_enum_text);
867
868static const struct snd_kcontrol_new sun6i_codec_lineout_src[] = {
869 SOC_DAPM_ENUM("Line Out Source Playback Route",
870 sun6i_codec_lineout_src_enum),
871};
872
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800873/* volume / mute controls */
874static const DECLARE_TLV_DB_SCALE(sun6i_codec_dvol_scale, -7308, 116, 0);
875static const DECLARE_TLV_DB_SCALE(sun6i_codec_hp_vol_scale, -6300, 100, 1);
Chen-Yu Tsaidff50512016-11-03 15:55:49 +0800876static const DECLARE_TLV_DB_SCALE(sun6i_codec_out_mixer_pregain_scale,
877 -450, 150, 0);
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +0800878static const DECLARE_TLV_DB_RANGE(sun6i_codec_lineout_vol_scale,
879 0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
880 2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
881);
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +0800882static const DECLARE_TLV_DB_RANGE(sun6i_codec_mic_gain_scale,
883 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
884 1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
885);
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800886
887static const struct snd_kcontrol_new sun6i_codec_codec_widgets[] = {
888 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
889 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
890 sun6i_codec_dvol_scale),
891 SOC_SINGLE_TLV("Headphone Playback Volume",
892 SUN6I_CODEC_OM_DACA_CTRL,
893 SUN6I_CODEC_OM_DACA_CTRL_HPVOL, 0x3f, 0,
894 sun6i_codec_hp_vol_scale),
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +0800895 SOC_SINGLE_TLV("Line Out Playback Volume",
896 SUN6I_CODEC_MIC_CTRL,
897 SUN6I_CODEC_MIC_CTRL_LINEOUTVC, 0x1f, 0,
898 sun6i_codec_lineout_vol_scale),
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800899 SOC_DOUBLE("Headphone Playback Switch",
900 SUN6I_CODEC_OM_DACA_CTRL,
901 SUN6I_CODEC_OM_DACA_CTRL_LHPPAMUTE,
902 SUN6I_CODEC_OM_DACA_CTRL_RHPPAMUTE, 1, 0),
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +0800903 SOC_DOUBLE("Line Out Playback Switch",
904 SUN6I_CODEC_MIC_CTRL,
905 SUN6I_CODEC_MIC_CTRL_LINEOUTLEN,
906 SUN6I_CODEC_MIC_CTRL_LINEOUTREN, 1, 0),
Chen-Yu Tsaidff50512016-11-03 15:55:49 +0800907 /* Mixer pre-gains */
908 SOC_SINGLE_TLV("Line In Playback Volume",
909 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_LINEING,
910 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +0800911 SOC_SINGLE_TLV("Mic1 Playback Volume",
912 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC1G,
913 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
914 SOC_SINGLE_TLV("Mic2 Playback Volume",
915 SUN6I_CODEC_OM_PA_CTRL, SUN6I_CODEC_OM_PA_CTRL_MIC2G,
916 0x7, 0, sun6i_codec_out_mixer_pregain_scale),
917
918 /* Microphone Amp boost gains */
919 SOC_SINGLE_TLV("Mic1 Boost Volume", SUN6I_CODEC_MIC_CTRL,
920 SUN6I_CODEC_MIC_CTRL_MIC1BOOST, 0x7, 0,
921 sun6i_codec_mic_gain_scale),
922 SOC_SINGLE_TLV("Mic2 Boost Volume", SUN6I_CODEC_MIC_CTRL,
923 SUN6I_CODEC_MIC_CTRL_MIC2BOOST, 0x7, 0,
924 sun6i_codec_mic_gain_scale),
Chen-Yu Tsai24c99f82016-11-07 18:06:59 +0800925 SOC_DOUBLE_TLV("ADC Capture Volume",
926 SUN6I_CODEC_ADC_ACTL, SUN6I_CODEC_ADC_ACTL_ADCLG,
927 SUN6I_CODEC_ADC_ACTL_ADCRG, 0x7, 0,
928 sun6i_codec_out_mixer_pregain_scale),
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800929};
930
931static const struct snd_soc_dapm_widget sun6i_codec_codec_dapm_widgets[] = {
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +0800932 /* Microphone inputs */
933 SND_SOC_DAPM_INPUT("MIC1"),
934 SND_SOC_DAPM_INPUT("MIC2"),
935 SND_SOC_DAPM_INPUT("MIC3"),
936
937 /* Microphone Bias */
938 SND_SOC_DAPM_SUPPLY("HBIAS", SUN6I_CODEC_MIC_CTRL,
939 SUN6I_CODEC_MIC_CTRL_HBIASEN, 0, NULL, 0),
940 SND_SOC_DAPM_SUPPLY("MBIAS", SUN6I_CODEC_MIC_CTRL,
941 SUN6I_CODEC_MIC_CTRL_MBIASEN, 0, NULL, 0),
942
943 /* Mic input path */
944 SND_SOC_DAPM_MUX("Mic2 Amplifier Source Route",
945 SND_SOC_NOPM, 0, 0, sun6i_codec_mic2_src),
946 SND_SOC_DAPM_PGA("Mic1 Amplifier", SUN6I_CODEC_MIC_CTRL,
947 SUN6I_CODEC_MIC_CTRL_MIC1AMPEN, 0, NULL, 0),
948 SND_SOC_DAPM_PGA("Mic2 Amplifier", SUN6I_CODEC_MIC_CTRL,
949 SUN6I_CODEC_MIC_CTRL_MIC2AMPEN, 0, NULL, 0),
950
Chen-Yu Tsaidff50512016-11-03 15:55:49 +0800951 /* Line In */
952 SND_SOC_DAPM_INPUT("LINEIN"),
953
Chen-Yu Tsai24c99f82016-11-07 18:06:59 +0800954 /* Digital parts of the ADCs */
955 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
956 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0,
957 NULL, 0),
958
959 /* Analog parts of the ADCs */
960 SND_SOC_DAPM_ADC("Left ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
961 SUN6I_CODEC_ADC_ACTL_ADCLEN, 0),
962 SND_SOC_DAPM_ADC("Right ADC", "Codec Capture", SUN6I_CODEC_ADC_ACTL,
963 SUN6I_CODEC_ADC_ACTL_ADCREN, 0),
964
965 /* ADC Mixers */
966 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
967 sun6i_codec_adc_mixer_controls),
968 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
969 sun6i_codec_adc_mixer_controls),
970
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +0800971 /* Digital parts of the DACs */
972 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
973 SUN4I_CODEC_DAC_DPC_EN_DA, 0,
974 NULL, 0),
975
976 /* Analog parts of the DACs */
977 SND_SOC_DAPM_DAC("Left DAC", "Codec Playback",
978 SUN6I_CODEC_OM_DACA_CTRL,
979 SUN6I_CODEC_OM_DACA_CTRL_DACALEN, 0),
980 SND_SOC_DAPM_DAC("Right DAC", "Codec Playback",
981 SUN6I_CODEC_OM_DACA_CTRL,
982 SUN6I_CODEC_OM_DACA_CTRL_DACAREN, 0),
983
984 /* Mixers */
985 SOC_MIXER_ARRAY("Left Mixer", SUN6I_CODEC_OM_DACA_CTRL,
986 SUN6I_CODEC_OM_DACA_CTRL_LMIXEN, 0,
987 sun6i_codec_mixer_controls),
988 SOC_MIXER_ARRAY("Right Mixer", SUN6I_CODEC_OM_DACA_CTRL,
989 SUN6I_CODEC_OM_DACA_CTRL_RMIXEN, 0,
990 sun6i_codec_mixer_controls),
991
992 /* Headphone output path */
993 SND_SOC_DAPM_MUX("Headphone Source Playback Route",
994 SND_SOC_NOPM, 0, 0, sun6i_codec_hp_src),
995 SND_SOC_DAPM_OUT_DRV("Headphone Amp", SUN6I_CODEC_OM_PA_CTRL,
996 SUN6I_CODEC_OM_PA_CTRL_HPPAEN, 0, NULL, 0),
997 SND_SOC_DAPM_SUPPLY("HPCOM Protection", SUN6I_CODEC_OM_PA_CTRL,
998 SUN6I_CODEC_OM_PA_CTRL_COMPTEN, 0, NULL, 0),
999 SND_SOC_DAPM_REG(snd_soc_dapm_supply, "HPCOM", SUN6I_CODEC_OM_PA_CTRL,
1000 SUN6I_CODEC_OM_PA_CTRL_HPCOM_CTL, 0x3, 0x3, 0),
1001 SND_SOC_DAPM_OUTPUT("HP"),
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +08001002
1003 /* Line Out path */
1004 SND_SOC_DAPM_MUX("Line Out Source Playback Route",
1005 SND_SOC_NOPM, 0, 0, sun6i_codec_lineout_src),
1006 SND_SOC_DAPM_OUTPUT("LINEOUT"),
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001007};
1008
1009static const struct snd_soc_dapm_route sun6i_codec_codec_dapm_routes[] = {
1010 /* DAC Routes */
1011 { "Left DAC", NULL, "DAC Enable" },
1012 { "Right DAC", NULL, "DAC Enable" },
1013
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +08001014 /* Microphone Routes */
1015 { "Mic1 Amplifier", NULL, "MIC1"},
1016 { "Mic2 Amplifier Source Route", "Mic2", "MIC2" },
1017 { "Mic2 Amplifier Source Route", "Mic3", "MIC3" },
1018 { "Mic2 Amplifier", NULL, "Mic2 Amplifier Source Route"},
1019
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001020 /* Left Mixer Routes */
1021 { "Left Mixer", "DAC Playback Switch", "Left DAC" },
1022 { "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
Chen-Yu Tsaidff50512016-11-03 15:55:49 +08001023 { "Left Mixer", "Line In Playback Switch", "LINEIN" },
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +08001024 { "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
1025 { "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001026
1027 /* Right Mixer Routes */
1028 { "Right Mixer", "DAC Playback Switch", "Right DAC" },
1029 { "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
Chen-Yu Tsaidff50512016-11-03 15:55:49 +08001030 { "Right Mixer", "Line In Playback Switch", "LINEIN" },
Chen-Yu Tsaiecd5cdb2016-11-03 15:55:51 +08001031 { "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
1032 { "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001033
Chen-Yu Tsai24c99f82016-11-07 18:06:59 +08001034 /* Left ADC Mixer Routes */
1035 { "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
1036 { "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
1037 { "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
1038 { "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
1039 { "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
1040
1041 /* Right ADC Mixer Routes */
1042 { "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
1043 { "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
1044 { "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
1045 { "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
1046 { "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
1047
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001048 /* Headphone Routes */
1049 { "Headphone Source Playback Route", "DAC", "Left DAC" },
1050 { "Headphone Source Playback Route", "DAC", "Right DAC" },
1051 { "Headphone Source Playback Route", "Mixer", "Left Mixer" },
1052 { "Headphone Source Playback Route", "Mixer", "Right Mixer" },
1053 { "Headphone Amp", NULL, "Headphone Source Playback Route" },
1054 { "HP", NULL, "Headphone Amp" },
1055 { "HPCOM", NULL, "HPCOM Protection" },
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +08001056
1057 /* Line Out Routes */
1058 { "Line Out Source Playback Route", "Stereo", "Left Mixer" },
1059 { "Line Out Source Playback Route", "Stereo", "Right Mixer" },
1060 { "Line Out Source Playback Route", "Mono Differential", "Left Mixer" },
Chen-Yu Tsai19426bd2017-01-08 02:57:06 +08001061 { "Line Out Source Playback Route", "Mono Differential", "Right Mixer" },
Chen-Yu Tsai0f909f92016-11-03 15:55:50 +08001062 { "LINEOUT", NULL, "Line Out Source Playback Route" },
Chen-Yu Tsai24c99f82016-11-07 18:06:59 +08001063
1064 /* ADC Routes */
1065 { "Left ADC", NULL, "ADC Enable" },
1066 { "Right ADC", NULL, "ADC Enable" },
1067 { "Left ADC", NULL, "Left ADC Mixer" },
1068 { "Right ADC", NULL, "Right ADC Mixer" },
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001069};
1070
1071static struct snd_soc_codec_driver sun6i_codec_codec = {
1072 .component_driver = {
1073 .controls = sun6i_codec_codec_widgets,
1074 .num_controls = ARRAY_SIZE(sun6i_codec_codec_widgets),
1075 .dapm_widgets = sun6i_codec_codec_dapm_widgets,
1076 .num_dapm_widgets = ARRAY_SIZE(sun6i_codec_codec_dapm_widgets),
1077 .dapm_routes = sun6i_codec_codec_dapm_routes,
1078 .num_dapm_routes = ARRAY_SIZE(sun6i_codec_codec_dapm_routes),
1079 },
1080};
1081
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +08001082/* sun8i A23 codec */
1083static const struct snd_kcontrol_new sun8i_a23_codec_codec_controls[] = {
1084 SOC_SINGLE_TLV("DAC Playback Volume", SUN4I_CODEC_DAC_DPC,
1085 SUN4I_CODEC_DAC_DPC_DVOL, 0x3f, 1,
1086 sun6i_codec_dvol_scale),
1087};
1088
1089static const struct snd_soc_dapm_widget sun8i_a23_codec_codec_widgets[] = {
1090 /* Digital parts of the ADCs */
1091 SND_SOC_DAPM_SUPPLY("ADC Enable", SUN6I_CODEC_ADC_FIFOC,
1092 SUN6I_CODEC_ADC_FIFOC_EN_AD, 0, NULL, 0),
1093 /* Digital parts of the DACs */
1094 SND_SOC_DAPM_SUPPLY("DAC Enable", SUN4I_CODEC_DAC_DPC,
1095 SUN4I_CODEC_DAC_DPC_EN_DA, 0, NULL, 0),
1096
1097};
1098
1099static struct snd_soc_codec_driver sun8i_a23_codec_codec = {
1100 .component_driver = {
1101 .controls = sun8i_a23_codec_codec_controls,
1102 .num_controls = ARRAY_SIZE(sun8i_a23_codec_codec_controls),
1103 .dapm_widgets = sun8i_a23_codec_codec_widgets,
1104 .num_dapm_widgets = ARRAY_SIZE(sun8i_a23_codec_codec_widgets),
1105 },
1106};
1107
Emilio López45fb6b62015-09-12 15:26:24 +02001108static const struct snd_soc_component_driver sun4i_codec_component = {
1109 .name = "sun4i-codec",
1110};
1111
1112#define SUN4I_CODEC_RATES SNDRV_PCM_RATE_8000_192000
1113#define SUN4I_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
1114 SNDRV_PCM_FMTBIT_S32_LE)
1115
1116static int sun4i_codec_dai_probe(struct snd_soc_dai *dai)
1117{
1118 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1119 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
1120
1121 snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data,
Maxime Ripard1fb34b42015-11-30 16:37:47 +01001122 &scodec->capture_dma_data);
Emilio López45fb6b62015-09-12 15:26:24 +02001123
1124 return 0;
1125}
1126
1127static struct snd_soc_dai_driver dummy_cpu_dai = {
1128 .name = "sun4i-codec-cpu-dai",
1129 .probe = sun4i_codec_dai_probe,
1130 .playback = {
1131 .stream_name = "Playback",
1132 .channels_min = 1,
1133 .channels_max = 2,
1134 .rates = SUN4I_CODEC_RATES,
1135 .formats = SUN4I_CODEC_FORMATS,
1136 .sig_bits = 24,
1137 },
Maxime Ripard1fb34b42015-11-30 16:37:47 +01001138 .capture = {
1139 .stream_name = "Capture",
1140 .channels_min = 1,
1141 .channels_max = 2,
1142 .rates = SUN4I_CODEC_RATES,
1143 .formats = SUN4I_CODEC_FORMATS,
1144 .sig_bits = 24,
1145 },
Emilio López45fb6b62015-09-12 15:26:24 +02001146};
1147
Emilio López45fb6b62015-09-12 15:26:24 +02001148static struct snd_soc_dai_link *sun4i_codec_create_link(struct device *dev,
1149 int *num_links)
1150{
1151 struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link),
1152 GFP_KERNEL);
1153 if (!link)
1154 return NULL;
1155
1156 link->name = "cdc";
1157 link->stream_name = "CDC PCM";
1158 link->codec_dai_name = "Codec";
1159 link->cpu_dai_name = dev_name(dev);
1160 link->codec_name = dev_name(dev);
1161 link->platform_name = dev_name(dev);
1162 link->dai_fmt = SND_SOC_DAIFMT_I2S;
1163
1164 *num_links = 1;
1165
1166 return link;
1167};
1168
Hans de Goede40592622015-12-11 19:43:57 +01001169static int sun4i_codec_spk_event(struct snd_soc_dapm_widget *w,
1170 struct snd_kcontrol *k, int event)
1171{
1172 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card);
1173
1174 if (scodec->gpio_pa)
1175 gpiod_set_value_cansleep(scodec->gpio_pa,
1176 !!SND_SOC_DAPM_EVENT_ON(event));
1177
1178 return 0;
1179}
1180
1181static const struct snd_soc_dapm_widget sun4i_codec_card_dapm_widgets[] = {
1182 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
1183};
1184
1185static const struct snd_soc_dapm_route sun4i_codec_card_dapm_routes[] = {
Hans de Goede6b803c62015-12-22 23:00:17 +01001186 { "Speaker", NULL, "HP Right" },
1187 { "Speaker", NULL, "HP Left" },
Hans de Goede40592622015-12-11 19:43:57 +01001188};
1189
Emilio López45fb6b62015-09-12 15:26:24 +02001190static struct snd_soc_card *sun4i_codec_create_card(struct device *dev)
1191{
1192 struct snd_soc_card *card;
Emilio López45fb6b62015-09-12 15:26:24 +02001193
1194 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1195 if (!card)
Chen-Yu Tsai85915b62016-10-31 14:42:09 +08001196 return ERR_PTR(-ENOMEM);
Emilio López45fb6b62015-09-12 15:26:24 +02001197
1198 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1199 if (!card->dai_link)
Chen-Yu Tsai85915b62016-10-31 14:42:09 +08001200 return ERR_PTR(-ENOMEM);
Emilio López45fb6b62015-09-12 15:26:24 +02001201
1202 card->dev = dev;
1203 card->name = "sun4i-codec";
Hans de Goede40592622015-12-11 19:43:57 +01001204 card->dapm_widgets = sun4i_codec_card_dapm_widgets;
1205 card->num_dapm_widgets = ARRAY_SIZE(sun4i_codec_card_dapm_widgets);
1206 card->dapm_routes = sun4i_codec_card_dapm_routes;
1207 card->num_dapm_routes = ARRAY_SIZE(sun4i_codec_card_dapm_routes);
Emilio López45fb6b62015-09-12 15:26:24 +02001208
Emilio López45fb6b62015-09-12 15:26:24 +02001209 return card;
1210};
1211
Chen-Yu Tsai300a18d2016-11-03 15:55:53 +08001212static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = {
1213 SND_SOC_DAPM_HP("Headphone", NULL),
1214 SND_SOC_DAPM_LINE("Line In", NULL),
1215 SND_SOC_DAPM_LINE("Line Out", NULL),
1216 SND_SOC_DAPM_MIC("Headset Mic", NULL),
1217 SND_SOC_DAPM_MIC("Mic", NULL),
1218 SND_SOC_DAPM_SPK("Speaker", sun4i_codec_spk_event),
1219};
1220
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001221static struct snd_soc_card *sun6i_codec_create_card(struct device *dev)
1222{
1223 struct snd_soc_card *card;
Chen-Yu Tsai300a18d2016-11-03 15:55:53 +08001224 int ret;
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001225
1226 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1227 if (!card)
1228 return ERR_PTR(-ENOMEM);
1229
1230 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1231 if (!card->dai_link)
1232 return ERR_PTR(-ENOMEM);
1233
Chen-Yu Tsai300a18d2016-11-03 15:55:53 +08001234 card->dev = dev;
1235 card->name = "A31 Audio Codec";
1236 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1237 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1238 card->fully_routed = true;
1239
1240 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1241 if (ret)
1242 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001243
1244 return card;
1245};
1246
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +08001247/* Connect digital side enables to analog side widgets */
1248static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = {
1249 /* ADC Routes */
1250 { "Left ADC", NULL, "ADC Enable" },
1251 { "Right ADC", NULL, "ADC Enable" },
1252 { "Codec Capture", NULL, "Left ADC" },
1253 { "Codec Capture", NULL, "Right ADC" },
1254
1255 /* DAC Routes */
1256 { "Left DAC", NULL, "DAC Enable" },
1257 { "Right DAC", NULL, "DAC Enable" },
1258 { "Left DAC", NULL, "Codec Playback" },
1259 { "Right DAC", NULL, "Codec Playback" },
1260};
1261
1262static struct snd_soc_aux_dev aux_dev = {
1263 .name = "Codec Analog Controls",
1264};
1265
1266static struct snd_soc_card *sun8i_a23_codec_create_card(struct device *dev)
1267{
1268 struct snd_soc_card *card;
1269 int ret;
1270
1271 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1272 if (!card)
1273 return ERR_PTR(-ENOMEM);
1274
1275 aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
1276 "allwinner,codec-analog-controls",
1277 0);
1278 if (!aux_dev.codec_of_node) {
1279 dev_err(dev, "Can't find analog controls for codec.\n");
1280 return ERR_PTR(-EINVAL);
1281 };
1282
1283 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1284 if (!card->dai_link)
1285 return ERR_PTR(-ENOMEM);
1286
1287 card->dev = dev;
1288 card->name = "A23 Audio Codec";
1289 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1290 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1291 card->dapm_routes = sun8i_codec_card_routes;
1292 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
1293 card->aux_dev = &aux_dev;
1294 card->num_aux_devs = 1;
1295 card->fully_routed = true;
1296
1297 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1298 if (ret)
1299 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1300
1301 return card;
1302};
1303
Chen-Yu Tsai4a15b242016-11-25 20:34:40 +08001304static struct snd_soc_card *sun8i_h3_codec_create_card(struct device *dev)
1305{
1306 struct snd_soc_card *card;
1307 int ret;
1308
1309 card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
1310 if (!card)
1311 return ERR_PTR(-ENOMEM);
1312
1313 aux_dev.codec_of_node = of_parse_phandle(dev->of_node,
1314 "allwinner,codec-analog-controls",
1315 0);
1316 if (!aux_dev.codec_of_node) {
1317 dev_err(dev, "Can't find analog controls for codec.\n");
1318 return ERR_PTR(-EINVAL);
1319 };
1320
1321 card->dai_link = sun4i_codec_create_link(dev, &card->num_links);
1322 if (!card->dai_link)
1323 return ERR_PTR(-ENOMEM);
1324
1325 card->dev = dev;
1326 card->name = "H3 Audio Codec";
1327 card->dapm_widgets = sun6i_codec_card_dapm_widgets;
1328 card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets);
1329 card->dapm_routes = sun8i_codec_card_routes;
1330 card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes);
1331 card->aux_dev = &aux_dev;
1332 card->num_aux_devs = 1;
1333 card->fully_routed = true;
1334
1335 ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing");
1336 if (ret)
1337 dev_warn(dev, "failed to parse audio-routing: %d\n", ret);
1338
1339 return card;
1340};
1341
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001342static const struct regmap_config sun4i_codec_regmap_config = {
1343 .reg_bits = 32,
1344 .reg_stride = 4,
1345 .val_bits = 32,
1346 .max_register = SUN4I_CODEC_ADC_RXCNT,
1347};
1348
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001349static const struct regmap_config sun6i_codec_regmap_config = {
1350 .reg_bits = 32,
1351 .reg_stride = 4,
1352 .val_bits = 32,
1353 .max_register = SUN6I_CODEC_HMIC_DATA,
1354};
1355
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001356static const struct regmap_config sun7i_codec_regmap_config = {
1357 .reg_bits = 32,
1358 .reg_stride = 4,
1359 .val_bits = 32,
1360 .max_register = SUN7I_CODEC_AC_MIC_PHONE_CAL,
1361};
1362
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +08001363static const struct regmap_config sun8i_a23_codec_regmap_config = {
1364 .reg_bits = 32,
1365 .reg_stride = 4,
1366 .val_bits = 32,
1367 .max_register = SUN8I_A23_CODEC_ADC_RXCNT,
1368};
1369
Chen-Yu Tsai4a15b242016-11-25 20:34:40 +08001370static const struct regmap_config sun8i_h3_codec_regmap_config = {
1371 .reg_bits = 32,
1372 .reg_stride = 4,
1373 .val_bits = 32,
1374 .max_register = SUN8I_H3_CODEC_ADC_DBG,
1375};
1376
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001377struct sun4i_codec_quirks {
1378 const struct regmap_config *regmap_config;
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001379 const struct snd_soc_codec_driver *codec;
1380 struct snd_soc_card * (*create_card)(struct device *dev);
1381 struct reg_field reg_adc_fifoc; /* used for regmap_field */
1382 unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */
1383 unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001384 bool has_reset;
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001385};
1386
1387static const struct sun4i_codec_quirks sun4i_codec_quirks = {
1388 .regmap_config = &sun4i_codec_regmap_config,
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001389 .codec = &sun4i_codec_codec,
1390 .create_card = sun4i_codec_create_card,
1391 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
1392 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1393 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001394};
1395
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001396static const struct sun4i_codec_quirks sun6i_a31_codec_quirks = {
1397 .regmap_config = &sun6i_codec_regmap_config,
1398 .codec = &sun6i_codec_codec,
1399 .create_card = sun6i_codec_create_card,
1400 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1401 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1402 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1403 .has_reset = true,
1404};
1405
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001406static const struct sun4i_codec_quirks sun7i_codec_quirks = {
1407 .regmap_config = &sun7i_codec_regmap_config,
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001408 .codec = &sun4i_codec_codec,
1409 .create_card = sun4i_codec_create_card,
1410 .reg_adc_fifoc = REG_FIELD(SUN4I_CODEC_ADC_FIFOC, 0, 31),
1411 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1412 .reg_adc_rxdata = SUN4I_CODEC_ADC_RXDATA,
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001413};
1414
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +08001415static const struct sun4i_codec_quirks sun8i_a23_codec_quirks = {
1416 .regmap_config = &sun8i_a23_codec_regmap_config,
1417 .codec = &sun8i_a23_codec_codec,
1418 .create_card = sun8i_a23_codec_create_card,
1419 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1420 .reg_dac_txdata = SUN4I_CODEC_DAC_TXDATA,
1421 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1422 .has_reset = true,
1423};
1424
Chen-Yu Tsai4a15b242016-11-25 20:34:40 +08001425static const struct sun4i_codec_quirks sun8i_h3_codec_quirks = {
1426 .regmap_config = &sun8i_h3_codec_regmap_config,
1427 /*
1428 * TODO Share the codec structure with A23 for now.
1429 * This should be split out when adding digital audio
1430 * processing support for the H3.
1431 */
1432 .codec = &sun8i_a23_codec_codec,
1433 .create_card = sun8i_h3_codec_create_card,
1434 .reg_adc_fifoc = REG_FIELD(SUN6I_CODEC_ADC_FIFOC, 0, 31),
1435 .reg_dac_txdata = SUN8I_H3_CODEC_DAC_TXDATA,
1436 .reg_adc_rxdata = SUN6I_CODEC_ADC_RXDATA,
1437 .has_reset = true,
1438};
1439
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001440static const struct of_device_id sun4i_codec_of_match[] = {
1441 {
1442 .compatible = "allwinner,sun4i-a10-codec",
1443 .data = &sun4i_codec_quirks,
1444 },
1445 {
Chen-Yu Tsai8d9e4c9e2016-11-03 15:55:48 +08001446 .compatible = "allwinner,sun6i-a31-codec",
1447 .data = &sun6i_a31_codec_quirks,
1448 },
1449 {
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001450 .compatible = "allwinner,sun7i-a20-codec",
1451 .data = &sun7i_codec_quirks,
1452 },
Chen-Yu Tsaidac5f862016-11-25 20:34:36 +08001453 {
1454 .compatible = "allwinner,sun8i-a23-codec",
1455 .data = &sun8i_a23_codec_quirks,
1456 },
Chen-Yu Tsai4a15b242016-11-25 20:34:40 +08001457 {
1458 .compatible = "allwinner,sun8i-h3-codec",
1459 .data = &sun8i_h3_codec_quirks,
1460 },
Chen-Yu Tsai2f2a3462016-11-03 15:55:43 +08001461 {}
1462};
1463MODULE_DEVICE_TABLE(of, sun4i_codec_of_match);
1464
Emilio López45fb6b62015-09-12 15:26:24 +02001465static int sun4i_codec_probe(struct platform_device *pdev)
1466{
1467 struct snd_soc_card *card;
1468 struct sun4i_codec *scodec;
Danny Milosavljevicc1d50652016-09-22 09:13:13 +02001469 const struct sun4i_codec_quirks *quirks;
Emilio López45fb6b62015-09-12 15:26:24 +02001470 struct resource *res;
1471 void __iomem *base;
1472 int ret;
1473
1474 scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
1475 if (!scodec)
1476 return -ENOMEM;
1477
1478 scodec->dev = &pdev->dev;
1479
1480 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481 base = devm_ioremap_resource(&pdev->dev, res);
1482 if (IS_ERR(base)) {
1483 dev_err(&pdev->dev, "Failed to map the registers\n");
1484 return PTR_ERR(base);
1485 }
1486
Danny Milosavljevicc1d50652016-09-22 09:13:13 +02001487 quirks = of_device_get_match_data(&pdev->dev);
1488 if (quirks == NULL) {
1489 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1490 return -ENODEV;
1491 }
1492
Emilio López45fb6b62015-09-12 15:26:24 +02001493 scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
Danny Milosavljevicc1d50652016-09-22 09:13:13 +02001494 quirks->regmap_config);
Emilio López45fb6b62015-09-12 15:26:24 +02001495 if (IS_ERR(scodec->regmap)) {
1496 dev_err(&pdev->dev, "Failed to create our regmap\n");
1497 return PTR_ERR(scodec->regmap);
1498 }
1499
1500 /* Get the clocks from the DT */
1501 scodec->clk_apb = devm_clk_get(&pdev->dev, "apb");
1502 if (IS_ERR(scodec->clk_apb)) {
1503 dev_err(&pdev->dev, "Failed to get the APB clock\n");
1504 return PTR_ERR(scodec->clk_apb);
1505 }
1506
1507 scodec->clk_module = devm_clk_get(&pdev->dev, "codec");
1508 if (IS_ERR(scodec->clk_module)) {
1509 dev_err(&pdev->dev, "Failed to get the module clock\n");
1510 return PTR_ERR(scodec->clk_module);
1511 }
1512
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001513 if (quirks->has_reset) {
1514 scodec->rst = devm_reset_control_get(&pdev->dev, NULL);
1515 if (IS_ERR(scodec->rst)) {
1516 dev_err(&pdev->dev, "Failed to get reset control\n");
1517 return PTR_ERR(scodec->rst);
1518 }
kbuild test robot35db5762016-11-10 00:35:18 +08001519 }
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001520
Hans de Goede40592622015-12-11 19:43:57 +01001521 scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa",
1522 GPIOD_OUT_LOW);
1523 if (IS_ERR(scodec->gpio_pa)) {
1524 ret = PTR_ERR(scodec->gpio_pa);
1525 if (ret != -EPROBE_DEFER)
1526 dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret);
1527 return ret;
1528 }
1529
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001530 /* reg_field setup */
1531 scodec->reg_adc_fifoc = devm_regmap_field_alloc(&pdev->dev,
1532 scodec->regmap,
1533 quirks->reg_adc_fifoc);
1534 if (IS_ERR(scodec->reg_adc_fifoc)) {
1535 ret = PTR_ERR(scodec->reg_adc_fifoc);
1536 dev_err(&pdev->dev, "Failed to create regmap fields: %d\n",
1537 ret);
1538 return ret;
1539 }
1540
Chen-Yu Tsai3716a892016-11-01 14:31:55 +08001541 /* Enable the bus clock */
1542 if (clk_prepare_enable(scodec->clk_apb)) {
1543 dev_err(&pdev->dev, "Failed to enable the APB clock\n");
1544 return -EINVAL;
1545 }
1546
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001547 /* Deassert the reset control */
1548 if (scodec->rst) {
1549 ret = reset_control_deassert(scodec->rst);
1550 if (ret) {
1551 dev_err(&pdev->dev,
1552 "Failed to deassert the reset control\n");
1553 goto err_clk_disable;
1554 }
1555 }
1556
Emilio López45fb6b62015-09-12 15:26:24 +02001557 /* DMA configuration for TX FIFO */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001558 scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata;
Chen-Yu Tsai730e2dd2016-11-03 15:55:46 +08001559 scodec->playback_dma_data.maxburst = 8;
Emilio López45fb6b62015-09-12 15:26:24 +02001560 scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1561
Maxime Ripard1fb34b42015-11-30 16:37:47 +01001562 /* DMA configuration for RX FIFO */
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001563 scodec->capture_dma_data.addr = res->start + quirks->reg_adc_rxdata;
Chen-Yu Tsai730e2dd2016-11-03 15:55:46 +08001564 scodec->capture_dma_data.maxburst = 8;
Maxime Ripard1fb34b42015-11-30 16:37:47 +01001565 scodec->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1566
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001567 ret = snd_soc_register_codec(&pdev->dev, quirks->codec,
Emilio López45fb6b62015-09-12 15:26:24 +02001568 &sun4i_codec_dai, 1);
1569 if (ret) {
1570 dev_err(&pdev->dev, "Failed to register our codec\n");
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001571 goto err_assert_reset;
Emilio López45fb6b62015-09-12 15:26:24 +02001572 }
1573
1574 ret = devm_snd_soc_register_component(&pdev->dev,
1575 &sun4i_codec_component,
1576 &dummy_cpu_dai, 1);
1577 if (ret) {
1578 dev_err(&pdev->dev, "Failed to register our DAI\n");
1579 goto err_unregister_codec;
1580 }
1581
1582 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1583 if (ret) {
1584 dev_err(&pdev->dev, "Failed to register against DMAEngine\n");
1585 goto err_unregister_codec;
1586 }
1587
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001588 card = quirks->create_card(&pdev->dev);
Chen-Yu Tsai85915b62016-10-31 14:42:09 +08001589 if (IS_ERR(card)) {
1590 ret = PTR_ERR(card);
Emilio López45fb6b62015-09-12 15:26:24 +02001591 dev_err(&pdev->dev, "Failed to create our card\n");
1592 goto err_unregister_codec;
1593 }
1594
1595 platform_set_drvdata(pdev, card);
1596 snd_soc_card_set_drvdata(card, scodec);
1597
1598 ret = snd_soc_register_card(card);
1599 if (ret) {
1600 dev_err(&pdev->dev, "Failed to register our card\n");
1601 goto err_unregister_codec;
1602 }
1603
1604 return 0;
1605
1606err_unregister_codec:
1607 snd_soc_unregister_codec(&pdev->dev);
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001608err_assert_reset:
1609 if (scodec->rst)
1610 reset_control_assert(scodec->rst);
Emilio López45fb6b62015-09-12 15:26:24 +02001611err_clk_disable:
1612 clk_disable_unprepare(scodec->clk_apb);
1613 return ret;
1614}
1615
1616static int sun4i_codec_remove(struct platform_device *pdev)
1617{
1618 struct snd_soc_card *card = platform_get_drvdata(pdev);
1619 struct sun4i_codec *scodec = snd_soc_card_get_drvdata(card);
1620
1621 snd_soc_unregister_card(card);
1622 snd_soc_unregister_codec(&pdev->dev);
Chen-Yu Tsai9aead152016-11-07 18:06:58 +08001623 if (scodec->rst)
1624 reset_control_assert(scodec->rst);
Emilio López45fb6b62015-09-12 15:26:24 +02001625 clk_disable_unprepare(scodec->clk_apb);
1626
1627 return 0;
1628}
1629
1630static struct platform_driver sun4i_codec_driver = {
1631 .driver = {
1632 .name = "sun4i-codec",
Emilio López45fb6b62015-09-12 15:26:24 +02001633 .of_match_table = sun4i_codec_of_match,
1634 },
1635 .probe = sun4i_codec_probe,
1636 .remove = sun4i_codec_remove,
1637};
1638module_platform_driver(sun4i_codec_driver);
1639
1640MODULE_DESCRIPTION("Allwinner A10 codec driver");
1641MODULE_AUTHOR("Emilio López <emilio@elopez.com.ar>");
1642MODULE_AUTHOR("Jon Smirl <jonsmirl@gmail.com>");
1643MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
Chen-Yu Tsaibc03f0d2016-11-03 15:55:44 +08001644MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
Emilio López45fb6b62015-09-12 15:26:24 +02001645MODULE_LICENSE("GPL");