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Tony Lindgren1dbae812005-11-10 14:26:51 +00001/*
2 * linux/arch/arm/mach-omap2/io.c
3 *
4 * OMAP2 I/O mapping code
5 *
6 * Copyright (C) 2005 Nokia Corporation
Santosh Shilimkar44169072009-05-28 14:16:04 -07007 * Copyright (C) 2007-2009 Texas Instruments
Tony Lindgren646e3ed2008-10-06 15:49:36 +03008 *
9 * Author:
10 * Juha Yrjola <juha.yrjola@nokia.com>
11 * Syed Khasim <x0khasim@ti.com>
Tony Lindgren1dbae812005-11-10 14:26:51 +000012 *
Santosh Shilimkar44169072009-05-28 14:16:04 -070013 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
14 *
Tony Lindgren1dbae812005-11-10 14:26:51 +000015 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
Tony Lindgren1dbae812005-11-10 14:26:51 +000020#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
Russell Kingfced80c2008-09-06 12:10:45 +010023#include <linux/io.h>
Paul Walmsley2f135ea2009-06-19 19:08:25 -060024#include <linux/clk.h>
Tomi Valkeinen91773a02009-08-03 15:06:36 +030025#include <linux/omapfb.h>
Tony Lindgren1dbae812005-11-10 14:26:51 +000026
Tony Lindgren120db2c2006-04-02 17:46:27 +010027#include <asm/tlb.h>
Tony Lindgren120db2c2006-04-02 17:46:27 +010028
29#include <asm/mach/map.h>
30
Tony Lindgrence491cf2009-10-20 09:40:47 -070031#include <plat/mux.h>
Tony Lindgrence491cf2009-10-20 09:40:47 -070032#include <plat/sram.h>
33#include <plat/sdrc.h>
34#include <plat/gpmc.h>
35#include <plat/serial.h>
Tomi Valkeinenafedec12009-08-07 12:01:55 +030036#include <plat/vram.h>
Tony Lindgren646e3ed2008-10-06 15:49:36 +030037
38#include "clock.h"
Tony Lindgren1dbae812005-11-10 14:26:51 +000039
Tony Lindgrence491cf2009-10-20 09:40:47 -070040#include <plat/omap-pm.h>
41#include <plat/powerdomain.h>
Paul Walmsley97171002008-08-19 11:08:40 +030042#include "powerdomains.h"
43
Tony Lindgrence491cf2009-10-20 09:40:47 -070044#include <plat/clockdomain.h>
Paul Walmsley801954d2008-08-19 11:08:44 +030045#include "clockdomains.h"
Tony Lindgrence491cf2009-10-20 09:40:47 -070046#include <plat/omap_hwmod.h>
Paul Walmsley02bfc032009-09-03 20:14:05 +030047#include "omap_hwmod_2420.h"
48#include "omap_hwmod_2430.h"
49#include "omap_hwmod_34xx.h"
50
Tony Lindgren1dbae812005-11-10 14:26:51 +000051/*
52 * The machine specific code may provide the extra mapping besides the
53 * default mapping provided here.
54 */
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030055
56#ifdef CONFIG_ARCH_OMAP24XX
57static struct map_desc omap24xx_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000058 {
59 .virtual = L3_24XX_VIRT,
60 .pfn = __phys_to_pfn(L3_24XX_PHYS),
61 .length = L3_24XX_SIZE,
62 .type = MT_DEVICE
63 },
Kyungmin Park09f21ed2008-02-20 15:30:06 -080064 {
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030065 .virtual = L4_24XX_VIRT,
66 .pfn = __phys_to_pfn(L4_24XX_PHYS),
67 .length = L4_24XX_SIZE,
Syed Mohammed Khasim72d0f1c2006-12-06 17:14:05 -080068 .type = MT_DEVICE
69 },
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030070};
71
72#ifdef CONFIG_ARCH_OMAP2420
73static struct map_desc omap242x_io_desc[] __initdata = {
Tony Lindgren1dbae812005-11-10 14:26:51 +000074 {
Tony Lindgrenc40fae952006-12-07 13:58:10 -080075 .virtual = DSP_MEM_24XX_VIRT,
76 .pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
77 .length = DSP_MEM_24XX_SIZE,
78 .type = MT_DEVICE
79 },
80 {
81 .virtual = DSP_IPI_24XX_VIRT,
82 .pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
83 .length = DSP_IPI_24XX_SIZE,
84 .type = MT_DEVICE
85 },
86 {
87 .virtual = DSP_MMU_24XX_VIRT,
88 .pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
89 .length = DSP_MMU_24XX_SIZE,
Tony Lindgren1dbae812005-11-10 14:26:51 +000090 .type = MT_DEVICE
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030091 },
Tony Lindgren1dbae812005-11-10 14:26:51 +000092};
93
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +030094#endif
95
96#ifdef CONFIG_ARCH_OMAP2430
97static struct map_desc omap243x_io_desc[] __initdata = {
98 {
99 .virtual = L4_WK_243X_VIRT,
100 .pfn = __phys_to_pfn(L4_WK_243X_PHYS),
101 .length = L4_WK_243X_SIZE,
102 .type = MT_DEVICE
103 },
104 {
105 .virtual = OMAP243X_GPMC_VIRT,
106 .pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
107 .length = OMAP243X_GPMC_SIZE,
108 .type = MT_DEVICE
109 },
110 {
111 .virtual = OMAP243X_SDRC_VIRT,
112 .pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
113 .length = OMAP243X_SDRC_SIZE,
114 .type = MT_DEVICE
115 },
116 {
117 .virtual = OMAP243X_SMS_VIRT,
118 .pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
119 .length = OMAP243X_SMS_SIZE,
120 .type = MT_DEVICE
121 },
122};
123#endif
124#endif
125
126#ifdef CONFIG_ARCH_OMAP34XX
127static struct map_desc omap34xx_io_desc[] __initdata = {
128 {
129 .virtual = L3_34XX_VIRT,
130 .pfn = __phys_to_pfn(L3_34XX_PHYS),
131 .length = L3_34XX_SIZE,
132 .type = MT_DEVICE
133 },
134 {
135 .virtual = L4_34XX_VIRT,
136 .pfn = __phys_to_pfn(L4_34XX_PHYS),
137 .length = L4_34XX_SIZE,
138 .type = MT_DEVICE
139 },
140 {
141 .virtual = L4_WK_34XX_VIRT,
142 .pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
143 .length = L4_WK_34XX_SIZE,
144 .type = MT_DEVICE
145 },
146 {
147 .virtual = OMAP34XX_GPMC_VIRT,
148 .pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
149 .length = OMAP34XX_GPMC_SIZE,
150 .type = MT_DEVICE
151 },
152 {
153 .virtual = OMAP343X_SMS_VIRT,
154 .pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
155 .length = OMAP343X_SMS_SIZE,
156 .type = MT_DEVICE
157 },
158 {
159 .virtual = OMAP343X_SDRC_VIRT,
160 .pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
161 .length = OMAP343X_SDRC_SIZE,
162 .type = MT_DEVICE
163 },
164 {
165 .virtual = L4_PER_34XX_VIRT,
166 .pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
167 .length = L4_PER_34XX_SIZE,
168 .type = MT_DEVICE
169 },
170 {
171 .virtual = L4_EMU_34XX_VIRT,
172 .pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
173 .length = L4_EMU_34XX_SIZE,
174 .type = MT_DEVICE
175 },
176};
177#endif
Santosh Shilimkar44169072009-05-28 14:16:04 -0700178#ifdef CONFIG_ARCH_OMAP4
179static struct map_desc omap44xx_io_desc[] __initdata = {
180 {
181 .virtual = L3_44XX_VIRT,
182 .pfn = __phys_to_pfn(L3_44XX_PHYS),
183 .length = L3_44XX_SIZE,
184 .type = MT_DEVICE,
185 },
186 {
187 .virtual = L4_44XX_VIRT,
188 .pfn = __phys_to_pfn(L4_44XX_PHYS),
189 .length = L4_44XX_SIZE,
190 .type = MT_DEVICE,
191 },
192 {
193 .virtual = L4_WK_44XX_VIRT,
194 .pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
195 .length = L4_WK_44XX_SIZE,
196 .type = MT_DEVICE,
197 },
198 {
199 .virtual = OMAP44XX_GPMC_VIRT,
200 .pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
201 .length = OMAP44XX_GPMC_SIZE,
202 .type = MT_DEVICE,
203 },
204 {
Santosh Shilimkarf5d2d652009-10-19 17:25:57 -0700205 .virtual = OMAP44XX_EMIF1_VIRT,
206 .pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
207 .length = OMAP44XX_EMIF1_SIZE,
208 .type = MT_DEVICE,
209 },
210 {
211 .virtual = OMAP44XX_EMIF2_VIRT,
212 .pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
213 .length = OMAP44XX_EMIF2_SIZE,
214 .type = MT_DEVICE,
215 },
216 {
217 .virtual = OMAP44XX_DMM_VIRT,
218 .pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
219 .length = OMAP44XX_DMM_SIZE,
220 .type = MT_DEVICE,
221 },
222 {
Santosh Shilimkar44169072009-05-28 14:16:04 -0700223 .virtual = L4_PER_44XX_VIRT,
224 .pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
225 .length = L4_PER_44XX_SIZE,
226 .type = MT_DEVICE,
227 },
228 {
229 .virtual = L4_EMU_44XX_VIRT,
230 .pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
231 .length = L4_EMU_44XX_SIZE,
232 .type = MT_DEVICE,
233 },
234};
235#endif
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300236
Tony Lindgren120db2c2006-04-02 17:46:27 +0100237void __init omap2_map_common_io(void)
Tony Lindgren1dbae812005-11-10 14:26:51 +0000238{
Syed Mohammed, Khasimcc26b3b2008-10-09 17:51:41 +0300239#if defined(CONFIG_ARCH_OMAP2420)
240 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
241 iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
242#endif
243
244#if defined(CONFIG_ARCH_OMAP2430)
245 iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
246 iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
247#endif
248
249#if defined(CONFIG_ARCH_OMAP34XX)
250 iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
251#endif
Tony Lindgren120db2c2006-04-02 17:46:27 +0100252
Santosh Shilimkar44169072009-05-28 14:16:04 -0700253#if defined(CONFIG_ARCH_OMAP4)
254 iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
255#endif
Tony Lindgren120db2c2006-04-02 17:46:27 +0100256 /* Normally devicemaps_init() would flush caches and tlb after
257 * mdesc->map_io(), but we must also do it here because of the CPU
258 * revision check below.
259 */
260 local_flush_tlb_all();
261 flush_cache_all();
262
Tony Lindgren1dbae812005-11-10 14:26:51 +0000263 omap2_check_revision();
264 omap_sram_init();
Imre Deakb7cc6d42007-03-06 03:16:36 -0800265 omapfb_reserve_sdram();
Tomi Valkeinenafedec12009-08-07 12:01:55 +0300266 omap_vram_reserve_sdram();
Tony Lindgren120db2c2006-04-02 17:46:27 +0100267}
268
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600269/*
270 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
271 *
272 * Sets the CORE DPLL3 M2 divider to the same value that it's at
273 * currently. This has the effect of setting the SDRC SDRAM AC timing
274 * registers to the values currently defined by the kernel. Currently
275 * only defined for OMAP3; will return 0 if called on OMAP2. Returns
276 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
277 * or passes along the return value of clk_set_rate().
278 */
279static int __init _omap2_init_reprogram_sdrc(void)
280{
281 struct clk *dpll3_m2_ck;
282 int v = -EINVAL;
283 long rate;
284
285 if (!cpu_is_omap34xx())
286 return 0;
287
288 dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
289 if (!dpll3_m2_ck)
290 return -EINVAL;
291
292 rate = clk_get_rate(dpll3_m2_ck);
293 pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
294 v = clk_set_rate(dpll3_m2_ck, rate);
295 if (v)
296 pr_err("dpll3_m2_clk rate change failed: %d\n", v);
297
298 clk_put(dpll3_m2_ck);
299
300 return v;
301}
302
Jean Pihet58cda882009-07-24 19:43:25 -0600303void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
304 struct omap_sdrc_params *sdrc_cs1)
Tony Lindgren120db2c2006-04-02 17:46:27 +0100305{
Paul Walmsley02bfc032009-09-03 20:14:05 +0300306 struct omap_hwmod **hwmods = NULL;
307
308 if (cpu_is_omap2420())
309 hwmods = omap2420_hwmods;
310 else if (cpu_is_omap2430())
311 hwmods = omap2430_hwmods;
312 else if (cpu_is_omap34xx())
313 hwmods = omap34xx_hwmods;
314
Santosh Shilimkar44169072009-05-28 14:16:04 -0700315#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300316 /* The OPP tables have to be registered before a clk init */
Tony Lindgren61f04ee2009-09-24 16:23:07 -0700317 omap_hwmod_init(hwmods);
318 omap2_mux_init();
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300319 omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
Paul Walmsley97171002008-08-19 11:08:40 +0300320 pwrdm_init(powerdomains_omap);
Paul Walmsley801954d2008-08-19 11:08:44 +0300321 clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
Santosh Shilimkar5b7815b2009-10-22 14:48:14 -0700322#endif
Rajendra Nayakd79b1262009-12-09 00:01:44 +0530323 omap2_clk_init();
Paul Walmsleyb3c6df32009-09-03 20:14:02 +0300324 omap_serial_early_init();
Santosh Shilimkar5b7815b2009-10-22 14:48:14 -0700325#ifndef CONFIG_ARCH_OMAP4
Paul Walmsley02bfc032009-09-03 20:14:05 +0300326 omap_hwmod_late_init();
Paul Walmsleyc0407a92009-09-03 20:14:01 +0300327 omap_pm_if_init();
Jean Pihet58cda882009-07-24 19:43:25 -0600328 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
Paul Walmsley2f135ea2009-06-19 19:08:25 -0600329 _omap2_init_reprogram_sdrc();
Santosh Shilimkar44169072009-05-28 14:16:04 -0700330#endif
Juha Yrjola4bbbc1a2006-06-26 16:16:16 -0700331 gpmc_init();
Tony Lindgren1dbae812005-11-10 14:26:51 +0000332}