blob: f194b4e4f86aa86cd9ac90f9eb63f6526e5def73 [file] [log] [blame]
Andrew Isaacsondc41f942005-10-19 23:58:49 -07001/*
2 * Copyright (C) 2001,2002,2005 Broadcom Corporation
3 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 */
19
20/*
21 * BCM1x80/1x55-specific PCI support
22 *
23 * This module provides the glue between Linux's PCI subsystem
24 * and the hardware. We basically provide glue for accessing
25 * configuration space, and set up the translation for I/O
26 * space accesses.
27 *
28 * To access configuration space, we use ioremap. In the 32-bit
29 * kernel, this consumes either 4 or 8 page table pages, and 16MB of
30 * kernel mapped memory. Hopefully neither of these should be a huge
31 * problem.
32 *
33 * XXX: AT THIS TIME, ONLY the NATIVE PCI-X INTERFACE IS SUPPORTED.
34 */
35#include <linux/config.h>
36#include <linux/types.h>
37#include <linux/pci.h>
38#include <linux/kernel.h>
39#include <linux/init.h>
40#include <linux/mm.h>
41#include <linux/console.h>
42#include <linux/tty.h>
43
44#include <asm/sibyte/bcm1480_regs.h>
45#include <asm/sibyte/bcm1480_scd.h>
46#include <asm/sibyte/board.h>
47#include <asm/io.h>
48
49/*
50 * Macros for calculating offsets into config space given a device
51 * structure or dev/fun/reg
52 */
53#define CFGOFFSET(bus,devfn,where) (((bus)<<16)+((devfn)<<8)+(where))
54#define CFGADDR(bus,devfn,where) CFGOFFSET((bus)->number,(devfn),where)
55
56static void *cfg_space;
57
58#define PCI_BUS_ENABLED 1
Andrew Isaacson8a1417d2005-10-19 23:59:11 -070059#define PCI_DEVICE_MODE 2
Andrew Isaacsondc41f942005-10-19 23:58:49 -070060
61static int bcm1480_bus_status = 0;
62
63#define PCI_BRIDGE_DEVICE 0
Andrew Isaacsondc41f942005-10-19 23:58:49 -070064
65/*
66 * Read/write 32-bit values in config space.
67 */
68static inline u32 READCFG32(u32 addr)
69{
70 return *(u32 *)(cfg_space + (addr&~3));
71}
72
73static inline void WRITECFG32(u32 addr, u32 data)
74{
75 *(u32 *)(cfg_space + (addr & ~3)) = data;
76}
77
78int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
79{
80 return dev->irq;
81}
82
83/* Do platform specific device initialization at pci_enable_device() time */
84int pcibios_plat_dev_init(struct pci_dev *dev)
85{
86 return 0;
87}
88
89/*
90 * Some checks before doing config cycles:
91 * In PCI Device Mode, hide everything on bus 0 except the LDT host
92 * bridge. Otherwise, access is controlled by bridge MasterEn bits.
93 */
94static int bcm1480_pci_can_access(struct pci_bus *bus, int devfn)
95{
Andrew Isaacson8a1417d2005-10-19 23:59:11 -070096 u32 devno;
97
Andrew Isaacsondc41f942005-10-19 23:58:49 -070098 if (!(bcm1480_bus_status & (PCI_BUS_ENABLED | PCI_DEVICE_MODE)))
99 return 0;
100
101 if (bus->number == 0) {
Andrew Isaacson8a1417d2005-10-19 23:59:11 -0700102 devno = PCI_SLOT(devfn);
Andrew Isaacsondc41f942005-10-19 23:58:49 -0700103 if (bcm1480_bus_status & PCI_DEVICE_MODE)
104 return 0;
105 else
106 return 1;
107 } else
108 return 1;
109}
110
111/*
112 * Read/write access functions for various sizes of values
113 * in config space. Return all 1's for disallowed accesses
114 * for a kludgy but adequate simulation of master aborts.
115 */
116
117static int bcm1480_pcibios_read(struct pci_bus *bus, unsigned int devfn,
118 int where, int size, u32 * val)
119{
120 u32 data = 0;
121
122 if ((size == 2) && (where & 1))
123 return PCIBIOS_BAD_REGISTER_NUMBER;
124 else if ((size == 4) && (where & 3))
125 return PCIBIOS_BAD_REGISTER_NUMBER;
126
127 if (bcm1480_pci_can_access(bus, devfn))
128 data = READCFG32(CFGADDR(bus, devfn, where));
129 else
130 data = 0xFFFFFFFF;
131
132 if (size == 1)
133 *val = (data >> ((where & 3) << 3)) & 0xff;
134 else if (size == 2)
135 *val = (data >> ((where & 3) << 3)) & 0xffff;
136 else
137 *val = data;
138
139 return PCIBIOS_SUCCESSFUL;
140}
141
142static int bcm1480_pcibios_write(struct pci_bus *bus, unsigned int devfn,
143 int where, int size, u32 val)
144{
145 u32 cfgaddr = CFGADDR(bus, devfn, where);
146 u32 data = 0;
147
148 if ((size == 2) && (where & 1))
149 return PCIBIOS_BAD_REGISTER_NUMBER;
150 else if ((size == 4) && (where & 3))
151 return PCIBIOS_BAD_REGISTER_NUMBER;
152
153 if (!bcm1480_pci_can_access(bus, devfn))
154 return PCIBIOS_BAD_REGISTER_NUMBER;
155
156 data = READCFG32(cfgaddr);
157
158 if (size == 1)
159 data = (data & ~(0xff << ((where & 3) << 3))) |
160 (val << ((where & 3) << 3));
161 else if (size == 2)
162 data = (data & ~(0xffff << ((where & 3) << 3))) |
163 (val << ((where & 3) << 3));
164 else
165 data = val;
166
167 WRITECFG32(cfgaddr, data);
168
169 return PCIBIOS_SUCCESSFUL;
170}
171
172struct pci_ops bcm1480_pci_ops = {
173 bcm1480_pcibios_read,
174 bcm1480_pcibios_write,
175};
176
177static struct resource bcm1480_mem_resource = {
178 .name = "BCM1480 PCI MEM",
Andrew Isaacson8a1417d2005-10-19 23:59:11 -0700179 .start = 0x30000000UL,
180 .end = 0x3fffffffUL,
Andrew Isaacsondc41f942005-10-19 23:58:49 -0700181 .flags = IORESOURCE_MEM,
182};
183
184static struct resource bcm1480_io_resource = {
185 .name = "BCM1480 PCI I/O",
Andrew Isaacson8a1417d2005-10-19 23:59:11 -0700186 .start = 0x2c000000UL,
187 .end = 0x2dffffffUL,
Andrew Isaacsondc41f942005-10-19 23:58:49 -0700188 .flags = IORESOURCE_IO,
189};
190
191struct pci_controller bcm1480_controller = {
192 .pci_ops = &bcm1480_pci_ops,
193 .mem_resource = &bcm1480_mem_resource,
194 .io_resource = &bcm1480_io_resource,
195};
196
197
198static int __init bcm1480_pcibios_init(void)
199{
200 uint32_t cmdreg;
201 uint64_t reg;
202 extern int pci_probe_only;
203
204 /* CFE will assign PCI resources */
205 pci_probe_only = 1;
206
207 /* Avoid ISA compat ranges. */
208 PCIBIOS_MIN_IO = 0x00008000UL;
209 PCIBIOS_MIN_MEM = 0x01000000UL;
210
Andrew Isaacson8a1417d2005-10-19 23:59:11 -0700211 /* Set I/O resource limits. - unlimited for now to accomodate HT */
212 ioport_resource.end = 0xffffffffUL;
213 iomem_resource.end = 0xffffffffUL;
Andrew Isaacsondc41f942005-10-19 23:58:49 -0700214
215 cfg_space = ioremap(A_BCM1480_PHYS_PCI_CFG_MATCH_BITS, 16*1024*1024);
216
217 /*
218 * See if the PCI bus has been configured by the firmware.
219 */
220 reg = *((volatile uint64_t *) IOADDR(A_SCD_SYSTEM_CFG));
221 if (!(reg & M_BCM1480_SYS_PCI_HOST)) {
222 bcm1480_bus_status |= PCI_DEVICE_MODE;
223 } else {
224 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0),
225 PCI_COMMAND));
226 if (!(cmdreg & PCI_COMMAND_MASTER)) {
227 printk
228 ("PCI: Skipping PCI probe. Bus is not initialized.\n");
229 iounmap(cfg_space);
230 return 1; /* XXX */
231 }
232 bcm1480_bus_status |= PCI_BUS_ENABLED;
233 }
234
Andrew Isaacsoncb426242005-10-19 23:59:46 -0700235 /* turn on ExpMemEn */
236 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
237 printk("PCIFeatureCtrl = %x\n", cmdreg);
238 WRITECFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40),
239 cmdreg | 0x10);
240 cmdreg = READCFG32(CFGOFFSET(0, PCI_DEVFN(PCI_BRIDGE_DEVICE, 0), 0x40));
241 printk("PCIFeatureCtrl = %x\n", cmdreg);
242
Andrew Isaacsondc41f942005-10-19 23:58:49 -0700243 /*
244 * Establish mappings in KSEG2 (kernel virtual) to PCI I/O
245 * space. Use "match bytes" policy to make everything look
246 * little-endian. So, you need to also set
247 * CONFIG_SWAP_IO_SPACE, but this is the combination that
248 * works correctly with most of Linux's drivers.
249 * XXX ehs: Should this happen in PCI Device mode?
250 */
251
252 set_io_port_base((unsigned long)
253 ioremap(A_BCM1480_PHYS_PCI_IO_MATCH_BYTES, 65536));
254 isa_slot_offset = (unsigned long)
255 ioremap(A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES, 1024*1024);
256
257 register_pci_controller(&bcm1480_controller);
258
259#ifdef CONFIG_VGA_CONSOLE
260 take_over_console(&vga_con,0,MAX_NR_CONSOLES-1,1);
261#endif
262 return 0;
263}
264
265arch_initcall(bcm1480_pcibios_init);